1 /* 2 * Xilinx Zynq MPSoC emulation 3 * 4 * Copyright (C) 2015 Xilinx Inc 5 * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15 * for more details. 16 */ 17 18 #include "qemu/osdep.h" 19 #include "qapi/error.h" 20 #include "qemu/module.h" 21 #include "cpu.h" 22 #include "hw/arm/xlnx-zynqmp.h" 23 #include "hw/intc/arm_gic_common.h" 24 #include "hw/boards.h" 25 #include "exec/address-spaces.h" 26 #include "sysemu/kvm.h" 27 #include "sysemu/sysemu.h" 28 #include "kvm_arm.h" 29 30 #define GIC_NUM_SPI_INTR 160 31 32 #define ARM_PHYS_TIMER_PPI 30 33 #define ARM_VIRT_TIMER_PPI 27 34 #define ARM_HYP_TIMER_PPI 26 35 #define ARM_SEC_TIMER_PPI 29 36 #define GIC_MAINTENANCE_PPI 25 37 38 #define GEM_REVISION 0x40070106 39 40 #define GIC_BASE_ADDR 0xf9000000 41 #define GIC_DIST_ADDR 0xf9010000 42 #define GIC_CPU_ADDR 0xf9020000 43 #define GIC_VIFACE_ADDR 0xf9040000 44 #define GIC_VCPU_ADDR 0xf9060000 45 46 #define SATA_INTR 133 47 #define SATA_ADDR 0xFD0C0000 48 #define SATA_NUM_PORTS 2 49 50 #define QSPI_ADDR 0xff0f0000 51 #define LQSPI_ADDR 0xc0000000 52 #define QSPI_IRQ 15 53 54 #define DP_ADDR 0xfd4a0000 55 #define DP_IRQ 113 56 57 #define DPDMA_ADDR 0xfd4c0000 58 #define DPDMA_IRQ 116 59 60 #define IPI_ADDR 0xFF300000 61 #define IPI_IRQ 64 62 63 #define RTC_ADDR 0xffa60000 64 #define RTC_IRQ 26 65 66 #define SDHCI_CAPABILITIES 0x280737ec6481 /* Datasheet: UG1085 (v1.7) */ 67 68 static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = { 69 0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000, 70 }; 71 72 static const int gem_intr[XLNX_ZYNQMP_NUM_GEMS] = { 73 57, 59, 61, 63, 74 }; 75 76 static const uint64_t uart_addr[XLNX_ZYNQMP_NUM_UARTS] = { 77 0xFF000000, 0xFF010000, 78 }; 79 80 static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = { 81 21, 22, 82 }; 83 84 static const uint64_t sdhci_addr[XLNX_ZYNQMP_NUM_SDHCI] = { 85 0xFF160000, 0xFF170000, 86 }; 87 88 static const int sdhci_intr[XLNX_ZYNQMP_NUM_SDHCI] = { 89 48, 49, 90 }; 91 92 static const uint64_t spi_addr[XLNX_ZYNQMP_NUM_SPIS] = { 93 0xFF040000, 0xFF050000, 94 }; 95 96 static const int spi_intr[XLNX_ZYNQMP_NUM_SPIS] = { 97 19, 20, 98 }; 99 100 static const uint64_t gdma_ch_addr[XLNX_ZYNQMP_NUM_GDMA_CH] = { 101 0xFD500000, 0xFD510000, 0xFD520000, 0xFD530000, 102 0xFD540000, 0xFD550000, 0xFD560000, 0xFD570000 103 }; 104 105 static const int gdma_ch_intr[XLNX_ZYNQMP_NUM_GDMA_CH] = { 106 124, 125, 126, 127, 128, 129, 130, 131 107 }; 108 109 static const uint64_t adma_ch_addr[XLNX_ZYNQMP_NUM_ADMA_CH] = { 110 0xFFA80000, 0xFFA90000, 0xFFAA0000, 0xFFAB0000, 111 0xFFAC0000, 0xFFAD0000, 0xFFAE0000, 0xFFAF0000 112 }; 113 114 static const int adma_ch_intr[XLNX_ZYNQMP_NUM_ADMA_CH] = { 115 77, 78, 79, 80, 81, 82, 83, 84 116 }; 117 118 typedef struct XlnxZynqMPGICRegion { 119 int region_index; 120 uint32_t address; 121 uint32_t offset; 122 bool virt; 123 } XlnxZynqMPGICRegion; 124 125 static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_regions[] = { 126 /* Distributor */ 127 { 128 .region_index = 0, 129 .address = GIC_DIST_ADDR, 130 .offset = 0, 131 .virt = false 132 }, 133 134 /* CPU interface */ 135 { 136 .region_index = 1, 137 .address = GIC_CPU_ADDR, 138 .offset = 0, 139 .virt = false 140 }, 141 { 142 .region_index = 1, 143 .address = GIC_CPU_ADDR + 0x10000, 144 .offset = 0x1000, 145 .virt = false 146 }, 147 148 /* Virtual interface */ 149 { 150 .region_index = 2, 151 .address = GIC_VIFACE_ADDR, 152 .offset = 0, 153 .virt = true 154 }, 155 156 /* Virtual CPU interface */ 157 { 158 .region_index = 3, 159 .address = GIC_VCPU_ADDR, 160 .offset = 0, 161 .virt = true 162 }, 163 { 164 .region_index = 3, 165 .address = GIC_VCPU_ADDR + 0x10000, 166 .offset = 0x1000, 167 .virt = true 168 }, 169 }; 170 171 static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index) 172 { 173 return GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_index; 174 } 175 176 static void xlnx_zynqmp_create_rpu(MachineState *ms, XlnxZynqMPState *s, 177 const char *boot_cpu, Error **errp) 178 { 179 Error *err = NULL; 180 int i; 181 int num_rpus = MIN(ms->smp.cpus - XLNX_ZYNQMP_NUM_APU_CPUS, 182 XLNX_ZYNQMP_NUM_RPU_CPUS); 183 184 if (num_rpus <= 0) { 185 /* Don't create rpu-cluster object if there's nothing to put in it */ 186 return; 187 } 188 189 object_initialize_child(OBJECT(s), "rpu-cluster", &s->rpu_cluster, 190 TYPE_CPU_CLUSTER); 191 qdev_prop_set_uint32(DEVICE(&s->rpu_cluster), "cluster-id", 1); 192 193 for (i = 0; i < num_rpus; i++) { 194 char *name; 195 196 object_initialize_child(OBJECT(&s->rpu_cluster), "rpu-cpu[*]", 197 &s->rpu_cpu[i], 198 ARM_CPU_TYPE_NAME("cortex-r5f")); 199 200 name = object_get_canonical_path_component(OBJECT(&s->rpu_cpu[i])); 201 if (strcmp(name, boot_cpu)) { 202 /* Secondary CPUs start in PSCI powered-down state */ 203 object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, 204 "start-powered-off", &error_abort); 205 } else { 206 s->boot_cpu_ptr = &s->rpu_cpu[i]; 207 } 208 g_free(name); 209 210 object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "reset-hivecs", 211 &error_abort); 212 if (!qdev_realize(DEVICE(&s->rpu_cpu[i]), NULL, &err)) { 213 error_propagate(errp, err); 214 return; 215 } 216 } 217 218 qdev_realize(DEVICE(&s->rpu_cluster), NULL, &error_fatal); 219 } 220 221 static void xlnx_zynqmp_init(Object *obj) 222 { 223 MachineState *ms = MACHINE(qdev_get_machine()); 224 XlnxZynqMPState *s = XLNX_ZYNQMP(obj); 225 int i; 226 int num_apus = MIN(ms->smp.cpus, XLNX_ZYNQMP_NUM_APU_CPUS); 227 228 object_initialize_child(obj, "apu-cluster", &s->apu_cluster, 229 TYPE_CPU_CLUSTER); 230 qdev_prop_set_uint32(DEVICE(&s->apu_cluster), "cluster-id", 0); 231 232 for (i = 0; i < num_apus; i++) { 233 object_initialize_child(OBJECT(&s->apu_cluster), "apu-cpu[*]", 234 &s->apu_cpu[i], 235 ARM_CPU_TYPE_NAME("cortex-a53")); 236 } 237 238 object_initialize_child(obj, "gic", &s->gic, gic_class_name()); 239 240 for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) { 241 object_initialize_child(obj, "gem[*]", &s->gem[i], TYPE_CADENCE_GEM); 242 } 243 244 for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) { 245 object_initialize_child(obj, "uart[*]", &s->uart[i], 246 TYPE_CADENCE_UART); 247 } 248 249 object_initialize_child(obj, "sata", &s->sata, TYPE_SYSBUS_AHCI); 250 251 for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) { 252 object_initialize_child(obj, "sdhci[*]", &s->sdhci[i], 253 TYPE_SYSBUS_SDHCI); 254 } 255 256 for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) { 257 object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_XILINX_SPIPS); 258 } 259 260 object_initialize_child(obj, "qspi", &s->qspi, TYPE_XLNX_ZYNQMP_QSPIPS); 261 262 object_initialize_child(obj, "xxxdp", &s->dp, TYPE_XLNX_DP); 263 264 object_initialize_child(obj, "dp-dma", &s->dpdma, TYPE_XLNX_DPDMA); 265 266 object_initialize_child(obj, "ipi", &s->ipi, TYPE_XLNX_ZYNQMP_IPI); 267 268 object_initialize_child(obj, "rtc", &s->rtc, TYPE_XLNX_ZYNQMP_RTC); 269 270 for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) { 271 object_initialize_child(obj, "gdma[*]", &s->gdma[i], TYPE_XLNX_ZDMA); 272 } 273 274 for (i = 0; i < XLNX_ZYNQMP_NUM_ADMA_CH; i++) { 275 object_initialize_child(obj, "adma[*]", &s->adma[i], TYPE_XLNX_ZDMA); 276 } 277 } 278 279 static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) 280 { 281 MachineState *ms = MACHINE(qdev_get_machine()); 282 XlnxZynqMPState *s = XLNX_ZYNQMP(dev); 283 MemoryRegion *system_memory = get_system_memory(); 284 uint8_t i; 285 uint64_t ram_size; 286 int num_apus = MIN(ms->smp.cpus, XLNX_ZYNQMP_NUM_APU_CPUS); 287 const char *boot_cpu = s->boot_cpu ? s->boot_cpu : "apu-cpu[0]"; 288 ram_addr_t ddr_low_size, ddr_high_size; 289 qemu_irq gic_spi[GIC_NUM_SPI_INTR]; 290 Error *err = NULL; 291 292 ram_size = memory_region_size(s->ddr_ram); 293 294 /* Create the DDR Memory Regions. User friendly checks should happen at 295 * the board level 296 */ 297 if (ram_size > XLNX_ZYNQMP_MAX_LOW_RAM_SIZE) { 298 /* The RAM size is above the maximum available for the low DDR. 299 * Create the high DDR memory region as well. 300 */ 301 assert(ram_size <= XLNX_ZYNQMP_MAX_RAM_SIZE); 302 ddr_low_size = XLNX_ZYNQMP_MAX_LOW_RAM_SIZE; 303 ddr_high_size = ram_size - XLNX_ZYNQMP_MAX_LOW_RAM_SIZE; 304 305 memory_region_init_alias(&s->ddr_ram_high, OBJECT(dev), 306 "ddr-ram-high", s->ddr_ram, ddr_low_size, 307 ddr_high_size); 308 memory_region_add_subregion(get_system_memory(), 309 XLNX_ZYNQMP_HIGH_RAM_START, 310 &s->ddr_ram_high); 311 } else { 312 /* RAM must be non-zero */ 313 assert(ram_size); 314 ddr_low_size = ram_size; 315 } 316 317 memory_region_init_alias(&s->ddr_ram_low, OBJECT(dev), "ddr-ram-low", 318 s->ddr_ram, 0, ddr_low_size); 319 memory_region_add_subregion(get_system_memory(), 0, &s->ddr_ram_low); 320 321 /* Create the four OCM banks */ 322 for (i = 0; i < XLNX_ZYNQMP_NUM_OCM_BANKS; i++) { 323 char *ocm_name = g_strdup_printf("zynqmp.ocm_ram_bank_%d", i); 324 325 memory_region_init_ram(&s->ocm_ram[i], NULL, ocm_name, 326 XLNX_ZYNQMP_OCM_RAM_SIZE, &error_fatal); 327 memory_region_add_subregion(get_system_memory(), 328 XLNX_ZYNQMP_OCM_RAM_0_ADDRESS + 329 i * XLNX_ZYNQMP_OCM_RAM_SIZE, 330 &s->ocm_ram[i]); 331 332 g_free(ocm_name); 333 } 334 335 qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32); 336 qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2); 337 qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", num_apus); 338 qdev_prop_set_bit(DEVICE(&s->gic), "has-security-extensions", s->secure); 339 qdev_prop_set_bit(DEVICE(&s->gic), 340 "has-virtualization-extensions", s->virt); 341 342 qdev_realize(DEVICE(&s->apu_cluster), NULL, &error_fatal); 343 344 /* Realize APUs before realizing the GIC. KVM requires this. */ 345 for (i = 0; i < num_apus; i++) { 346 char *name; 347 348 object_property_set_int(OBJECT(&s->apu_cpu[i]), QEMU_PSCI_CONDUIT_SMC, 349 "psci-conduit", &error_abort); 350 351 name = object_get_canonical_path_component(OBJECT(&s->apu_cpu[i])); 352 if (strcmp(name, boot_cpu)) { 353 /* Secondary CPUs start in PSCI powered-down state */ 354 object_property_set_bool(OBJECT(&s->apu_cpu[i]), true, 355 "start-powered-off", &error_abort); 356 } else { 357 s->boot_cpu_ptr = &s->apu_cpu[i]; 358 } 359 g_free(name); 360 361 object_property_set_bool(OBJECT(&s->apu_cpu[i]), 362 s->secure, "has_el3", NULL); 363 object_property_set_bool(OBJECT(&s->apu_cpu[i]), 364 s->virt, "has_el2", NULL); 365 object_property_set_int(OBJECT(&s->apu_cpu[i]), GIC_BASE_ADDR, 366 "reset-cbar", &error_abort); 367 object_property_set_int(OBJECT(&s->apu_cpu[i]), num_apus, 368 "core-count", &error_abort); 369 if (!qdev_realize(DEVICE(&s->apu_cpu[i]), NULL, &err)) { 370 error_propagate(errp, err); 371 return; 372 } 373 } 374 375 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gic), &err)) { 376 error_propagate(errp, err); 377 return; 378 } 379 380 assert(ARRAY_SIZE(xlnx_zynqmp_gic_regions) == XLNX_ZYNQMP_GIC_REGIONS); 381 for (i = 0; i < XLNX_ZYNQMP_GIC_REGIONS; i++) { 382 SysBusDevice *gic = SYS_BUS_DEVICE(&s->gic); 383 const XlnxZynqMPGICRegion *r = &xlnx_zynqmp_gic_regions[i]; 384 MemoryRegion *mr; 385 uint32_t addr = r->address; 386 int j; 387 388 if (r->virt && !s->virt) { 389 continue; 390 } 391 392 mr = sysbus_mmio_get_region(gic, r->region_index); 393 for (j = 0; j < XLNX_ZYNQMP_GIC_ALIASES; j++) { 394 MemoryRegion *alias = &s->gic_mr[i][j]; 395 396 memory_region_init_alias(alias, OBJECT(s), "zynqmp-gic-alias", mr, 397 r->offset, XLNX_ZYNQMP_GIC_REGION_SIZE); 398 memory_region_add_subregion(system_memory, addr, alias); 399 400 addr += XLNX_ZYNQMP_GIC_REGION_SIZE; 401 } 402 } 403 404 for (i = 0; i < num_apus; i++) { 405 qemu_irq irq; 406 407 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i, 408 qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]), 409 ARM_CPU_IRQ)); 410 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus, 411 qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]), 412 ARM_CPU_FIQ)); 413 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 2, 414 qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]), 415 ARM_CPU_VIRQ)); 416 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 3, 417 qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]), 418 ARM_CPU_VFIQ)); 419 irq = qdev_get_gpio_in(DEVICE(&s->gic), 420 arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI)); 421 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_PHYS, irq); 422 irq = qdev_get_gpio_in(DEVICE(&s->gic), 423 arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI)); 424 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_VIRT, irq); 425 irq = qdev_get_gpio_in(DEVICE(&s->gic), 426 arm_gic_ppi_index(i, ARM_HYP_TIMER_PPI)); 427 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_HYP, irq); 428 irq = qdev_get_gpio_in(DEVICE(&s->gic), 429 arm_gic_ppi_index(i, ARM_SEC_TIMER_PPI)); 430 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_SEC, irq); 431 432 if (s->virt) { 433 irq = qdev_get_gpio_in(DEVICE(&s->gic), 434 arm_gic_ppi_index(i, GIC_MAINTENANCE_PPI)); 435 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 4, irq); 436 } 437 } 438 439 if (s->has_rpu) { 440 info_report("The 'has_rpu' property is no longer required, to use the " 441 "RPUs just use -smp 6."); 442 } 443 444 xlnx_zynqmp_create_rpu(ms, s, boot_cpu, &err); 445 if (err) { 446 error_propagate(errp, err); 447 return; 448 } 449 450 if (!s->boot_cpu_ptr) { 451 error_setg(errp, "ZynqMP Boot cpu %s not found", boot_cpu); 452 return; 453 } 454 455 for (i = 0; i < GIC_NUM_SPI_INTR; i++) { 456 gic_spi[i] = qdev_get_gpio_in(DEVICE(&s->gic), i); 457 } 458 459 for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) { 460 NICInfo *nd = &nd_table[i]; 461 462 if (nd->used) { 463 qemu_check_nic_model(nd, TYPE_CADENCE_GEM); 464 qdev_set_nic_properties(DEVICE(&s->gem[i]), nd); 465 } 466 object_property_set_int(OBJECT(&s->gem[i]), GEM_REVISION, "revision", 467 &error_abort); 468 object_property_set_int(OBJECT(&s->gem[i]), 2, "num-priority-queues", 469 &error_abort); 470 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gem[i]), &err)) { 471 error_propagate(errp, err); 472 return; 473 } 474 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem[i]), 0, gem_addr[i]); 475 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem[i]), 0, 476 gic_spi[gem_intr[i]]); 477 } 478 479 for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) { 480 qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i)); 481 if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), &err)) { 482 error_propagate(errp, err); 483 return; 484 } 485 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, uart_addr[i]); 486 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, 487 gic_spi[uart_intr[i]]); 488 } 489 490 object_property_set_int(OBJECT(&s->sata), SATA_NUM_PORTS, "num-ports", 491 &error_abort); 492 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sata), &err)) { 493 error_propagate(errp, err); 494 return; 495 } 496 497 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, SATA_ADDR); 498 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, gic_spi[SATA_INTR]); 499 500 for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) { 501 char *bus_name; 502 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->sdhci[i]); 503 Object *sdhci = OBJECT(&s->sdhci[i]); 504 505 /* Compatible with: 506 * - SD Host Controller Specification Version 3.00 507 * - SDIO Specification Version 3.0 508 * - eMMC Specification Version 4.51 509 */ 510 object_property_set_uint(sdhci, 3, "sd-spec-version", &err); 511 if (err) { 512 error_propagate(errp, err); 513 return; 514 } 515 object_property_set_uint(sdhci, SDHCI_CAPABILITIES, "capareg", &err); 516 if (err) { 517 error_propagate(errp, err); 518 return; 519 } 520 object_property_set_uint(sdhci, UHS_I, "uhs", &err); 521 if (err) { 522 error_propagate(errp, err); 523 return; 524 } 525 if (!sysbus_realize(SYS_BUS_DEVICE(sdhci), &err)) { 526 error_propagate(errp, err); 527 return; 528 } 529 sysbus_mmio_map(sbd, 0, sdhci_addr[i]); 530 sysbus_connect_irq(sbd, 0, gic_spi[sdhci_intr[i]]); 531 532 /* Alias controller SD bus to the SoC itself */ 533 bus_name = g_strdup_printf("sd-bus%d", i); 534 object_property_add_alias(OBJECT(s), bus_name, sdhci, "sd-bus"); 535 g_free(bus_name); 536 } 537 538 for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) { 539 gchar *bus_name; 540 541 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), &err)) { 542 error_propagate(errp, err); 543 return; 544 } 545 546 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]); 547 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0, 548 gic_spi[spi_intr[i]]); 549 550 /* Alias controller SPI bus to the SoC itself */ 551 bus_name = g_strdup_printf("spi%d", i); 552 object_property_add_alias(OBJECT(s), bus_name, 553 OBJECT(&s->spi[i]), "spi0"); 554 g_free(bus_name); 555 } 556 557 if (!sysbus_realize(SYS_BUS_DEVICE(&s->qspi), &err)) { 558 error_propagate(errp, err); 559 return; 560 } 561 sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 0, QSPI_ADDR); 562 sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 1, LQSPI_ADDR); 563 sysbus_connect_irq(SYS_BUS_DEVICE(&s->qspi), 0, gic_spi[QSPI_IRQ]); 564 565 for (i = 0; i < XLNX_ZYNQMP_NUM_QSPI_BUS; i++) { 566 gchar *bus_name; 567 gchar *target_bus; 568 569 /* Alias controller SPI bus to the SoC itself */ 570 bus_name = g_strdup_printf("qspi%d", i); 571 target_bus = g_strdup_printf("spi%d", i); 572 object_property_add_alias(OBJECT(s), bus_name, 573 OBJECT(&s->qspi), target_bus); 574 g_free(bus_name); 575 g_free(target_bus); 576 } 577 578 if (!sysbus_realize(SYS_BUS_DEVICE(&s->dp), &err)) { 579 error_propagate(errp, err); 580 return; 581 } 582 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dp), 0, DP_ADDR); 583 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dp), 0, gic_spi[DP_IRQ]); 584 585 if (!sysbus_realize(SYS_BUS_DEVICE(&s->dpdma), &err)) { 586 error_propagate(errp, err); 587 return; 588 } 589 object_property_set_link(OBJECT(&s->dp), OBJECT(&s->dpdma), "dpdma", 590 &error_abort); 591 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dpdma), 0, DPDMA_ADDR); 592 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dpdma), 0, gic_spi[DPDMA_IRQ]); 593 594 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ipi), &err)) { 595 error_propagate(errp, err); 596 return; 597 } 598 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ipi), 0, IPI_ADDR); 599 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ipi), 0, gic_spi[IPI_IRQ]); 600 601 if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), &err)) { 602 error_propagate(errp, err); 603 return; 604 } 605 sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, RTC_ADDR); 606 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, gic_spi[RTC_IRQ]); 607 608 for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) { 609 object_property_set_uint(OBJECT(&s->gdma[i]), 128, "bus-width", &err); 610 if (err) { 611 error_propagate(errp, err); 612 return; 613 } 614 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gdma[i]), &err)) { 615 error_propagate(errp, err); 616 return; 617 } 618 619 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gdma[i]), 0, gdma_ch_addr[i]); 620 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gdma[i]), 0, 621 gic_spi[gdma_ch_intr[i]]); 622 } 623 624 for (i = 0; i < XLNX_ZYNQMP_NUM_ADMA_CH; i++) { 625 if (!sysbus_realize(SYS_BUS_DEVICE(&s->adma[i]), &err)) { 626 error_propagate(errp, err); 627 return; 628 } 629 630 sysbus_mmio_map(SYS_BUS_DEVICE(&s->adma[i]), 0, adma_ch_addr[i]); 631 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adma[i]), 0, 632 gic_spi[adma_ch_intr[i]]); 633 } 634 } 635 636 static Property xlnx_zynqmp_props[] = { 637 DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState, boot_cpu), 638 DEFINE_PROP_BOOL("secure", XlnxZynqMPState, secure, false), 639 DEFINE_PROP_BOOL("virtualization", XlnxZynqMPState, virt, false), 640 DEFINE_PROP_BOOL("has_rpu", XlnxZynqMPState, has_rpu, false), 641 DEFINE_PROP_LINK("ddr-ram", XlnxZynqMPState, ddr_ram, TYPE_MEMORY_REGION, 642 MemoryRegion *), 643 DEFINE_PROP_END_OF_LIST() 644 }; 645 646 static void xlnx_zynqmp_class_init(ObjectClass *oc, void *data) 647 { 648 DeviceClass *dc = DEVICE_CLASS(oc); 649 650 device_class_set_props(dc, xlnx_zynqmp_props); 651 dc->realize = xlnx_zynqmp_realize; 652 /* Reason: Uses serial_hds in realize function, thus can't be used twice */ 653 dc->user_creatable = false; 654 } 655 656 static const TypeInfo xlnx_zynqmp_type_info = { 657 .name = TYPE_XLNX_ZYNQMP, 658 .parent = TYPE_DEVICE, 659 .instance_size = sizeof(XlnxZynqMPState), 660 .instance_init = xlnx_zynqmp_init, 661 .class_init = xlnx_zynqmp_class_init, 662 }; 663 664 static void xlnx_zynqmp_register_types(void) 665 { 666 type_register_static(&xlnx_zynqmp_type_info); 667 } 668 669 type_init(xlnx_zynqmp_register_types) 670