1 /* 2 * Xilinx Zynq MPSoC emulation 3 * 4 * Copyright (C) 2015 Xilinx Inc 5 * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15 * for more details. 16 */ 17 18 #include "qemu/osdep.h" 19 #include "qapi/error.h" 20 #include "qemu-common.h" 21 #include "cpu.h" 22 #include "hw/arm/xlnx-zynqmp.h" 23 #include "hw/intc/arm_gic_common.h" 24 #include "exec/address-spaces.h" 25 26 #define GIC_NUM_SPI_INTR 160 27 28 #define ARM_PHYS_TIMER_PPI 30 29 #define ARM_VIRT_TIMER_PPI 27 30 31 #define GIC_BASE_ADDR 0xf9000000 32 #define GIC_DIST_ADDR 0xf9010000 33 #define GIC_CPU_ADDR 0xf9020000 34 35 #define SATA_INTR 133 36 #define SATA_ADDR 0xFD0C0000 37 #define SATA_NUM_PORTS 2 38 39 static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = { 40 0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000, 41 }; 42 43 static const int gem_intr[XLNX_ZYNQMP_NUM_GEMS] = { 44 57, 59, 61, 63, 45 }; 46 47 static const uint64_t uart_addr[XLNX_ZYNQMP_NUM_UARTS] = { 48 0xFF000000, 0xFF010000, 49 }; 50 51 static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = { 52 21, 22, 53 }; 54 55 static const uint64_t sdhci_addr[XLNX_ZYNQMP_NUM_SDHCI] = { 56 0xFF160000, 0xFF170000, 57 }; 58 59 static const int sdhci_intr[XLNX_ZYNQMP_NUM_SDHCI] = { 60 48, 49, 61 }; 62 63 static const uint64_t spi_addr[XLNX_ZYNQMP_NUM_SPIS] = { 64 0xFF040000, 0xFF050000, 65 }; 66 67 static const int spi_intr[XLNX_ZYNQMP_NUM_SPIS] = { 68 19, 20, 69 }; 70 71 typedef struct XlnxZynqMPGICRegion { 72 int region_index; 73 uint32_t address; 74 } XlnxZynqMPGICRegion; 75 76 static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_regions[] = { 77 { .region_index = 0, .address = GIC_DIST_ADDR, }, 78 { .region_index = 1, .address = GIC_CPU_ADDR, }, 79 }; 80 81 static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index) 82 { 83 return GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_index; 84 } 85 86 static void xlnx_zynqmp_create_rpu(XlnxZynqMPState *s, const char *boot_cpu, 87 Error **errp) 88 { 89 Error *err = NULL; 90 int i; 91 92 for (i = 0; i < XLNX_ZYNQMP_NUM_RPU_CPUS; i++) { 93 char *name; 94 95 object_initialize(&s->rpu_cpu[i], sizeof(s->rpu_cpu[i]), 96 "cortex-r5-" TYPE_ARM_CPU); 97 object_property_add_child(OBJECT(s), "rpu-cpu[*]", 98 OBJECT(&s->rpu_cpu[i]), &error_abort); 99 100 name = object_get_canonical_path_component(OBJECT(&s->rpu_cpu[i])); 101 if (strcmp(name, boot_cpu)) { 102 /* Secondary CPUs start in PSCI powered-down state */ 103 object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, 104 "start-powered-off", &error_abort); 105 } else { 106 s->boot_cpu_ptr = &s->rpu_cpu[i]; 107 } 108 g_free(name); 109 110 object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "reset-hivecs", 111 &error_abort); 112 object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "realized", 113 &err); 114 if (err) { 115 error_propagate(errp, err); 116 return; 117 } 118 } 119 } 120 121 static void xlnx_zynqmp_init(Object *obj) 122 { 123 XlnxZynqMPState *s = XLNX_ZYNQMP(obj); 124 int i; 125 126 for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) { 127 object_initialize(&s->apu_cpu[i], sizeof(s->apu_cpu[i]), 128 "cortex-a53-" TYPE_ARM_CPU); 129 object_property_add_child(obj, "apu-cpu[*]", OBJECT(&s->apu_cpu[i]), 130 &error_abort); 131 } 132 133 object_property_add_link(obj, "ddr-ram", TYPE_MEMORY_REGION, 134 (Object **)&s->ddr_ram, 135 qdev_prop_allow_set_link_before_realize, 136 OBJ_PROP_LINK_UNREF_ON_RELEASE, &error_abort); 137 138 object_initialize(&s->gic, sizeof(s->gic), TYPE_ARM_GIC); 139 qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default()); 140 141 for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) { 142 object_initialize(&s->gem[i], sizeof(s->gem[i]), TYPE_CADENCE_GEM); 143 qdev_set_parent_bus(DEVICE(&s->gem[i]), sysbus_get_default()); 144 } 145 146 for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) { 147 object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_CADENCE_UART); 148 qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus_get_default()); 149 } 150 151 object_initialize(&s->sata, sizeof(s->sata), TYPE_SYSBUS_AHCI); 152 qdev_set_parent_bus(DEVICE(&s->sata), sysbus_get_default()); 153 154 for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) { 155 object_initialize(&s->sdhci[i], sizeof(s->sdhci[i]), 156 TYPE_SYSBUS_SDHCI); 157 qdev_set_parent_bus(DEVICE(&s->sdhci[i]), 158 sysbus_get_default()); 159 } 160 161 for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) { 162 object_initialize(&s->spi[i], sizeof(s->spi[i]), 163 TYPE_XILINX_SPIPS); 164 qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default()); 165 } 166 } 167 168 static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) 169 { 170 XlnxZynqMPState *s = XLNX_ZYNQMP(dev); 171 MemoryRegion *system_memory = get_system_memory(); 172 uint8_t i; 173 uint64_t ram_size; 174 const char *boot_cpu = s->boot_cpu ? s->boot_cpu : "apu-cpu[0]"; 175 ram_addr_t ddr_low_size, ddr_high_size; 176 qemu_irq gic_spi[GIC_NUM_SPI_INTR]; 177 Error *err = NULL; 178 179 ram_size = memory_region_size(s->ddr_ram); 180 181 /* Create the DDR Memory Regions. User friendly checks should happen at 182 * the board level 183 */ 184 if (ram_size > XLNX_ZYNQMP_MAX_LOW_RAM_SIZE) { 185 /* The RAM size is above the maximum available for the low DDR. 186 * Create the high DDR memory region as well. 187 */ 188 assert(ram_size <= XLNX_ZYNQMP_MAX_RAM_SIZE); 189 ddr_low_size = XLNX_ZYNQMP_MAX_LOW_RAM_SIZE; 190 ddr_high_size = ram_size - XLNX_ZYNQMP_MAX_LOW_RAM_SIZE; 191 192 memory_region_init_alias(&s->ddr_ram_high, NULL, 193 "ddr-ram-high", s->ddr_ram, 194 ddr_low_size, ddr_high_size); 195 memory_region_add_subregion(get_system_memory(), 196 XLNX_ZYNQMP_HIGH_RAM_START, 197 &s->ddr_ram_high); 198 } else { 199 /* RAM must be non-zero */ 200 assert(ram_size); 201 ddr_low_size = ram_size; 202 } 203 204 memory_region_init_alias(&s->ddr_ram_low, NULL, 205 "ddr-ram-low", s->ddr_ram, 206 0, ddr_low_size); 207 memory_region_add_subregion(get_system_memory(), 0, &s->ddr_ram_low); 208 209 /* Create the four OCM banks */ 210 for (i = 0; i < XLNX_ZYNQMP_NUM_OCM_BANKS; i++) { 211 char *ocm_name = g_strdup_printf("zynqmp.ocm_ram_bank_%d", i); 212 213 memory_region_init_ram(&s->ocm_ram[i], NULL, ocm_name, 214 XLNX_ZYNQMP_OCM_RAM_SIZE, &error_fatal); 215 vmstate_register_ram_global(&s->ocm_ram[i]); 216 memory_region_add_subregion(get_system_memory(), 217 XLNX_ZYNQMP_OCM_RAM_0_ADDRESS + 218 i * XLNX_ZYNQMP_OCM_RAM_SIZE, 219 &s->ocm_ram[i]); 220 221 g_free(ocm_name); 222 } 223 224 qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32); 225 qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2); 226 qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", XLNX_ZYNQMP_NUM_APU_CPUS); 227 228 /* Realize APUs before realizing the GIC. KVM requires this. */ 229 for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) { 230 char *name; 231 232 object_property_set_int(OBJECT(&s->apu_cpu[i]), QEMU_PSCI_CONDUIT_SMC, 233 "psci-conduit", &error_abort); 234 235 name = object_get_canonical_path_component(OBJECT(&s->apu_cpu[i])); 236 if (strcmp(name, boot_cpu)) { 237 /* Secondary CPUs start in PSCI powered-down state */ 238 object_property_set_bool(OBJECT(&s->apu_cpu[i]), true, 239 "start-powered-off", &error_abort); 240 } else { 241 s->boot_cpu_ptr = &s->apu_cpu[i]; 242 } 243 g_free(name); 244 245 object_property_set_bool(OBJECT(&s->apu_cpu[i]), 246 s->secure, "has_el3", NULL); 247 object_property_set_int(OBJECT(&s->apu_cpu[i]), GIC_BASE_ADDR, 248 "reset-cbar", &error_abort); 249 object_property_set_bool(OBJECT(&s->apu_cpu[i]), true, "realized", 250 &err); 251 if (err) { 252 error_propagate(errp, err); 253 return; 254 } 255 } 256 257 object_property_set_bool(OBJECT(&s->gic), true, "realized", &err); 258 if (err) { 259 error_propagate(errp, err); 260 return; 261 } 262 263 assert(ARRAY_SIZE(xlnx_zynqmp_gic_regions) == XLNX_ZYNQMP_GIC_REGIONS); 264 for (i = 0; i < XLNX_ZYNQMP_GIC_REGIONS; i++) { 265 SysBusDevice *gic = SYS_BUS_DEVICE(&s->gic); 266 const XlnxZynqMPGICRegion *r = &xlnx_zynqmp_gic_regions[i]; 267 MemoryRegion *mr = sysbus_mmio_get_region(gic, r->region_index); 268 uint32_t addr = r->address; 269 int j; 270 271 sysbus_mmio_map(gic, r->region_index, addr); 272 273 for (j = 0; j < XLNX_ZYNQMP_GIC_ALIASES; j++) { 274 MemoryRegion *alias = &s->gic_mr[i][j]; 275 276 addr += XLNX_ZYNQMP_GIC_REGION_SIZE; 277 memory_region_init_alias(alias, OBJECT(s), "zynqmp-gic-alias", mr, 278 0, XLNX_ZYNQMP_GIC_REGION_SIZE); 279 memory_region_add_subregion(system_memory, addr, alias); 280 } 281 } 282 283 for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) { 284 qemu_irq irq; 285 286 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i, 287 qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]), 288 ARM_CPU_IRQ)); 289 irq = qdev_get_gpio_in(DEVICE(&s->gic), 290 arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI)); 291 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 0, irq); 292 irq = qdev_get_gpio_in(DEVICE(&s->gic), 293 arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI)); 294 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 1, irq); 295 } 296 297 if (s->has_rpu) { 298 xlnx_zynqmp_create_rpu(s, boot_cpu, &err); 299 if (err) { 300 error_propagate(errp, err); 301 return; 302 } 303 } 304 305 if (!s->boot_cpu_ptr) { 306 error_setg(errp, "ZynqMP Boot cpu %s not found", boot_cpu); 307 return; 308 } 309 310 for (i = 0; i < GIC_NUM_SPI_INTR; i++) { 311 gic_spi[i] = qdev_get_gpio_in(DEVICE(&s->gic), i); 312 } 313 314 for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) { 315 NICInfo *nd = &nd_table[i]; 316 317 if (nd->used) { 318 qemu_check_nic_model(nd, TYPE_CADENCE_GEM); 319 qdev_set_nic_properties(DEVICE(&s->gem[i]), nd); 320 } 321 object_property_set_bool(OBJECT(&s->gem[i]), true, "realized", &err); 322 if (err) { 323 error_propagate(errp, err); 324 return; 325 } 326 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem[i]), 0, gem_addr[i]); 327 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem[i]), 0, 328 gic_spi[gem_intr[i]]); 329 } 330 331 for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) { 332 object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err); 333 if (err) { 334 error_propagate(errp, err); 335 return; 336 } 337 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, uart_addr[i]); 338 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, 339 gic_spi[uart_intr[i]]); 340 } 341 342 object_property_set_int(OBJECT(&s->sata), SATA_NUM_PORTS, "num-ports", 343 &error_abort); 344 object_property_set_bool(OBJECT(&s->sata), true, "realized", &err); 345 if (err) { 346 error_propagate(errp, err); 347 return; 348 } 349 350 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, SATA_ADDR); 351 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, gic_spi[SATA_INTR]); 352 353 for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) { 354 char *bus_name; 355 356 object_property_set_bool(OBJECT(&s->sdhci[i]), true, 357 "realized", &err); 358 if (err) { 359 error_propagate(errp, err); 360 return; 361 } 362 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci[i]), 0, 363 sdhci_addr[i]); 364 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci[i]), 0, 365 gic_spi[sdhci_intr[i]]); 366 /* Alias controller SD bus to the SoC itself */ 367 bus_name = g_strdup_printf("sd-bus%d", i); 368 object_property_add_alias(OBJECT(s), bus_name, 369 OBJECT(&s->sdhci[i]), "sd-bus", 370 &error_abort); 371 g_free(bus_name); 372 } 373 374 for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) { 375 gchar *bus_name; 376 377 object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err); 378 379 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]); 380 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0, 381 gic_spi[spi_intr[i]]); 382 383 /* Alias controller SPI bus to the SoC itself */ 384 bus_name = g_strdup_printf("spi%d", i); 385 object_property_add_alias(OBJECT(s), bus_name, 386 OBJECT(&s->spi[i]), "spi0", 387 &error_abort); 388 g_free(bus_name); 389 } 390 } 391 392 static Property xlnx_zynqmp_props[] = { 393 DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState, boot_cpu), 394 DEFINE_PROP_BOOL("secure", XlnxZynqMPState, secure, false), 395 DEFINE_PROP_BOOL("has_rpu", XlnxZynqMPState, has_rpu, false), 396 DEFINE_PROP_END_OF_LIST() 397 }; 398 399 static void xlnx_zynqmp_class_init(ObjectClass *oc, void *data) 400 { 401 DeviceClass *dc = DEVICE_CLASS(oc); 402 403 dc->props = xlnx_zynqmp_props; 404 dc->realize = xlnx_zynqmp_realize; 405 406 /* 407 * Reason: creates an ARM CPU, thus use after free(), see 408 * arm_cpu_class_init() 409 */ 410 dc->cannot_destroy_with_object_finalize_yet = true; 411 } 412 413 static const TypeInfo xlnx_zynqmp_type_info = { 414 .name = TYPE_XLNX_ZYNQMP, 415 .parent = TYPE_DEVICE, 416 .instance_size = sizeof(XlnxZynqMPState), 417 .instance_init = xlnx_zynqmp_init, 418 .class_init = xlnx_zynqmp_class_init, 419 }; 420 421 static void xlnx_zynqmp_register_types(void) 422 { 423 type_register_static(&xlnx_zynqmp_type_info); 424 } 425 426 type_init(xlnx_zynqmp_register_types) 427