1 /* 2 * ASPEED SoC 27x0 family 3 * 4 * Copyright (C) 2024 ASPEED Technology Inc. 5 * 6 * This code is licensed under the GPL version 2 or later. See 7 * the COPYING file in the top-level directory. 8 * 9 * Implementation extracted from the AST2600 and adapted for AST27x0. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qapi/error.h" 14 #include "hw/misc/unimp.h" 15 #include "hw/arm/aspeed_soc.h" 16 #include "hw/arm/bsa.h" 17 #include "qemu/module.h" 18 #include "qemu/error-report.h" 19 #include "hw/i2c/aspeed_i2c.h" 20 #include "net/net.h" 21 #include "system/system.h" 22 #include "hw/intc/arm_gicv3.h" 23 #include "qobject/qlist.h" 24 #include "qemu/log.h" 25 26 #define AST2700_SOC_IO_SIZE 0x01000000 27 #define AST2700_SOC_IOMEM_SIZE 0x01000000 28 #define AST2700_SOC_DPMCU_SIZE 0x00040000 29 #define AST2700_SOC_LTPI_SIZE 0x01000000 30 31 static const hwaddr aspeed_soc_ast2700_memmap[] = { 32 [ASPEED_DEV_IOMEM] = 0x00000000, 33 [ASPEED_DEV_VBOOTROM] = 0x00000000, 34 [ASPEED_DEV_SRAM] = 0x10000000, 35 [ASPEED_DEV_DPMCU] = 0x11000000, 36 [ASPEED_DEV_IOMEM0] = 0x12000000, 37 [ASPEED_DEV_EHCI1] = 0x12061000, 38 [ASPEED_DEV_EHCI2] = 0x12063000, 39 [ASPEED_DEV_HACE] = 0x12070000, 40 [ASPEED_DEV_EMMC] = 0x12090000, 41 [ASPEED_DEV_INTC] = 0x12100000, 42 [ASPEED_GIC_DIST] = 0x12200000, 43 [ASPEED_GIC_REDIST] = 0x12280000, 44 [ASPEED_DEV_SDMC] = 0x12C00000, 45 [ASPEED_DEV_SCU] = 0x12C02000, 46 [ASPEED_DEV_RTC] = 0x12C0F000, 47 [ASPEED_DEV_TIMER1] = 0x12C10000, 48 [ASPEED_DEV_SLI] = 0x12C17000, 49 [ASPEED_DEV_UART4] = 0x12C1A000, 50 [ASPEED_DEV_IOMEM1] = 0x14000000, 51 [ASPEED_DEV_FMC] = 0x14000000, 52 [ASPEED_DEV_SPI0] = 0x14010000, 53 [ASPEED_DEV_SPI1] = 0x14020000, 54 [ASPEED_DEV_SPI2] = 0x14030000, 55 [ASPEED_DEV_MII1] = 0x14040000, 56 [ASPEED_DEV_MII2] = 0x14040008, 57 [ASPEED_DEV_MII3] = 0x14040010, 58 [ASPEED_DEV_ETH1] = 0x14050000, 59 [ASPEED_DEV_ETH2] = 0x14060000, 60 [ASPEED_DEV_ETH3] = 0x14070000, 61 [ASPEED_DEV_SDHCI] = 0x14080000, 62 [ASPEED_DEV_EHCI3] = 0x14121000, 63 [ASPEED_DEV_EHCI4] = 0x14123000, 64 [ASPEED_DEV_ADC] = 0x14C00000, 65 [ASPEED_DEV_SCUIO] = 0x14C02000, 66 [ASPEED_DEV_GPIO] = 0x14C0B000, 67 [ASPEED_DEV_I2C] = 0x14C0F000, 68 [ASPEED_DEV_INTCIO] = 0x14C18000, 69 [ASPEED_DEV_SLIIO] = 0x14C1E000, 70 [ASPEED_DEV_VUART] = 0x14C30000, 71 [ASPEED_DEV_UART0] = 0x14C33000, 72 [ASPEED_DEV_UART1] = 0x14C33100, 73 [ASPEED_DEV_UART2] = 0x14C33200, 74 [ASPEED_DEV_UART3] = 0x14C33300, 75 [ASPEED_DEV_UART5] = 0x14C33400, 76 [ASPEED_DEV_UART6] = 0x14C33500, 77 [ASPEED_DEV_UART7] = 0x14C33600, 78 [ASPEED_DEV_UART8] = 0x14C33700, 79 [ASPEED_DEV_UART9] = 0x14C33800, 80 [ASPEED_DEV_UART10] = 0x14C33900, 81 [ASPEED_DEV_UART11] = 0x14C33A00, 82 [ASPEED_DEV_UART12] = 0x14C33B00, 83 [ASPEED_DEV_WDT] = 0x14C37000, 84 [ASPEED_DEV_SPI_BOOT] = 0x100000000, 85 [ASPEED_DEV_LTPI] = 0x300000000, 86 [ASPEED_DEV_SDRAM] = 0x400000000, 87 }; 88 89 #define AST2700_MAX_IRQ 256 90 91 /* Shared Peripheral Interrupt values below are offset by -32 from datasheet */ 92 static const int aspeed_soc_ast2700a0_irqmap[] = { 93 [ASPEED_DEV_SDMC] = 0, 94 [ASPEED_DEV_HACE] = 4, 95 [ASPEED_DEV_XDMA] = 5, 96 [ASPEED_DEV_UART4] = 8, 97 [ASPEED_DEV_SCU] = 12, 98 [ASPEED_DEV_RTC] = 13, 99 [ASPEED_DEV_EMMC] = 15, 100 [ASPEED_DEV_TIMER1] = 16, 101 [ASPEED_DEV_TIMER2] = 17, 102 [ASPEED_DEV_TIMER3] = 18, 103 [ASPEED_DEV_TIMER4] = 19, 104 [ASPEED_DEV_TIMER5] = 20, 105 [ASPEED_DEV_TIMER6] = 21, 106 [ASPEED_DEV_TIMER7] = 22, 107 [ASPEED_DEV_TIMER8] = 23, 108 [ASPEED_DEV_DP] = 28, 109 [ASPEED_DEV_EHCI1] = 33, 110 [ASPEED_DEV_EHCI2] = 37, 111 [ASPEED_DEV_LPC] = 128, 112 [ASPEED_DEV_IBT] = 128, 113 [ASPEED_DEV_KCS] = 128, 114 [ASPEED_DEV_ADC] = 130, 115 [ASPEED_DEV_GPIO] = 130, 116 [ASPEED_DEV_I2C] = 130, 117 [ASPEED_DEV_FMC] = 131, 118 [ASPEED_DEV_WDT] = 131, 119 [ASPEED_DEV_PWM] = 131, 120 [ASPEED_DEV_I3C] = 131, 121 [ASPEED_DEV_UART0] = 132, 122 [ASPEED_DEV_UART1] = 132, 123 [ASPEED_DEV_UART2] = 132, 124 [ASPEED_DEV_UART3] = 132, 125 [ASPEED_DEV_UART5] = 132, 126 [ASPEED_DEV_UART6] = 132, 127 [ASPEED_DEV_UART7] = 132, 128 [ASPEED_DEV_UART8] = 132, 129 [ASPEED_DEV_UART9] = 132, 130 [ASPEED_DEV_UART10] = 132, 131 [ASPEED_DEV_UART11] = 132, 132 [ASPEED_DEV_UART12] = 132, 133 [ASPEED_DEV_ETH1] = 132, 134 [ASPEED_DEV_ETH2] = 132, 135 [ASPEED_DEV_ETH3] = 132, 136 [ASPEED_DEV_PECI] = 133, 137 [ASPEED_DEV_SDHCI] = 133, 138 }; 139 140 static const int aspeed_soc_ast2700a1_irqmap[] = { 141 [ASPEED_DEV_SDMC] = 0, 142 [ASPEED_DEV_HACE] = 4, 143 [ASPEED_DEV_XDMA] = 5, 144 [ASPEED_DEV_UART4] = 8, 145 [ASPEED_DEV_SCU] = 12, 146 [ASPEED_DEV_RTC] = 13, 147 [ASPEED_DEV_EMMC] = 15, 148 [ASPEED_DEV_TIMER1] = 16, 149 [ASPEED_DEV_TIMER2] = 17, 150 [ASPEED_DEV_TIMER3] = 18, 151 [ASPEED_DEV_TIMER4] = 19, 152 [ASPEED_DEV_TIMER5] = 20, 153 [ASPEED_DEV_TIMER6] = 21, 154 [ASPEED_DEV_TIMER7] = 22, 155 [ASPEED_DEV_TIMER8] = 23, 156 [ASPEED_DEV_DP] = 28, 157 [ASPEED_DEV_EHCI1] = 33, 158 [ASPEED_DEV_EHCI2] = 37, 159 [ASPEED_DEV_LPC] = 192, 160 [ASPEED_DEV_IBT] = 192, 161 [ASPEED_DEV_KCS] = 192, 162 [ASPEED_DEV_I2C] = 194, 163 [ASPEED_DEV_ADC] = 194, 164 [ASPEED_DEV_GPIO] = 194, 165 [ASPEED_DEV_FMC] = 195, 166 [ASPEED_DEV_WDT] = 195, 167 [ASPEED_DEV_PWM] = 195, 168 [ASPEED_DEV_I3C] = 195, 169 [ASPEED_DEV_UART0] = 196, 170 [ASPEED_DEV_UART1] = 196, 171 [ASPEED_DEV_UART2] = 196, 172 [ASPEED_DEV_UART3] = 196, 173 [ASPEED_DEV_UART5] = 196, 174 [ASPEED_DEV_UART6] = 196, 175 [ASPEED_DEV_UART7] = 196, 176 [ASPEED_DEV_UART8] = 196, 177 [ASPEED_DEV_UART9] = 196, 178 [ASPEED_DEV_UART10] = 196, 179 [ASPEED_DEV_UART11] = 196, 180 [ASPEED_DEV_UART12] = 196, 181 [ASPEED_DEV_ETH1] = 196, 182 [ASPEED_DEV_ETH2] = 196, 183 [ASPEED_DEV_ETH3] = 196, 184 [ASPEED_DEV_PECI] = 197, 185 [ASPEED_DEV_SDHCI] = 197, 186 }; 187 188 /* GICINT 128 */ 189 /* GICINT 192 */ 190 static const int ast2700_gic128_gic192_intcmap[] = { 191 [ASPEED_DEV_LPC] = 0, 192 [ASPEED_DEV_IBT] = 2, 193 [ASPEED_DEV_KCS] = 4, 194 }; 195 196 /* GICINT 129 */ 197 /* GICINT 193 */ 198 199 /* GICINT 130 */ 200 /* GICINT 194 */ 201 static const int ast2700_gic130_gic194_intcmap[] = { 202 [ASPEED_DEV_I2C] = 0, 203 [ASPEED_DEV_ADC] = 16, 204 [ASPEED_DEV_GPIO] = 18, 205 }; 206 207 /* GICINT 131 */ 208 /* GICINT 195 */ 209 static const int ast2700_gic131_gic195_intcmap[] = { 210 [ASPEED_DEV_I3C] = 0, 211 [ASPEED_DEV_WDT] = 16, 212 [ASPEED_DEV_FMC] = 25, 213 [ASPEED_DEV_PWM] = 29, 214 }; 215 216 /* GICINT 132 */ 217 /* GICINT 196 */ 218 static const int ast2700_gic132_gic196_intcmap[] = { 219 [ASPEED_DEV_ETH1] = 0, 220 [ASPEED_DEV_ETH2] = 1, 221 [ASPEED_DEV_ETH3] = 2, 222 [ASPEED_DEV_UART0] = 7, 223 [ASPEED_DEV_UART1] = 8, 224 [ASPEED_DEV_UART2] = 9, 225 [ASPEED_DEV_UART3] = 10, 226 [ASPEED_DEV_UART5] = 11, 227 [ASPEED_DEV_UART6] = 12, 228 [ASPEED_DEV_UART7] = 13, 229 [ASPEED_DEV_UART8] = 14, 230 [ASPEED_DEV_UART9] = 15, 231 [ASPEED_DEV_UART10] = 16, 232 [ASPEED_DEV_UART11] = 17, 233 [ASPEED_DEV_UART12] = 18, 234 [ASPEED_DEV_EHCI3] = 28, 235 [ASPEED_DEV_EHCI4] = 29, 236 }; 237 238 /* GICINT 133 */ 239 /* GICINT 197 */ 240 static const int ast2700_gic133_gic197_intcmap[] = { 241 [ASPEED_DEV_SDHCI] = 1, 242 [ASPEED_DEV_PECI] = 4, 243 }; 244 245 /* GICINT 128 ~ 136 */ 246 /* GICINT 192 ~ 201 */ 247 struct gic_intc_irq_info { 248 int irq; 249 int intc_idx; 250 int orgate_idx; 251 const int *ptr; 252 }; 253 254 static const struct gic_intc_irq_info ast2700_gic_intcmap[] = { 255 {192, 1, 0, ast2700_gic128_gic192_intcmap}, 256 {193, 1, 1, NULL}, 257 {194, 1, 2, ast2700_gic130_gic194_intcmap}, 258 {195, 1, 3, ast2700_gic131_gic195_intcmap}, 259 {196, 1, 4, ast2700_gic132_gic196_intcmap}, 260 {197, 1, 5, ast2700_gic133_gic197_intcmap}, 261 {198, 1, 6, NULL}, 262 {199, 1, 7, NULL}, 263 {200, 1, 8, NULL}, 264 {201, 1, 9, NULL}, 265 {128, 0, 1, ast2700_gic128_gic192_intcmap}, 266 {129, 0, 2, NULL}, 267 {130, 0, 3, ast2700_gic130_gic194_intcmap}, 268 {131, 0, 4, ast2700_gic131_gic195_intcmap}, 269 {132, 0, 5, ast2700_gic132_gic196_intcmap}, 270 {133, 0, 6, ast2700_gic133_gic197_intcmap}, 271 {134, 0, 7, NULL}, 272 {135, 0, 8, NULL}, 273 {136, 0, 9, NULL}, 274 }; 275 276 static qemu_irq aspeed_soc_ast2700_get_irq(AspeedSoCState *s, int dev) 277 { 278 Aspeed27x0SoCState *a = ASPEED27X0_SOC(s); 279 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 280 int or_idx; 281 int idx; 282 int i; 283 284 for (i = 0; i < ARRAY_SIZE(ast2700_gic_intcmap); i++) { 285 if (sc->irqmap[dev] == ast2700_gic_intcmap[i].irq) { 286 assert(ast2700_gic_intcmap[i].ptr); 287 or_idx = ast2700_gic_intcmap[i].orgate_idx; 288 idx = ast2700_gic_intcmap[i].intc_idx; 289 return qdev_get_gpio_in(DEVICE(&a->intc[idx].orgates[or_idx]), 290 ast2700_gic_intcmap[i].ptr[dev]); 291 } 292 } 293 294 return qdev_get_gpio_in(DEVICE(&a->gic), sc->irqmap[dev]); 295 } 296 297 static qemu_irq aspeed_soc_ast2700_get_irq_index(AspeedSoCState *s, int dev, 298 int index) 299 { 300 Aspeed27x0SoCState *a = ASPEED27X0_SOC(s); 301 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 302 int or_idx; 303 int idx; 304 int i; 305 306 for (i = 0; i < ARRAY_SIZE(ast2700_gic_intcmap); i++) { 307 if (sc->irqmap[dev] == ast2700_gic_intcmap[i].irq) { 308 assert(ast2700_gic_intcmap[i].ptr); 309 or_idx = ast2700_gic_intcmap[i].orgate_idx; 310 idx = ast2700_gic_intcmap[i].intc_idx; 311 return qdev_get_gpio_in(DEVICE(&a->intc[idx].orgates[or_idx]), 312 ast2700_gic_intcmap[i].ptr[dev] + index); 313 } 314 } 315 316 /* 317 * Invalid OR gate index, device IRQ should be between 128 to 136 318 * and 192 to 201. 319 */ 320 g_assert_not_reached(); 321 } 322 323 static uint64_t aspeed_ram_capacity_read(void *opaque, hwaddr addr, 324 unsigned int size) 325 { 326 qemu_log_mask(LOG_GUEST_ERROR, 327 "%s: DRAM read out of ram size, addr:0x%" PRIx64 "\n", 328 __func__, addr); 329 return 0; 330 } 331 332 static void aspeed_ram_capacity_write(void *opaque, hwaddr addr, uint64_t data, 333 unsigned int size) 334 { 335 AspeedSoCState *s = ASPEED_SOC(opaque); 336 ram_addr_t ram_size; 337 MemTxResult result; 338 339 ram_size = object_property_get_uint(OBJECT(&s->sdmc), "ram-size", 340 &error_abort); 341 342 assert(ram_size > 0); 343 344 /* 345 * Emulate ddr capacity hardware behavior. 346 * If writes the data to the address which is beyond the ram size, 347 * it would write the data to the "address % ram_size". 348 */ 349 result = address_space_write(&s->dram_as, addr % ram_size, 350 MEMTXATTRS_UNSPECIFIED, &data, 4); 351 if (result != MEMTX_OK) { 352 qemu_log_mask(LOG_GUEST_ERROR, 353 "%s: DRAM write failed, addr:0x%" HWADDR_PRIx 354 ", data :0x%" PRIx64 "\n", 355 __func__, addr % ram_size, data); 356 } 357 } 358 359 static const MemoryRegionOps aspeed_ram_capacity_ops = { 360 .read = aspeed_ram_capacity_read, 361 .write = aspeed_ram_capacity_write, 362 .endianness = DEVICE_LITTLE_ENDIAN, 363 .valid = { 364 .min_access_size = 1, 365 .max_access_size = 8, 366 }, 367 }; 368 369 /* 370 * SDMC should be realized first to get correct RAM size and max size 371 * values 372 */ 373 static bool aspeed_soc_ast2700_dram_init(DeviceState *dev, Error **errp) 374 { 375 ram_addr_t ram_size, max_ram_size; 376 Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev); 377 AspeedSoCState *s = ASPEED_SOC(dev); 378 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 379 380 ram_size = object_property_get_uint(OBJECT(&s->sdmc), "ram-size", 381 &error_abort); 382 max_ram_size = object_property_get_uint(OBJECT(&s->sdmc), "max-ram-size", 383 &error_abort); 384 385 memory_region_init(&s->dram_container, OBJECT(s), "ram-container", 386 ram_size); 387 memory_region_add_subregion(&s->dram_container, 0, s->dram_mr); 388 address_space_init(&s->dram_as, s->dram_mr, "dram"); 389 390 /* 391 * Add a memory region beyond the RAM region to emulate 392 * ddr capacity hardware behavior. 393 */ 394 if (ram_size < max_ram_size) { 395 memory_region_init_io(&a->dram_empty, OBJECT(s), 396 &aspeed_ram_capacity_ops, s, 397 "ram-empty", max_ram_size - ram_size); 398 399 memory_region_add_subregion(s->memory, 400 sc->memmap[ASPEED_DEV_SDRAM] + ram_size, 401 &a->dram_empty); 402 } 403 404 memory_region_add_subregion(s->memory, 405 sc->memmap[ASPEED_DEV_SDRAM], &s->dram_container); 406 return true; 407 } 408 409 static void aspeed_soc_ast2700_init(Object *obj) 410 { 411 Aspeed27x0SoCState *a = ASPEED27X0_SOC(obj); 412 AspeedSoCState *s = ASPEED_SOC(obj); 413 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 414 int i; 415 char socname[8]; 416 char typename[64]; 417 418 if (sscanf(object_get_typename(obj), "%7s", socname) != 1) { 419 g_assert_not_reached(); 420 } 421 422 for (i = 0; i < sc->num_cpus; i++) { 423 object_initialize_child(obj, "cpu[*]", &a->cpu[i], 424 aspeed_soc_cpu_type(sc)); 425 } 426 427 object_initialize_child(obj, "gic", &a->gic, gicv3_class_name()); 428 429 object_initialize_child(obj, "scu", &s->scu, TYPE_ASPEED_2700_SCU); 430 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", 431 sc->silicon_rev); 432 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), 433 "hw-strap1"); 434 object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu), 435 "hw-prot-key"); 436 437 object_initialize_child(obj, "scuio", &s->scuio, TYPE_ASPEED_2700_SCUIO); 438 qdev_prop_set_uint32(DEVICE(&s->scuio), "silicon-rev", 439 sc->silicon_rev); 440 /* 441 * There is one hw-strap1 register in the SCU (CPU DIE) and another 442 * hw-strap1 register in the SCUIO (IO DIE). To reuse the current design 443 * of hw-strap, hw-strap1 is assigned to the SCU and sets the value in the 444 * SCU hw-strap1 register, while hw-strap2 is assigned to the SCUIO and 445 * sets the value in the SCUIO hw-strap1 register. 446 */ 447 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scuio), 448 "hw-strap1"); 449 450 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); 451 object_initialize_child(obj, "fmc", &s->fmc, typename); 452 453 for (i = 0; i < sc->spis_num; i++) { 454 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i, socname); 455 object_initialize_child(obj, "spi[*]", &s->spi[i], typename); 456 } 457 458 for (i = 0; i < sc->ehcis_num; i++) { 459 object_initialize_child(obj, "ehci[*]", &s->ehci[i], 460 TYPE_PLATFORM_EHCI); 461 } 462 463 snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname); 464 object_initialize_child(obj, "sdmc", &s->sdmc, typename); 465 object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), 466 "ram-size"); 467 468 for (i = 0; i < sc->wdts_num; i++) { 469 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); 470 object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename); 471 } 472 473 for (i = 0; i < sc->macs_num; i++) { 474 object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i], 475 TYPE_FTGMAC100); 476 477 object_initialize_child(obj, "mii[*]", &s->mii[i], TYPE_ASPEED_MII); 478 } 479 480 for (i = 0; i < sc->uarts_num; i++) { 481 object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM); 482 } 483 484 object_initialize_child(obj, "sli", &s->sli, TYPE_ASPEED_2700_SLI); 485 object_initialize_child(obj, "sliio", &s->sliio, TYPE_ASPEED_2700_SLIIO); 486 object_initialize_child(obj, "intc", &a->intc[0], TYPE_ASPEED_2700_INTC); 487 object_initialize_child(obj, "intcio", &a->intc[1], 488 TYPE_ASPEED_2700_INTCIO); 489 490 snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname); 491 object_initialize_child(obj, "adc", &s->adc, typename); 492 493 snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); 494 object_initialize_child(obj, "i2c", &s->i2c, typename); 495 496 snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); 497 object_initialize_child(obj, "gpio", &s->gpio, typename); 498 499 object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC); 500 501 snprintf(typename, sizeof(typename), "aspeed.sdhci-%s", socname); 502 object_initialize_child(obj, "sd-controller", &s->sdhci, typename); 503 object_property_set_int(OBJECT(&s->sdhci), "num-slots", 1, &error_abort); 504 505 /* Init sd card slot class here so that they're under the correct parent */ 506 object_initialize_child(obj, "sd-controller.sdhci", 507 &s->sdhci.slots[0], TYPE_SYSBUS_SDHCI); 508 509 object_initialize_child(obj, "emmc-controller", &s->emmc, typename); 510 object_property_set_int(OBJECT(&s->emmc), "num-slots", 1, &error_abort); 511 512 object_initialize_child(obj, "emmc-controller.sdhci", &s->emmc.slots[0], 513 TYPE_SYSBUS_SDHCI); 514 515 snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname); 516 object_initialize_child(obj, "timerctrl", &s->timerctrl, typename); 517 518 snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname); 519 object_initialize_child(obj, "hace", &s->hace, typename); 520 object_initialize_child(obj, "dpmcu", &s->dpmcu, 521 TYPE_UNIMPLEMENTED_DEVICE); 522 object_initialize_child(obj, "ltpi", &s->ltpi, 523 TYPE_UNIMPLEMENTED_DEVICE); 524 object_initialize_child(obj, "iomem", &s->iomem, 525 TYPE_UNIMPLEMENTED_DEVICE); 526 object_initialize_child(obj, "iomem0", &s->iomem0, 527 TYPE_UNIMPLEMENTED_DEVICE); 528 object_initialize_child(obj, "iomem1", &s->iomem1, 529 TYPE_UNIMPLEMENTED_DEVICE); 530 } 531 532 /* 533 * ASPEED ast2700 has 0x0 as cluster ID 534 * 535 * https://developer.arm.com/documentation/100236/0100/register-descriptions/aarch64-system-registers/multiprocessor-affinity-register--el1 536 */ 537 static uint64_t aspeed_calc_affinity(int cpu) 538 { 539 return (0x0 << ARM_AFF1_SHIFT) | cpu; 540 } 541 542 static bool aspeed_soc_ast2700_gic_realize(DeviceState *dev, Error **errp) 543 { 544 Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev); 545 AspeedSoCState *s = ASPEED_SOC(dev); 546 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 547 SysBusDevice *gicbusdev; 548 DeviceState *gicdev; 549 QList *redist_region_count; 550 int i; 551 552 gicbusdev = SYS_BUS_DEVICE(&a->gic); 553 gicdev = DEVICE(&a->gic); 554 qdev_prop_set_uint32(gicdev, "revision", 3); 555 qdev_prop_set_uint32(gicdev, "num-cpu", sc->num_cpus); 556 qdev_prop_set_uint32(gicdev, "num-irq", AST2700_MAX_IRQ + GIC_INTERNAL); 557 558 redist_region_count = qlist_new(); 559 qlist_append_int(redist_region_count, sc->num_cpus); 560 qdev_prop_set_array(gicdev, "redist-region-count", redist_region_count); 561 562 if (!sysbus_realize(gicbusdev, errp)) { 563 return false; 564 } 565 566 aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->gic), 0, 567 sc->memmap[ASPEED_GIC_DIST]); 568 aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->gic), 1, 569 sc->memmap[ASPEED_GIC_REDIST]); 570 571 for (i = 0; i < sc->num_cpus; i++) { 572 DeviceState *cpudev = DEVICE(&a->cpu[i]); 573 int intidbase = AST2700_MAX_IRQ + i * GIC_INTERNAL; 574 575 const int timer_irq[] = { 576 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, 577 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, 578 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, 579 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, 580 }; 581 int j; 582 583 for (j = 0; j < ARRAY_SIZE(timer_irq); j++) { 584 qdev_connect_gpio_out(cpudev, j, 585 qdev_get_gpio_in(gicdev, intidbase + timer_irq[j])); 586 } 587 588 qemu_irq irq = qdev_get_gpio_in(gicdev, 589 intidbase + ARCH_GIC_MAINT_IRQ); 590 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 591 0, irq); 592 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, 593 qdev_get_gpio_in(gicdev, intidbase + VIRTUAL_PMU_IRQ)); 594 595 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 596 sysbus_connect_irq(gicbusdev, i + sc->num_cpus, 597 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 598 sysbus_connect_irq(gicbusdev, i + 2 * sc->num_cpus, 599 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 600 sysbus_connect_irq(gicbusdev, i + 3 * sc->num_cpus, 601 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 602 sysbus_connect_irq(gicbusdev, i + 4 * sc->num_cpus, 603 qdev_get_gpio_in(cpudev, ARM_CPU_NMI)); 604 sysbus_connect_irq(gicbusdev, i + 5 * sc->num_cpus, 605 qdev_get_gpio_in(cpudev, ARM_CPU_VINMI)); 606 } 607 608 return true; 609 } 610 611 static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp) 612 { 613 int i; 614 Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev); 615 AspeedSoCState *s = ASPEED_SOC(dev); 616 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 617 AspeedINTCClass *ic = ASPEED_INTC_GET_CLASS(&a->intc[0]); 618 AspeedINTCClass *icio = ASPEED_INTC_GET_CLASS(&a->intc[1]); 619 g_autofree char *name = NULL; 620 qemu_irq irq; 621 622 /* Default boot region (SPI memory or ROMs) */ 623 memory_region_init(&s->spi_boot_container, OBJECT(s), 624 "aspeed.spi_boot_container", 0x400000000); 625 memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SPI_BOOT], 626 &s->spi_boot_container); 627 628 /* CPU */ 629 for (i = 0; i < sc->num_cpus; i++) { 630 object_property_set_int(OBJECT(&a->cpu[i]), "mp-affinity", 631 aspeed_calc_affinity(i), &error_abort); 632 633 object_property_set_int(OBJECT(&a->cpu[i]), "cntfrq", 1125000000, 634 &error_abort); 635 object_property_set_link(OBJECT(&a->cpu[i]), "memory", 636 OBJECT(s->memory), &error_abort); 637 638 if (!qdev_realize(DEVICE(&a->cpu[i]), NULL, errp)) { 639 return; 640 } 641 } 642 643 /* GIC */ 644 if (!aspeed_soc_ast2700_gic_realize(dev, errp)) { 645 return; 646 } 647 648 /* INTC */ 649 if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[0]), errp)) { 650 return; 651 } 652 653 aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc[0]), 0, 654 sc->memmap[ASPEED_DEV_INTC]); 655 656 /* INTCIO */ 657 if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[1]), errp)) { 658 return; 659 } 660 661 aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc[1]), 0, 662 sc->memmap[ASPEED_DEV_INTCIO]); 663 664 /* irq sources -> orgates -> INTC */ 665 for (i = 0; i < ic->num_inpins; i++) { 666 qdev_connect_gpio_out(DEVICE(&a->intc[0].orgates[i]), 0, 667 qdev_get_gpio_in(DEVICE(&a->intc[0]), i)); 668 } 669 670 /* INTC -> GIC192 - GIC201 */ 671 /* INTC -> GIC128 - GIC136 */ 672 for (i = 0; i < ic->num_outpins; i++) { 673 sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc[0]), i, 674 qdev_get_gpio_in(DEVICE(&a->gic), 675 ast2700_gic_intcmap[i].irq)); 676 } 677 678 /* irq source -> orgates -> INTCIO */ 679 for (i = 0; i < icio->num_inpins; i++) { 680 qdev_connect_gpio_out(DEVICE(&a->intc[1].orgates[i]), 0, 681 qdev_get_gpio_in(DEVICE(&a->intc[1]), i)); 682 } 683 684 /* INTCIO -> INTC */ 685 for (i = 0; i < icio->num_outpins; i++) { 686 sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc[1]), i, 687 qdev_get_gpio_in(DEVICE(&a->intc[0].orgates[0]), i)); 688 } 689 690 /* SRAM */ 691 name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index); 692 if (!memory_region_init_ram(&s->sram, OBJECT(s), name, sc->sram_size, 693 errp)) { 694 return; 695 } 696 memory_region_add_subregion(s->memory, 697 sc->memmap[ASPEED_DEV_SRAM], &s->sram); 698 699 /* VBOOTROM */ 700 if (!memory_region_init_ram(&s->vbootrom, OBJECT(s), "aspeed.vbootrom", 701 0x20000, errp)) { 702 return; 703 } 704 memory_region_add_subregion(s->memory, 705 sc->memmap[ASPEED_DEV_VBOOTROM], &s->vbootrom); 706 707 /* SCU */ 708 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { 709 return; 710 } 711 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]); 712 713 /* SCU1 */ 714 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scuio), errp)) { 715 return; 716 } 717 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scuio), 0, 718 sc->memmap[ASPEED_DEV_SCUIO]); 719 720 /* UART */ 721 if (!aspeed_soc_uart_realize(s, errp)) { 722 return; 723 } 724 725 /* FMC, The number of CS is set at the board level */ 726 object_property_set_int(OBJECT(&s->fmc), "dram-base", 727 sc->memmap[ASPEED_DEV_SDRAM], 728 &error_abort); 729 object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr), 730 &error_abort); 731 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) { 732 return; 733 } 734 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]); 735 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 1, 736 ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base); 737 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, 738 aspeed_soc_get_irq(s, ASPEED_DEV_FMC)); 739 740 /* Set up an alias on the FMC CE0 region (boot default) */ 741 MemoryRegion *fmc0_mmio = &s->fmc.flashes[0].mmio; 742 memory_region_init_alias(&s->spi_boot, OBJECT(s), "aspeed.spi_boot", 743 fmc0_mmio, 0, memory_region_size(fmc0_mmio)); 744 memory_region_add_subregion(&s->spi_boot_container, 0x0, &s->spi_boot); 745 746 /* SPI */ 747 for (i = 0; i < sc->spis_num; i++) { 748 object_property_set_link(OBJECT(&s->spi[i]), "dram", 749 OBJECT(s->dram_mr), &error_abort); 750 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { 751 return; 752 } 753 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 0, 754 sc->memmap[ASPEED_DEV_SPI0 + i]); 755 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 1, 756 ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base); 757 } 758 759 /* EHCI */ 760 for (i = 0; i < sc->ehcis_num; i++) { 761 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), errp)) { 762 return; 763 } 764 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ehci[i]), 0, 765 sc->memmap[ASPEED_DEV_EHCI1 + i]); 766 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0, 767 aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i)); 768 } 769 770 /* 771 * SDMC - SDRAM Memory Controller 772 * The SDMC controller is unlocked at SPL stage. 773 * At present, only supports to emulate booting 774 * start from u-boot stage. Set SDMC controller 775 * unlocked by default. It is a temporarily solution. 776 */ 777 object_property_set_bool(OBJECT(&s->sdmc), "unlocked", true, 778 &error_abort); 779 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) { 780 return; 781 } 782 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdmc), 0, 783 sc->memmap[ASPEED_DEV_SDMC]); 784 785 /* RAM */ 786 if (!aspeed_soc_ast2700_dram_init(dev, errp)) { 787 return; 788 } 789 790 /* Net */ 791 for (i = 0; i < sc->macs_num; i++) { 792 object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true, 793 &error_abort); 794 object_property_set_bool(OBJECT(&s->ftgmac100[i]), "dma64", true, 795 &error_abort); 796 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) { 797 return; 798 } 799 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 800 sc->memmap[ASPEED_DEV_ETH1 + i]); 801 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 802 aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i)); 803 804 object_property_set_link(OBJECT(&s->mii[i]), "nic", 805 OBJECT(&s->ftgmac100[i]), &error_abort); 806 if (!sysbus_realize(SYS_BUS_DEVICE(&s->mii[i]), errp)) { 807 return; 808 } 809 810 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->mii[i]), 0, 811 sc->memmap[ASPEED_DEV_MII1 + i]); 812 } 813 814 /* Watch dog */ 815 for (i = 0; i < sc->wdts_num; i++) { 816 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); 817 hwaddr wdt_offset = sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize; 818 819 object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu), 820 &error_abort); 821 if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) { 822 return; 823 } 824 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offset); 825 } 826 827 /* SLI */ 828 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sli), errp)) { 829 return; 830 } 831 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sli), 0, sc->memmap[ASPEED_DEV_SLI]); 832 833 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sliio), errp)) { 834 return; 835 } 836 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sliio), 0, 837 sc->memmap[ASPEED_DEV_SLIIO]); 838 839 /* ADC */ 840 if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) { 841 return; 842 } 843 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]); 844 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0, 845 aspeed_soc_get_irq(s, ASPEED_DEV_ADC)); 846 847 /* I2C */ 848 object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr), 849 &error_abort); 850 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) { 851 return; 852 } 853 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]); 854 for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) { 855 /* 856 * The AST2700 I2C controller has one source INTC per bus. 857 * 858 * For AST2700 A0: 859 * I2C bus interrupts are connected to the OR gate from bit 0 to bit 860 * 15, and the OR gate output pin is connected to the input pin of 861 * GICINT130 of INTC (CPU Die). Then, the output pin is connected to 862 * the GIC. 863 * 864 * For AST2700 A1: 865 * I2C bus interrupts are connected to the OR gate from bit 0 to bit 866 * 15, and the OR gate output pin is connected to the input pin of 867 * GICINT194 of INTCIO (IO Die). Then, the output pin is connected 868 * to the INTC (CPU Die) input pin, and its output pin is connected 869 * to the GIC. 870 * 871 * I2C bus 0 is connected to the OR gate at bit 0. 872 * I2C bus 15 is connected to the OR gate at bit 15. 873 */ 874 irq = aspeed_soc_ast2700_get_irq_index(s, ASPEED_DEV_I2C, i); 875 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq); 876 } 877 878 /* GPIO */ 879 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { 880 return; 881 } 882 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio), 0, 883 sc->memmap[ASPEED_DEV_GPIO]); 884 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, 885 aspeed_soc_get_irq(s, ASPEED_DEV_GPIO)); 886 887 /* RTC */ 888 if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) { 889 return; 890 } 891 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_RTC]); 892 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, 893 aspeed_soc_get_irq(s, ASPEED_DEV_RTC)); 894 895 /* SDHCI */ 896 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) { 897 return; 898 } 899 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdhci), 0, 900 sc->memmap[ASPEED_DEV_SDHCI]); 901 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, 902 aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI)); 903 904 /* eMMC */ 905 if (!sysbus_realize(SYS_BUS_DEVICE(&s->emmc), errp)) { 906 return; 907 } 908 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->emmc), 0, 909 sc->memmap[ASPEED_DEV_EMMC]); 910 sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0, 911 aspeed_soc_get_irq(s, ASPEED_DEV_EMMC)); 912 913 /* Timer */ 914 object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu), 915 &error_abort); 916 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) { 917 return; 918 } 919 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->timerctrl), 0, 920 sc->memmap[ASPEED_DEV_TIMER1]); 921 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) { 922 irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i); 923 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); 924 } 925 926 /* HACE */ 927 object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(s->dram_mr), 928 &error_abort); 929 if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) { 930 return; 931 } 932 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->hace), 0, 933 sc->memmap[ASPEED_DEV_HACE]); 934 sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0, 935 aspeed_soc_get_irq(s, ASPEED_DEV_HACE)); 936 937 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->dpmcu), 938 "aspeed.dpmcu", 939 sc->memmap[ASPEED_DEV_DPMCU], 940 AST2700_SOC_DPMCU_SIZE); 941 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->ltpi), 942 "aspeed.ltpi", 943 sc->memmap[ASPEED_DEV_LTPI], 944 AST2700_SOC_LTPI_SIZE); 945 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem), 946 "aspeed.io", 947 sc->memmap[ASPEED_DEV_IOMEM], 948 AST2700_SOC_IO_SIZE); 949 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem0), 950 "aspeed.iomem0", 951 sc->memmap[ASPEED_DEV_IOMEM0], 952 AST2700_SOC_IOMEM_SIZE); 953 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem1), 954 "aspeed.iomem1", 955 sc->memmap[ASPEED_DEV_IOMEM1], 956 AST2700_SOC_IOMEM_SIZE); 957 } 958 959 static void aspeed_soc_ast2700a0_class_init(ObjectClass *oc, const void *data) 960 { 961 static const char * const valid_cpu_types[] = { 962 ARM_CPU_TYPE_NAME("cortex-a35"), 963 NULL 964 }; 965 DeviceClass *dc = DEVICE_CLASS(oc); 966 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); 967 968 /* Reason: The Aspeed SoC can only be instantiated from a board */ 969 dc->user_creatable = false; 970 dc->realize = aspeed_soc_ast2700_realize; 971 972 sc->valid_cpu_types = valid_cpu_types; 973 sc->silicon_rev = AST2700_A0_SILICON_REV; 974 sc->sram_size = 0x20000; 975 sc->spis_num = 3; 976 sc->ehcis_num = 2; 977 sc->wdts_num = 8; 978 sc->macs_num = 1; 979 sc->uarts_num = 13; 980 sc->num_cpus = 4; 981 sc->uarts_base = ASPEED_DEV_UART0; 982 sc->irqmap = aspeed_soc_ast2700a0_irqmap; 983 sc->memmap = aspeed_soc_ast2700_memmap; 984 sc->get_irq = aspeed_soc_ast2700_get_irq; 985 } 986 987 static void aspeed_soc_ast2700a1_class_init(ObjectClass *oc, const void *data) 988 { 989 static const char * const valid_cpu_types[] = { 990 ARM_CPU_TYPE_NAME("cortex-a35"), 991 NULL 992 }; 993 DeviceClass *dc = DEVICE_CLASS(oc); 994 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); 995 996 /* Reason: The Aspeed SoC can only be instantiated from a board */ 997 dc->user_creatable = false; 998 dc->realize = aspeed_soc_ast2700_realize; 999 1000 sc->valid_cpu_types = valid_cpu_types; 1001 sc->silicon_rev = AST2700_A1_SILICON_REV; 1002 sc->sram_size = 0x20000; 1003 sc->spis_num = 3; 1004 sc->ehcis_num = 4; 1005 sc->wdts_num = 8; 1006 sc->macs_num = 3; 1007 sc->uarts_num = 13; 1008 sc->num_cpus = 4; 1009 sc->uarts_base = ASPEED_DEV_UART0; 1010 sc->irqmap = aspeed_soc_ast2700a1_irqmap; 1011 sc->memmap = aspeed_soc_ast2700_memmap; 1012 sc->get_irq = aspeed_soc_ast2700_get_irq; 1013 } 1014 1015 static const TypeInfo aspeed_soc_ast27x0_types[] = { 1016 { 1017 .name = TYPE_ASPEED27X0_SOC, 1018 .parent = TYPE_ASPEED_SOC, 1019 .instance_size = sizeof(Aspeed27x0SoCState), 1020 .abstract = true, 1021 }, { 1022 .name = "ast2700-a0", 1023 .parent = TYPE_ASPEED27X0_SOC, 1024 .instance_init = aspeed_soc_ast2700_init, 1025 .class_init = aspeed_soc_ast2700a0_class_init, 1026 }, 1027 { 1028 .name = "ast2700-a1", 1029 .parent = TYPE_ASPEED27X0_SOC, 1030 .instance_init = aspeed_soc_ast2700_init, 1031 .class_init = aspeed_soc_ast2700a1_class_init, 1032 }, 1033 }; 1034 1035 DEFINE_TYPES(aspeed_soc_ast27x0_types) 1036