1 /* 2 * ASPEED SoC 27x0 family 3 * 4 * Copyright (C) 2024 ASPEED Technology Inc. 5 * 6 * This code is licensed under the GPL version 2 or later. See 7 * the COPYING file in the top-level directory. 8 * 9 * Implementation extracted from the AST2600 and adapted for AST27x0. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qapi/error.h" 14 #include "hw/misc/unimp.h" 15 #include "hw/arm/aspeed_soc.h" 16 #include "hw/arm/bsa.h" 17 #include "qemu/module.h" 18 #include "qemu/error-report.h" 19 #include "hw/i2c/aspeed_i2c.h" 20 #include "net/net.h" 21 #include "system/system.h" 22 #include "hw/intc/arm_gicv3.h" 23 #include "qobject/qlist.h" 24 #include "qemu/log.h" 25 26 static const hwaddr aspeed_soc_ast2700_memmap[] = { 27 [ASPEED_DEV_SPI_BOOT] = 0x100000000, 28 [ASPEED_DEV_SRAM] = 0x10000000, 29 [ASPEED_DEV_SDMC] = 0x12C00000, 30 [ASPEED_DEV_SCU] = 0x12C02000, 31 [ASPEED_DEV_SCUIO] = 0x14C02000, 32 [ASPEED_DEV_UART0] = 0X14C33000, 33 [ASPEED_DEV_UART1] = 0X14C33100, 34 [ASPEED_DEV_UART2] = 0X14C33200, 35 [ASPEED_DEV_UART3] = 0X14C33300, 36 [ASPEED_DEV_UART4] = 0X12C1A000, 37 [ASPEED_DEV_UART5] = 0X14C33400, 38 [ASPEED_DEV_UART6] = 0X14C33500, 39 [ASPEED_DEV_UART7] = 0X14C33600, 40 [ASPEED_DEV_UART8] = 0X14C33700, 41 [ASPEED_DEV_UART9] = 0X14C33800, 42 [ASPEED_DEV_UART10] = 0X14C33900, 43 [ASPEED_DEV_UART11] = 0X14C33A00, 44 [ASPEED_DEV_UART12] = 0X14C33B00, 45 [ASPEED_DEV_WDT] = 0x14C37000, 46 [ASPEED_DEV_VUART] = 0X14C30000, 47 [ASPEED_DEV_FMC] = 0x14000000, 48 [ASPEED_DEV_SPI0] = 0x14010000, 49 [ASPEED_DEV_SPI1] = 0x14020000, 50 [ASPEED_DEV_SPI2] = 0x14030000, 51 [ASPEED_DEV_SDRAM] = 0x400000000, 52 [ASPEED_DEV_MII1] = 0x14040000, 53 [ASPEED_DEV_MII2] = 0x14040008, 54 [ASPEED_DEV_MII3] = 0x14040010, 55 [ASPEED_DEV_ETH1] = 0x14050000, 56 [ASPEED_DEV_ETH2] = 0x14060000, 57 [ASPEED_DEV_ETH3] = 0x14070000, 58 [ASPEED_DEV_EMMC] = 0x12090000, 59 [ASPEED_DEV_INTC] = 0x12100000, 60 [ASPEED_DEV_SLI] = 0x12C17000, 61 [ASPEED_DEV_SLIIO] = 0x14C1E000, 62 [ASPEED_GIC_DIST] = 0x12200000, 63 [ASPEED_GIC_REDIST] = 0x12280000, 64 [ASPEED_DEV_ADC] = 0x14C00000, 65 [ASPEED_DEV_I2C] = 0x14C0F000, 66 [ASPEED_DEV_GPIO] = 0x14C0B000, 67 [ASPEED_DEV_RTC] = 0x12C0F000, 68 [ASPEED_DEV_SDHCI] = 0x14080000, 69 [ASPEED_DEV_TIMER1] = 0x12C10000, 70 [ASPEED_DEV_HACE] = 0x12070000, 71 }; 72 73 #define AST2700_MAX_IRQ 256 74 75 /* Shared Peripheral Interrupt values below are offset by -32 from datasheet */ 76 static const int aspeed_soc_ast2700a0_irqmap[] = { 77 [ASPEED_DEV_SDMC] = 0, 78 [ASPEED_DEV_HACE] = 4, 79 [ASPEED_DEV_XDMA] = 5, 80 [ASPEED_DEV_UART4] = 8, 81 [ASPEED_DEV_SCU] = 12, 82 [ASPEED_DEV_RTC] = 13, 83 [ASPEED_DEV_EMMC] = 15, 84 [ASPEED_DEV_TIMER1] = 16, 85 [ASPEED_DEV_TIMER2] = 17, 86 [ASPEED_DEV_TIMER3] = 18, 87 [ASPEED_DEV_TIMER4] = 19, 88 [ASPEED_DEV_TIMER5] = 20, 89 [ASPEED_DEV_TIMER6] = 21, 90 [ASPEED_DEV_TIMER7] = 22, 91 [ASPEED_DEV_TIMER8] = 23, 92 [ASPEED_DEV_DP] = 28, 93 [ASPEED_DEV_LPC] = 128, 94 [ASPEED_DEV_IBT] = 128, 95 [ASPEED_DEV_KCS] = 128, 96 [ASPEED_DEV_ADC] = 130, 97 [ASPEED_DEV_GPIO] = 130, 98 [ASPEED_DEV_I2C] = 130, 99 [ASPEED_DEV_FMC] = 131, 100 [ASPEED_DEV_WDT] = 131, 101 [ASPEED_DEV_PWM] = 131, 102 [ASPEED_DEV_I3C] = 131, 103 [ASPEED_DEV_UART0] = 132, 104 [ASPEED_DEV_UART1] = 132, 105 [ASPEED_DEV_UART2] = 132, 106 [ASPEED_DEV_UART3] = 132, 107 [ASPEED_DEV_UART5] = 132, 108 [ASPEED_DEV_UART6] = 132, 109 [ASPEED_DEV_UART7] = 132, 110 [ASPEED_DEV_UART8] = 132, 111 [ASPEED_DEV_UART9] = 132, 112 [ASPEED_DEV_UART10] = 132, 113 [ASPEED_DEV_UART11] = 132, 114 [ASPEED_DEV_UART12] = 132, 115 [ASPEED_DEV_ETH1] = 132, 116 [ASPEED_DEV_ETH2] = 132, 117 [ASPEED_DEV_ETH3] = 132, 118 [ASPEED_DEV_PECI] = 133, 119 [ASPEED_DEV_SDHCI] = 133, 120 }; 121 122 /* GICINT 128 */ 123 /* GICINT 192 */ 124 static const int ast2700_gic128_gic192_intcmap[] = { 125 [ASPEED_DEV_LPC] = 0, 126 [ASPEED_DEV_IBT] = 2, 127 [ASPEED_DEV_KCS] = 4, 128 }; 129 130 /* GICINT 129 */ 131 /* GICINT 193 */ 132 133 /* GICINT 130 */ 134 /* GICINT 194 */ 135 static const int ast2700_gic130_gic194_intcmap[] = { 136 [ASPEED_DEV_I2C] = 0, 137 [ASPEED_DEV_ADC] = 16, 138 [ASPEED_DEV_GPIO] = 18, 139 }; 140 141 /* GICINT 131 */ 142 /* GICINT 195 */ 143 static const int ast2700_gic131_gic195_intcmap[] = { 144 [ASPEED_DEV_I3C] = 0, 145 [ASPEED_DEV_WDT] = 16, 146 [ASPEED_DEV_FMC] = 25, 147 [ASPEED_DEV_PWM] = 29, 148 }; 149 150 /* GICINT 132 */ 151 /* GICINT 196 */ 152 static const int ast2700_gic132_gic196_intcmap[] = { 153 [ASPEED_DEV_ETH1] = 0, 154 [ASPEED_DEV_ETH2] = 1, 155 [ASPEED_DEV_ETH3] = 2, 156 [ASPEED_DEV_UART0] = 7, 157 [ASPEED_DEV_UART1] = 8, 158 [ASPEED_DEV_UART2] = 9, 159 [ASPEED_DEV_UART3] = 10, 160 [ASPEED_DEV_UART5] = 11, 161 [ASPEED_DEV_UART6] = 12, 162 [ASPEED_DEV_UART7] = 13, 163 [ASPEED_DEV_UART8] = 14, 164 [ASPEED_DEV_UART9] = 15, 165 [ASPEED_DEV_UART10] = 16, 166 [ASPEED_DEV_UART11] = 17, 167 [ASPEED_DEV_UART12] = 18, 168 }; 169 170 /* GICINT 133 */ 171 /* GICINT 197 */ 172 static const int ast2700_gic133_gic197_intcmap[] = { 173 [ASPEED_DEV_SDHCI] = 1, 174 [ASPEED_DEV_PECI] = 4, 175 }; 176 177 /* GICINT 128 ~ 136 */ 178 /* GICINT 192 ~ 201 */ 179 struct gic_intc_irq_info { 180 int irq; 181 const int *ptr; 182 }; 183 184 static const struct gic_intc_irq_info ast2700_gic_intcmap[] = { 185 {128, ast2700_gic128_gic192_intcmap}, 186 {129, NULL}, 187 {130, ast2700_gic130_gic194_intcmap}, 188 {131, ast2700_gic131_gic195_intcmap}, 189 {132, ast2700_gic132_gic196_intcmap}, 190 {133, ast2700_gic133_gic197_intcmap}, 191 {134, NULL}, 192 {135, NULL}, 193 {136, NULL}, 194 }; 195 196 static qemu_irq aspeed_soc_ast2700_get_irq(AspeedSoCState *s, int dev) 197 { 198 Aspeed27x0SoCState *a = ASPEED27X0_SOC(s); 199 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 200 int i; 201 202 for (i = 0; i < ARRAY_SIZE(ast2700_gic_intcmap); i++) { 203 if (sc->irqmap[dev] == ast2700_gic_intcmap[i].irq) { 204 assert(ast2700_gic_intcmap[i].ptr); 205 return qdev_get_gpio_in(DEVICE(&a->intc.orgates[i]), 206 ast2700_gic_intcmap[i].ptr[dev]); 207 } 208 } 209 210 return qdev_get_gpio_in(DEVICE(&a->gic), sc->irqmap[dev]); 211 } 212 213 static qemu_irq aspeed_soc_ast2700_get_irq_index(AspeedSoCState *s, int dev, 214 int index) 215 { 216 Aspeed27x0SoCState *a = ASPEED27X0_SOC(s); 217 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 218 int i; 219 220 for (i = 0; i < ARRAY_SIZE(ast2700_gic_intcmap); i++) { 221 if (sc->irqmap[dev] == ast2700_gic_intcmap[i].irq) { 222 assert(ast2700_gic_intcmap[i].ptr); 223 return qdev_get_gpio_in(DEVICE(&a->intc.orgates[i]), 224 ast2700_gic_intcmap[i].ptr[dev] + index); 225 } 226 } 227 228 /* 229 * Invalid OR gate index, device IRQ should be between 128 to 136 230 * and 192 to 201. 231 */ 232 g_assert_not_reached(); 233 } 234 235 static uint64_t aspeed_ram_capacity_read(void *opaque, hwaddr addr, 236 unsigned int size) 237 { 238 qemu_log_mask(LOG_GUEST_ERROR, 239 "%s: DRAM read out of ram size, addr:0x%" PRIx64 "\n", 240 __func__, addr); 241 return 0; 242 } 243 244 static void aspeed_ram_capacity_write(void *opaque, hwaddr addr, uint64_t data, 245 unsigned int size) 246 { 247 AspeedSoCState *s = ASPEED_SOC(opaque); 248 ram_addr_t ram_size; 249 MemTxResult result; 250 251 ram_size = object_property_get_uint(OBJECT(&s->sdmc), "ram-size", 252 &error_abort); 253 254 assert(ram_size > 0); 255 256 /* 257 * Emulate ddr capacity hardware behavior. 258 * If writes the data to the address which is beyond the ram size, 259 * it would write the data to the "address % ram_size". 260 */ 261 result = address_space_write(&s->dram_as, addr % ram_size, 262 MEMTXATTRS_UNSPECIFIED, &data, 4); 263 if (result != MEMTX_OK) { 264 qemu_log_mask(LOG_GUEST_ERROR, 265 "%s: DRAM write failed, addr:0x%" HWADDR_PRIx 266 ", data :0x%" PRIx64 "\n", 267 __func__, addr % ram_size, data); 268 } 269 } 270 271 static const MemoryRegionOps aspeed_ram_capacity_ops = { 272 .read = aspeed_ram_capacity_read, 273 .write = aspeed_ram_capacity_write, 274 .endianness = DEVICE_LITTLE_ENDIAN, 275 .valid = { 276 .min_access_size = 1, 277 .max_access_size = 8, 278 }, 279 }; 280 281 /* 282 * SDMC should be realized first to get correct RAM size and max size 283 * values 284 */ 285 static bool aspeed_soc_ast2700_dram_init(DeviceState *dev, Error **errp) 286 { 287 ram_addr_t ram_size, max_ram_size; 288 Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev); 289 AspeedSoCState *s = ASPEED_SOC(dev); 290 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 291 292 ram_size = object_property_get_uint(OBJECT(&s->sdmc), "ram-size", 293 &error_abort); 294 max_ram_size = object_property_get_uint(OBJECT(&s->sdmc), "max-ram-size", 295 &error_abort); 296 297 memory_region_init(&s->dram_container, OBJECT(s), "ram-container", 298 ram_size); 299 memory_region_add_subregion(&s->dram_container, 0, s->dram_mr); 300 address_space_init(&s->dram_as, s->dram_mr, "dram"); 301 302 /* 303 * Add a memory region beyond the RAM region to emulate 304 * ddr capacity hardware behavior. 305 */ 306 if (ram_size < max_ram_size) { 307 memory_region_init_io(&a->dram_empty, OBJECT(s), 308 &aspeed_ram_capacity_ops, s, 309 "ram-empty", max_ram_size - ram_size); 310 311 memory_region_add_subregion(s->memory, 312 sc->memmap[ASPEED_DEV_SDRAM] + ram_size, 313 &a->dram_empty); 314 } 315 316 memory_region_add_subregion(s->memory, 317 sc->memmap[ASPEED_DEV_SDRAM], &s->dram_container); 318 return true; 319 } 320 321 static void aspeed_soc_ast2700_init(Object *obj) 322 { 323 Aspeed27x0SoCState *a = ASPEED27X0_SOC(obj); 324 AspeedSoCState *s = ASPEED_SOC(obj); 325 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 326 int i; 327 char socname[8]; 328 char typename[64]; 329 330 if (sscanf(object_get_typename(obj), "%7s", socname) != 1) { 331 g_assert_not_reached(); 332 } 333 334 for (i = 0; i < sc->num_cpus; i++) { 335 object_initialize_child(obj, "cpu[*]", &a->cpu[i], 336 aspeed_soc_cpu_type(sc)); 337 } 338 339 object_initialize_child(obj, "gic", &a->gic, gicv3_class_name()); 340 341 object_initialize_child(obj, "scu", &s->scu, TYPE_ASPEED_2700_SCU); 342 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", 343 sc->silicon_rev); 344 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), 345 "hw-strap1"); 346 object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu), 347 "hw-prot-key"); 348 349 object_initialize_child(obj, "scuio", &s->scuio, TYPE_ASPEED_2700_SCUIO); 350 qdev_prop_set_uint32(DEVICE(&s->scuio), "silicon-rev", 351 sc->silicon_rev); 352 /* 353 * There is one hw-strap1 register in the SCU (CPU DIE) and another 354 * hw-strap1 register in the SCUIO (IO DIE). To reuse the current design 355 * of hw-strap, hw-strap1 is assigned to the SCU and sets the value in the 356 * SCU hw-strap1 register, while hw-strap2 is assigned to the SCUIO and 357 * sets the value in the SCUIO hw-strap1 register. 358 */ 359 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scuio), 360 "hw-strap1"); 361 362 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); 363 object_initialize_child(obj, "fmc", &s->fmc, typename); 364 365 for (i = 0; i < sc->spis_num; i++) { 366 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i, socname); 367 object_initialize_child(obj, "spi[*]", &s->spi[i], typename); 368 } 369 370 snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname); 371 object_initialize_child(obj, "sdmc", &s->sdmc, typename); 372 object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), 373 "ram-size"); 374 375 for (i = 0; i < sc->wdts_num; i++) { 376 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); 377 object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename); 378 } 379 380 for (i = 0; i < sc->macs_num; i++) { 381 object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i], 382 TYPE_FTGMAC100); 383 384 object_initialize_child(obj, "mii[*]", &s->mii[i], TYPE_ASPEED_MII); 385 } 386 387 for (i = 0; i < sc->uarts_num; i++) { 388 object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM); 389 } 390 391 object_initialize_child(obj, "sli", &s->sli, TYPE_ASPEED_2700_SLI); 392 object_initialize_child(obj, "sliio", &s->sliio, TYPE_ASPEED_2700_SLIIO); 393 object_initialize_child(obj, "intc", &a->intc, TYPE_ASPEED_2700_INTC); 394 395 snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname); 396 object_initialize_child(obj, "adc", &s->adc, typename); 397 398 snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); 399 object_initialize_child(obj, "i2c", &s->i2c, typename); 400 401 snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); 402 object_initialize_child(obj, "gpio", &s->gpio, typename); 403 404 object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC); 405 406 snprintf(typename, sizeof(typename), "aspeed.sdhci-%s", socname); 407 object_initialize_child(obj, "sd-controller", &s->sdhci, typename); 408 object_property_set_int(OBJECT(&s->sdhci), "num-slots", 1, &error_abort); 409 410 /* Init sd card slot class here so that they're under the correct parent */ 411 object_initialize_child(obj, "sd-controller.sdhci", 412 &s->sdhci.slots[0], TYPE_SYSBUS_SDHCI); 413 414 object_initialize_child(obj, "emmc-controller", &s->emmc, typename); 415 object_property_set_int(OBJECT(&s->emmc), "num-slots", 1, &error_abort); 416 417 object_initialize_child(obj, "emmc-controller.sdhci", &s->emmc.slots[0], 418 TYPE_SYSBUS_SDHCI); 419 420 snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname); 421 object_initialize_child(obj, "timerctrl", &s->timerctrl, typename); 422 423 snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname); 424 object_initialize_child(obj, "hace", &s->hace, typename); 425 } 426 427 /* 428 * ASPEED ast2700 has 0x0 as cluster ID 429 * 430 * https://developer.arm.com/documentation/100236/0100/register-descriptions/aarch64-system-registers/multiprocessor-affinity-register--el1 431 */ 432 static uint64_t aspeed_calc_affinity(int cpu) 433 { 434 return (0x0 << ARM_AFF1_SHIFT) | cpu; 435 } 436 437 static bool aspeed_soc_ast2700_gic_realize(DeviceState *dev, Error **errp) 438 { 439 Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev); 440 AspeedSoCState *s = ASPEED_SOC(dev); 441 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 442 SysBusDevice *gicbusdev; 443 DeviceState *gicdev; 444 QList *redist_region_count; 445 int i; 446 447 gicbusdev = SYS_BUS_DEVICE(&a->gic); 448 gicdev = DEVICE(&a->gic); 449 qdev_prop_set_uint32(gicdev, "revision", 3); 450 qdev_prop_set_uint32(gicdev, "num-cpu", sc->num_cpus); 451 qdev_prop_set_uint32(gicdev, "num-irq", AST2700_MAX_IRQ + GIC_INTERNAL); 452 453 redist_region_count = qlist_new(); 454 qlist_append_int(redist_region_count, sc->num_cpus); 455 qdev_prop_set_array(gicdev, "redist-region-count", redist_region_count); 456 457 if (!sysbus_realize(gicbusdev, errp)) { 458 return false; 459 } 460 sysbus_mmio_map(gicbusdev, 0, sc->memmap[ASPEED_GIC_DIST]); 461 sysbus_mmio_map(gicbusdev, 1, sc->memmap[ASPEED_GIC_REDIST]); 462 463 for (i = 0; i < sc->num_cpus; i++) { 464 DeviceState *cpudev = DEVICE(&a->cpu[i]); 465 int intidbase = AST2700_MAX_IRQ + i * GIC_INTERNAL; 466 467 const int timer_irq[] = { 468 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, 469 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, 470 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, 471 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, 472 }; 473 int j; 474 475 for (j = 0; j < ARRAY_SIZE(timer_irq); j++) { 476 qdev_connect_gpio_out(cpudev, j, 477 qdev_get_gpio_in(gicdev, intidbase + timer_irq[j])); 478 } 479 480 qemu_irq irq = qdev_get_gpio_in(gicdev, 481 intidbase + ARCH_GIC_MAINT_IRQ); 482 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 483 0, irq); 484 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, 485 qdev_get_gpio_in(gicdev, intidbase + VIRTUAL_PMU_IRQ)); 486 487 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 488 sysbus_connect_irq(gicbusdev, i + sc->num_cpus, 489 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 490 sysbus_connect_irq(gicbusdev, i + 2 * sc->num_cpus, 491 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 492 sysbus_connect_irq(gicbusdev, i + 3 * sc->num_cpus, 493 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 494 sysbus_connect_irq(gicbusdev, i + 4 * sc->num_cpus, 495 qdev_get_gpio_in(cpudev, ARM_CPU_NMI)); 496 sysbus_connect_irq(gicbusdev, i + 5 * sc->num_cpus, 497 qdev_get_gpio_in(cpudev, ARM_CPU_VINMI)); 498 } 499 500 return true; 501 } 502 503 static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp) 504 { 505 int i; 506 Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev); 507 AspeedSoCState *s = ASPEED_SOC(dev); 508 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 509 AspeedINTCClass *ic = ASPEED_INTC_GET_CLASS(&a->intc); 510 g_autofree char *sram_name = NULL; 511 qemu_irq irq; 512 513 /* Default boot region (SPI memory or ROMs) */ 514 memory_region_init(&s->spi_boot_container, OBJECT(s), 515 "aspeed.spi_boot_container", 0x400000000); 516 memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SPI_BOOT], 517 &s->spi_boot_container); 518 519 /* CPU */ 520 for (i = 0; i < sc->num_cpus; i++) { 521 object_property_set_int(OBJECT(&a->cpu[i]), "mp-affinity", 522 aspeed_calc_affinity(i), &error_abort); 523 524 object_property_set_int(OBJECT(&a->cpu[i]), "cntfrq", 1125000000, 525 &error_abort); 526 object_property_set_link(OBJECT(&a->cpu[i]), "memory", 527 OBJECT(s->memory), &error_abort); 528 529 if (!qdev_realize(DEVICE(&a->cpu[i]), NULL, errp)) { 530 return; 531 } 532 } 533 534 /* GIC */ 535 if (!aspeed_soc_ast2700_gic_realize(dev, errp)) { 536 return; 537 } 538 539 /* INTC */ 540 if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc), errp)) { 541 return; 542 } 543 544 aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc), 0, 545 sc->memmap[ASPEED_DEV_INTC]); 546 547 /* irq sources -> orgates -> INTC */ 548 for (i = 0; i < ic->num_inpins; i++) { 549 qdev_connect_gpio_out(DEVICE(&a->intc.orgates[i]), 0, 550 qdev_get_gpio_in(DEVICE(&a->intc), i)); 551 } 552 553 /* INTC -> GIC192 - GIC201 */ 554 /* INTC -> GIC128 - GIC136 */ 555 for (i = 0; i < ic->num_outpins; i++) { 556 sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc), i, 557 qdev_get_gpio_in(DEVICE(&a->gic), 558 ast2700_gic_intcmap[i].irq)); 559 } 560 561 /* SRAM */ 562 sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index); 563 if (!memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, 564 errp)) { 565 return; 566 } 567 memory_region_add_subregion(s->memory, 568 sc->memmap[ASPEED_DEV_SRAM], &s->sram); 569 570 /* SCU */ 571 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { 572 return; 573 } 574 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]); 575 576 /* SCU1 */ 577 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scuio), errp)) { 578 return; 579 } 580 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scuio), 0, 581 sc->memmap[ASPEED_DEV_SCUIO]); 582 583 /* UART */ 584 if (!aspeed_soc_uart_realize(s, errp)) { 585 return; 586 } 587 588 /* FMC, The number of CS is set at the board level */ 589 object_property_set_int(OBJECT(&s->fmc), "dram-base", 590 sc->memmap[ASPEED_DEV_SDRAM], 591 &error_abort); 592 object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr), 593 &error_abort); 594 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) { 595 return; 596 } 597 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]); 598 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 1, 599 ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base); 600 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, 601 aspeed_soc_get_irq(s, ASPEED_DEV_FMC)); 602 603 /* Set up an alias on the FMC CE0 region (boot default) */ 604 MemoryRegion *fmc0_mmio = &s->fmc.flashes[0].mmio; 605 memory_region_init_alias(&s->spi_boot, OBJECT(s), "aspeed.spi_boot", 606 fmc0_mmio, 0, memory_region_size(fmc0_mmio)); 607 memory_region_add_subregion(&s->spi_boot_container, 0x0, &s->spi_boot); 608 609 /* SPI */ 610 for (i = 0; i < sc->spis_num; i++) { 611 object_property_set_link(OBJECT(&s->spi[i]), "dram", 612 OBJECT(s->dram_mr), &error_abort); 613 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { 614 return; 615 } 616 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 0, 617 sc->memmap[ASPEED_DEV_SPI0 + i]); 618 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 1, 619 ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base); 620 } 621 622 /* 623 * SDMC - SDRAM Memory Controller 624 * The SDMC controller is unlocked at SPL stage. 625 * At present, only supports to emulate booting 626 * start from u-boot stage. Set SDMC controller 627 * unlocked by default. It is a temporarily solution. 628 */ 629 object_property_set_bool(OBJECT(&s->sdmc), "unlocked", true, 630 &error_abort); 631 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) { 632 return; 633 } 634 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdmc), 0, 635 sc->memmap[ASPEED_DEV_SDMC]); 636 637 /* RAM */ 638 if (!aspeed_soc_ast2700_dram_init(dev, errp)) { 639 return; 640 } 641 642 /* Net */ 643 for (i = 0; i < sc->macs_num; i++) { 644 object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true, 645 &error_abort); 646 object_property_set_bool(OBJECT(&s->ftgmac100[i]), "dma64", true, 647 &error_abort); 648 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) { 649 return; 650 } 651 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 652 sc->memmap[ASPEED_DEV_ETH1 + i]); 653 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 654 aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i)); 655 656 object_property_set_link(OBJECT(&s->mii[i]), "nic", 657 OBJECT(&s->ftgmac100[i]), &error_abort); 658 if (!sysbus_realize(SYS_BUS_DEVICE(&s->mii[i]), errp)) { 659 return; 660 } 661 662 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->mii[i]), 0, 663 sc->memmap[ASPEED_DEV_MII1 + i]); 664 } 665 666 /* Watch dog */ 667 for (i = 0; i < sc->wdts_num; i++) { 668 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); 669 hwaddr wdt_offset = sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize; 670 671 object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu), 672 &error_abort); 673 if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) { 674 return; 675 } 676 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offset); 677 } 678 679 /* SLI */ 680 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sli), errp)) { 681 return; 682 } 683 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sli), 0, sc->memmap[ASPEED_DEV_SLI]); 684 685 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sliio), errp)) { 686 return; 687 } 688 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sliio), 0, 689 sc->memmap[ASPEED_DEV_SLIIO]); 690 691 /* ADC */ 692 if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) { 693 return; 694 } 695 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]); 696 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0, 697 aspeed_soc_get_irq(s, ASPEED_DEV_ADC)); 698 699 /* I2C */ 700 object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr), 701 &error_abort); 702 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) { 703 return; 704 } 705 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]); 706 for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) { 707 /* 708 * The AST2700 I2C controller has one source INTC per bus. 709 * 710 * For AST2700 A0: 711 * I2C bus interrupts are connected to the OR gate from bit 0 to bit 712 * 15, and the OR gate output pin is connected to the input pin of 713 * GICINT130 of INTC (CPU Die). Then, the output pin is connected to 714 * the GIC. 715 * 716 * For AST2700 A1: 717 * I2C bus interrupts are connected to the OR gate from bit 0 to bit 718 * 15, and the OR gate output pin is connected to the input pin of 719 * GICINT194 of INTCIO (IO Die). Then, the output pin is connected 720 * to the INTC (CPU Die) input pin, and its output pin is connected 721 * to the GIC. 722 * 723 * I2C bus 0 is connected to the OR gate at bit 0. 724 * I2C bus 15 is connected to the OR gate at bit 15. 725 */ 726 irq = aspeed_soc_ast2700_get_irq_index(s, ASPEED_DEV_I2C, i); 727 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq); 728 } 729 730 /* GPIO */ 731 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { 732 return; 733 } 734 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio), 0, 735 sc->memmap[ASPEED_DEV_GPIO]); 736 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, 737 aspeed_soc_get_irq(s, ASPEED_DEV_GPIO)); 738 739 /* RTC */ 740 if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) { 741 return; 742 } 743 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_RTC]); 744 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, 745 aspeed_soc_get_irq(s, ASPEED_DEV_RTC)); 746 747 /* SDHCI */ 748 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) { 749 return; 750 } 751 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdhci), 0, 752 sc->memmap[ASPEED_DEV_SDHCI]); 753 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, 754 aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI)); 755 756 /* eMMC */ 757 if (!sysbus_realize(SYS_BUS_DEVICE(&s->emmc), errp)) { 758 return; 759 } 760 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->emmc), 0, 761 sc->memmap[ASPEED_DEV_EMMC]); 762 sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0, 763 aspeed_soc_get_irq(s, ASPEED_DEV_EMMC)); 764 765 /* Timer */ 766 object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu), 767 &error_abort); 768 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) { 769 return; 770 } 771 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->timerctrl), 0, 772 sc->memmap[ASPEED_DEV_TIMER1]); 773 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) { 774 irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i); 775 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); 776 } 777 778 /* HACE */ 779 object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(s->dram_mr), 780 &error_abort); 781 if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) { 782 return; 783 } 784 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->hace), 0, 785 sc->memmap[ASPEED_DEV_HACE]); 786 sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0, 787 aspeed_soc_get_irq(s, ASPEED_DEV_HACE)); 788 789 create_unimplemented_device("ast2700.dpmcu", 0x11000000, 0x40000); 790 create_unimplemented_device("ast2700.iomem0", 0x12000000, 0x01000000); 791 create_unimplemented_device("ast2700.iomem1", 0x14000000, 0x01000000); 792 create_unimplemented_device("ast2700.ltpi", 0x30000000, 0x1000000); 793 create_unimplemented_device("ast2700.io", 0x0, 0x4000000); 794 } 795 796 static void aspeed_soc_ast2700a0_class_init(ObjectClass *oc, void *data) 797 { 798 static const char * const valid_cpu_types[] = { 799 ARM_CPU_TYPE_NAME("cortex-a35"), 800 NULL 801 }; 802 DeviceClass *dc = DEVICE_CLASS(oc); 803 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); 804 805 /* Reason: The Aspeed SoC can only be instantiated from a board */ 806 dc->user_creatable = false; 807 dc->realize = aspeed_soc_ast2700_realize; 808 809 sc->valid_cpu_types = valid_cpu_types; 810 sc->silicon_rev = AST2700_A0_SILICON_REV; 811 sc->sram_size = 0x20000; 812 sc->spis_num = 3; 813 sc->wdts_num = 8; 814 sc->macs_num = 1; 815 sc->uarts_num = 13; 816 sc->num_cpus = 4; 817 sc->uarts_base = ASPEED_DEV_UART0; 818 sc->irqmap = aspeed_soc_ast2700a0_irqmap; 819 sc->memmap = aspeed_soc_ast2700_memmap; 820 sc->get_irq = aspeed_soc_ast2700_get_irq; 821 } 822 823 static const TypeInfo aspeed_soc_ast27x0_types[] = { 824 { 825 .name = TYPE_ASPEED27X0_SOC, 826 .parent = TYPE_ASPEED_SOC, 827 .instance_size = sizeof(Aspeed27x0SoCState), 828 .abstract = true, 829 }, { 830 .name = "ast2700-a0", 831 .parent = TYPE_ASPEED27X0_SOC, 832 .instance_init = aspeed_soc_ast2700_init, 833 .class_init = aspeed_soc_ast2700a0_class_init, 834 }, 835 }; 836 837 DEFINE_TYPES(aspeed_soc_ast27x0_types) 838