1 /* 2 * ASPEED SoC 27x0 family 3 * 4 * Copyright (C) 2024 ASPEED Technology Inc. 5 * 6 * This code is licensed under the GPL version 2 or later. See 7 * the COPYING file in the top-level directory. 8 * 9 * Implementation extracted from the AST2600 and adapted for AST27x0. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qapi/error.h" 14 #include "hw/misc/unimp.h" 15 #include "hw/arm/aspeed_soc.h" 16 #include "hw/arm/bsa.h" 17 #include "qemu/module.h" 18 #include "qemu/error-report.h" 19 #include "hw/i2c/aspeed_i2c.h" 20 #include "net/net.h" 21 #include "system/system.h" 22 #include "hw/intc/arm_gicv3.h" 23 #include "qobject/qlist.h" 24 #include "qemu/log.h" 25 26 static const hwaddr aspeed_soc_ast2700_memmap[] = { 27 [ASPEED_DEV_SRAM] = 0x10000000, 28 [ASPEED_DEV_EHCI1] = 0x12061000, 29 [ASPEED_DEV_EHCI2] = 0x12063000, 30 [ASPEED_DEV_HACE] = 0x12070000, 31 [ASPEED_DEV_EMMC] = 0x12090000, 32 [ASPEED_DEV_INTC] = 0x12100000, 33 [ASPEED_GIC_DIST] = 0x12200000, 34 [ASPEED_GIC_REDIST] = 0x12280000, 35 [ASPEED_DEV_SDMC] = 0x12C00000, 36 [ASPEED_DEV_SCU] = 0x12C02000, 37 [ASPEED_DEV_RTC] = 0x12C0F000, 38 [ASPEED_DEV_TIMER1] = 0x12C10000, 39 [ASPEED_DEV_SLI] = 0x12C17000, 40 [ASPEED_DEV_UART4] = 0X12C1A000, 41 [ASPEED_DEV_FMC] = 0x14000000, 42 [ASPEED_DEV_SPI0] = 0x14010000, 43 [ASPEED_DEV_SPI1] = 0x14020000, 44 [ASPEED_DEV_SPI2] = 0x14030000, 45 [ASPEED_DEV_MII1] = 0x14040000, 46 [ASPEED_DEV_MII2] = 0x14040008, 47 [ASPEED_DEV_MII3] = 0x14040010, 48 [ASPEED_DEV_ETH1] = 0x14050000, 49 [ASPEED_DEV_ETH2] = 0x14060000, 50 [ASPEED_DEV_ETH3] = 0x14070000, 51 [ASPEED_DEV_SDHCI] = 0x14080000, 52 [ASPEED_DEV_EHCI3] = 0x14121000, 53 [ASPEED_DEV_EHCI4] = 0x14123000, 54 [ASPEED_DEV_ADC] = 0x14C00000, 55 [ASPEED_DEV_SCUIO] = 0x14C02000, 56 [ASPEED_DEV_GPIO] = 0x14C0B000, 57 [ASPEED_DEV_I2C] = 0x14C0F000, 58 [ASPEED_DEV_INTCIO] = 0x14C18000, 59 [ASPEED_DEV_SLIIO] = 0x14C1E000, 60 [ASPEED_DEV_VUART] = 0X14C30000, 61 [ASPEED_DEV_UART0] = 0X14C33000, 62 [ASPEED_DEV_UART1] = 0X14C33100, 63 [ASPEED_DEV_UART2] = 0X14C33200, 64 [ASPEED_DEV_UART3] = 0X14C33300, 65 [ASPEED_DEV_UART5] = 0X14C33400, 66 [ASPEED_DEV_UART6] = 0X14C33500, 67 [ASPEED_DEV_UART7] = 0X14C33600, 68 [ASPEED_DEV_UART8] = 0X14C33700, 69 [ASPEED_DEV_UART9] = 0X14C33800, 70 [ASPEED_DEV_UART10] = 0X14C33900, 71 [ASPEED_DEV_UART11] = 0X14C33A00, 72 [ASPEED_DEV_UART12] = 0X14C33B00, 73 [ASPEED_DEV_WDT] = 0x14C37000, 74 [ASPEED_DEV_SPI_BOOT] = 0x100000000, 75 [ASPEED_DEV_SDRAM] = 0x400000000, 76 }; 77 78 #define AST2700_MAX_IRQ 256 79 80 /* Shared Peripheral Interrupt values below are offset by -32 from datasheet */ 81 static const int aspeed_soc_ast2700a0_irqmap[] = { 82 [ASPEED_DEV_SDMC] = 0, 83 [ASPEED_DEV_HACE] = 4, 84 [ASPEED_DEV_XDMA] = 5, 85 [ASPEED_DEV_UART4] = 8, 86 [ASPEED_DEV_SCU] = 12, 87 [ASPEED_DEV_RTC] = 13, 88 [ASPEED_DEV_EMMC] = 15, 89 [ASPEED_DEV_TIMER1] = 16, 90 [ASPEED_DEV_TIMER2] = 17, 91 [ASPEED_DEV_TIMER3] = 18, 92 [ASPEED_DEV_TIMER4] = 19, 93 [ASPEED_DEV_TIMER5] = 20, 94 [ASPEED_DEV_TIMER6] = 21, 95 [ASPEED_DEV_TIMER7] = 22, 96 [ASPEED_DEV_TIMER8] = 23, 97 [ASPEED_DEV_DP] = 28, 98 [ASPEED_DEV_EHCI1] = 33, 99 [ASPEED_DEV_EHCI2] = 37, 100 [ASPEED_DEV_LPC] = 128, 101 [ASPEED_DEV_IBT] = 128, 102 [ASPEED_DEV_KCS] = 128, 103 [ASPEED_DEV_ADC] = 130, 104 [ASPEED_DEV_GPIO] = 130, 105 [ASPEED_DEV_I2C] = 130, 106 [ASPEED_DEV_FMC] = 131, 107 [ASPEED_DEV_WDT] = 131, 108 [ASPEED_DEV_PWM] = 131, 109 [ASPEED_DEV_I3C] = 131, 110 [ASPEED_DEV_UART0] = 132, 111 [ASPEED_DEV_UART1] = 132, 112 [ASPEED_DEV_UART2] = 132, 113 [ASPEED_DEV_UART3] = 132, 114 [ASPEED_DEV_UART5] = 132, 115 [ASPEED_DEV_UART6] = 132, 116 [ASPEED_DEV_UART7] = 132, 117 [ASPEED_DEV_UART8] = 132, 118 [ASPEED_DEV_UART9] = 132, 119 [ASPEED_DEV_UART10] = 132, 120 [ASPEED_DEV_UART11] = 132, 121 [ASPEED_DEV_UART12] = 132, 122 [ASPEED_DEV_ETH1] = 132, 123 [ASPEED_DEV_ETH2] = 132, 124 [ASPEED_DEV_ETH3] = 132, 125 [ASPEED_DEV_PECI] = 133, 126 [ASPEED_DEV_SDHCI] = 133, 127 }; 128 129 static const int aspeed_soc_ast2700a1_irqmap[] = { 130 [ASPEED_DEV_SDMC] = 0, 131 [ASPEED_DEV_HACE] = 4, 132 [ASPEED_DEV_XDMA] = 5, 133 [ASPEED_DEV_UART4] = 8, 134 [ASPEED_DEV_SCU] = 12, 135 [ASPEED_DEV_RTC] = 13, 136 [ASPEED_DEV_EMMC] = 15, 137 [ASPEED_DEV_TIMER1] = 16, 138 [ASPEED_DEV_TIMER2] = 17, 139 [ASPEED_DEV_TIMER3] = 18, 140 [ASPEED_DEV_TIMER4] = 19, 141 [ASPEED_DEV_TIMER5] = 20, 142 [ASPEED_DEV_TIMER6] = 21, 143 [ASPEED_DEV_TIMER7] = 22, 144 [ASPEED_DEV_TIMER8] = 23, 145 [ASPEED_DEV_DP] = 28, 146 [ASPEED_DEV_EHCI1] = 33, 147 [ASPEED_DEV_EHCI2] = 37, 148 [ASPEED_DEV_LPC] = 192, 149 [ASPEED_DEV_IBT] = 192, 150 [ASPEED_DEV_KCS] = 192, 151 [ASPEED_DEV_I2C] = 194, 152 [ASPEED_DEV_ADC] = 194, 153 [ASPEED_DEV_GPIO] = 194, 154 [ASPEED_DEV_FMC] = 195, 155 [ASPEED_DEV_WDT] = 195, 156 [ASPEED_DEV_PWM] = 195, 157 [ASPEED_DEV_I3C] = 195, 158 [ASPEED_DEV_UART0] = 196, 159 [ASPEED_DEV_UART1] = 196, 160 [ASPEED_DEV_UART2] = 196, 161 [ASPEED_DEV_UART3] = 196, 162 [ASPEED_DEV_UART5] = 196, 163 [ASPEED_DEV_UART6] = 196, 164 [ASPEED_DEV_UART7] = 196, 165 [ASPEED_DEV_UART8] = 196, 166 [ASPEED_DEV_UART9] = 196, 167 [ASPEED_DEV_UART10] = 196, 168 [ASPEED_DEV_UART11] = 196, 169 [ASPEED_DEV_UART12] = 196, 170 [ASPEED_DEV_ETH1] = 196, 171 [ASPEED_DEV_ETH2] = 196, 172 [ASPEED_DEV_ETH3] = 196, 173 [ASPEED_DEV_PECI] = 197, 174 [ASPEED_DEV_SDHCI] = 197, 175 }; 176 177 /* GICINT 128 */ 178 /* GICINT 192 */ 179 static const int ast2700_gic128_gic192_intcmap[] = { 180 [ASPEED_DEV_LPC] = 0, 181 [ASPEED_DEV_IBT] = 2, 182 [ASPEED_DEV_KCS] = 4, 183 }; 184 185 /* GICINT 129 */ 186 /* GICINT 193 */ 187 188 /* GICINT 130 */ 189 /* GICINT 194 */ 190 static const int ast2700_gic130_gic194_intcmap[] = { 191 [ASPEED_DEV_I2C] = 0, 192 [ASPEED_DEV_ADC] = 16, 193 [ASPEED_DEV_GPIO] = 18, 194 }; 195 196 /* GICINT 131 */ 197 /* GICINT 195 */ 198 static const int ast2700_gic131_gic195_intcmap[] = { 199 [ASPEED_DEV_I3C] = 0, 200 [ASPEED_DEV_WDT] = 16, 201 [ASPEED_DEV_FMC] = 25, 202 [ASPEED_DEV_PWM] = 29, 203 }; 204 205 /* GICINT 132 */ 206 /* GICINT 196 */ 207 static const int ast2700_gic132_gic196_intcmap[] = { 208 [ASPEED_DEV_ETH1] = 0, 209 [ASPEED_DEV_ETH2] = 1, 210 [ASPEED_DEV_ETH3] = 2, 211 [ASPEED_DEV_UART0] = 7, 212 [ASPEED_DEV_UART1] = 8, 213 [ASPEED_DEV_UART2] = 9, 214 [ASPEED_DEV_UART3] = 10, 215 [ASPEED_DEV_UART5] = 11, 216 [ASPEED_DEV_UART6] = 12, 217 [ASPEED_DEV_UART7] = 13, 218 [ASPEED_DEV_UART8] = 14, 219 [ASPEED_DEV_UART9] = 15, 220 [ASPEED_DEV_UART10] = 16, 221 [ASPEED_DEV_UART11] = 17, 222 [ASPEED_DEV_UART12] = 18, 223 [ASPEED_DEV_EHCI3] = 28, 224 [ASPEED_DEV_EHCI4] = 29, 225 }; 226 227 /* GICINT 133 */ 228 /* GICINT 197 */ 229 static const int ast2700_gic133_gic197_intcmap[] = { 230 [ASPEED_DEV_SDHCI] = 1, 231 [ASPEED_DEV_PECI] = 4, 232 }; 233 234 /* GICINT 128 ~ 136 */ 235 /* GICINT 192 ~ 201 */ 236 struct gic_intc_irq_info { 237 int irq; 238 int intc_idx; 239 int orgate_idx; 240 const int *ptr; 241 }; 242 243 static const struct gic_intc_irq_info ast2700_gic_intcmap[] = { 244 {192, 1, 0, ast2700_gic128_gic192_intcmap}, 245 {193, 1, 1, NULL}, 246 {194, 1, 2, ast2700_gic130_gic194_intcmap}, 247 {195, 1, 3, ast2700_gic131_gic195_intcmap}, 248 {196, 1, 4, ast2700_gic132_gic196_intcmap}, 249 {197, 1, 5, ast2700_gic133_gic197_intcmap}, 250 {198, 1, 6, NULL}, 251 {199, 1, 7, NULL}, 252 {200, 1, 8, NULL}, 253 {201, 1, 9, NULL}, 254 {128, 0, 1, ast2700_gic128_gic192_intcmap}, 255 {129, 0, 2, NULL}, 256 {130, 0, 3, ast2700_gic130_gic194_intcmap}, 257 {131, 0, 4, ast2700_gic131_gic195_intcmap}, 258 {132, 0, 5, ast2700_gic132_gic196_intcmap}, 259 {133, 0, 6, ast2700_gic133_gic197_intcmap}, 260 {134, 0, 7, NULL}, 261 {135, 0, 8, NULL}, 262 {136, 0, 9, NULL}, 263 }; 264 265 static qemu_irq aspeed_soc_ast2700_get_irq(AspeedSoCState *s, int dev) 266 { 267 Aspeed27x0SoCState *a = ASPEED27X0_SOC(s); 268 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 269 int or_idx; 270 int idx; 271 int i; 272 273 for (i = 0; i < ARRAY_SIZE(ast2700_gic_intcmap); i++) { 274 if (sc->irqmap[dev] == ast2700_gic_intcmap[i].irq) { 275 assert(ast2700_gic_intcmap[i].ptr); 276 or_idx = ast2700_gic_intcmap[i].orgate_idx; 277 idx = ast2700_gic_intcmap[i].intc_idx; 278 return qdev_get_gpio_in(DEVICE(&a->intc[idx].orgates[or_idx]), 279 ast2700_gic_intcmap[i].ptr[dev]); 280 } 281 } 282 283 return qdev_get_gpio_in(DEVICE(&a->gic), sc->irqmap[dev]); 284 } 285 286 static qemu_irq aspeed_soc_ast2700_get_irq_index(AspeedSoCState *s, int dev, 287 int index) 288 { 289 Aspeed27x0SoCState *a = ASPEED27X0_SOC(s); 290 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 291 int or_idx; 292 int idx; 293 int i; 294 295 for (i = 0; i < ARRAY_SIZE(ast2700_gic_intcmap); i++) { 296 if (sc->irqmap[dev] == ast2700_gic_intcmap[i].irq) { 297 assert(ast2700_gic_intcmap[i].ptr); 298 or_idx = ast2700_gic_intcmap[i].orgate_idx; 299 idx = ast2700_gic_intcmap[i].intc_idx; 300 return qdev_get_gpio_in(DEVICE(&a->intc[idx].orgates[or_idx]), 301 ast2700_gic_intcmap[i].ptr[dev] + index); 302 } 303 } 304 305 /* 306 * Invalid OR gate index, device IRQ should be between 128 to 136 307 * and 192 to 201. 308 */ 309 g_assert_not_reached(); 310 } 311 312 static uint64_t aspeed_ram_capacity_read(void *opaque, hwaddr addr, 313 unsigned int size) 314 { 315 qemu_log_mask(LOG_GUEST_ERROR, 316 "%s: DRAM read out of ram size, addr:0x%" PRIx64 "\n", 317 __func__, addr); 318 return 0; 319 } 320 321 static void aspeed_ram_capacity_write(void *opaque, hwaddr addr, uint64_t data, 322 unsigned int size) 323 { 324 AspeedSoCState *s = ASPEED_SOC(opaque); 325 ram_addr_t ram_size; 326 MemTxResult result; 327 328 ram_size = object_property_get_uint(OBJECT(&s->sdmc), "ram-size", 329 &error_abort); 330 331 assert(ram_size > 0); 332 333 /* 334 * Emulate ddr capacity hardware behavior. 335 * If writes the data to the address which is beyond the ram size, 336 * it would write the data to the "address % ram_size". 337 */ 338 result = address_space_write(&s->dram_as, addr % ram_size, 339 MEMTXATTRS_UNSPECIFIED, &data, 4); 340 if (result != MEMTX_OK) { 341 qemu_log_mask(LOG_GUEST_ERROR, 342 "%s: DRAM write failed, addr:0x%" HWADDR_PRIx 343 ", data :0x%" PRIx64 "\n", 344 __func__, addr % ram_size, data); 345 } 346 } 347 348 static const MemoryRegionOps aspeed_ram_capacity_ops = { 349 .read = aspeed_ram_capacity_read, 350 .write = aspeed_ram_capacity_write, 351 .endianness = DEVICE_LITTLE_ENDIAN, 352 .valid = { 353 .min_access_size = 1, 354 .max_access_size = 8, 355 }, 356 }; 357 358 /* 359 * SDMC should be realized first to get correct RAM size and max size 360 * values 361 */ 362 static bool aspeed_soc_ast2700_dram_init(DeviceState *dev, Error **errp) 363 { 364 ram_addr_t ram_size, max_ram_size; 365 Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev); 366 AspeedSoCState *s = ASPEED_SOC(dev); 367 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 368 369 ram_size = object_property_get_uint(OBJECT(&s->sdmc), "ram-size", 370 &error_abort); 371 max_ram_size = object_property_get_uint(OBJECT(&s->sdmc), "max-ram-size", 372 &error_abort); 373 374 memory_region_init(&s->dram_container, OBJECT(s), "ram-container", 375 ram_size); 376 memory_region_add_subregion(&s->dram_container, 0, s->dram_mr); 377 address_space_init(&s->dram_as, s->dram_mr, "dram"); 378 379 /* 380 * Add a memory region beyond the RAM region to emulate 381 * ddr capacity hardware behavior. 382 */ 383 if (ram_size < max_ram_size) { 384 memory_region_init_io(&a->dram_empty, OBJECT(s), 385 &aspeed_ram_capacity_ops, s, 386 "ram-empty", max_ram_size - ram_size); 387 388 memory_region_add_subregion(s->memory, 389 sc->memmap[ASPEED_DEV_SDRAM] + ram_size, 390 &a->dram_empty); 391 } 392 393 memory_region_add_subregion(s->memory, 394 sc->memmap[ASPEED_DEV_SDRAM], &s->dram_container); 395 return true; 396 } 397 398 static void aspeed_soc_ast2700_init(Object *obj) 399 { 400 Aspeed27x0SoCState *a = ASPEED27X0_SOC(obj); 401 AspeedSoCState *s = ASPEED_SOC(obj); 402 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 403 int i; 404 char socname[8]; 405 char typename[64]; 406 407 if (sscanf(object_get_typename(obj), "%7s", socname) != 1) { 408 g_assert_not_reached(); 409 } 410 411 for (i = 0; i < sc->num_cpus; i++) { 412 object_initialize_child(obj, "cpu[*]", &a->cpu[i], 413 aspeed_soc_cpu_type(sc)); 414 } 415 416 object_initialize_child(obj, "gic", &a->gic, gicv3_class_name()); 417 418 object_initialize_child(obj, "scu", &s->scu, TYPE_ASPEED_2700_SCU); 419 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", 420 sc->silicon_rev); 421 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), 422 "hw-strap1"); 423 object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu), 424 "hw-prot-key"); 425 426 object_initialize_child(obj, "scuio", &s->scuio, TYPE_ASPEED_2700_SCUIO); 427 qdev_prop_set_uint32(DEVICE(&s->scuio), "silicon-rev", 428 sc->silicon_rev); 429 /* 430 * There is one hw-strap1 register in the SCU (CPU DIE) and another 431 * hw-strap1 register in the SCUIO (IO DIE). To reuse the current design 432 * of hw-strap, hw-strap1 is assigned to the SCU and sets the value in the 433 * SCU hw-strap1 register, while hw-strap2 is assigned to the SCUIO and 434 * sets the value in the SCUIO hw-strap1 register. 435 */ 436 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scuio), 437 "hw-strap1"); 438 439 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); 440 object_initialize_child(obj, "fmc", &s->fmc, typename); 441 442 for (i = 0; i < sc->spis_num; i++) { 443 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i, socname); 444 object_initialize_child(obj, "spi[*]", &s->spi[i], typename); 445 } 446 447 for (i = 0; i < sc->ehcis_num; i++) { 448 object_initialize_child(obj, "ehci[*]", &s->ehci[i], 449 TYPE_PLATFORM_EHCI); 450 } 451 452 snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname); 453 object_initialize_child(obj, "sdmc", &s->sdmc, typename); 454 object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), 455 "ram-size"); 456 457 for (i = 0; i < sc->wdts_num; i++) { 458 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); 459 object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename); 460 } 461 462 for (i = 0; i < sc->macs_num; i++) { 463 object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i], 464 TYPE_FTGMAC100); 465 466 object_initialize_child(obj, "mii[*]", &s->mii[i], TYPE_ASPEED_MII); 467 } 468 469 for (i = 0; i < sc->uarts_num; i++) { 470 object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM); 471 } 472 473 object_initialize_child(obj, "sli", &s->sli, TYPE_ASPEED_2700_SLI); 474 object_initialize_child(obj, "sliio", &s->sliio, TYPE_ASPEED_2700_SLIIO); 475 object_initialize_child(obj, "intc", &a->intc[0], TYPE_ASPEED_2700_INTC); 476 object_initialize_child(obj, "intcio", &a->intc[1], 477 TYPE_ASPEED_2700_INTCIO); 478 479 snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname); 480 object_initialize_child(obj, "adc", &s->adc, typename); 481 482 snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); 483 object_initialize_child(obj, "i2c", &s->i2c, typename); 484 485 snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); 486 object_initialize_child(obj, "gpio", &s->gpio, typename); 487 488 object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC); 489 490 snprintf(typename, sizeof(typename), "aspeed.sdhci-%s", socname); 491 object_initialize_child(obj, "sd-controller", &s->sdhci, typename); 492 object_property_set_int(OBJECT(&s->sdhci), "num-slots", 1, &error_abort); 493 494 /* Init sd card slot class here so that they're under the correct parent */ 495 object_initialize_child(obj, "sd-controller.sdhci", 496 &s->sdhci.slots[0], TYPE_SYSBUS_SDHCI); 497 498 object_initialize_child(obj, "emmc-controller", &s->emmc, typename); 499 object_property_set_int(OBJECT(&s->emmc), "num-slots", 1, &error_abort); 500 501 object_initialize_child(obj, "emmc-controller.sdhci", &s->emmc.slots[0], 502 TYPE_SYSBUS_SDHCI); 503 504 snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname); 505 object_initialize_child(obj, "timerctrl", &s->timerctrl, typename); 506 507 snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname); 508 object_initialize_child(obj, "hace", &s->hace, typename); 509 } 510 511 /* 512 * ASPEED ast2700 has 0x0 as cluster ID 513 * 514 * https://developer.arm.com/documentation/100236/0100/register-descriptions/aarch64-system-registers/multiprocessor-affinity-register--el1 515 */ 516 static uint64_t aspeed_calc_affinity(int cpu) 517 { 518 return (0x0 << ARM_AFF1_SHIFT) | cpu; 519 } 520 521 static bool aspeed_soc_ast2700_gic_realize(DeviceState *dev, Error **errp) 522 { 523 Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev); 524 AspeedSoCState *s = ASPEED_SOC(dev); 525 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 526 SysBusDevice *gicbusdev; 527 DeviceState *gicdev; 528 QList *redist_region_count; 529 int i; 530 531 gicbusdev = SYS_BUS_DEVICE(&a->gic); 532 gicdev = DEVICE(&a->gic); 533 qdev_prop_set_uint32(gicdev, "revision", 3); 534 qdev_prop_set_uint32(gicdev, "num-cpu", sc->num_cpus); 535 qdev_prop_set_uint32(gicdev, "num-irq", AST2700_MAX_IRQ + GIC_INTERNAL); 536 537 redist_region_count = qlist_new(); 538 qlist_append_int(redist_region_count, sc->num_cpus); 539 qdev_prop_set_array(gicdev, "redist-region-count", redist_region_count); 540 541 if (!sysbus_realize(gicbusdev, errp)) { 542 return false; 543 } 544 sysbus_mmio_map(gicbusdev, 0, sc->memmap[ASPEED_GIC_DIST]); 545 sysbus_mmio_map(gicbusdev, 1, sc->memmap[ASPEED_GIC_REDIST]); 546 547 for (i = 0; i < sc->num_cpus; i++) { 548 DeviceState *cpudev = DEVICE(&a->cpu[i]); 549 int intidbase = AST2700_MAX_IRQ + i * GIC_INTERNAL; 550 551 const int timer_irq[] = { 552 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, 553 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, 554 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, 555 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, 556 }; 557 int j; 558 559 for (j = 0; j < ARRAY_SIZE(timer_irq); j++) { 560 qdev_connect_gpio_out(cpudev, j, 561 qdev_get_gpio_in(gicdev, intidbase + timer_irq[j])); 562 } 563 564 qemu_irq irq = qdev_get_gpio_in(gicdev, 565 intidbase + ARCH_GIC_MAINT_IRQ); 566 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 567 0, irq); 568 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, 569 qdev_get_gpio_in(gicdev, intidbase + VIRTUAL_PMU_IRQ)); 570 571 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 572 sysbus_connect_irq(gicbusdev, i + sc->num_cpus, 573 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 574 sysbus_connect_irq(gicbusdev, i + 2 * sc->num_cpus, 575 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 576 sysbus_connect_irq(gicbusdev, i + 3 * sc->num_cpus, 577 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 578 sysbus_connect_irq(gicbusdev, i + 4 * sc->num_cpus, 579 qdev_get_gpio_in(cpudev, ARM_CPU_NMI)); 580 sysbus_connect_irq(gicbusdev, i + 5 * sc->num_cpus, 581 qdev_get_gpio_in(cpudev, ARM_CPU_VINMI)); 582 } 583 584 return true; 585 } 586 587 static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp) 588 { 589 int i; 590 Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev); 591 AspeedSoCState *s = ASPEED_SOC(dev); 592 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 593 AspeedINTCClass *ic = ASPEED_INTC_GET_CLASS(&a->intc[0]); 594 AspeedINTCClass *icio = ASPEED_INTC_GET_CLASS(&a->intc[1]); 595 g_autofree char *sram_name = NULL; 596 qemu_irq irq; 597 598 /* Default boot region (SPI memory or ROMs) */ 599 memory_region_init(&s->spi_boot_container, OBJECT(s), 600 "aspeed.spi_boot_container", 0x400000000); 601 memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SPI_BOOT], 602 &s->spi_boot_container); 603 604 /* CPU */ 605 for (i = 0; i < sc->num_cpus; i++) { 606 object_property_set_int(OBJECT(&a->cpu[i]), "mp-affinity", 607 aspeed_calc_affinity(i), &error_abort); 608 609 object_property_set_int(OBJECT(&a->cpu[i]), "cntfrq", 1125000000, 610 &error_abort); 611 object_property_set_link(OBJECT(&a->cpu[i]), "memory", 612 OBJECT(s->memory), &error_abort); 613 614 if (!qdev_realize(DEVICE(&a->cpu[i]), NULL, errp)) { 615 return; 616 } 617 } 618 619 /* GIC */ 620 if (!aspeed_soc_ast2700_gic_realize(dev, errp)) { 621 return; 622 } 623 624 /* INTC */ 625 if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[0]), errp)) { 626 return; 627 } 628 629 aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc[0]), 0, 630 sc->memmap[ASPEED_DEV_INTC]); 631 632 /* INTCIO */ 633 if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[1]), errp)) { 634 return; 635 } 636 637 aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc[1]), 0, 638 sc->memmap[ASPEED_DEV_INTCIO]); 639 640 /* irq sources -> orgates -> INTC */ 641 for (i = 0; i < ic->num_inpins; i++) { 642 qdev_connect_gpio_out(DEVICE(&a->intc[0].orgates[i]), 0, 643 qdev_get_gpio_in(DEVICE(&a->intc[0]), i)); 644 } 645 646 /* INTC -> GIC192 - GIC201 */ 647 /* INTC -> GIC128 - GIC136 */ 648 for (i = 0; i < ic->num_outpins; i++) { 649 sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc[0]), i, 650 qdev_get_gpio_in(DEVICE(&a->gic), 651 ast2700_gic_intcmap[i].irq)); 652 } 653 654 /* irq source -> orgates -> INTCIO */ 655 for (i = 0; i < icio->num_inpins; i++) { 656 qdev_connect_gpio_out(DEVICE(&a->intc[1].orgates[i]), 0, 657 qdev_get_gpio_in(DEVICE(&a->intc[1]), i)); 658 } 659 660 /* INTCIO -> INTC */ 661 for (i = 0; i < icio->num_outpins; i++) { 662 sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc[1]), i, 663 qdev_get_gpio_in(DEVICE(&a->intc[0].orgates[0]), i)); 664 } 665 666 /* SRAM */ 667 sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index); 668 if (!memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, 669 errp)) { 670 return; 671 } 672 memory_region_add_subregion(s->memory, 673 sc->memmap[ASPEED_DEV_SRAM], &s->sram); 674 675 /* SCU */ 676 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { 677 return; 678 } 679 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]); 680 681 /* SCU1 */ 682 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scuio), errp)) { 683 return; 684 } 685 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scuio), 0, 686 sc->memmap[ASPEED_DEV_SCUIO]); 687 688 /* UART */ 689 if (!aspeed_soc_uart_realize(s, errp)) { 690 return; 691 } 692 693 /* FMC, The number of CS is set at the board level */ 694 object_property_set_int(OBJECT(&s->fmc), "dram-base", 695 sc->memmap[ASPEED_DEV_SDRAM], 696 &error_abort); 697 object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr), 698 &error_abort); 699 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) { 700 return; 701 } 702 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]); 703 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 1, 704 ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base); 705 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, 706 aspeed_soc_get_irq(s, ASPEED_DEV_FMC)); 707 708 /* Set up an alias on the FMC CE0 region (boot default) */ 709 MemoryRegion *fmc0_mmio = &s->fmc.flashes[0].mmio; 710 memory_region_init_alias(&s->spi_boot, OBJECT(s), "aspeed.spi_boot", 711 fmc0_mmio, 0, memory_region_size(fmc0_mmio)); 712 memory_region_add_subregion(&s->spi_boot_container, 0x0, &s->spi_boot); 713 714 /* SPI */ 715 for (i = 0; i < sc->spis_num; i++) { 716 object_property_set_link(OBJECT(&s->spi[i]), "dram", 717 OBJECT(s->dram_mr), &error_abort); 718 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { 719 return; 720 } 721 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 0, 722 sc->memmap[ASPEED_DEV_SPI0 + i]); 723 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 1, 724 ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base); 725 } 726 727 /* EHCI */ 728 for (i = 0; i < sc->ehcis_num; i++) { 729 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), errp)) { 730 return; 731 } 732 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ehci[i]), 0, 733 sc->memmap[ASPEED_DEV_EHCI1 + i]); 734 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0, 735 aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i)); 736 } 737 738 /* 739 * SDMC - SDRAM Memory Controller 740 * The SDMC controller is unlocked at SPL stage. 741 * At present, only supports to emulate booting 742 * start from u-boot stage. Set SDMC controller 743 * unlocked by default. It is a temporarily solution. 744 */ 745 object_property_set_bool(OBJECT(&s->sdmc), "unlocked", true, 746 &error_abort); 747 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) { 748 return; 749 } 750 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdmc), 0, 751 sc->memmap[ASPEED_DEV_SDMC]); 752 753 /* RAM */ 754 if (!aspeed_soc_ast2700_dram_init(dev, errp)) { 755 return; 756 } 757 758 /* Net */ 759 for (i = 0; i < sc->macs_num; i++) { 760 object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true, 761 &error_abort); 762 object_property_set_bool(OBJECT(&s->ftgmac100[i]), "dma64", true, 763 &error_abort); 764 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) { 765 return; 766 } 767 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 768 sc->memmap[ASPEED_DEV_ETH1 + i]); 769 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 770 aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i)); 771 772 object_property_set_link(OBJECT(&s->mii[i]), "nic", 773 OBJECT(&s->ftgmac100[i]), &error_abort); 774 if (!sysbus_realize(SYS_BUS_DEVICE(&s->mii[i]), errp)) { 775 return; 776 } 777 778 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->mii[i]), 0, 779 sc->memmap[ASPEED_DEV_MII1 + i]); 780 } 781 782 /* Watch dog */ 783 for (i = 0; i < sc->wdts_num; i++) { 784 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); 785 hwaddr wdt_offset = sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize; 786 787 object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu), 788 &error_abort); 789 if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) { 790 return; 791 } 792 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offset); 793 } 794 795 /* SLI */ 796 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sli), errp)) { 797 return; 798 } 799 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sli), 0, sc->memmap[ASPEED_DEV_SLI]); 800 801 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sliio), errp)) { 802 return; 803 } 804 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sliio), 0, 805 sc->memmap[ASPEED_DEV_SLIIO]); 806 807 /* ADC */ 808 if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) { 809 return; 810 } 811 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]); 812 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0, 813 aspeed_soc_get_irq(s, ASPEED_DEV_ADC)); 814 815 /* I2C */ 816 object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr), 817 &error_abort); 818 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) { 819 return; 820 } 821 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]); 822 for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) { 823 /* 824 * The AST2700 I2C controller has one source INTC per bus. 825 * 826 * For AST2700 A0: 827 * I2C bus interrupts are connected to the OR gate from bit 0 to bit 828 * 15, and the OR gate output pin is connected to the input pin of 829 * GICINT130 of INTC (CPU Die). Then, the output pin is connected to 830 * the GIC. 831 * 832 * For AST2700 A1: 833 * I2C bus interrupts are connected to the OR gate from bit 0 to bit 834 * 15, and the OR gate output pin is connected to the input pin of 835 * GICINT194 of INTCIO (IO Die). Then, the output pin is connected 836 * to the INTC (CPU Die) input pin, and its output pin is connected 837 * to the GIC. 838 * 839 * I2C bus 0 is connected to the OR gate at bit 0. 840 * I2C bus 15 is connected to the OR gate at bit 15. 841 */ 842 irq = aspeed_soc_ast2700_get_irq_index(s, ASPEED_DEV_I2C, i); 843 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq); 844 } 845 846 /* GPIO */ 847 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { 848 return; 849 } 850 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio), 0, 851 sc->memmap[ASPEED_DEV_GPIO]); 852 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, 853 aspeed_soc_get_irq(s, ASPEED_DEV_GPIO)); 854 855 /* RTC */ 856 if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) { 857 return; 858 } 859 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_RTC]); 860 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, 861 aspeed_soc_get_irq(s, ASPEED_DEV_RTC)); 862 863 /* SDHCI */ 864 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) { 865 return; 866 } 867 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdhci), 0, 868 sc->memmap[ASPEED_DEV_SDHCI]); 869 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, 870 aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI)); 871 872 /* eMMC */ 873 if (!sysbus_realize(SYS_BUS_DEVICE(&s->emmc), errp)) { 874 return; 875 } 876 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->emmc), 0, 877 sc->memmap[ASPEED_DEV_EMMC]); 878 sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0, 879 aspeed_soc_get_irq(s, ASPEED_DEV_EMMC)); 880 881 /* Timer */ 882 object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu), 883 &error_abort); 884 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) { 885 return; 886 } 887 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->timerctrl), 0, 888 sc->memmap[ASPEED_DEV_TIMER1]); 889 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) { 890 irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i); 891 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); 892 } 893 894 /* HACE */ 895 object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(s->dram_mr), 896 &error_abort); 897 if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) { 898 return; 899 } 900 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->hace), 0, 901 sc->memmap[ASPEED_DEV_HACE]); 902 sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0, 903 aspeed_soc_get_irq(s, ASPEED_DEV_HACE)); 904 905 create_unimplemented_device("ast2700.dpmcu", 0x11000000, 0x40000); 906 create_unimplemented_device("ast2700.iomem0", 0x12000000, 0x01000000); 907 create_unimplemented_device("ast2700.iomem1", 0x14000000, 0x01000000); 908 create_unimplemented_device("ast2700.ltpi", 0x30000000, 0x1000000); 909 create_unimplemented_device("ast2700.io", 0x0, 0x4000000); 910 } 911 912 static void aspeed_soc_ast2700a0_class_init(ObjectClass *oc, const void *data) 913 { 914 static const char * const valid_cpu_types[] = { 915 ARM_CPU_TYPE_NAME("cortex-a35"), 916 NULL 917 }; 918 DeviceClass *dc = DEVICE_CLASS(oc); 919 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); 920 921 /* Reason: The Aspeed SoC can only be instantiated from a board */ 922 dc->user_creatable = false; 923 dc->realize = aspeed_soc_ast2700_realize; 924 925 sc->valid_cpu_types = valid_cpu_types; 926 sc->silicon_rev = AST2700_A0_SILICON_REV; 927 sc->sram_size = 0x20000; 928 sc->spis_num = 3; 929 sc->ehcis_num = 2; 930 sc->wdts_num = 8; 931 sc->macs_num = 1; 932 sc->uarts_num = 13; 933 sc->num_cpus = 4; 934 sc->uarts_base = ASPEED_DEV_UART0; 935 sc->irqmap = aspeed_soc_ast2700a0_irqmap; 936 sc->memmap = aspeed_soc_ast2700_memmap; 937 sc->get_irq = aspeed_soc_ast2700_get_irq; 938 } 939 940 static void aspeed_soc_ast2700a1_class_init(ObjectClass *oc, const void *data) 941 { 942 static const char * const valid_cpu_types[] = { 943 ARM_CPU_TYPE_NAME("cortex-a35"), 944 NULL 945 }; 946 DeviceClass *dc = DEVICE_CLASS(oc); 947 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); 948 949 /* Reason: The Aspeed SoC can only be instantiated from a board */ 950 dc->user_creatable = false; 951 dc->realize = aspeed_soc_ast2700_realize; 952 953 sc->valid_cpu_types = valid_cpu_types; 954 sc->silicon_rev = AST2700_A1_SILICON_REV; 955 sc->sram_size = 0x20000; 956 sc->spis_num = 3; 957 sc->ehcis_num = 4; 958 sc->wdts_num = 8; 959 sc->macs_num = 3; 960 sc->uarts_num = 13; 961 sc->num_cpus = 4; 962 sc->uarts_base = ASPEED_DEV_UART0; 963 sc->irqmap = aspeed_soc_ast2700a1_irqmap; 964 sc->memmap = aspeed_soc_ast2700_memmap; 965 sc->get_irq = aspeed_soc_ast2700_get_irq; 966 } 967 968 static const TypeInfo aspeed_soc_ast27x0_types[] = { 969 { 970 .name = TYPE_ASPEED27X0_SOC, 971 .parent = TYPE_ASPEED_SOC, 972 .instance_size = sizeof(Aspeed27x0SoCState), 973 .abstract = true, 974 }, { 975 .name = "ast2700-a0", 976 .parent = TYPE_ASPEED27X0_SOC, 977 .instance_init = aspeed_soc_ast2700_init, 978 .class_init = aspeed_soc_ast2700a0_class_init, 979 }, 980 { 981 .name = "ast2700-a1", 982 .parent = TYPE_ASPEED27X0_SOC, 983 .instance_init = aspeed_soc_ast2700_init, 984 .class_init = aspeed_soc_ast2700a1_class_init, 985 }, 986 }; 987 988 DEFINE_TYPES(aspeed_soc_ast27x0_types) 989