1 /* 2 * ASPEED SoC 27x0 family 3 * 4 * Copyright (C) 2024 ASPEED Technology Inc. 5 * 6 * This code is licensed under the GPL version 2 or later. See 7 * the COPYING file in the top-level directory. 8 * 9 * Implementation extracted from the AST2600 and adapted for AST27x0. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qapi/error.h" 14 #include "hw/misc/unimp.h" 15 #include "hw/arm/aspeed_soc.h" 16 #include "hw/arm/bsa.h" 17 #include "qemu/module.h" 18 #include "qemu/error-report.h" 19 #include "hw/i2c/aspeed_i2c.h" 20 #include "net/net.h" 21 #include "system/system.h" 22 #include "hw/intc/arm_gicv3.h" 23 #include "qobject/qlist.h" 24 #include "qemu/log.h" 25 26 static const hwaddr aspeed_soc_ast2700_memmap[] = { 27 [ASPEED_DEV_SRAM] = 0x10000000, 28 [ASPEED_DEV_HACE] = 0x12070000, 29 [ASPEED_DEV_EMMC] = 0x12090000, 30 [ASPEED_DEV_INTC] = 0x12100000, 31 [ASPEED_GIC_DIST] = 0x12200000, 32 [ASPEED_GIC_REDIST] = 0x12280000, 33 [ASPEED_DEV_SDMC] = 0x12C00000, 34 [ASPEED_DEV_SCU] = 0x12C02000, 35 [ASPEED_DEV_RTC] = 0x12C0F000, 36 [ASPEED_DEV_TIMER1] = 0x12C10000, 37 [ASPEED_DEV_SLI] = 0x12C17000, 38 [ASPEED_DEV_UART4] = 0X12C1A000, 39 [ASPEED_DEV_FMC] = 0x14000000, 40 [ASPEED_DEV_SPI0] = 0x14010000, 41 [ASPEED_DEV_SPI1] = 0x14020000, 42 [ASPEED_DEV_SPI2] = 0x14030000, 43 [ASPEED_DEV_MII1] = 0x14040000, 44 [ASPEED_DEV_MII2] = 0x14040008, 45 [ASPEED_DEV_MII3] = 0x14040010, 46 [ASPEED_DEV_ETH1] = 0x14050000, 47 [ASPEED_DEV_ETH2] = 0x14060000, 48 [ASPEED_DEV_ETH3] = 0x14070000, 49 [ASPEED_DEV_SDHCI] = 0x14080000, 50 [ASPEED_DEV_ADC] = 0x14C00000, 51 [ASPEED_DEV_SCUIO] = 0x14C02000, 52 [ASPEED_DEV_GPIO] = 0x14C0B000, 53 [ASPEED_DEV_I2C] = 0x14C0F000, 54 [ASPEED_DEV_INTCIO] = 0x14C18000, 55 [ASPEED_DEV_SLIIO] = 0x14C1E000, 56 [ASPEED_DEV_VUART] = 0X14C30000, 57 [ASPEED_DEV_UART0] = 0X14C33000, 58 [ASPEED_DEV_UART1] = 0X14C33100, 59 [ASPEED_DEV_UART2] = 0X14C33200, 60 [ASPEED_DEV_UART3] = 0X14C33300, 61 [ASPEED_DEV_UART5] = 0X14C33400, 62 [ASPEED_DEV_UART6] = 0X14C33500, 63 [ASPEED_DEV_UART7] = 0X14C33600, 64 [ASPEED_DEV_UART8] = 0X14C33700, 65 [ASPEED_DEV_UART9] = 0X14C33800, 66 [ASPEED_DEV_UART10] = 0X14C33900, 67 [ASPEED_DEV_UART11] = 0X14C33A00, 68 [ASPEED_DEV_UART12] = 0X14C33B00, 69 [ASPEED_DEV_WDT] = 0x14C37000, 70 [ASPEED_DEV_SPI_BOOT] = 0x100000000, 71 [ASPEED_DEV_SDRAM] = 0x400000000, 72 }; 73 74 #define AST2700_MAX_IRQ 256 75 76 /* Shared Peripheral Interrupt values below are offset by -32 from datasheet */ 77 static const int aspeed_soc_ast2700a0_irqmap[] = { 78 [ASPEED_DEV_SDMC] = 0, 79 [ASPEED_DEV_HACE] = 4, 80 [ASPEED_DEV_XDMA] = 5, 81 [ASPEED_DEV_UART4] = 8, 82 [ASPEED_DEV_SCU] = 12, 83 [ASPEED_DEV_RTC] = 13, 84 [ASPEED_DEV_EMMC] = 15, 85 [ASPEED_DEV_TIMER1] = 16, 86 [ASPEED_DEV_TIMER2] = 17, 87 [ASPEED_DEV_TIMER3] = 18, 88 [ASPEED_DEV_TIMER4] = 19, 89 [ASPEED_DEV_TIMER5] = 20, 90 [ASPEED_DEV_TIMER6] = 21, 91 [ASPEED_DEV_TIMER7] = 22, 92 [ASPEED_DEV_TIMER8] = 23, 93 [ASPEED_DEV_DP] = 28, 94 [ASPEED_DEV_LPC] = 128, 95 [ASPEED_DEV_IBT] = 128, 96 [ASPEED_DEV_KCS] = 128, 97 [ASPEED_DEV_ADC] = 130, 98 [ASPEED_DEV_GPIO] = 130, 99 [ASPEED_DEV_I2C] = 130, 100 [ASPEED_DEV_FMC] = 131, 101 [ASPEED_DEV_WDT] = 131, 102 [ASPEED_DEV_PWM] = 131, 103 [ASPEED_DEV_I3C] = 131, 104 [ASPEED_DEV_UART0] = 132, 105 [ASPEED_DEV_UART1] = 132, 106 [ASPEED_DEV_UART2] = 132, 107 [ASPEED_DEV_UART3] = 132, 108 [ASPEED_DEV_UART5] = 132, 109 [ASPEED_DEV_UART6] = 132, 110 [ASPEED_DEV_UART7] = 132, 111 [ASPEED_DEV_UART8] = 132, 112 [ASPEED_DEV_UART9] = 132, 113 [ASPEED_DEV_UART10] = 132, 114 [ASPEED_DEV_UART11] = 132, 115 [ASPEED_DEV_UART12] = 132, 116 [ASPEED_DEV_ETH1] = 132, 117 [ASPEED_DEV_ETH2] = 132, 118 [ASPEED_DEV_ETH3] = 132, 119 [ASPEED_DEV_PECI] = 133, 120 [ASPEED_DEV_SDHCI] = 133, 121 }; 122 123 static const int aspeed_soc_ast2700a1_irqmap[] = { 124 [ASPEED_DEV_SDMC] = 0, 125 [ASPEED_DEV_HACE] = 4, 126 [ASPEED_DEV_XDMA] = 5, 127 [ASPEED_DEV_UART4] = 8, 128 [ASPEED_DEV_SCU] = 12, 129 [ASPEED_DEV_RTC] = 13, 130 [ASPEED_DEV_EMMC] = 15, 131 [ASPEED_DEV_TIMER1] = 16, 132 [ASPEED_DEV_TIMER2] = 17, 133 [ASPEED_DEV_TIMER3] = 18, 134 [ASPEED_DEV_TIMER4] = 19, 135 [ASPEED_DEV_TIMER5] = 20, 136 [ASPEED_DEV_TIMER6] = 21, 137 [ASPEED_DEV_TIMER7] = 22, 138 [ASPEED_DEV_TIMER8] = 23, 139 [ASPEED_DEV_DP] = 28, 140 [ASPEED_DEV_LPC] = 192, 141 [ASPEED_DEV_IBT] = 192, 142 [ASPEED_DEV_KCS] = 192, 143 [ASPEED_DEV_I2C] = 194, 144 [ASPEED_DEV_ADC] = 194, 145 [ASPEED_DEV_GPIO] = 194, 146 [ASPEED_DEV_FMC] = 195, 147 [ASPEED_DEV_WDT] = 195, 148 [ASPEED_DEV_PWM] = 195, 149 [ASPEED_DEV_I3C] = 195, 150 [ASPEED_DEV_UART0] = 196, 151 [ASPEED_DEV_UART1] = 196, 152 [ASPEED_DEV_UART2] = 196, 153 [ASPEED_DEV_UART3] = 196, 154 [ASPEED_DEV_UART5] = 196, 155 [ASPEED_DEV_UART6] = 196, 156 [ASPEED_DEV_UART7] = 196, 157 [ASPEED_DEV_UART8] = 196, 158 [ASPEED_DEV_UART9] = 196, 159 [ASPEED_DEV_UART10] = 196, 160 [ASPEED_DEV_UART11] = 196, 161 [ASPEED_DEV_UART12] = 196, 162 [ASPEED_DEV_ETH1] = 196, 163 [ASPEED_DEV_ETH2] = 196, 164 [ASPEED_DEV_ETH3] = 196, 165 [ASPEED_DEV_PECI] = 197, 166 [ASPEED_DEV_SDHCI] = 197, 167 }; 168 169 /* GICINT 128 */ 170 /* GICINT 192 */ 171 static const int ast2700_gic128_gic192_intcmap[] = { 172 [ASPEED_DEV_LPC] = 0, 173 [ASPEED_DEV_IBT] = 2, 174 [ASPEED_DEV_KCS] = 4, 175 }; 176 177 /* GICINT 129 */ 178 /* GICINT 193 */ 179 180 /* GICINT 130 */ 181 /* GICINT 194 */ 182 static const int ast2700_gic130_gic194_intcmap[] = { 183 [ASPEED_DEV_I2C] = 0, 184 [ASPEED_DEV_ADC] = 16, 185 [ASPEED_DEV_GPIO] = 18, 186 }; 187 188 /* GICINT 131 */ 189 /* GICINT 195 */ 190 static const int ast2700_gic131_gic195_intcmap[] = { 191 [ASPEED_DEV_I3C] = 0, 192 [ASPEED_DEV_WDT] = 16, 193 [ASPEED_DEV_FMC] = 25, 194 [ASPEED_DEV_PWM] = 29, 195 }; 196 197 /* GICINT 132 */ 198 /* GICINT 196 */ 199 static const int ast2700_gic132_gic196_intcmap[] = { 200 [ASPEED_DEV_ETH1] = 0, 201 [ASPEED_DEV_ETH2] = 1, 202 [ASPEED_DEV_ETH3] = 2, 203 [ASPEED_DEV_UART0] = 7, 204 [ASPEED_DEV_UART1] = 8, 205 [ASPEED_DEV_UART2] = 9, 206 [ASPEED_DEV_UART3] = 10, 207 [ASPEED_DEV_UART5] = 11, 208 [ASPEED_DEV_UART6] = 12, 209 [ASPEED_DEV_UART7] = 13, 210 [ASPEED_DEV_UART8] = 14, 211 [ASPEED_DEV_UART9] = 15, 212 [ASPEED_DEV_UART10] = 16, 213 [ASPEED_DEV_UART11] = 17, 214 [ASPEED_DEV_UART12] = 18, 215 }; 216 217 /* GICINT 133 */ 218 /* GICINT 197 */ 219 static const int ast2700_gic133_gic197_intcmap[] = { 220 [ASPEED_DEV_SDHCI] = 1, 221 [ASPEED_DEV_PECI] = 4, 222 }; 223 224 /* GICINT 128 ~ 136 */ 225 /* GICINT 192 ~ 201 */ 226 struct gic_intc_irq_info { 227 int irq; 228 int intc_idx; 229 int orgate_idx; 230 const int *ptr; 231 }; 232 233 static const struct gic_intc_irq_info ast2700_gic_intcmap[] = { 234 {192, 1, 0, ast2700_gic128_gic192_intcmap}, 235 {193, 1, 1, NULL}, 236 {194, 1, 2, ast2700_gic130_gic194_intcmap}, 237 {195, 1, 3, ast2700_gic131_gic195_intcmap}, 238 {196, 1, 4, ast2700_gic132_gic196_intcmap}, 239 {197, 1, 5, ast2700_gic133_gic197_intcmap}, 240 {198, 1, 6, NULL}, 241 {199, 1, 7, NULL}, 242 {200, 1, 8, NULL}, 243 {201, 1, 9, NULL}, 244 {128, 0, 1, ast2700_gic128_gic192_intcmap}, 245 {129, 0, 2, NULL}, 246 {130, 0, 3, ast2700_gic130_gic194_intcmap}, 247 {131, 0, 4, ast2700_gic131_gic195_intcmap}, 248 {132, 0, 5, ast2700_gic132_gic196_intcmap}, 249 {133, 0, 6, ast2700_gic133_gic197_intcmap}, 250 {134, 0, 7, NULL}, 251 {135, 0, 8, NULL}, 252 {136, 0, 9, NULL}, 253 }; 254 255 static qemu_irq aspeed_soc_ast2700_get_irq(AspeedSoCState *s, int dev) 256 { 257 Aspeed27x0SoCState *a = ASPEED27X0_SOC(s); 258 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 259 int or_idx; 260 int idx; 261 int i; 262 263 for (i = 0; i < ARRAY_SIZE(ast2700_gic_intcmap); i++) { 264 if (sc->irqmap[dev] == ast2700_gic_intcmap[i].irq) { 265 assert(ast2700_gic_intcmap[i].ptr); 266 or_idx = ast2700_gic_intcmap[i].orgate_idx; 267 idx = ast2700_gic_intcmap[i].intc_idx; 268 return qdev_get_gpio_in(DEVICE(&a->intc[idx].orgates[or_idx]), 269 ast2700_gic_intcmap[i].ptr[dev]); 270 } 271 } 272 273 return qdev_get_gpio_in(DEVICE(&a->gic), sc->irqmap[dev]); 274 } 275 276 static qemu_irq aspeed_soc_ast2700_get_irq_index(AspeedSoCState *s, int dev, 277 int index) 278 { 279 Aspeed27x0SoCState *a = ASPEED27X0_SOC(s); 280 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 281 int or_idx; 282 int idx; 283 int i; 284 285 for (i = 0; i < ARRAY_SIZE(ast2700_gic_intcmap); i++) { 286 if (sc->irqmap[dev] == ast2700_gic_intcmap[i].irq) { 287 assert(ast2700_gic_intcmap[i].ptr); 288 or_idx = ast2700_gic_intcmap[i].orgate_idx; 289 idx = ast2700_gic_intcmap[i].intc_idx; 290 return qdev_get_gpio_in(DEVICE(&a->intc[idx].orgates[or_idx]), 291 ast2700_gic_intcmap[i].ptr[dev] + index); 292 } 293 } 294 295 /* 296 * Invalid OR gate index, device IRQ should be between 128 to 136 297 * and 192 to 201. 298 */ 299 g_assert_not_reached(); 300 } 301 302 static uint64_t aspeed_ram_capacity_read(void *opaque, hwaddr addr, 303 unsigned int size) 304 { 305 qemu_log_mask(LOG_GUEST_ERROR, 306 "%s: DRAM read out of ram size, addr:0x%" PRIx64 "\n", 307 __func__, addr); 308 return 0; 309 } 310 311 static void aspeed_ram_capacity_write(void *opaque, hwaddr addr, uint64_t data, 312 unsigned int size) 313 { 314 AspeedSoCState *s = ASPEED_SOC(opaque); 315 ram_addr_t ram_size; 316 MemTxResult result; 317 318 ram_size = object_property_get_uint(OBJECT(&s->sdmc), "ram-size", 319 &error_abort); 320 321 assert(ram_size > 0); 322 323 /* 324 * Emulate ddr capacity hardware behavior. 325 * If writes the data to the address which is beyond the ram size, 326 * it would write the data to the "address % ram_size". 327 */ 328 result = address_space_write(&s->dram_as, addr % ram_size, 329 MEMTXATTRS_UNSPECIFIED, &data, 4); 330 if (result != MEMTX_OK) { 331 qemu_log_mask(LOG_GUEST_ERROR, 332 "%s: DRAM write failed, addr:0x%" HWADDR_PRIx 333 ", data :0x%" PRIx64 "\n", 334 __func__, addr % ram_size, data); 335 } 336 } 337 338 static const MemoryRegionOps aspeed_ram_capacity_ops = { 339 .read = aspeed_ram_capacity_read, 340 .write = aspeed_ram_capacity_write, 341 .endianness = DEVICE_LITTLE_ENDIAN, 342 .valid = { 343 .min_access_size = 1, 344 .max_access_size = 8, 345 }, 346 }; 347 348 /* 349 * SDMC should be realized first to get correct RAM size and max size 350 * values 351 */ 352 static bool aspeed_soc_ast2700_dram_init(DeviceState *dev, Error **errp) 353 { 354 ram_addr_t ram_size, max_ram_size; 355 Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev); 356 AspeedSoCState *s = ASPEED_SOC(dev); 357 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 358 359 ram_size = object_property_get_uint(OBJECT(&s->sdmc), "ram-size", 360 &error_abort); 361 max_ram_size = object_property_get_uint(OBJECT(&s->sdmc), "max-ram-size", 362 &error_abort); 363 364 memory_region_init(&s->dram_container, OBJECT(s), "ram-container", 365 ram_size); 366 memory_region_add_subregion(&s->dram_container, 0, s->dram_mr); 367 address_space_init(&s->dram_as, s->dram_mr, "dram"); 368 369 /* 370 * Add a memory region beyond the RAM region to emulate 371 * ddr capacity hardware behavior. 372 */ 373 if (ram_size < max_ram_size) { 374 memory_region_init_io(&a->dram_empty, OBJECT(s), 375 &aspeed_ram_capacity_ops, s, 376 "ram-empty", max_ram_size - ram_size); 377 378 memory_region_add_subregion(s->memory, 379 sc->memmap[ASPEED_DEV_SDRAM] + ram_size, 380 &a->dram_empty); 381 } 382 383 memory_region_add_subregion(s->memory, 384 sc->memmap[ASPEED_DEV_SDRAM], &s->dram_container); 385 return true; 386 } 387 388 static void aspeed_soc_ast2700_init(Object *obj) 389 { 390 Aspeed27x0SoCState *a = ASPEED27X0_SOC(obj); 391 AspeedSoCState *s = ASPEED_SOC(obj); 392 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 393 int i; 394 char socname[8]; 395 char typename[64]; 396 397 if (sscanf(object_get_typename(obj), "%7s", socname) != 1) { 398 g_assert_not_reached(); 399 } 400 401 for (i = 0; i < sc->num_cpus; i++) { 402 object_initialize_child(obj, "cpu[*]", &a->cpu[i], 403 aspeed_soc_cpu_type(sc)); 404 } 405 406 object_initialize_child(obj, "gic", &a->gic, gicv3_class_name()); 407 408 object_initialize_child(obj, "scu", &s->scu, TYPE_ASPEED_2700_SCU); 409 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", 410 sc->silicon_rev); 411 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), 412 "hw-strap1"); 413 object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu), 414 "hw-prot-key"); 415 416 object_initialize_child(obj, "scuio", &s->scuio, TYPE_ASPEED_2700_SCUIO); 417 qdev_prop_set_uint32(DEVICE(&s->scuio), "silicon-rev", 418 sc->silicon_rev); 419 /* 420 * There is one hw-strap1 register in the SCU (CPU DIE) and another 421 * hw-strap1 register in the SCUIO (IO DIE). To reuse the current design 422 * of hw-strap, hw-strap1 is assigned to the SCU and sets the value in the 423 * SCU hw-strap1 register, while hw-strap2 is assigned to the SCUIO and 424 * sets the value in the SCUIO hw-strap1 register. 425 */ 426 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scuio), 427 "hw-strap1"); 428 429 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); 430 object_initialize_child(obj, "fmc", &s->fmc, typename); 431 432 for (i = 0; i < sc->spis_num; i++) { 433 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i, socname); 434 object_initialize_child(obj, "spi[*]", &s->spi[i], typename); 435 } 436 437 snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname); 438 object_initialize_child(obj, "sdmc", &s->sdmc, typename); 439 object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), 440 "ram-size"); 441 442 for (i = 0; i < sc->wdts_num; i++) { 443 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); 444 object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename); 445 } 446 447 for (i = 0; i < sc->macs_num; i++) { 448 object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i], 449 TYPE_FTGMAC100); 450 451 object_initialize_child(obj, "mii[*]", &s->mii[i], TYPE_ASPEED_MII); 452 } 453 454 for (i = 0; i < sc->uarts_num; i++) { 455 object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM); 456 } 457 458 object_initialize_child(obj, "sli", &s->sli, TYPE_ASPEED_2700_SLI); 459 object_initialize_child(obj, "sliio", &s->sliio, TYPE_ASPEED_2700_SLIIO); 460 object_initialize_child(obj, "intc", &a->intc[0], TYPE_ASPEED_2700_INTC); 461 object_initialize_child(obj, "intcio", &a->intc[1], 462 TYPE_ASPEED_2700_INTCIO); 463 464 snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname); 465 object_initialize_child(obj, "adc", &s->adc, typename); 466 467 snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); 468 object_initialize_child(obj, "i2c", &s->i2c, typename); 469 470 snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); 471 object_initialize_child(obj, "gpio", &s->gpio, typename); 472 473 object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC); 474 475 snprintf(typename, sizeof(typename), "aspeed.sdhci-%s", socname); 476 object_initialize_child(obj, "sd-controller", &s->sdhci, typename); 477 object_property_set_int(OBJECT(&s->sdhci), "num-slots", 1, &error_abort); 478 479 /* Init sd card slot class here so that they're under the correct parent */ 480 object_initialize_child(obj, "sd-controller.sdhci", 481 &s->sdhci.slots[0], TYPE_SYSBUS_SDHCI); 482 483 object_initialize_child(obj, "emmc-controller", &s->emmc, typename); 484 object_property_set_int(OBJECT(&s->emmc), "num-slots", 1, &error_abort); 485 486 object_initialize_child(obj, "emmc-controller.sdhci", &s->emmc.slots[0], 487 TYPE_SYSBUS_SDHCI); 488 489 snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname); 490 object_initialize_child(obj, "timerctrl", &s->timerctrl, typename); 491 492 snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname); 493 object_initialize_child(obj, "hace", &s->hace, typename); 494 } 495 496 /* 497 * ASPEED ast2700 has 0x0 as cluster ID 498 * 499 * https://developer.arm.com/documentation/100236/0100/register-descriptions/aarch64-system-registers/multiprocessor-affinity-register--el1 500 */ 501 static uint64_t aspeed_calc_affinity(int cpu) 502 { 503 return (0x0 << ARM_AFF1_SHIFT) | cpu; 504 } 505 506 static bool aspeed_soc_ast2700_gic_realize(DeviceState *dev, Error **errp) 507 { 508 Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev); 509 AspeedSoCState *s = ASPEED_SOC(dev); 510 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 511 SysBusDevice *gicbusdev; 512 DeviceState *gicdev; 513 QList *redist_region_count; 514 int i; 515 516 gicbusdev = SYS_BUS_DEVICE(&a->gic); 517 gicdev = DEVICE(&a->gic); 518 qdev_prop_set_uint32(gicdev, "revision", 3); 519 qdev_prop_set_uint32(gicdev, "num-cpu", sc->num_cpus); 520 qdev_prop_set_uint32(gicdev, "num-irq", AST2700_MAX_IRQ + GIC_INTERNAL); 521 522 redist_region_count = qlist_new(); 523 qlist_append_int(redist_region_count, sc->num_cpus); 524 qdev_prop_set_array(gicdev, "redist-region-count", redist_region_count); 525 526 if (!sysbus_realize(gicbusdev, errp)) { 527 return false; 528 } 529 sysbus_mmio_map(gicbusdev, 0, sc->memmap[ASPEED_GIC_DIST]); 530 sysbus_mmio_map(gicbusdev, 1, sc->memmap[ASPEED_GIC_REDIST]); 531 532 for (i = 0; i < sc->num_cpus; i++) { 533 DeviceState *cpudev = DEVICE(&a->cpu[i]); 534 int intidbase = AST2700_MAX_IRQ + i * GIC_INTERNAL; 535 536 const int timer_irq[] = { 537 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, 538 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, 539 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, 540 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, 541 }; 542 int j; 543 544 for (j = 0; j < ARRAY_SIZE(timer_irq); j++) { 545 qdev_connect_gpio_out(cpudev, j, 546 qdev_get_gpio_in(gicdev, intidbase + timer_irq[j])); 547 } 548 549 qemu_irq irq = qdev_get_gpio_in(gicdev, 550 intidbase + ARCH_GIC_MAINT_IRQ); 551 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 552 0, irq); 553 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, 554 qdev_get_gpio_in(gicdev, intidbase + VIRTUAL_PMU_IRQ)); 555 556 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 557 sysbus_connect_irq(gicbusdev, i + sc->num_cpus, 558 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 559 sysbus_connect_irq(gicbusdev, i + 2 * sc->num_cpus, 560 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 561 sysbus_connect_irq(gicbusdev, i + 3 * sc->num_cpus, 562 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 563 sysbus_connect_irq(gicbusdev, i + 4 * sc->num_cpus, 564 qdev_get_gpio_in(cpudev, ARM_CPU_NMI)); 565 sysbus_connect_irq(gicbusdev, i + 5 * sc->num_cpus, 566 qdev_get_gpio_in(cpudev, ARM_CPU_VINMI)); 567 } 568 569 return true; 570 } 571 572 static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp) 573 { 574 int i; 575 Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev); 576 AspeedSoCState *s = ASPEED_SOC(dev); 577 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 578 AspeedINTCClass *ic = ASPEED_INTC_GET_CLASS(&a->intc[0]); 579 AspeedINTCClass *icio = ASPEED_INTC_GET_CLASS(&a->intc[1]); 580 g_autofree char *sram_name = NULL; 581 qemu_irq irq; 582 583 /* Default boot region (SPI memory or ROMs) */ 584 memory_region_init(&s->spi_boot_container, OBJECT(s), 585 "aspeed.spi_boot_container", 0x400000000); 586 memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SPI_BOOT], 587 &s->spi_boot_container); 588 589 /* CPU */ 590 for (i = 0; i < sc->num_cpus; i++) { 591 object_property_set_int(OBJECT(&a->cpu[i]), "mp-affinity", 592 aspeed_calc_affinity(i), &error_abort); 593 594 object_property_set_int(OBJECT(&a->cpu[i]), "cntfrq", 1125000000, 595 &error_abort); 596 object_property_set_link(OBJECT(&a->cpu[i]), "memory", 597 OBJECT(s->memory), &error_abort); 598 599 if (!qdev_realize(DEVICE(&a->cpu[i]), NULL, errp)) { 600 return; 601 } 602 } 603 604 /* GIC */ 605 if (!aspeed_soc_ast2700_gic_realize(dev, errp)) { 606 return; 607 } 608 609 /* INTC */ 610 if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[0]), errp)) { 611 return; 612 } 613 614 aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc[0]), 0, 615 sc->memmap[ASPEED_DEV_INTC]); 616 617 /* INTCIO */ 618 if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[1]), errp)) { 619 return; 620 } 621 622 aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc[1]), 0, 623 sc->memmap[ASPEED_DEV_INTCIO]); 624 625 /* irq sources -> orgates -> INTC */ 626 for (i = 0; i < ic->num_inpins; i++) { 627 qdev_connect_gpio_out(DEVICE(&a->intc[0].orgates[i]), 0, 628 qdev_get_gpio_in(DEVICE(&a->intc[0]), i)); 629 } 630 631 /* INTC -> GIC192 - GIC201 */ 632 /* INTC -> GIC128 - GIC136 */ 633 for (i = 0; i < ic->num_outpins; i++) { 634 sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc[0]), i, 635 qdev_get_gpio_in(DEVICE(&a->gic), 636 ast2700_gic_intcmap[i].irq)); 637 } 638 639 /* irq source -> orgates -> INTCIO */ 640 for (i = 0; i < icio->num_inpins; i++) { 641 qdev_connect_gpio_out(DEVICE(&a->intc[1].orgates[i]), 0, 642 qdev_get_gpio_in(DEVICE(&a->intc[1]), i)); 643 } 644 645 /* INTCIO -> INTC */ 646 for (i = 0; i < icio->num_outpins; i++) { 647 sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc[1]), i, 648 qdev_get_gpio_in(DEVICE(&a->intc[0].orgates[0]), i)); 649 } 650 651 /* SRAM */ 652 sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index); 653 if (!memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, 654 errp)) { 655 return; 656 } 657 memory_region_add_subregion(s->memory, 658 sc->memmap[ASPEED_DEV_SRAM], &s->sram); 659 660 /* SCU */ 661 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { 662 return; 663 } 664 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]); 665 666 /* SCU1 */ 667 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scuio), errp)) { 668 return; 669 } 670 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scuio), 0, 671 sc->memmap[ASPEED_DEV_SCUIO]); 672 673 /* UART */ 674 if (!aspeed_soc_uart_realize(s, errp)) { 675 return; 676 } 677 678 /* FMC, The number of CS is set at the board level */ 679 object_property_set_int(OBJECT(&s->fmc), "dram-base", 680 sc->memmap[ASPEED_DEV_SDRAM], 681 &error_abort); 682 object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr), 683 &error_abort); 684 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) { 685 return; 686 } 687 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]); 688 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 1, 689 ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base); 690 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, 691 aspeed_soc_get_irq(s, ASPEED_DEV_FMC)); 692 693 /* Set up an alias on the FMC CE0 region (boot default) */ 694 MemoryRegion *fmc0_mmio = &s->fmc.flashes[0].mmio; 695 memory_region_init_alias(&s->spi_boot, OBJECT(s), "aspeed.spi_boot", 696 fmc0_mmio, 0, memory_region_size(fmc0_mmio)); 697 memory_region_add_subregion(&s->spi_boot_container, 0x0, &s->spi_boot); 698 699 /* SPI */ 700 for (i = 0; i < sc->spis_num; i++) { 701 object_property_set_link(OBJECT(&s->spi[i]), "dram", 702 OBJECT(s->dram_mr), &error_abort); 703 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { 704 return; 705 } 706 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 0, 707 sc->memmap[ASPEED_DEV_SPI0 + i]); 708 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 1, 709 ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base); 710 } 711 712 /* 713 * SDMC - SDRAM Memory Controller 714 * The SDMC controller is unlocked at SPL stage. 715 * At present, only supports to emulate booting 716 * start from u-boot stage. Set SDMC controller 717 * unlocked by default. It is a temporarily solution. 718 */ 719 object_property_set_bool(OBJECT(&s->sdmc), "unlocked", true, 720 &error_abort); 721 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) { 722 return; 723 } 724 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdmc), 0, 725 sc->memmap[ASPEED_DEV_SDMC]); 726 727 /* RAM */ 728 if (!aspeed_soc_ast2700_dram_init(dev, errp)) { 729 return; 730 } 731 732 /* Net */ 733 for (i = 0; i < sc->macs_num; i++) { 734 object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true, 735 &error_abort); 736 object_property_set_bool(OBJECT(&s->ftgmac100[i]), "dma64", true, 737 &error_abort); 738 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) { 739 return; 740 } 741 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 742 sc->memmap[ASPEED_DEV_ETH1 + i]); 743 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 744 aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i)); 745 746 object_property_set_link(OBJECT(&s->mii[i]), "nic", 747 OBJECT(&s->ftgmac100[i]), &error_abort); 748 if (!sysbus_realize(SYS_BUS_DEVICE(&s->mii[i]), errp)) { 749 return; 750 } 751 752 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->mii[i]), 0, 753 sc->memmap[ASPEED_DEV_MII1 + i]); 754 } 755 756 /* Watch dog */ 757 for (i = 0; i < sc->wdts_num; i++) { 758 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); 759 hwaddr wdt_offset = sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize; 760 761 object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu), 762 &error_abort); 763 if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) { 764 return; 765 } 766 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offset); 767 } 768 769 /* SLI */ 770 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sli), errp)) { 771 return; 772 } 773 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sli), 0, sc->memmap[ASPEED_DEV_SLI]); 774 775 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sliio), errp)) { 776 return; 777 } 778 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sliio), 0, 779 sc->memmap[ASPEED_DEV_SLIIO]); 780 781 /* ADC */ 782 if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) { 783 return; 784 } 785 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]); 786 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0, 787 aspeed_soc_get_irq(s, ASPEED_DEV_ADC)); 788 789 /* I2C */ 790 object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr), 791 &error_abort); 792 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) { 793 return; 794 } 795 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]); 796 for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) { 797 /* 798 * The AST2700 I2C controller has one source INTC per bus. 799 * 800 * For AST2700 A0: 801 * I2C bus interrupts are connected to the OR gate from bit 0 to bit 802 * 15, and the OR gate output pin is connected to the input pin of 803 * GICINT130 of INTC (CPU Die). Then, the output pin is connected to 804 * the GIC. 805 * 806 * For AST2700 A1: 807 * I2C bus interrupts are connected to the OR gate from bit 0 to bit 808 * 15, and the OR gate output pin is connected to the input pin of 809 * GICINT194 of INTCIO (IO Die). Then, the output pin is connected 810 * to the INTC (CPU Die) input pin, and its output pin is connected 811 * to the GIC. 812 * 813 * I2C bus 0 is connected to the OR gate at bit 0. 814 * I2C bus 15 is connected to the OR gate at bit 15. 815 */ 816 irq = aspeed_soc_ast2700_get_irq_index(s, ASPEED_DEV_I2C, i); 817 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq); 818 } 819 820 /* GPIO */ 821 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { 822 return; 823 } 824 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio), 0, 825 sc->memmap[ASPEED_DEV_GPIO]); 826 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, 827 aspeed_soc_get_irq(s, ASPEED_DEV_GPIO)); 828 829 /* RTC */ 830 if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) { 831 return; 832 } 833 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_RTC]); 834 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, 835 aspeed_soc_get_irq(s, ASPEED_DEV_RTC)); 836 837 /* SDHCI */ 838 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) { 839 return; 840 } 841 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdhci), 0, 842 sc->memmap[ASPEED_DEV_SDHCI]); 843 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, 844 aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI)); 845 846 /* eMMC */ 847 if (!sysbus_realize(SYS_BUS_DEVICE(&s->emmc), errp)) { 848 return; 849 } 850 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->emmc), 0, 851 sc->memmap[ASPEED_DEV_EMMC]); 852 sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0, 853 aspeed_soc_get_irq(s, ASPEED_DEV_EMMC)); 854 855 /* Timer */ 856 object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu), 857 &error_abort); 858 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) { 859 return; 860 } 861 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->timerctrl), 0, 862 sc->memmap[ASPEED_DEV_TIMER1]); 863 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) { 864 irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i); 865 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); 866 } 867 868 /* HACE */ 869 object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(s->dram_mr), 870 &error_abort); 871 if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) { 872 return; 873 } 874 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->hace), 0, 875 sc->memmap[ASPEED_DEV_HACE]); 876 sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0, 877 aspeed_soc_get_irq(s, ASPEED_DEV_HACE)); 878 879 create_unimplemented_device("ast2700.dpmcu", 0x11000000, 0x40000); 880 create_unimplemented_device("ast2700.iomem0", 0x12000000, 0x01000000); 881 create_unimplemented_device("ast2700.iomem1", 0x14000000, 0x01000000); 882 create_unimplemented_device("ast2700.ltpi", 0x30000000, 0x1000000); 883 create_unimplemented_device("ast2700.io", 0x0, 0x4000000); 884 } 885 886 static void aspeed_soc_ast2700a0_class_init(ObjectClass *oc, void *data) 887 { 888 static const char * const valid_cpu_types[] = { 889 ARM_CPU_TYPE_NAME("cortex-a35"), 890 NULL 891 }; 892 DeviceClass *dc = DEVICE_CLASS(oc); 893 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); 894 895 /* Reason: The Aspeed SoC can only be instantiated from a board */ 896 dc->user_creatable = false; 897 dc->realize = aspeed_soc_ast2700_realize; 898 899 sc->valid_cpu_types = valid_cpu_types; 900 sc->silicon_rev = AST2700_A0_SILICON_REV; 901 sc->sram_size = 0x20000; 902 sc->spis_num = 3; 903 sc->wdts_num = 8; 904 sc->macs_num = 1; 905 sc->uarts_num = 13; 906 sc->num_cpus = 4; 907 sc->uarts_base = ASPEED_DEV_UART0; 908 sc->irqmap = aspeed_soc_ast2700a0_irqmap; 909 sc->memmap = aspeed_soc_ast2700_memmap; 910 sc->get_irq = aspeed_soc_ast2700_get_irq; 911 } 912 913 static void aspeed_soc_ast2700a1_class_init(ObjectClass *oc, void *data) 914 { 915 static const char * const valid_cpu_types[] = { 916 ARM_CPU_TYPE_NAME("cortex-a35"), 917 NULL 918 }; 919 DeviceClass *dc = DEVICE_CLASS(oc); 920 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); 921 922 /* Reason: The Aspeed SoC can only be instantiated from a board */ 923 dc->user_creatable = false; 924 dc->realize = aspeed_soc_ast2700_realize; 925 926 sc->valid_cpu_types = valid_cpu_types; 927 sc->silicon_rev = AST2700_A1_SILICON_REV; 928 sc->sram_size = 0x20000; 929 sc->spis_num = 3; 930 sc->wdts_num = 8; 931 sc->macs_num = 3; 932 sc->uarts_num = 13; 933 sc->num_cpus = 4; 934 sc->uarts_base = ASPEED_DEV_UART0; 935 sc->irqmap = aspeed_soc_ast2700a1_irqmap; 936 sc->memmap = aspeed_soc_ast2700_memmap; 937 sc->get_irq = aspeed_soc_ast2700_get_irq; 938 } 939 940 static const TypeInfo aspeed_soc_ast27x0_types[] = { 941 { 942 .name = TYPE_ASPEED27X0_SOC, 943 .parent = TYPE_ASPEED_SOC, 944 .instance_size = sizeof(Aspeed27x0SoCState), 945 .abstract = true, 946 }, { 947 .name = "ast2700-a0", 948 .parent = TYPE_ASPEED27X0_SOC, 949 .instance_init = aspeed_soc_ast2700_init, 950 .class_init = aspeed_soc_ast2700a0_class_init, 951 }, 952 { 953 .name = "ast2700-a1", 954 .parent = TYPE_ASPEED27X0_SOC, 955 .instance_init = aspeed_soc_ast2700_init, 956 .class_init = aspeed_soc_ast2700a1_class_init, 957 }, 958 }; 959 960 DEFINE_TYPES(aspeed_soc_ast27x0_types) 961