1 /* 2 * ASPEED SoC 27x0 family 3 * 4 * Copyright (C) 2024 ASPEED Technology Inc. 5 * 6 * This code is licensed under the GPL version 2 or later. See 7 * the COPYING file in the top-level directory. 8 * 9 * Implementation extracted from the AST2600 and adapted for AST27x0. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qapi/error.h" 14 #include "hw/misc/unimp.h" 15 #include "hw/arm/aspeed_soc.h" 16 #include "hw/arm/bsa.h" 17 #include "qemu/module.h" 18 #include "qemu/error-report.h" 19 #include "hw/i2c/aspeed_i2c.h" 20 #include "net/net.h" 21 #include "system/system.h" 22 #include "hw/intc/arm_gicv3.h" 23 #include "qobject/qlist.h" 24 #include "qemu/log.h" 25 26 static const hwaddr aspeed_soc_ast2700_memmap[] = { 27 [ASPEED_DEV_VBOOTROM] = 0x00000000, 28 [ASPEED_DEV_SRAM] = 0x10000000, 29 [ASPEED_DEV_EHCI1] = 0x12061000, 30 [ASPEED_DEV_EHCI2] = 0x12063000, 31 [ASPEED_DEV_HACE] = 0x12070000, 32 [ASPEED_DEV_EMMC] = 0x12090000, 33 [ASPEED_DEV_INTC] = 0x12100000, 34 [ASPEED_GIC_DIST] = 0x12200000, 35 [ASPEED_GIC_REDIST] = 0x12280000, 36 [ASPEED_DEV_SDMC] = 0x12C00000, 37 [ASPEED_DEV_SCU] = 0x12C02000, 38 [ASPEED_DEV_RTC] = 0x12C0F000, 39 [ASPEED_DEV_TIMER1] = 0x12C10000, 40 [ASPEED_DEV_SLI] = 0x12C17000, 41 [ASPEED_DEV_UART4] = 0X12C1A000, 42 [ASPEED_DEV_FMC] = 0x14000000, 43 [ASPEED_DEV_SPI0] = 0x14010000, 44 [ASPEED_DEV_SPI1] = 0x14020000, 45 [ASPEED_DEV_SPI2] = 0x14030000, 46 [ASPEED_DEV_MII1] = 0x14040000, 47 [ASPEED_DEV_MII2] = 0x14040008, 48 [ASPEED_DEV_MII3] = 0x14040010, 49 [ASPEED_DEV_ETH1] = 0x14050000, 50 [ASPEED_DEV_ETH2] = 0x14060000, 51 [ASPEED_DEV_ETH3] = 0x14070000, 52 [ASPEED_DEV_SDHCI] = 0x14080000, 53 [ASPEED_DEV_EHCI3] = 0x14121000, 54 [ASPEED_DEV_EHCI4] = 0x14123000, 55 [ASPEED_DEV_ADC] = 0x14C00000, 56 [ASPEED_DEV_SCUIO] = 0x14C02000, 57 [ASPEED_DEV_GPIO] = 0x14C0B000, 58 [ASPEED_DEV_I2C] = 0x14C0F000, 59 [ASPEED_DEV_INTCIO] = 0x14C18000, 60 [ASPEED_DEV_SLIIO] = 0x14C1E000, 61 [ASPEED_DEV_VUART] = 0X14C30000, 62 [ASPEED_DEV_UART0] = 0X14C33000, 63 [ASPEED_DEV_UART1] = 0X14C33100, 64 [ASPEED_DEV_UART2] = 0X14C33200, 65 [ASPEED_DEV_UART3] = 0X14C33300, 66 [ASPEED_DEV_UART5] = 0X14C33400, 67 [ASPEED_DEV_UART6] = 0X14C33500, 68 [ASPEED_DEV_UART7] = 0X14C33600, 69 [ASPEED_DEV_UART8] = 0X14C33700, 70 [ASPEED_DEV_UART9] = 0X14C33800, 71 [ASPEED_DEV_UART10] = 0X14C33900, 72 [ASPEED_DEV_UART11] = 0X14C33A00, 73 [ASPEED_DEV_UART12] = 0X14C33B00, 74 [ASPEED_DEV_WDT] = 0x14C37000, 75 [ASPEED_DEV_SPI_BOOT] = 0x100000000, 76 [ASPEED_DEV_SDRAM] = 0x400000000, 77 }; 78 79 #define AST2700_MAX_IRQ 256 80 81 /* Shared Peripheral Interrupt values below are offset by -32 from datasheet */ 82 static const int aspeed_soc_ast2700a0_irqmap[] = { 83 [ASPEED_DEV_SDMC] = 0, 84 [ASPEED_DEV_HACE] = 4, 85 [ASPEED_DEV_XDMA] = 5, 86 [ASPEED_DEV_UART4] = 8, 87 [ASPEED_DEV_SCU] = 12, 88 [ASPEED_DEV_RTC] = 13, 89 [ASPEED_DEV_EMMC] = 15, 90 [ASPEED_DEV_TIMER1] = 16, 91 [ASPEED_DEV_TIMER2] = 17, 92 [ASPEED_DEV_TIMER3] = 18, 93 [ASPEED_DEV_TIMER4] = 19, 94 [ASPEED_DEV_TIMER5] = 20, 95 [ASPEED_DEV_TIMER6] = 21, 96 [ASPEED_DEV_TIMER7] = 22, 97 [ASPEED_DEV_TIMER8] = 23, 98 [ASPEED_DEV_DP] = 28, 99 [ASPEED_DEV_EHCI1] = 33, 100 [ASPEED_DEV_EHCI2] = 37, 101 [ASPEED_DEV_LPC] = 128, 102 [ASPEED_DEV_IBT] = 128, 103 [ASPEED_DEV_KCS] = 128, 104 [ASPEED_DEV_ADC] = 130, 105 [ASPEED_DEV_GPIO] = 130, 106 [ASPEED_DEV_I2C] = 130, 107 [ASPEED_DEV_FMC] = 131, 108 [ASPEED_DEV_WDT] = 131, 109 [ASPEED_DEV_PWM] = 131, 110 [ASPEED_DEV_I3C] = 131, 111 [ASPEED_DEV_UART0] = 132, 112 [ASPEED_DEV_UART1] = 132, 113 [ASPEED_DEV_UART2] = 132, 114 [ASPEED_DEV_UART3] = 132, 115 [ASPEED_DEV_UART5] = 132, 116 [ASPEED_DEV_UART6] = 132, 117 [ASPEED_DEV_UART7] = 132, 118 [ASPEED_DEV_UART8] = 132, 119 [ASPEED_DEV_UART9] = 132, 120 [ASPEED_DEV_UART10] = 132, 121 [ASPEED_DEV_UART11] = 132, 122 [ASPEED_DEV_UART12] = 132, 123 [ASPEED_DEV_ETH1] = 132, 124 [ASPEED_DEV_ETH2] = 132, 125 [ASPEED_DEV_ETH3] = 132, 126 [ASPEED_DEV_PECI] = 133, 127 [ASPEED_DEV_SDHCI] = 133, 128 }; 129 130 static const int aspeed_soc_ast2700a1_irqmap[] = { 131 [ASPEED_DEV_SDMC] = 0, 132 [ASPEED_DEV_HACE] = 4, 133 [ASPEED_DEV_XDMA] = 5, 134 [ASPEED_DEV_UART4] = 8, 135 [ASPEED_DEV_SCU] = 12, 136 [ASPEED_DEV_RTC] = 13, 137 [ASPEED_DEV_EMMC] = 15, 138 [ASPEED_DEV_TIMER1] = 16, 139 [ASPEED_DEV_TIMER2] = 17, 140 [ASPEED_DEV_TIMER3] = 18, 141 [ASPEED_DEV_TIMER4] = 19, 142 [ASPEED_DEV_TIMER5] = 20, 143 [ASPEED_DEV_TIMER6] = 21, 144 [ASPEED_DEV_TIMER7] = 22, 145 [ASPEED_DEV_TIMER8] = 23, 146 [ASPEED_DEV_DP] = 28, 147 [ASPEED_DEV_EHCI1] = 33, 148 [ASPEED_DEV_EHCI2] = 37, 149 [ASPEED_DEV_LPC] = 192, 150 [ASPEED_DEV_IBT] = 192, 151 [ASPEED_DEV_KCS] = 192, 152 [ASPEED_DEV_I2C] = 194, 153 [ASPEED_DEV_ADC] = 194, 154 [ASPEED_DEV_GPIO] = 194, 155 [ASPEED_DEV_FMC] = 195, 156 [ASPEED_DEV_WDT] = 195, 157 [ASPEED_DEV_PWM] = 195, 158 [ASPEED_DEV_I3C] = 195, 159 [ASPEED_DEV_UART0] = 196, 160 [ASPEED_DEV_UART1] = 196, 161 [ASPEED_DEV_UART2] = 196, 162 [ASPEED_DEV_UART3] = 196, 163 [ASPEED_DEV_UART5] = 196, 164 [ASPEED_DEV_UART6] = 196, 165 [ASPEED_DEV_UART7] = 196, 166 [ASPEED_DEV_UART8] = 196, 167 [ASPEED_DEV_UART9] = 196, 168 [ASPEED_DEV_UART10] = 196, 169 [ASPEED_DEV_UART11] = 196, 170 [ASPEED_DEV_UART12] = 196, 171 [ASPEED_DEV_ETH1] = 196, 172 [ASPEED_DEV_ETH2] = 196, 173 [ASPEED_DEV_ETH3] = 196, 174 [ASPEED_DEV_PECI] = 197, 175 [ASPEED_DEV_SDHCI] = 197, 176 }; 177 178 /* GICINT 128 */ 179 /* GICINT 192 */ 180 static const int ast2700_gic128_gic192_intcmap[] = { 181 [ASPEED_DEV_LPC] = 0, 182 [ASPEED_DEV_IBT] = 2, 183 [ASPEED_DEV_KCS] = 4, 184 }; 185 186 /* GICINT 129 */ 187 /* GICINT 193 */ 188 189 /* GICINT 130 */ 190 /* GICINT 194 */ 191 static const int ast2700_gic130_gic194_intcmap[] = { 192 [ASPEED_DEV_I2C] = 0, 193 [ASPEED_DEV_ADC] = 16, 194 [ASPEED_DEV_GPIO] = 18, 195 }; 196 197 /* GICINT 131 */ 198 /* GICINT 195 */ 199 static const int ast2700_gic131_gic195_intcmap[] = { 200 [ASPEED_DEV_I3C] = 0, 201 [ASPEED_DEV_WDT] = 16, 202 [ASPEED_DEV_FMC] = 25, 203 [ASPEED_DEV_PWM] = 29, 204 }; 205 206 /* GICINT 132 */ 207 /* GICINT 196 */ 208 static const int ast2700_gic132_gic196_intcmap[] = { 209 [ASPEED_DEV_ETH1] = 0, 210 [ASPEED_DEV_ETH2] = 1, 211 [ASPEED_DEV_ETH3] = 2, 212 [ASPEED_DEV_UART0] = 7, 213 [ASPEED_DEV_UART1] = 8, 214 [ASPEED_DEV_UART2] = 9, 215 [ASPEED_DEV_UART3] = 10, 216 [ASPEED_DEV_UART5] = 11, 217 [ASPEED_DEV_UART6] = 12, 218 [ASPEED_DEV_UART7] = 13, 219 [ASPEED_DEV_UART8] = 14, 220 [ASPEED_DEV_UART9] = 15, 221 [ASPEED_DEV_UART10] = 16, 222 [ASPEED_DEV_UART11] = 17, 223 [ASPEED_DEV_UART12] = 18, 224 [ASPEED_DEV_EHCI3] = 28, 225 [ASPEED_DEV_EHCI4] = 29, 226 }; 227 228 /* GICINT 133 */ 229 /* GICINT 197 */ 230 static const int ast2700_gic133_gic197_intcmap[] = { 231 [ASPEED_DEV_SDHCI] = 1, 232 [ASPEED_DEV_PECI] = 4, 233 }; 234 235 /* GICINT 128 ~ 136 */ 236 /* GICINT 192 ~ 201 */ 237 struct gic_intc_irq_info { 238 int irq; 239 int intc_idx; 240 int orgate_idx; 241 const int *ptr; 242 }; 243 244 static const struct gic_intc_irq_info ast2700_gic_intcmap[] = { 245 {192, 1, 0, ast2700_gic128_gic192_intcmap}, 246 {193, 1, 1, NULL}, 247 {194, 1, 2, ast2700_gic130_gic194_intcmap}, 248 {195, 1, 3, ast2700_gic131_gic195_intcmap}, 249 {196, 1, 4, ast2700_gic132_gic196_intcmap}, 250 {197, 1, 5, ast2700_gic133_gic197_intcmap}, 251 {198, 1, 6, NULL}, 252 {199, 1, 7, NULL}, 253 {200, 1, 8, NULL}, 254 {201, 1, 9, NULL}, 255 {128, 0, 1, ast2700_gic128_gic192_intcmap}, 256 {129, 0, 2, NULL}, 257 {130, 0, 3, ast2700_gic130_gic194_intcmap}, 258 {131, 0, 4, ast2700_gic131_gic195_intcmap}, 259 {132, 0, 5, ast2700_gic132_gic196_intcmap}, 260 {133, 0, 6, ast2700_gic133_gic197_intcmap}, 261 {134, 0, 7, NULL}, 262 {135, 0, 8, NULL}, 263 {136, 0, 9, NULL}, 264 }; 265 266 static qemu_irq aspeed_soc_ast2700_get_irq(AspeedSoCState *s, int dev) 267 { 268 Aspeed27x0SoCState *a = ASPEED27X0_SOC(s); 269 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 270 int or_idx; 271 int idx; 272 int i; 273 274 for (i = 0; i < ARRAY_SIZE(ast2700_gic_intcmap); i++) { 275 if (sc->irqmap[dev] == ast2700_gic_intcmap[i].irq) { 276 assert(ast2700_gic_intcmap[i].ptr); 277 or_idx = ast2700_gic_intcmap[i].orgate_idx; 278 idx = ast2700_gic_intcmap[i].intc_idx; 279 return qdev_get_gpio_in(DEVICE(&a->intc[idx].orgates[or_idx]), 280 ast2700_gic_intcmap[i].ptr[dev]); 281 } 282 } 283 284 return qdev_get_gpio_in(DEVICE(&a->gic), sc->irqmap[dev]); 285 } 286 287 static qemu_irq aspeed_soc_ast2700_get_irq_index(AspeedSoCState *s, int dev, 288 int index) 289 { 290 Aspeed27x0SoCState *a = ASPEED27X0_SOC(s); 291 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 292 int or_idx; 293 int idx; 294 int i; 295 296 for (i = 0; i < ARRAY_SIZE(ast2700_gic_intcmap); i++) { 297 if (sc->irqmap[dev] == ast2700_gic_intcmap[i].irq) { 298 assert(ast2700_gic_intcmap[i].ptr); 299 or_idx = ast2700_gic_intcmap[i].orgate_idx; 300 idx = ast2700_gic_intcmap[i].intc_idx; 301 return qdev_get_gpio_in(DEVICE(&a->intc[idx].orgates[or_idx]), 302 ast2700_gic_intcmap[i].ptr[dev] + index); 303 } 304 } 305 306 /* 307 * Invalid OR gate index, device IRQ should be between 128 to 136 308 * and 192 to 201. 309 */ 310 g_assert_not_reached(); 311 } 312 313 static uint64_t aspeed_ram_capacity_read(void *opaque, hwaddr addr, 314 unsigned int size) 315 { 316 qemu_log_mask(LOG_GUEST_ERROR, 317 "%s: DRAM read out of ram size, addr:0x%" PRIx64 "\n", 318 __func__, addr); 319 return 0; 320 } 321 322 static void aspeed_ram_capacity_write(void *opaque, hwaddr addr, uint64_t data, 323 unsigned int size) 324 { 325 AspeedSoCState *s = ASPEED_SOC(opaque); 326 ram_addr_t ram_size; 327 MemTxResult result; 328 329 ram_size = object_property_get_uint(OBJECT(&s->sdmc), "ram-size", 330 &error_abort); 331 332 assert(ram_size > 0); 333 334 /* 335 * Emulate ddr capacity hardware behavior. 336 * If writes the data to the address which is beyond the ram size, 337 * it would write the data to the "address % ram_size". 338 */ 339 result = address_space_write(&s->dram_as, addr % ram_size, 340 MEMTXATTRS_UNSPECIFIED, &data, 4); 341 if (result != MEMTX_OK) { 342 qemu_log_mask(LOG_GUEST_ERROR, 343 "%s: DRAM write failed, addr:0x%" HWADDR_PRIx 344 ", data :0x%" PRIx64 "\n", 345 __func__, addr % ram_size, data); 346 } 347 } 348 349 static const MemoryRegionOps aspeed_ram_capacity_ops = { 350 .read = aspeed_ram_capacity_read, 351 .write = aspeed_ram_capacity_write, 352 .endianness = DEVICE_LITTLE_ENDIAN, 353 .valid = { 354 .min_access_size = 1, 355 .max_access_size = 8, 356 }, 357 }; 358 359 /* 360 * SDMC should be realized first to get correct RAM size and max size 361 * values 362 */ 363 static bool aspeed_soc_ast2700_dram_init(DeviceState *dev, Error **errp) 364 { 365 ram_addr_t ram_size, max_ram_size; 366 Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev); 367 AspeedSoCState *s = ASPEED_SOC(dev); 368 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 369 370 ram_size = object_property_get_uint(OBJECT(&s->sdmc), "ram-size", 371 &error_abort); 372 max_ram_size = object_property_get_uint(OBJECT(&s->sdmc), "max-ram-size", 373 &error_abort); 374 375 memory_region_init(&s->dram_container, OBJECT(s), "ram-container", 376 ram_size); 377 memory_region_add_subregion(&s->dram_container, 0, s->dram_mr); 378 address_space_init(&s->dram_as, s->dram_mr, "dram"); 379 380 /* 381 * Add a memory region beyond the RAM region to emulate 382 * ddr capacity hardware behavior. 383 */ 384 if (ram_size < max_ram_size) { 385 memory_region_init_io(&a->dram_empty, OBJECT(s), 386 &aspeed_ram_capacity_ops, s, 387 "ram-empty", max_ram_size - ram_size); 388 389 memory_region_add_subregion(s->memory, 390 sc->memmap[ASPEED_DEV_SDRAM] + ram_size, 391 &a->dram_empty); 392 } 393 394 memory_region_add_subregion(s->memory, 395 sc->memmap[ASPEED_DEV_SDRAM], &s->dram_container); 396 return true; 397 } 398 399 static void aspeed_soc_ast2700_init(Object *obj) 400 { 401 Aspeed27x0SoCState *a = ASPEED27X0_SOC(obj); 402 AspeedSoCState *s = ASPEED_SOC(obj); 403 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 404 int i; 405 char socname[8]; 406 char typename[64]; 407 408 if (sscanf(object_get_typename(obj), "%7s", socname) != 1) { 409 g_assert_not_reached(); 410 } 411 412 for (i = 0; i < sc->num_cpus; i++) { 413 object_initialize_child(obj, "cpu[*]", &a->cpu[i], 414 aspeed_soc_cpu_type(sc)); 415 } 416 417 object_initialize_child(obj, "gic", &a->gic, gicv3_class_name()); 418 419 object_initialize_child(obj, "scu", &s->scu, TYPE_ASPEED_2700_SCU); 420 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", 421 sc->silicon_rev); 422 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), 423 "hw-strap1"); 424 object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu), 425 "hw-prot-key"); 426 427 object_initialize_child(obj, "scuio", &s->scuio, TYPE_ASPEED_2700_SCUIO); 428 qdev_prop_set_uint32(DEVICE(&s->scuio), "silicon-rev", 429 sc->silicon_rev); 430 /* 431 * There is one hw-strap1 register in the SCU (CPU DIE) and another 432 * hw-strap1 register in the SCUIO (IO DIE). To reuse the current design 433 * of hw-strap, hw-strap1 is assigned to the SCU and sets the value in the 434 * SCU hw-strap1 register, while hw-strap2 is assigned to the SCUIO and 435 * sets the value in the SCUIO hw-strap1 register. 436 */ 437 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scuio), 438 "hw-strap1"); 439 440 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); 441 object_initialize_child(obj, "fmc", &s->fmc, typename); 442 443 for (i = 0; i < sc->spis_num; i++) { 444 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i, socname); 445 object_initialize_child(obj, "spi[*]", &s->spi[i], typename); 446 } 447 448 for (i = 0; i < sc->ehcis_num; i++) { 449 object_initialize_child(obj, "ehci[*]", &s->ehci[i], 450 TYPE_PLATFORM_EHCI); 451 } 452 453 snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname); 454 object_initialize_child(obj, "sdmc", &s->sdmc, typename); 455 object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), 456 "ram-size"); 457 458 for (i = 0; i < sc->wdts_num; i++) { 459 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); 460 object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename); 461 } 462 463 for (i = 0; i < sc->macs_num; i++) { 464 object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i], 465 TYPE_FTGMAC100); 466 467 object_initialize_child(obj, "mii[*]", &s->mii[i], TYPE_ASPEED_MII); 468 } 469 470 for (i = 0; i < sc->uarts_num; i++) { 471 object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM); 472 } 473 474 object_initialize_child(obj, "sli", &s->sli, TYPE_ASPEED_2700_SLI); 475 object_initialize_child(obj, "sliio", &s->sliio, TYPE_ASPEED_2700_SLIIO); 476 object_initialize_child(obj, "intc", &a->intc[0], TYPE_ASPEED_2700_INTC); 477 object_initialize_child(obj, "intcio", &a->intc[1], 478 TYPE_ASPEED_2700_INTCIO); 479 480 snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname); 481 object_initialize_child(obj, "adc", &s->adc, typename); 482 483 snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); 484 object_initialize_child(obj, "i2c", &s->i2c, typename); 485 486 snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); 487 object_initialize_child(obj, "gpio", &s->gpio, typename); 488 489 object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC); 490 491 snprintf(typename, sizeof(typename), "aspeed.sdhci-%s", socname); 492 object_initialize_child(obj, "sd-controller", &s->sdhci, typename); 493 object_property_set_int(OBJECT(&s->sdhci), "num-slots", 1, &error_abort); 494 495 /* Init sd card slot class here so that they're under the correct parent */ 496 object_initialize_child(obj, "sd-controller.sdhci", 497 &s->sdhci.slots[0], TYPE_SYSBUS_SDHCI); 498 499 object_initialize_child(obj, "emmc-controller", &s->emmc, typename); 500 object_property_set_int(OBJECT(&s->emmc), "num-slots", 1, &error_abort); 501 502 object_initialize_child(obj, "emmc-controller.sdhci", &s->emmc.slots[0], 503 TYPE_SYSBUS_SDHCI); 504 505 snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname); 506 object_initialize_child(obj, "timerctrl", &s->timerctrl, typename); 507 508 snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname); 509 object_initialize_child(obj, "hace", &s->hace, typename); 510 } 511 512 /* 513 * ASPEED ast2700 has 0x0 as cluster ID 514 * 515 * https://developer.arm.com/documentation/100236/0100/register-descriptions/aarch64-system-registers/multiprocessor-affinity-register--el1 516 */ 517 static uint64_t aspeed_calc_affinity(int cpu) 518 { 519 return (0x0 << ARM_AFF1_SHIFT) | cpu; 520 } 521 522 static bool aspeed_soc_ast2700_gic_realize(DeviceState *dev, Error **errp) 523 { 524 Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev); 525 AspeedSoCState *s = ASPEED_SOC(dev); 526 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 527 SysBusDevice *gicbusdev; 528 DeviceState *gicdev; 529 QList *redist_region_count; 530 int i; 531 532 gicbusdev = SYS_BUS_DEVICE(&a->gic); 533 gicdev = DEVICE(&a->gic); 534 qdev_prop_set_uint32(gicdev, "revision", 3); 535 qdev_prop_set_uint32(gicdev, "num-cpu", sc->num_cpus); 536 qdev_prop_set_uint32(gicdev, "num-irq", AST2700_MAX_IRQ + GIC_INTERNAL); 537 538 redist_region_count = qlist_new(); 539 qlist_append_int(redist_region_count, sc->num_cpus); 540 qdev_prop_set_array(gicdev, "redist-region-count", redist_region_count); 541 542 if (!sysbus_realize(gicbusdev, errp)) { 543 return false; 544 } 545 sysbus_mmio_map(gicbusdev, 0, sc->memmap[ASPEED_GIC_DIST]); 546 sysbus_mmio_map(gicbusdev, 1, sc->memmap[ASPEED_GIC_REDIST]); 547 548 for (i = 0; i < sc->num_cpus; i++) { 549 DeviceState *cpudev = DEVICE(&a->cpu[i]); 550 int intidbase = AST2700_MAX_IRQ + i * GIC_INTERNAL; 551 552 const int timer_irq[] = { 553 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, 554 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, 555 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, 556 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, 557 }; 558 int j; 559 560 for (j = 0; j < ARRAY_SIZE(timer_irq); j++) { 561 qdev_connect_gpio_out(cpudev, j, 562 qdev_get_gpio_in(gicdev, intidbase + timer_irq[j])); 563 } 564 565 qemu_irq irq = qdev_get_gpio_in(gicdev, 566 intidbase + ARCH_GIC_MAINT_IRQ); 567 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 568 0, irq); 569 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, 570 qdev_get_gpio_in(gicdev, intidbase + VIRTUAL_PMU_IRQ)); 571 572 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 573 sysbus_connect_irq(gicbusdev, i + sc->num_cpus, 574 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 575 sysbus_connect_irq(gicbusdev, i + 2 * sc->num_cpus, 576 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 577 sysbus_connect_irq(gicbusdev, i + 3 * sc->num_cpus, 578 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 579 sysbus_connect_irq(gicbusdev, i + 4 * sc->num_cpus, 580 qdev_get_gpio_in(cpudev, ARM_CPU_NMI)); 581 sysbus_connect_irq(gicbusdev, i + 5 * sc->num_cpus, 582 qdev_get_gpio_in(cpudev, ARM_CPU_VINMI)); 583 } 584 585 return true; 586 } 587 588 static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp) 589 { 590 int i; 591 Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev); 592 AspeedSoCState *s = ASPEED_SOC(dev); 593 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 594 AspeedINTCClass *ic = ASPEED_INTC_GET_CLASS(&a->intc[0]); 595 AspeedINTCClass *icio = ASPEED_INTC_GET_CLASS(&a->intc[1]); 596 g_autofree char *name = NULL; 597 qemu_irq irq; 598 599 /* Default boot region (SPI memory or ROMs) */ 600 memory_region_init(&s->spi_boot_container, OBJECT(s), 601 "aspeed.spi_boot_container", 0x400000000); 602 memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SPI_BOOT], 603 &s->spi_boot_container); 604 605 /* CPU */ 606 for (i = 0; i < sc->num_cpus; i++) { 607 object_property_set_int(OBJECT(&a->cpu[i]), "mp-affinity", 608 aspeed_calc_affinity(i), &error_abort); 609 610 object_property_set_int(OBJECT(&a->cpu[i]), "cntfrq", 1125000000, 611 &error_abort); 612 object_property_set_link(OBJECT(&a->cpu[i]), "memory", 613 OBJECT(s->memory), &error_abort); 614 615 if (!qdev_realize(DEVICE(&a->cpu[i]), NULL, errp)) { 616 return; 617 } 618 } 619 620 /* GIC */ 621 if (!aspeed_soc_ast2700_gic_realize(dev, errp)) { 622 return; 623 } 624 625 /* INTC */ 626 if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[0]), errp)) { 627 return; 628 } 629 630 aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc[0]), 0, 631 sc->memmap[ASPEED_DEV_INTC]); 632 633 /* INTCIO */ 634 if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[1]), errp)) { 635 return; 636 } 637 638 aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc[1]), 0, 639 sc->memmap[ASPEED_DEV_INTCIO]); 640 641 /* irq sources -> orgates -> INTC */ 642 for (i = 0; i < ic->num_inpins; i++) { 643 qdev_connect_gpio_out(DEVICE(&a->intc[0].orgates[i]), 0, 644 qdev_get_gpio_in(DEVICE(&a->intc[0]), i)); 645 } 646 647 /* INTC -> GIC192 - GIC201 */ 648 /* INTC -> GIC128 - GIC136 */ 649 for (i = 0; i < ic->num_outpins; i++) { 650 sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc[0]), i, 651 qdev_get_gpio_in(DEVICE(&a->gic), 652 ast2700_gic_intcmap[i].irq)); 653 } 654 655 /* irq source -> orgates -> INTCIO */ 656 for (i = 0; i < icio->num_inpins; i++) { 657 qdev_connect_gpio_out(DEVICE(&a->intc[1].orgates[i]), 0, 658 qdev_get_gpio_in(DEVICE(&a->intc[1]), i)); 659 } 660 661 /* INTCIO -> INTC */ 662 for (i = 0; i < icio->num_outpins; i++) { 663 sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc[1]), i, 664 qdev_get_gpio_in(DEVICE(&a->intc[0].orgates[0]), i)); 665 } 666 667 /* SRAM */ 668 name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index); 669 if (!memory_region_init_ram(&s->sram, OBJECT(s), name, sc->sram_size, 670 errp)) { 671 return; 672 } 673 memory_region_add_subregion(s->memory, 674 sc->memmap[ASPEED_DEV_SRAM], &s->sram); 675 676 /* VBOOTROM */ 677 if (!memory_region_init_ram(&s->vbootrom, OBJECT(s), "aspeed.vbootrom", 678 0x20000, errp)) { 679 return; 680 } 681 memory_region_add_subregion(s->memory, 682 sc->memmap[ASPEED_DEV_VBOOTROM], &s->vbootrom); 683 684 /* SCU */ 685 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { 686 return; 687 } 688 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]); 689 690 /* SCU1 */ 691 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scuio), errp)) { 692 return; 693 } 694 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scuio), 0, 695 sc->memmap[ASPEED_DEV_SCUIO]); 696 697 /* UART */ 698 if (!aspeed_soc_uart_realize(s, errp)) { 699 return; 700 } 701 702 /* FMC, The number of CS is set at the board level */ 703 object_property_set_int(OBJECT(&s->fmc), "dram-base", 704 sc->memmap[ASPEED_DEV_SDRAM], 705 &error_abort); 706 object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr), 707 &error_abort); 708 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) { 709 return; 710 } 711 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]); 712 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 1, 713 ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base); 714 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, 715 aspeed_soc_get_irq(s, ASPEED_DEV_FMC)); 716 717 /* Set up an alias on the FMC CE0 region (boot default) */ 718 MemoryRegion *fmc0_mmio = &s->fmc.flashes[0].mmio; 719 memory_region_init_alias(&s->spi_boot, OBJECT(s), "aspeed.spi_boot", 720 fmc0_mmio, 0, memory_region_size(fmc0_mmio)); 721 memory_region_add_subregion(&s->spi_boot_container, 0x0, &s->spi_boot); 722 723 /* SPI */ 724 for (i = 0; i < sc->spis_num; i++) { 725 object_property_set_link(OBJECT(&s->spi[i]), "dram", 726 OBJECT(s->dram_mr), &error_abort); 727 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { 728 return; 729 } 730 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 0, 731 sc->memmap[ASPEED_DEV_SPI0 + i]); 732 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 1, 733 ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base); 734 } 735 736 /* EHCI */ 737 for (i = 0; i < sc->ehcis_num; i++) { 738 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), errp)) { 739 return; 740 } 741 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ehci[i]), 0, 742 sc->memmap[ASPEED_DEV_EHCI1 + i]); 743 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0, 744 aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i)); 745 } 746 747 /* 748 * SDMC - SDRAM Memory Controller 749 * The SDMC controller is unlocked at SPL stage. 750 * At present, only supports to emulate booting 751 * start from u-boot stage. Set SDMC controller 752 * unlocked by default. It is a temporarily solution. 753 */ 754 object_property_set_bool(OBJECT(&s->sdmc), "unlocked", true, 755 &error_abort); 756 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) { 757 return; 758 } 759 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdmc), 0, 760 sc->memmap[ASPEED_DEV_SDMC]); 761 762 /* RAM */ 763 if (!aspeed_soc_ast2700_dram_init(dev, errp)) { 764 return; 765 } 766 767 /* Net */ 768 for (i = 0; i < sc->macs_num; i++) { 769 object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true, 770 &error_abort); 771 object_property_set_bool(OBJECT(&s->ftgmac100[i]), "dma64", true, 772 &error_abort); 773 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) { 774 return; 775 } 776 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 777 sc->memmap[ASPEED_DEV_ETH1 + i]); 778 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 779 aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i)); 780 781 object_property_set_link(OBJECT(&s->mii[i]), "nic", 782 OBJECT(&s->ftgmac100[i]), &error_abort); 783 if (!sysbus_realize(SYS_BUS_DEVICE(&s->mii[i]), errp)) { 784 return; 785 } 786 787 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->mii[i]), 0, 788 sc->memmap[ASPEED_DEV_MII1 + i]); 789 } 790 791 /* Watch dog */ 792 for (i = 0; i < sc->wdts_num; i++) { 793 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); 794 hwaddr wdt_offset = sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize; 795 796 object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu), 797 &error_abort); 798 if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) { 799 return; 800 } 801 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offset); 802 } 803 804 /* SLI */ 805 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sli), errp)) { 806 return; 807 } 808 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sli), 0, sc->memmap[ASPEED_DEV_SLI]); 809 810 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sliio), errp)) { 811 return; 812 } 813 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sliio), 0, 814 sc->memmap[ASPEED_DEV_SLIIO]); 815 816 /* ADC */ 817 if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) { 818 return; 819 } 820 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]); 821 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0, 822 aspeed_soc_get_irq(s, ASPEED_DEV_ADC)); 823 824 /* I2C */ 825 object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr), 826 &error_abort); 827 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) { 828 return; 829 } 830 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]); 831 for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) { 832 /* 833 * The AST2700 I2C controller has one source INTC per bus. 834 * 835 * For AST2700 A0: 836 * I2C bus interrupts are connected to the OR gate from bit 0 to bit 837 * 15, and the OR gate output pin is connected to the input pin of 838 * GICINT130 of INTC (CPU Die). Then, the output pin is connected to 839 * the GIC. 840 * 841 * For AST2700 A1: 842 * I2C bus interrupts are connected to the OR gate from bit 0 to bit 843 * 15, and the OR gate output pin is connected to the input pin of 844 * GICINT194 of INTCIO (IO Die). Then, the output pin is connected 845 * to the INTC (CPU Die) input pin, and its output pin is connected 846 * to the GIC. 847 * 848 * I2C bus 0 is connected to the OR gate at bit 0. 849 * I2C bus 15 is connected to the OR gate at bit 15. 850 */ 851 irq = aspeed_soc_ast2700_get_irq_index(s, ASPEED_DEV_I2C, i); 852 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq); 853 } 854 855 /* GPIO */ 856 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { 857 return; 858 } 859 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio), 0, 860 sc->memmap[ASPEED_DEV_GPIO]); 861 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, 862 aspeed_soc_get_irq(s, ASPEED_DEV_GPIO)); 863 864 /* RTC */ 865 if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) { 866 return; 867 } 868 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_RTC]); 869 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, 870 aspeed_soc_get_irq(s, ASPEED_DEV_RTC)); 871 872 /* SDHCI */ 873 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) { 874 return; 875 } 876 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdhci), 0, 877 sc->memmap[ASPEED_DEV_SDHCI]); 878 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, 879 aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI)); 880 881 /* eMMC */ 882 if (!sysbus_realize(SYS_BUS_DEVICE(&s->emmc), errp)) { 883 return; 884 } 885 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->emmc), 0, 886 sc->memmap[ASPEED_DEV_EMMC]); 887 sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0, 888 aspeed_soc_get_irq(s, ASPEED_DEV_EMMC)); 889 890 /* Timer */ 891 object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu), 892 &error_abort); 893 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) { 894 return; 895 } 896 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->timerctrl), 0, 897 sc->memmap[ASPEED_DEV_TIMER1]); 898 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) { 899 irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i); 900 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); 901 } 902 903 /* HACE */ 904 object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(s->dram_mr), 905 &error_abort); 906 if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) { 907 return; 908 } 909 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->hace), 0, 910 sc->memmap[ASPEED_DEV_HACE]); 911 sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0, 912 aspeed_soc_get_irq(s, ASPEED_DEV_HACE)); 913 914 create_unimplemented_device("ast2700.dpmcu", 0x11000000, 0x40000); 915 create_unimplemented_device("ast2700.iomem0", 0x12000000, 0x01000000); 916 create_unimplemented_device("ast2700.iomem1", 0x14000000, 0x01000000); 917 create_unimplemented_device("ast2700.ltpi", 0x30000000, 0x1000000); 918 create_unimplemented_device("ast2700.io", 0x0, 0x4000000); 919 } 920 921 static void aspeed_soc_ast2700a0_class_init(ObjectClass *oc, const void *data) 922 { 923 static const char * const valid_cpu_types[] = { 924 ARM_CPU_TYPE_NAME("cortex-a35"), 925 NULL 926 }; 927 DeviceClass *dc = DEVICE_CLASS(oc); 928 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); 929 930 /* Reason: The Aspeed SoC can only be instantiated from a board */ 931 dc->user_creatable = false; 932 dc->realize = aspeed_soc_ast2700_realize; 933 934 sc->valid_cpu_types = valid_cpu_types; 935 sc->silicon_rev = AST2700_A0_SILICON_REV; 936 sc->sram_size = 0x20000; 937 sc->spis_num = 3; 938 sc->ehcis_num = 2; 939 sc->wdts_num = 8; 940 sc->macs_num = 1; 941 sc->uarts_num = 13; 942 sc->num_cpus = 4; 943 sc->uarts_base = ASPEED_DEV_UART0; 944 sc->irqmap = aspeed_soc_ast2700a0_irqmap; 945 sc->memmap = aspeed_soc_ast2700_memmap; 946 sc->get_irq = aspeed_soc_ast2700_get_irq; 947 } 948 949 static void aspeed_soc_ast2700a1_class_init(ObjectClass *oc, const void *data) 950 { 951 static const char * const valid_cpu_types[] = { 952 ARM_CPU_TYPE_NAME("cortex-a35"), 953 NULL 954 }; 955 DeviceClass *dc = DEVICE_CLASS(oc); 956 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); 957 958 /* Reason: The Aspeed SoC can only be instantiated from a board */ 959 dc->user_creatable = false; 960 dc->realize = aspeed_soc_ast2700_realize; 961 962 sc->valid_cpu_types = valid_cpu_types; 963 sc->silicon_rev = AST2700_A1_SILICON_REV; 964 sc->sram_size = 0x20000; 965 sc->spis_num = 3; 966 sc->ehcis_num = 4; 967 sc->wdts_num = 8; 968 sc->macs_num = 3; 969 sc->uarts_num = 13; 970 sc->num_cpus = 4; 971 sc->uarts_base = ASPEED_DEV_UART0; 972 sc->irqmap = aspeed_soc_ast2700a1_irqmap; 973 sc->memmap = aspeed_soc_ast2700_memmap; 974 sc->get_irq = aspeed_soc_ast2700_get_irq; 975 } 976 977 static const TypeInfo aspeed_soc_ast27x0_types[] = { 978 { 979 .name = TYPE_ASPEED27X0_SOC, 980 .parent = TYPE_ASPEED_SOC, 981 .instance_size = sizeof(Aspeed27x0SoCState), 982 .abstract = true, 983 }, { 984 .name = "ast2700-a0", 985 .parent = TYPE_ASPEED27X0_SOC, 986 .instance_init = aspeed_soc_ast2700_init, 987 .class_init = aspeed_soc_ast2700a0_class_init, 988 }, 989 { 990 .name = "ast2700-a1", 991 .parent = TYPE_ASPEED27X0_SOC, 992 .instance_init = aspeed_soc_ast2700_init, 993 .class_init = aspeed_soc_ast2700a1_class_init, 994 }, 995 }; 996 997 DEFINE_TYPES(aspeed_soc_ast27x0_types) 998