1 /* 2 * ASPEED SoC 27x0 family 3 * 4 * Copyright (C) 2024 ASPEED Technology Inc. 5 * 6 * This code is licensed under the GPL version 2 or later. See 7 * the COPYING file in the top-level directory. 8 * 9 * Implementation extracted from the AST2600 and adapted for AST27x0. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qapi/error.h" 14 #include "hw/misc/unimp.h" 15 #include "hw/arm/aspeed_soc.h" 16 #include "hw/arm/bsa.h" 17 #include "qemu/module.h" 18 #include "qemu/error-report.h" 19 #include "hw/i2c/aspeed_i2c.h" 20 #include "net/net.h" 21 #include "system/system.h" 22 #include "hw/intc/arm_gicv3.h" 23 #include "qapi/qmp/qlist.h" 24 #include "qemu/log.h" 25 26 static const hwaddr aspeed_soc_ast2700_memmap[] = { 27 [ASPEED_DEV_SPI_BOOT] = 0x400000000, 28 [ASPEED_DEV_SRAM] = 0x10000000, 29 [ASPEED_DEV_SDMC] = 0x12C00000, 30 [ASPEED_DEV_SCU] = 0x12C02000, 31 [ASPEED_DEV_SCUIO] = 0x14C02000, 32 [ASPEED_DEV_UART0] = 0X14C33000, 33 [ASPEED_DEV_UART1] = 0X14C33100, 34 [ASPEED_DEV_UART2] = 0X14C33200, 35 [ASPEED_DEV_UART3] = 0X14C33300, 36 [ASPEED_DEV_UART4] = 0X12C1A000, 37 [ASPEED_DEV_UART5] = 0X14C33400, 38 [ASPEED_DEV_UART6] = 0X14C33500, 39 [ASPEED_DEV_UART7] = 0X14C33600, 40 [ASPEED_DEV_UART8] = 0X14C33700, 41 [ASPEED_DEV_UART9] = 0X14C33800, 42 [ASPEED_DEV_UART10] = 0X14C33900, 43 [ASPEED_DEV_UART11] = 0X14C33A00, 44 [ASPEED_DEV_UART12] = 0X14C33B00, 45 [ASPEED_DEV_WDT] = 0x14C37000, 46 [ASPEED_DEV_VUART] = 0X14C30000, 47 [ASPEED_DEV_FMC] = 0x14000000, 48 [ASPEED_DEV_SPI0] = 0x14010000, 49 [ASPEED_DEV_SPI1] = 0x14020000, 50 [ASPEED_DEV_SPI2] = 0x14030000, 51 [ASPEED_DEV_SDRAM] = 0x400000000, 52 [ASPEED_DEV_MII1] = 0x14040000, 53 [ASPEED_DEV_MII2] = 0x14040008, 54 [ASPEED_DEV_MII3] = 0x14040010, 55 [ASPEED_DEV_ETH1] = 0x14050000, 56 [ASPEED_DEV_ETH2] = 0x14060000, 57 [ASPEED_DEV_ETH3] = 0x14070000, 58 [ASPEED_DEV_EMMC] = 0x12090000, 59 [ASPEED_DEV_INTC] = 0x12100000, 60 [ASPEED_DEV_SLI] = 0x12C17000, 61 [ASPEED_DEV_SLIIO] = 0x14C1E000, 62 [ASPEED_GIC_DIST] = 0x12200000, 63 [ASPEED_GIC_REDIST] = 0x12280000, 64 [ASPEED_DEV_ADC] = 0x14C00000, 65 [ASPEED_DEV_I2C] = 0x14C0F000, 66 [ASPEED_DEV_GPIO] = 0x14C0B000, 67 [ASPEED_DEV_RTC] = 0x12C0F000, 68 [ASPEED_DEV_SDHCI] = 0x14080000, 69 }; 70 71 #define AST2700_MAX_IRQ 256 72 73 /* Shared Peripheral Interrupt values below are offset by -32 from datasheet */ 74 static const int aspeed_soc_ast2700_irqmap[] = { 75 [ASPEED_DEV_UART0] = 132, 76 [ASPEED_DEV_UART1] = 132, 77 [ASPEED_DEV_UART2] = 132, 78 [ASPEED_DEV_UART3] = 132, 79 [ASPEED_DEV_UART4] = 8, 80 [ASPEED_DEV_UART5] = 132, 81 [ASPEED_DEV_UART6] = 132, 82 [ASPEED_DEV_UART7] = 132, 83 [ASPEED_DEV_UART8] = 132, 84 [ASPEED_DEV_UART9] = 132, 85 [ASPEED_DEV_UART10] = 132, 86 [ASPEED_DEV_UART11] = 132, 87 [ASPEED_DEV_UART12] = 132, 88 [ASPEED_DEV_FMC] = 131, 89 [ASPEED_DEV_SDMC] = 0, 90 [ASPEED_DEV_SCU] = 12, 91 [ASPEED_DEV_ADC] = 130, 92 [ASPEED_DEV_XDMA] = 5, 93 [ASPEED_DEV_EMMC] = 15, 94 [ASPEED_DEV_GPIO] = 130, 95 [ASPEED_DEV_RTC] = 13, 96 [ASPEED_DEV_TIMER1] = 16, 97 [ASPEED_DEV_TIMER2] = 17, 98 [ASPEED_DEV_TIMER3] = 18, 99 [ASPEED_DEV_TIMER4] = 19, 100 [ASPEED_DEV_TIMER5] = 20, 101 [ASPEED_DEV_TIMER6] = 21, 102 [ASPEED_DEV_TIMER7] = 22, 103 [ASPEED_DEV_TIMER8] = 23, 104 [ASPEED_DEV_WDT] = 131, 105 [ASPEED_DEV_PWM] = 131, 106 [ASPEED_DEV_LPC] = 128, 107 [ASPEED_DEV_IBT] = 128, 108 [ASPEED_DEV_I2C] = 130, 109 [ASPEED_DEV_PECI] = 133, 110 [ASPEED_DEV_ETH1] = 132, 111 [ASPEED_DEV_ETH2] = 132, 112 [ASPEED_DEV_ETH3] = 132, 113 [ASPEED_DEV_HACE] = 4, 114 [ASPEED_DEV_KCS] = 128, 115 [ASPEED_DEV_DP] = 28, 116 [ASPEED_DEV_I3C] = 131, 117 [ASPEED_DEV_SDHCI] = 133, 118 }; 119 120 /* GICINT 128 */ 121 static const int aspeed_soc_ast2700_gic128_intcmap[] = { 122 [ASPEED_DEV_LPC] = 0, 123 [ASPEED_DEV_IBT] = 2, 124 [ASPEED_DEV_KCS] = 4, 125 }; 126 127 /* GICINT 130 */ 128 static const int aspeed_soc_ast2700_gic130_intcmap[] = { 129 [ASPEED_DEV_I2C] = 0, 130 [ASPEED_DEV_ADC] = 16, 131 [ASPEED_DEV_GPIO] = 18, 132 }; 133 134 /* GICINT 131 */ 135 static const int aspeed_soc_ast2700_gic131_intcmap[] = { 136 [ASPEED_DEV_I3C] = 0, 137 [ASPEED_DEV_WDT] = 16, 138 [ASPEED_DEV_FMC] = 25, 139 [ASPEED_DEV_PWM] = 29, 140 }; 141 142 /* GICINT 132 */ 143 static const int aspeed_soc_ast2700_gic132_intcmap[] = { 144 [ASPEED_DEV_ETH1] = 0, 145 [ASPEED_DEV_ETH2] = 1, 146 [ASPEED_DEV_ETH3] = 2, 147 [ASPEED_DEV_UART0] = 7, 148 [ASPEED_DEV_UART1] = 8, 149 [ASPEED_DEV_UART2] = 9, 150 [ASPEED_DEV_UART3] = 10, 151 [ASPEED_DEV_UART5] = 11, 152 [ASPEED_DEV_UART6] = 12, 153 [ASPEED_DEV_UART7] = 13, 154 [ASPEED_DEV_UART8] = 14, 155 [ASPEED_DEV_UART9] = 15, 156 [ASPEED_DEV_UART10] = 16, 157 [ASPEED_DEV_UART11] = 17, 158 [ASPEED_DEV_UART12] = 18, 159 }; 160 161 /* GICINT 133 */ 162 static const int aspeed_soc_ast2700_gic133_intcmap[] = { 163 [ASPEED_DEV_SDHCI] = 1, 164 [ASPEED_DEV_PECI] = 4, 165 }; 166 167 /* GICINT 128 ~ 136 */ 168 struct gic_intc_irq_info { 169 int irq; 170 const int *ptr; 171 }; 172 173 static const struct gic_intc_irq_info aspeed_soc_ast2700_gic_intcmap[] = { 174 {128, aspeed_soc_ast2700_gic128_intcmap}, 175 {129, NULL}, 176 {130, aspeed_soc_ast2700_gic130_intcmap}, 177 {131, aspeed_soc_ast2700_gic131_intcmap}, 178 {132, aspeed_soc_ast2700_gic132_intcmap}, 179 {133, aspeed_soc_ast2700_gic133_intcmap}, 180 {134, NULL}, 181 {135, NULL}, 182 {136, NULL}, 183 }; 184 185 static qemu_irq aspeed_soc_ast2700_get_irq(AspeedSoCState *s, int dev) 186 { 187 Aspeed27x0SoCState *a = ASPEED27X0_SOC(s); 188 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 189 int i; 190 191 for (i = 0; i < ARRAY_SIZE(aspeed_soc_ast2700_gic_intcmap); i++) { 192 if (sc->irqmap[dev] == aspeed_soc_ast2700_gic_intcmap[i].irq) { 193 assert(aspeed_soc_ast2700_gic_intcmap[i].ptr); 194 return qdev_get_gpio_in(DEVICE(&a->intc.orgates[i]), 195 aspeed_soc_ast2700_gic_intcmap[i].ptr[dev]); 196 } 197 } 198 199 return qdev_get_gpio_in(DEVICE(&a->gic), sc->irqmap[dev]); 200 } 201 202 static qemu_irq aspeed_soc_ast2700_get_irq_index(AspeedSoCState *s, int dev, 203 int index) 204 { 205 Aspeed27x0SoCState *a = ASPEED27X0_SOC(s); 206 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 207 int i; 208 209 for (i = 0; i < ARRAY_SIZE(aspeed_soc_ast2700_gic_intcmap); i++) { 210 if (sc->irqmap[dev] == aspeed_soc_ast2700_gic_intcmap[i].irq) { 211 assert(aspeed_soc_ast2700_gic_intcmap[i].ptr); 212 return qdev_get_gpio_in(DEVICE(&a->intc.orgates[i]), 213 aspeed_soc_ast2700_gic_intcmap[i].ptr[dev] + index); 214 } 215 } 216 217 /* 218 * Invalid orgate index, device irq should be 128 to 136. 219 */ 220 g_assert_not_reached(); 221 } 222 223 static uint64_t aspeed_ram_capacity_read(void *opaque, hwaddr addr, 224 unsigned int size) 225 { 226 qemu_log_mask(LOG_GUEST_ERROR, 227 "%s: DRAM read out of ram size, addr:0x%" PRIx64 "\n", 228 __func__, addr); 229 return 0; 230 } 231 232 static void aspeed_ram_capacity_write(void *opaque, hwaddr addr, uint64_t data, 233 unsigned int size) 234 { 235 AspeedSoCState *s = ASPEED_SOC(opaque); 236 ram_addr_t ram_size; 237 MemTxResult result; 238 239 ram_size = object_property_get_uint(OBJECT(&s->sdmc), "ram-size", 240 &error_abort); 241 242 assert(ram_size > 0); 243 244 /* 245 * Emulate ddr capacity hardware behavior. 246 * If writes the data to the address which is beyond the ram size, 247 * it would write the data to the "address % ram_size". 248 */ 249 result = address_space_write(&s->dram_as, addr % ram_size, 250 MEMTXATTRS_UNSPECIFIED, &data, 4); 251 if (result != MEMTX_OK) { 252 qemu_log_mask(LOG_GUEST_ERROR, 253 "%s: DRAM write failed, addr:0x%" HWADDR_PRIx 254 ", data :0x%" PRIx64 "\n", 255 __func__, addr % ram_size, data); 256 } 257 } 258 259 static const MemoryRegionOps aspeed_ram_capacity_ops = { 260 .read = aspeed_ram_capacity_read, 261 .write = aspeed_ram_capacity_write, 262 .endianness = DEVICE_LITTLE_ENDIAN, 263 .valid = { 264 .min_access_size = 1, 265 .max_access_size = 8, 266 }, 267 }; 268 269 /* 270 * SDMC should be realized first to get correct RAM size and max size 271 * values 272 */ 273 static bool aspeed_soc_ast2700_dram_init(DeviceState *dev, Error **errp) 274 { 275 ram_addr_t ram_size, max_ram_size; 276 Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev); 277 AspeedSoCState *s = ASPEED_SOC(dev); 278 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 279 280 ram_size = object_property_get_uint(OBJECT(&s->sdmc), "ram-size", 281 &error_abort); 282 max_ram_size = object_property_get_uint(OBJECT(&s->sdmc), "max-ram-size", 283 &error_abort); 284 285 memory_region_init(&s->dram_container, OBJECT(s), "ram-container", 286 ram_size); 287 memory_region_add_subregion(&s->dram_container, 0, s->dram_mr); 288 address_space_init(&s->dram_as, s->dram_mr, "dram"); 289 290 /* 291 * Add a memory region beyond the RAM region to emulate 292 * ddr capacity hardware behavior. 293 */ 294 if (ram_size < max_ram_size) { 295 memory_region_init_io(&a->dram_empty, OBJECT(s), 296 &aspeed_ram_capacity_ops, s, 297 "ram-empty", max_ram_size - ram_size); 298 299 memory_region_add_subregion(s->memory, 300 sc->memmap[ASPEED_DEV_SDRAM] + ram_size, 301 &a->dram_empty); 302 } 303 304 memory_region_add_subregion(s->memory, 305 sc->memmap[ASPEED_DEV_SDRAM], &s->dram_container); 306 return true; 307 } 308 309 static void aspeed_soc_ast2700_init(Object *obj) 310 { 311 Aspeed27x0SoCState *a = ASPEED27X0_SOC(obj); 312 AspeedSoCState *s = ASPEED_SOC(obj); 313 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 314 int i; 315 char socname[8]; 316 char typename[64]; 317 318 if (sscanf(sc->name, "%7s", socname) != 1) { 319 g_assert_not_reached(); 320 } 321 322 for (i = 0; i < sc->num_cpus; i++) { 323 object_initialize_child(obj, "cpu[*]", &a->cpu[i], 324 aspeed_soc_cpu_type(sc)); 325 } 326 327 object_initialize_child(obj, "gic", &a->gic, gicv3_class_name()); 328 329 object_initialize_child(obj, "scu", &s->scu, TYPE_ASPEED_2700_SCU); 330 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", 331 sc->silicon_rev); 332 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), 333 "hw-strap1"); 334 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), 335 "hw-strap2"); 336 object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu), 337 "hw-prot-key"); 338 339 object_initialize_child(obj, "scuio", &s->scuio, TYPE_ASPEED_2700_SCUIO); 340 qdev_prop_set_uint32(DEVICE(&s->scuio), "silicon-rev", 341 sc->silicon_rev); 342 343 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); 344 object_initialize_child(obj, "fmc", &s->fmc, typename); 345 346 for (i = 0; i < sc->spis_num; i++) { 347 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i, socname); 348 object_initialize_child(obj, "spi[*]", &s->spi[i], typename); 349 } 350 351 snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname); 352 object_initialize_child(obj, "sdmc", &s->sdmc, typename); 353 object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), 354 "ram-size"); 355 356 for (i = 0; i < sc->wdts_num; i++) { 357 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); 358 object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename); 359 } 360 361 for (i = 0; i < sc->macs_num; i++) { 362 object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i], 363 TYPE_FTGMAC100); 364 365 object_initialize_child(obj, "mii[*]", &s->mii[i], TYPE_ASPEED_MII); 366 } 367 368 for (i = 0; i < sc->uarts_num; i++) { 369 object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM); 370 } 371 372 object_initialize_child(obj, "sli", &s->sli, TYPE_ASPEED_2700_SLI); 373 object_initialize_child(obj, "sliio", &s->sliio, TYPE_ASPEED_2700_SLIIO); 374 object_initialize_child(obj, "intc", &a->intc, TYPE_ASPEED_2700_INTC); 375 376 snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname); 377 object_initialize_child(obj, "adc", &s->adc, typename); 378 379 snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); 380 object_initialize_child(obj, "i2c", &s->i2c, typename); 381 382 snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); 383 object_initialize_child(obj, "gpio", &s->gpio, typename); 384 385 object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC); 386 387 snprintf(typename, sizeof(typename), "aspeed.sdhci-%s", socname); 388 object_initialize_child(obj, "sd-controller", &s->sdhci, typename); 389 object_property_set_int(OBJECT(&s->sdhci), "num-slots", 1, &error_abort); 390 391 /* Init sd card slot class here so that they're under the correct parent */ 392 object_initialize_child(obj, "sd-controller.sdhci", 393 &s->sdhci.slots[0], TYPE_SYSBUS_SDHCI); 394 395 object_initialize_child(obj, "emmc-controller", &s->emmc, typename); 396 object_property_set_int(OBJECT(&s->emmc), "num-slots", 1, &error_abort); 397 398 object_initialize_child(obj, "emmc-controller.sdhci", &s->emmc.slots[0], 399 TYPE_SYSBUS_SDHCI); 400 } 401 402 /* 403 * ASPEED ast2700 has 0x0 as cluster ID 404 * 405 * https://developer.arm.com/documentation/100236/0100/register-descriptions/aarch64-system-registers/multiprocessor-affinity-register--el1 406 */ 407 static uint64_t aspeed_calc_affinity(int cpu) 408 { 409 return (0x0 << ARM_AFF1_SHIFT) | cpu; 410 } 411 412 static bool aspeed_soc_ast2700_gic_realize(DeviceState *dev, Error **errp) 413 { 414 Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev); 415 AspeedSoCState *s = ASPEED_SOC(dev); 416 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 417 SysBusDevice *gicbusdev; 418 DeviceState *gicdev; 419 QList *redist_region_count; 420 int i; 421 422 gicbusdev = SYS_BUS_DEVICE(&a->gic); 423 gicdev = DEVICE(&a->gic); 424 qdev_prop_set_uint32(gicdev, "revision", 3); 425 qdev_prop_set_uint32(gicdev, "num-cpu", sc->num_cpus); 426 qdev_prop_set_uint32(gicdev, "num-irq", AST2700_MAX_IRQ + GIC_INTERNAL); 427 428 redist_region_count = qlist_new(); 429 qlist_append_int(redist_region_count, sc->num_cpus); 430 qdev_prop_set_array(gicdev, "redist-region-count", redist_region_count); 431 432 if (!sysbus_realize(gicbusdev, errp)) { 433 return false; 434 } 435 sysbus_mmio_map(gicbusdev, 0, sc->memmap[ASPEED_GIC_DIST]); 436 sysbus_mmio_map(gicbusdev, 1, sc->memmap[ASPEED_GIC_REDIST]); 437 438 for (i = 0; i < sc->num_cpus; i++) { 439 DeviceState *cpudev = DEVICE(&a->cpu[i]); 440 int intidbase = AST2700_MAX_IRQ + i * GIC_INTERNAL; 441 442 const int timer_irq[] = { 443 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, 444 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, 445 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, 446 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, 447 }; 448 int j; 449 450 for (j = 0; j < ARRAY_SIZE(timer_irq); j++) { 451 qdev_connect_gpio_out(cpudev, j, 452 qdev_get_gpio_in(gicdev, intidbase + timer_irq[j])); 453 } 454 455 qemu_irq irq = qdev_get_gpio_in(gicdev, 456 intidbase + ARCH_GIC_MAINT_IRQ); 457 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 458 0, irq); 459 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, 460 qdev_get_gpio_in(gicdev, intidbase + VIRTUAL_PMU_IRQ)); 461 462 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 463 sysbus_connect_irq(gicbusdev, i + sc->num_cpus, 464 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 465 sysbus_connect_irq(gicbusdev, i + 2 * sc->num_cpus, 466 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 467 sysbus_connect_irq(gicbusdev, i + 3 * sc->num_cpus, 468 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 469 } 470 471 return true; 472 } 473 474 static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp) 475 { 476 int i; 477 Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev); 478 AspeedSoCState *s = ASPEED_SOC(dev); 479 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 480 AspeedINTCClass *ic = ASPEED_INTC_GET_CLASS(&a->intc); 481 g_autofree char *sram_name = NULL; 482 qemu_irq irq; 483 484 /* Default boot region (SPI memory or ROMs) */ 485 memory_region_init(&s->spi_boot_container, OBJECT(s), 486 "aspeed.spi_boot_container", 0x400000000); 487 memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SPI_BOOT], 488 &s->spi_boot_container); 489 490 /* CPU */ 491 for (i = 0; i < sc->num_cpus; i++) { 492 object_property_set_int(OBJECT(&a->cpu[i]), "mp-affinity", 493 aspeed_calc_affinity(i), &error_abort); 494 495 object_property_set_int(OBJECT(&a->cpu[i]), "cntfrq", 1125000000, 496 &error_abort); 497 object_property_set_link(OBJECT(&a->cpu[i]), "memory", 498 OBJECT(s->memory), &error_abort); 499 500 if (!qdev_realize(DEVICE(&a->cpu[i]), NULL, errp)) { 501 return; 502 } 503 } 504 505 /* GIC */ 506 if (!aspeed_soc_ast2700_gic_realize(dev, errp)) { 507 return; 508 } 509 510 /* INTC */ 511 if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc), errp)) { 512 return; 513 } 514 515 aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc), 0, 516 sc->memmap[ASPEED_DEV_INTC]); 517 518 /* GICINT orgates -> INTC -> GIC */ 519 for (i = 0; i < ic->num_ints; i++) { 520 qdev_connect_gpio_out(DEVICE(&a->intc.orgates[i]), 0, 521 qdev_get_gpio_in(DEVICE(&a->intc), i)); 522 sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc), i, 523 qdev_get_gpio_in(DEVICE(&a->gic), 524 aspeed_soc_ast2700_gic_intcmap[i].irq)); 525 } 526 527 /* SRAM */ 528 sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index); 529 if (!memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, 530 errp)) { 531 return; 532 } 533 memory_region_add_subregion(s->memory, 534 sc->memmap[ASPEED_DEV_SRAM], &s->sram); 535 536 /* SCU */ 537 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { 538 return; 539 } 540 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]); 541 542 /* SCU1 */ 543 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scuio), errp)) { 544 return; 545 } 546 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scuio), 0, 547 sc->memmap[ASPEED_DEV_SCUIO]); 548 549 /* UART */ 550 if (!aspeed_soc_uart_realize(s, errp)) { 551 return; 552 } 553 554 /* FMC, The number of CS is set at the board level */ 555 object_property_set_int(OBJECT(&s->fmc), "dram-base", 556 sc->memmap[ASPEED_DEV_SDRAM], 557 &error_abort); 558 object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr), 559 &error_abort); 560 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) { 561 return; 562 } 563 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]); 564 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 1, 565 ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base); 566 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, 567 aspeed_soc_get_irq(s, ASPEED_DEV_FMC)); 568 569 /* Set up an alias on the FMC CE0 region (boot default) */ 570 MemoryRegion *fmc0_mmio = &s->fmc.flashes[0].mmio; 571 memory_region_init_alias(&s->spi_boot, OBJECT(s), "aspeed.spi_boot", 572 fmc0_mmio, 0, memory_region_size(fmc0_mmio)); 573 memory_region_add_subregion(&s->spi_boot_container, 0x0, &s->spi_boot); 574 575 /* SPI */ 576 for (i = 0; i < sc->spis_num; i++) { 577 object_property_set_link(OBJECT(&s->spi[i]), "dram", 578 OBJECT(s->dram_mr), &error_abort); 579 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { 580 return; 581 } 582 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 0, 583 sc->memmap[ASPEED_DEV_SPI0 + i]); 584 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 1, 585 ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base); 586 } 587 588 /* 589 * SDMC - SDRAM Memory Controller 590 * The SDMC controller is unlocked at SPL stage. 591 * At present, only supports to emulate booting 592 * start from u-boot stage. Set SDMC controller 593 * unlocked by default. It is a temporarily solution. 594 */ 595 object_property_set_bool(OBJECT(&s->sdmc), "unlocked", true, 596 &error_abort); 597 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) { 598 return; 599 } 600 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdmc), 0, 601 sc->memmap[ASPEED_DEV_SDMC]); 602 603 /* RAM */ 604 if (!aspeed_soc_ast2700_dram_init(dev, errp)) { 605 return; 606 } 607 608 /* Net */ 609 for (i = 0; i < sc->macs_num; i++) { 610 object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true, 611 &error_abort); 612 object_property_set_bool(OBJECT(&s->ftgmac100[i]), "dma64", true, 613 &error_abort); 614 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) { 615 return; 616 } 617 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 618 sc->memmap[ASPEED_DEV_ETH1 + i]); 619 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 620 aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i)); 621 622 object_property_set_link(OBJECT(&s->mii[i]), "nic", 623 OBJECT(&s->ftgmac100[i]), &error_abort); 624 if (!sysbus_realize(SYS_BUS_DEVICE(&s->mii[i]), errp)) { 625 return; 626 } 627 628 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->mii[i]), 0, 629 sc->memmap[ASPEED_DEV_MII1 + i]); 630 } 631 632 /* Watch dog */ 633 for (i = 0; i < sc->wdts_num; i++) { 634 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); 635 hwaddr wdt_offset = sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize; 636 637 object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu), 638 &error_abort); 639 if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) { 640 return; 641 } 642 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offset); 643 } 644 645 /* SLI */ 646 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sli), errp)) { 647 return; 648 } 649 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sli), 0, sc->memmap[ASPEED_DEV_SLI]); 650 651 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sliio), errp)) { 652 return; 653 } 654 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sliio), 0, 655 sc->memmap[ASPEED_DEV_SLIIO]); 656 657 /* ADC */ 658 if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) { 659 return; 660 } 661 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]); 662 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0, 663 aspeed_soc_get_irq(s, ASPEED_DEV_ADC)); 664 665 /* I2C */ 666 object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr), 667 &error_abort); 668 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) { 669 return; 670 } 671 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]); 672 for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) { 673 /* 674 * The AST2700 I2C controller has one source INTC per bus. 675 * I2C buses interrupt are connected to GICINT130_INTC 676 * from bit 0 to bit 15. 677 * I2C bus 0 is connected to GICINT130_INTC at bit 0. 678 * I2C bus 15 is connected to GICINT130_INTC at bit 15. 679 */ 680 irq = aspeed_soc_ast2700_get_irq_index(s, ASPEED_DEV_I2C, i); 681 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq); 682 } 683 684 /* GPIO */ 685 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { 686 return; 687 } 688 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio), 0, 689 sc->memmap[ASPEED_DEV_GPIO]); 690 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, 691 aspeed_soc_get_irq(s, ASPEED_DEV_GPIO)); 692 693 /* RTC */ 694 if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) { 695 return; 696 } 697 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_RTC]); 698 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, 699 aspeed_soc_get_irq(s, ASPEED_DEV_RTC)); 700 701 /* SDHCI */ 702 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) { 703 return; 704 } 705 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdhci), 0, 706 sc->memmap[ASPEED_DEV_SDHCI]); 707 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, 708 aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI)); 709 710 /* eMMC */ 711 if (!sysbus_realize(SYS_BUS_DEVICE(&s->emmc), errp)) { 712 return; 713 } 714 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->emmc), 0, 715 sc->memmap[ASPEED_DEV_EMMC]); 716 sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0, 717 aspeed_soc_get_irq(s, ASPEED_DEV_EMMC)); 718 719 create_unimplemented_device("ast2700.dpmcu", 0x11000000, 0x40000); 720 create_unimplemented_device("ast2700.iomem0", 0x12000000, 0x01000000); 721 create_unimplemented_device("ast2700.iomem1", 0x14000000, 0x01000000); 722 create_unimplemented_device("ast2700.ltpi", 0x30000000, 0x1000000); 723 create_unimplemented_device("ast2700.io", 0x0, 0x4000000); 724 } 725 726 static void aspeed_soc_ast2700_class_init(ObjectClass *oc, void *data) 727 { 728 static const char * const valid_cpu_types[] = { 729 ARM_CPU_TYPE_NAME("cortex-a35"), 730 NULL 731 }; 732 DeviceClass *dc = DEVICE_CLASS(oc); 733 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); 734 735 /* Reason: The Aspeed SoC can only be instantiated from a board */ 736 dc->user_creatable = false; 737 dc->realize = aspeed_soc_ast2700_realize; 738 739 sc->name = "ast2700-a0"; 740 sc->valid_cpu_types = valid_cpu_types; 741 sc->silicon_rev = AST2700_A0_SILICON_REV; 742 sc->sram_size = 0x20000; 743 sc->spis_num = 3; 744 sc->wdts_num = 8; 745 sc->macs_num = 1; 746 sc->uarts_num = 13; 747 sc->num_cpus = 4; 748 sc->uarts_base = ASPEED_DEV_UART0; 749 sc->irqmap = aspeed_soc_ast2700_irqmap; 750 sc->memmap = aspeed_soc_ast2700_memmap; 751 sc->get_irq = aspeed_soc_ast2700_get_irq; 752 } 753 754 static const TypeInfo aspeed_soc_ast27x0_types[] = { 755 { 756 .name = TYPE_ASPEED27X0_SOC, 757 .parent = TYPE_ASPEED_SOC, 758 .instance_size = sizeof(Aspeed27x0SoCState), 759 .abstract = true, 760 }, { 761 .name = "ast2700-a0", 762 .parent = TYPE_ASPEED27X0_SOC, 763 .instance_init = aspeed_soc_ast2700_init, 764 .class_init = aspeed_soc_ast2700_class_init, 765 }, 766 }; 767 768 DEFINE_TYPES(aspeed_soc_ast27x0_types) 769