1 /* 2 * ASPEED SoC 27x0 family 3 * 4 * Copyright (C) 2024 ASPEED Technology Inc. 5 * 6 * This code is licensed under the GPL version 2 or later. See 7 * the COPYING file in the top-level directory. 8 * 9 * Implementation extracted from the AST2600 and adapted for AST27x0. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qapi/error.h" 14 #include "hw/misc/unimp.h" 15 #include "hw/arm/aspeed_soc.h" 16 #include "hw/arm/bsa.h" 17 #include "qemu/module.h" 18 #include "qemu/error-report.h" 19 #include "hw/i2c/aspeed_i2c.h" 20 #include "net/net.h" 21 #include "system/system.h" 22 #include "hw/intc/arm_gicv3.h" 23 #include "qobject/qlist.h" 24 #include "qemu/log.h" 25 26 static const hwaddr aspeed_soc_ast2700_memmap[] = { 27 [ASPEED_DEV_SPI_BOOT] = 0x100000000, 28 [ASPEED_DEV_SRAM] = 0x10000000, 29 [ASPEED_DEV_SDMC] = 0x12C00000, 30 [ASPEED_DEV_SCU] = 0x12C02000, 31 [ASPEED_DEV_SCUIO] = 0x14C02000, 32 [ASPEED_DEV_UART0] = 0X14C33000, 33 [ASPEED_DEV_UART1] = 0X14C33100, 34 [ASPEED_DEV_UART2] = 0X14C33200, 35 [ASPEED_DEV_UART3] = 0X14C33300, 36 [ASPEED_DEV_UART4] = 0X12C1A000, 37 [ASPEED_DEV_UART5] = 0X14C33400, 38 [ASPEED_DEV_UART6] = 0X14C33500, 39 [ASPEED_DEV_UART7] = 0X14C33600, 40 [ASPEED_DEV_UART8] = 0X14C33700, 41 [ASPEED_DEV_UART9] = 0X14C33800, 42 [ASPEED_DEV_UART10] = 0X14C33900, 43 [ASPEED_DEV_UART11] = 0X14C33A00, 44 [ASPEED_DEV_UART12] = 0X14C33B00, 45 [ASPEED_DEV_WDT] = 0x14C37000, 46 [ASPEED_DEV_VUART] = 0X14C30000, 47 [ASPEED_DEV_FMC] = 0x14000000, 48 [ASPEED_DEV_SPI0] = 0x14010000, 49 [ASPEED_DEV_SPI1] = 0x14020000, 50 [ASPEED_DEV_SPI2] = 0x14030000, 51 [ASPEED_DEV_SDRAM] = 0x400000000, 52 [ASPEED_DEV_MII1] = 0x14040000, 53 [ASPEED_DEV_MII2] = 0x14040008, 54 [ASPEED_DEV_MII3] = 0x14040010, 55 [ASPEED_DEV_ETH1] = 0x14050000, 56 [ASPEED_DEV_ETH2] = 0x14060000, 57 [ASPEED_DEV_ETH3] = 0x14070000, 58 [ASPEED_DEV_EMMC] = 0x12090000, 59 [ASPEED_DEV_INTC] = 0x12100000, 60 [ASPEED_DEV_INTCIO] = 0x14C18000, 61 [ASPEED_DEV_SLI] = 0x12C17000, 62 [ASPEED_DEV_SLIIO] = 0x14C1E000, 63 [ASPEED_GIC_DIST] = 0x12200000, 64 [ASPEED_GIC_REDIST] = 0x12280000, 65 [ASPEED_DEV_ADC] = 0x14C00000, 66 [ASPEED_DEV_I2C] = 0x14C0F000, 67 [ASPEED_DEV_GPIO] = 0x14C0B000, 68 [ASPEED_DEV_RTC] = 0x12C0F000, 69 [ASPEED_DEV_SDHCI] = 0x14080000, 70 [ASPEED_DEV_TIMER1] = 0x12C10000, 71 [ASPEED_DEV_HACE] = 0x12070000, 72 }; 73 74 #define AST2700_MAX_IRQ 256 75 76 /* Shared Peripheral Interrupt values below are offset by -32 from datasheet */ 77 static const int aspeed_soc_ast2700a0_irqmap[] = { 78 [ASPEED_DEV_SDMC] = 0, 79 [ASPEED_DEV_HACE] = 4, 80 [ASPEED_DEV_XDMA] = 5, 81 [ASPEED_DEV_UART4] = 8, 82 [ASPEED_DEV_SCU] = 12, 83 [ASPEED_DEV_RTC] = 13, 84 [ASPEED_DEV_EMMC] = 15, 85 [ASPEED_DEV_TIMER1] = 16, 86 [ASPEED_DEV_TIMER2] = 17, 87 [ASPEED_DEV_TIMER3] = 18, 88 [ASPEED_DEV_TIMER4] = 19, 89 [ASPEED_DEV_TIMER5] = 20, 90 [ASPEED_DEV_TIMER6] = 21, 91 [ASPEED_DEV_TIMER7] = 22, 92 [ASPEED_DEV_TIMER8] = 23, 93 [ASPEED_DEV_DP] = 28, 94 [ASPEED_DEV_LPC] = 128, 95 [ASPEED_DEV_IBT] = 128, 96 [ASPEED_DEV_KCS] = 128, 97 [ASPEED_DEV_ADC] = 130, 98 [ASPEED_DEV_GPIO] = 130, 99 [ASPEED_DEV_I2C] = 130, 100 [ASPEED_DEV_FMC] = 131, 101 [ASPEED_DEV_WDT] = 131, 102 [ASPEED_DEV_PWM] = 131, 103 [ASPEED_DEV_I3C] = 131, 104 [ASPEED_DEV_UART0] = 132, 105 [ASPEED_DEV_UART1] = 132, 106 [ASPEED_DEV_UART2] = 132, 107 [ASPEED_DEV_UART3] = 132, 108 [ASPEED_DEV_UART5] = 132, 109 [ASPEED_DEV_UART6] = 132, 110 [ASPEED_DEV_UART7] = 132, 111 [ASPEED_DEV_UART8] = 132, 112 [ASPEED_DEV_UART9] = 132, 113 [ASPEED_DEV_UART10] = 132, 114 [ASPEED_DEV_UART11] = 132, 115 [ASPEED_DEV_UART12] = 132, 116 [ASPEED_DEV_ETH1] = 132, 117 [ASPEED_DEV_ETH2] = 132, 118 [ASPEED_DEV_ETH3] = 132, 119 [ASPEED_DEV_PECI] = 133, 120 [ASPEED_DEV_SDHCI] = 133, 121 }; 122 123 /* GICINT 128 */ 124 /* GICINT 192 */ 125 static const int ast2700_gic128_gic192_intcmap[] = { 126 [ASPEED_DEV_LPC] = 0, 127 [ASPEED_DEV_IBT] = 2, 128 [ASPEED_DEV_KCS] = 4, 129 }; 130 131 /* GICINT 129 */ 132 /* GICINT 193 */ 133 134 /* GICINT 130 */ 135 /* GICINT 194 */ 136 static const int ast2700_gic130_gic194_intcmap[] = { 137 [ASPEED_DEV_I2C] = 0, 138 [ASPEED_DEV_ADC] = 16, 139 [ASPEED_DEV_GPIO] = 18, 140 }; 141 142 /* GICINT 131 */ 143 /* GICINT 195 */ 144 static const int ast2700_gic131_gic195_intcmap[] = { 145 [ASPEED_DEV_I3C] = 0, 146 [ASPEED_DEV_WDT] = 16, 147 [ASPEED_DEV_FMC] = 25, 148 [ASPEED_DEV_PWM] = 29, 149 }; 150 151 /* GICINT 132 */ 152 /* GICINT 196 */ 153 static const int ast2700_gic132_gic196_intcmap[] = { 154 [ASPEED_DEV_ETH1] = 0, 155 [ASPEED_DEV_ETH2] = 1, 156 [ASPEED_DEV_ETH3] = 2, 157 [ASPEED_DEV_UART0] = 7, 158 [ASPEED_DEV_UART1] = 8, 159 [ASPEED_DEV_UART2] = 9, 160 [ASPEED_DEV_UART3] = 10, 161 [ASPEED_DEV_UART5] = 11, 162 [ASPEED_DEV_UART6] = 12, 163 [ASPEED_DEV_UART7] = 13, 164 [ASPEED_DEV_UART8] = 14, 165 [ASPEED_DEV_UART9] = 15, 166 [ASPEED_DEV_UART10] = 16, 167 [ASPEED_DEV_UART11] = 17, 168 [ASPEED_DEV_UART12] = 18, 169 }; 170 171 /* GICINT 133 */ 172 /* GICINT 197 */ 173 static const int ast2700_gic133_gic197_intcmap[] = { 174 [ASPEED_DEV_SDHCI] = 1, 175 [ASPEED_DEV_PECI] = 4, 176 }; 177 178 /* GICINT 128 ~ 136 */ 179 /* GICINT 192 ~ 201 */ 180 struct gic_intc_irq_info { 181 int irq; 182 int intc_idx; 183 int orgate_idx; 184 const int *ptr; 185 }; 186 187 static const struct gic_intc_irq_info ast2700_gic_intcmap[] = { 188 {192, 1, 0, ast2700_gic128_gic192_intcmap}, 189 {193, 1, 1, NULL}, 190 {194, 1, 2, ast2700_gic130_gic194_intcmap}, 191 {195, 1, 3, ast2700_gic131_gic195_intcmap}, 192 {196, 1, 4, ast2700_gic132_gic196_intcmap}, 193 {197, 1, 5, ast2700_gic133_gic197_intcmap}, 194 {198, 1, 6, NULL}, 195 {199, 1, 7, NULL}, 196 {200, 1, 8, NULL}, 197 {201, 1, 9, NULL}, 198 {128, 0, 1, ast2700_gic128_gic192_intcmap}, 199 {129, 0, 2, NULL}, 200 {130, 0, 3, ast2700_gic130_gic194_intcmap}, 201 {131, 0, 4, ast2700_gic131_gic195_intcmap}, 202 {132, 0, 5, ast2700_gic132_gic196_intcmap}, 203 {133, 0, 6, ast2700_gic133_gic197_intcmap}, 204 {134, 0, 7, NULL}, 205 {135, 0, 8, NULL}, 206 {136, 0, 9, NULL}, 207 }; 208 209 static qemu_irq aspeed_soc_ast2700_get_irq(AspeedSoCState *s, int dev) 210 { 211 Aspeed27x0SoCState *a = ASPEED27X0_SOC(s); 212 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 213 int or_idx; 214 int idx; 215 int i; 216 217 for (i = 0; i < ARRAY_SIZE(ast2700_gic_intcmap); i++) { 218 if (sc->irqmap[dev] == ast2700_gic_intcmap[i].irq) { 219 assert(ast2700_gic_intcmap[i].ptr); 220 or_idx = ast2700_gic_intcmap[i].orgate_idx; 221 idx = ast2700_gic_intcmap[i].intc_idx; 222 return qdev_get_gpio_in(DEVICE(&a->intc[idx].orgates[or_idx]), 223 ast2700_gic_intcmap[i].ptr[dev]); 224 } 225 } 226 227 return qdev_get_gpio_in(DEVICE(&a->gic), sc->irqmap[dev]); 228 } 229 230 static qemu_irq aspeed_soc_ast2700_get_irq_index(AspeedSoCState *s, int dev, 231 int index) 232 { 233 Aspeed27x0SoCState *a = ASPEED27X0_SOC(s); 234 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 235 int or_idx; 236 int idx; 237 int i; 238 239 for (i = 0; i < ARRAY_SIZE(ast2700_gic_intcmap); i++) { 240 if (sc->irqmap[dev] == ast2700_gic_intcmap[i].irq) { 241 assert(ast2700_gic_intcmap[i].ptr); 242 or_idx = ast2700_gic_intcmap[i].orgate_idx; 243 idx = ast2700_gic_intcmap[i].intc_idx; 244 return qdev_get_gpio_in(DEVICE(&a->intc[idx].orgates[or_idx]), 245 ast2700_gic_intcmap[i].ptr[dev] + index); 246 } 247 } 248 249 /* 250 * Invalid OR gate index, device IRQ should be between 128 to 136 251 * and 192 to 201. 252 */ 253 g_assert_not_reached(); 254 } 255 256 static uint64_t aspeed_ram_capacity_read(void *opaque, hwaddr addr, 257 unsigned int size) 258 { 259 qemu_log_mask(LOG_GUEST_ERROR, 260 "%s: DRAM read out of ram size, addr:0x%" PRIx64 "\n", 261 __func__, addr); 262 return 0; 263 } 264 265 static void aspeed_ram_capacity_write(void *opaque, hwaddr addr, uint64_t data, 266 unsigned int size) 267 { 268 AspeedSoCState *s = ASPEED_SOC(opaque); 269 ram_addr_t ram_size; 270 MemTxResult result; 271 272 ram_size = object_property_get_uint(OBJECT(&s->sdmc), "ram-size", 273 &error_abort); 274 275 assert(ram_size > 0); 276 277 /* 278 * Emulate ddr capacity hardware behavior. 279 * If writes the data to the address which is beyond the ram size, 280 * it would write the data to the "address % ram_size". 281 */ 282 result = address_space_write(&s->dram_as, addr % ram_size, 283 MEMTXATTRS_UNSPECIFIED, &data, 4); 284 if (result != MEMTX_OK) { 285 qemu_log_mask(LOG_GUEST_ERROR, 286 "%s: DRAM write failed, addr:0x%" HWADDR_PRIx 287 ", data :0x%" PRIx64 "\n", 288 __func__, addr % ram_size, data); 289 } 290 } 291 292 static const MemoryRegionOps aspeed_ram_capacity_ops = { 293 .read = aspeed_ram_capacity_read, 294 .write = aspeed_ram_capacity_write, 295 .endianness = DEVICE_LITTLE_ENDIAN, 296 .valid = { 297 .min_access_size = 1, 298 .max_access_size = 8, 299 }, 300 }; 301 302 /* 303 * SDMC should be realized first to get correct RAM size and max size 304 * values 305 */ 306 static bool aspeed_soc_ast2700_dram_init(DeviceState *dev, Error **errp) 307 { 308 ram_addr_t ram_size, max_ram_size; 309 Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev); 310 AspeedSoCState *s = ASPEED_SOC(dev); 311 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 312 313 ram_size = object_property_get_uint(OBJECT(&s->sdmc), "ram-size", 314 &error_abort); 315 max_ram_size = object_property_get_uint(OBJECT(&s->sdmc), "max-ram-size", 316 &error_abort); 317 318 memory_region_init(&s->dram_container, OBJECT(s), "ram-container", 319 ram_size); 320 memory_region_add_subregion(&s->dram_container, 0, s->dram_mr); 321 address_space_init(&s->dram_as, s->dram_mr, "dram"); 322 323 /* 324 * Add a memory region beyond the RAM region to emulate 325 * ddr capacity hardware behavior. 326 */ 327 if (ram_size < max_ram_size) { 328 memory_region_init_io(&a->dram_empty, OBJECT(s), 329 &aspeed_ram_capacity_ops, s, 330 "ram-empty", max_ram_size - ram_size); 331 332 memory_region_add_subregion(s->memory, 333 sc->memmap[ASPEED_DEV_SDRAM] + ram_size, 334 &a->dram_empty); 335 } 336 337 memory_region_add_subregion(s->memory, 338 sc->memmap[ASPEED_DEV_SDRAM], &s->dram_container); 339 return true; 340 } 341 342 static void aspeed_soc_ast2700_init(Object *obj) 343 { 344 Aspeed27x0SoCState *a = ASPEED27X0_SOC(obj); 345 AspeedSoCState *s = ASPEED_SOC(obj); 346 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 347 int i; 348 char socname[8]; 349 char typename[64]; 350 351 if (sscanf(object_get_typename(obj), "%7s", socname) != 1) { 352 g_assert_not_reached(); 353 } 354 355 for (i = 0; i < sc->num_cpus; i++) { 356 object_initialize_child(obj, "cpu[*]", &a->cpu[i], 357 aspeed_soc_cpu_type(sc)); 358 } 359 360 object_initialize_child(obj, "gic", &a->gic, gicv3_class_name()); 361 362 object_initialize_child(obj, "scu", &s->scu, TYPE_ASPEED_2700_SCU); 363 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", 364 sc->silicon_rev); 365 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), 366 "hw-strap1"); 367 object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu), 368 "hw-prot-key"); 369 370 object_initialize_child(obj, "scuio", &s->scuio, TYPE_ASPEED_2700_SCUIO); 371 qdev_prop_set_uint32(DEVICE(&s->scuio), "silicon-rev", 372 sc->silicon_rev); 373 /* 374 * There is one hw-strap1 register in the SCU (CPU DIE) and another 375 * hw-strap1 register in the SCUIO (IO DIE). To reuse the current design 376 * of hw-strap, hw-strap1 is assigned to the SCU and sets the value in the 377 * SCU hw-strap1 register, while hw-strap2 is assigned to the SCUIO and 378 * sets the value in the SCUIO hw-strap1 register. 379 */ 380 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scuio), 381 "hw-strap1"); 382 383 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); 384 object_initialize_child(obj, "fmc", &s->fmc, typename); 385 386 for (i = 0; i < sc->spis_num; i++) { 387 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i, socname); 388 object_initialize_child(obj, "spi[*]", &s->spi[i], typename); 389 } 390 391 snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname); 392 object_initialize_child(obj, "sdmc", &s->sdmc, typename); 393 object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), 394 "ram-size"); 395 396 for (i = 0; i < sc->wdts_num; i++) { 397 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); 398 object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename); 399 } 400 401 for (i = 0; i < sc->macs_num; i++) { 402 object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i], 403 TYPE_FTGMAC100); 404 405 object_initialize_child(obj, "mii[*]", &s->mii[i], TYPE_ASPEED_MII); 406 } 407 408 for (i = 0; i < sc->uarts_num; i++) { 409 object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM); 410 } 411 412 object_initialize_child(obj, "sli", &s->sli, TYPE_ASPEED_2700_SLI); 413 object_initialize_child(obj, "sliio", &s->sliio, TYPE_ASPEED_2700_SLIIO); 414 object_initialize_child(obj, "intc", &a->intc[0], TYPE_ASPEED_2700_INTC); 415 object_initialize_child(obj, "intcio", &a->intc[1], 416 TYPE_ASPEED_2700_INTCIO); 417 418 snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname); 419 object_initialize_child(obj, "adc", &s->adc, typename); 420 421 snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); 422 object_initialize_child(obj, "i2c", &s->i2c, typename); 423 424 snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); 425 object_initialize_child(obj, "gpio", &s->gpio, typename); 426 427 object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC); 428 429 snprintf(typename, sizeof(typename), "aspeed.sdhci-%s", socname); 430 object_initialize_child(obj, "sd-controller", &s->sdhci, typename); 431 object_property_set_int(OBJECT(&s->sdhci), "num-slots", 1, &error_abort); 432 433 /* Init sd card slot class here so that they're under the correct parent */ 434 object_initialize_child(obj, "sd-controller.sdhci", 435 &s->sdhci.slots[0], TYPE_SYSBUS_SDHCI); 436 437 object_initialize_child(obj, "emmc-controller", &s->emmc, typename); 438 object_property_set_int(OBJECT(&s->emmc), "num-slots", 1, &error_abort); 439 440 object_initialize_child(obj, "emmc-controller.sdhci", &s->emmc.slots[0], 441 TYPE_SYSBUS_SDHCI); 442 443 snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname); 444 object_initialize_child(obj, "timerctrl", &s->timerctrl, typename); 445 446 snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname); 447 object_initialize_child(obj, "hace", &s->hace, typename); 448 } 449 450 /* 451 * ASPEED ast2700 has 0x0 as cluster ID 452 * 453 * https://developer.arm.com/documentation/100236/0100/register-descriptions/aarch64-system-registers/multiprocessor-affinity-register--el1 454 */ 455 static uint64_t aspeed_calc_affinity(int cpu) 456 { 457 return (0x0 << ARM_AFF1_SHIFT) | cpu; 458 } 459 460 static bool aspeed_soc_ast2700_gic_realize(DeviceState *dev, Error **errp) 461 { 462 Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev); 463 AspeedSoCState *s = ASPEED_SOC(dev); 464 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 465 SysBusDevice *gicbusdev; 466 DeviceState *gicdev; 467 QList *redist_region_count; 468 int i; 469 470 gicbusdev = SYS_BUS_DEVICE(&a->gic); 471 gicdev = DEVICE(&a->gic); 472 qdev_prop_set_uint32(gicdev, "revision", 3); 473 qdev_prop_set_uint32(gicdev, "num-cpu", sc->num_cpus); 474 qdev_prop_set_uint32(gicdev, "num-irq", AST2700_MAX_IRQ + GIC_INTERNAL); 475 476 redist_region_count = qlist_new(); 477 qlist_append_int(redist_region_count, sc->num_cpus); 478 qdev_prop_set_array(gicdev, "redist-region-count", redist_region_count); 479 480 if (!sysbus_realize(gicbusdev, errp)) { 481 return false; 482 } 483 sysbus_mmio_map(gicbusdev, 0, sc->memmap[ASPEED_GIC_DIST]); 484 sysbus_mmio_map(gicbusdev, 1, sc->memmap[ASPEED_GIC_REDIST]); 485 486 for (i = 0; i < sc->num_cpus; i++) { 487 DeviceState *cpudev = DEVICE(&a->cpu[i]); 488 int intidbase = AST2700_MAX_IRQ + i * GIC_INTERNAL; 489 490 const int timer_irq[] = { 491 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, 492 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, 493 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, 494 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, 495 }; 496 int j; 497 498 for (j = 0; j < ARRAY_SIZE(timer_irq); j++) { 499 qdev_connect_gpio_out(cpudev, j, 500 qdev_get_gpio_in(gicdev, intidbase + timer_irq[j])); 501 } 502 503 qemu_irq irq = qdev_get_gpio_in(gicdev, 504 intidbase + ARCH_GIC_MAINT_IRQ); 505 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 506 0, irq); 507 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, 508 qdev_get_gpio_in(gicdev, intidbase + VIRTUAL_PMU_IRQ)); 509 510 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 511 sysbus_connect_irq(gicbusdev, i + sc->num_cpus, 512 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 513 sysbus_connect_irq(gicbusdev, i + 2 * sc->num_cpus, 514 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 515 sysbus_connect_irq(gicbusdev, i + 3 * sc->num_cpus, 516 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 517 sysbus_connect_irq(gicbusdev, i + 4 * sc->num_cpus, 518 qdev_get_gpio_in(cpudev, ARM_CPU_NMI)); 519 sysbus_connect_irq(gicbusdev, i + 5 * sc->num_cpus, 520 qdev_get_gpio_in(cpudev, ARM_CPU_VINMI)); 521 } 522 523 return true; 524 } 525 526 static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp) 527 { 528 int i; 529 Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev); 530 AspeedSoCState *s = ASPEED_SOC(dev); 531 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 532 AspeedINTCClass *ic = ASPEED_INTC_GET_CLASS(&a->intc[0]); 533 AspeedINTCClass *icio = ASPEED_INTC_GET_CLASS(&a->intc[1]); 534 g_autofree char *sram_name = NULL; 535 qemu_irq irq; 536 537 /* Default boot region (SPI memory or ROMs) */ 538 memory_region_init(&s->spi_boot_container, OBJECT(s), 539 "aspeed.spi_boot_container", 0x400000000); 540 memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SPI_BOOT], 541 &s->spi_boot_container); 542 543 /* CPU */ 544 for (i = 0; i < sc->num_cpus; i++) { 545 object_property_set_int(OBJECT(&a->cpu[i]), "mp-affinity", 546 aspeed_calc_affinity(i), &error_abort); 547 548 object_property_set_int(OBJECT(&a->cpu[i]), "cntfrq", 1125000000, 549 &error_abort); 550 object_property_set_link(OBJECT(&a->cpu[i]), "memory", 551 OBJECT(s->memory), &error_abort); 552 553 if (!qdev_realize(DEVICE(&a->cpu[i]), NULL, errp)) { 554 return; 555 } 556 } 557 558 /* GIC */ 559 if (!aspeed_soc_ast2700_gic_realize(dev, errp)) { 560 return; 561 } 562 563 /* INTC */ 564 if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[0]), errp)) { 565 return; 566 } 567 568 aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc[0]), 0, 569 sc->memmap[ASPEED_DEV_INTC]); 570 571 /* INTCIO */ 572 if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[1]), errp)) { 573 return; 574 } 575 576 aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc[1]), 0, 577 sc->memmap[ASPEED_DEV_INTCIO]); 578 579 /* irq sources -> orgates -> INTC */ 580 for (i = 0; i < ic->num_inpins; i++) { 581 qdev_connect_gpio_out(DEVICE(&a->intc[0].orgates[i]), 0, 582 qdev_get_gpio_in(DEVICE(&a->intc[0]), i)); 583 } 584 585 /* INTC -> GIC192 - GIC201 */ 586 /* INTC -> GIC128 - GIC136 */ 587 for (i = 0; i < ic->num_outpins; i++) { 588 sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc[0]), i, 589 qdev_get_gpio_in(DEVICE(&a->gic), 590 ast2700_gic_intcmap[i].irq)); 591 } 592 593 /* irq source -> orgates -> INTCIO */ 594 for (i = 0; i < icio->num_inpins; i++) { 595 qdev_connect_gpio_out(DEVICE(&a->intc[1].orgates[i]), 0, 596 qdev_get_gpio_in(DEVICE(&a->intc[1]), i)); 597 } 598 599 /* INTCIO -> INTC */ 600 for (i = 0; i < icio->num_outpins; i++) { 601 sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc[1]), i, 602 qdev_get_gpio_in(DEVICE(&a->intc[0].orgates[0]), i)); 603 } 604 605 /* SRAM */ 606 sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index); 607 if (!memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, 608 errp)) { 609 return; 610 } 611 memory_region_add_subregion(s->memory, 612 sc->memmap[ASPEED_DEV_SRAM], &s->sram); 613 614 /* SCU */ 615 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { 616 return; 617 } 618 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]); 619 620 /* SCU1 */ 621 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scuio), errp)) { 622 return; 623 } 624 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scuio), 0, 625 sc->memmap[ASPEED_DEV_SCUIO]); 626 627 /* UART */ 628 if (!aspeed_soc_uart_realize(s, errp)) { 629 return; 630 } 631 632 /* FMC, The number of CS is set at the board level */ 633 object_property_set_int(OBJECT(&s->fmc), "dram-base", 634 sc->memmap[ASPEED_DEV_SDRAM], 635 &error_abort); 636 object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr), 637 &error_abort); 638 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) { 639 return; 640 } 641 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]); 642 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 1, 643 ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base); 644 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, 645 aspeed_soc_get_irq(s, ASPEED_DEV_FMC)); 646 647 /* Set up an alias on the FMC CE0 region (boot default) */ 648 MemoryRegion *fmc0_mmio = &s->fmc.flashes[0].mmio; 649 memory_region_init_alias(&s->spi_boot, OBJECT(s), "aspeed.spi_boot", 650 fmc0_mmio, 0, memory_region_size(fmc0_mmio)); 651 memory_region_add_subregion(&s->spi_boot_container, 0x0, &s->spi_boot); 652 653 /* SPI */ 654 for (i = 0; i < sc->spis_num; i++) { 655 object_property_set_link(OBJECT(&s->spi[i]), "dram", 656 OBJECT(s->dram_mr), &error_abort); 657 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { 658 return; 659 } 660 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 0, 661 sc->memmap[ASPEED_DEV_SPI0 + i]); 662 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 1, 663 ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base); 664 } 665 666 /* 667 * SDMC - SDRAM Memory Controller 668 * The SDMC controller is unlocked at SPL stage. 669 * At present, only supports to emulate booting 670 * start from u-boot stage. Set SDMC controller 671 * unlocked by default. It is a temporarily solution. 672 */ 673 object_property_set_bool(OBJECT(&s->sdmc), "unlocked", true, 674 &error_abort); 675 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) { 676 return; 677 } 678 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdmc), 0, 679 sc->memmap[ASPEED_DEV_SDMC]); 680 681 /* RAM */ 682 if (!aspeed_soc_ast2700_dram_init(dev, errp)) { 683 return; 684 } 685 686 /* Net */ 687 for (i = 0; i < sc->macs_num; i++) { 688 object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true, 689 &error_abort); 690 object_property_set_bool(OBJECT(&s->ftgmac100[i]), "dma64", true, 691 &error_abort); 692 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) { 693 return; 694 } 695 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 696 sc->memmap[ASPEED_DEV_ETH1 + i]); 697 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 698 aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i)); 699 700 object_property_set_link(OBJECT(&s->mii[i]), "nic", 701 OBJECT(&s->ftgmac100[i]), &error_abort); 702 if (!sysbus_realize(SYS_BUS_DEVICE(&s->mii[i]), errp)) { 703 return; 704 } 705 706 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->mii[i]), 0, 707 sc->memmap[ASPEED_DEV_MII1 + i]); 708 } 709 710 /* Watch dog */ 711 for (i = 0; i < sc->wdts_num; i++) { 712 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); 713 hwaddr wdt_offset = sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize; 714 715 object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu), 716 &error_abort); 717 if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) { 718 return; 719 } 720 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offset); 721 } 722 723 /* SLI */ 724 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sli), errp)) { 725 return; 726 } 727 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sli), 0, sc->memmap[ASPEED_DEV_SLI]); 728 729 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sliio), errp)) { 730 return; 731 } 732 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sliio), 0, 733 sc->memmap[ASPEED_DEV_SLIIO]); 734 735 /* ADC */ 736 if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) { 737 return; 738 } 739 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]); 740 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0, 741 aspeed_soc_get_irq(s, ASPEED_DEV_ADC)); 742 743 /* I2C */ 744 object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr), 745 &error_abort); 746 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) { 747 return; 748 } 749 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]); 750 for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) { 751 /* 752 * The AST2700 I2C controller has one source INTC per bus. 753 * 754 * For AST2700 A0: 755 * I2C bus interrupts are connected to the OR gate from bit 0 to bit 756 * 15, and the OR gate output pin is connected to the input pin of 757 * GICINT130 of INTC (CPU Die). Then, the output pin is connected to 758 * the GIC. 759 * 760 * For AST2700 A1: 761 * I2C bus interrupts are connected to the OR gate from bit 0 to bit 762 * 15, and the OR gate output pin is connected to the input pin of 763 * GICINT194 of INTCIO (IO Die). Then, the output pin is connected 764 * to the INTC (CPU Die) input pin, and its output pin is connected 765 * to the GIC. 766 * 767 * I2C bus 0 is connected to the OR gate at bit 0. 768 * I2C bus 15 is connected to the OR gate at bit 15. 769 */ 770 irq = aspeed_soc_ast2700_get_irq_index(s, ASPEED_DEV_I2C, i); 771 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq); 772 } 773 774 /* GPIO */ 775 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { 776 return; 777 } 778 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio), 0, 779 sc->memmap[ASPEED_DEV_GPIO]); 780 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, 781 aspeed_soc_get_irq(s, ASPEED_DEV_GPIO)); 782 783 /* RTC */ 784 if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) { 785 return; 786 } 787 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_RTC]); 788 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, 789 aspeed_soc_get_irq(s, ASPEED_DEV_RTC)); 790 791 /* SDHCI */ 792 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) { 793 return; 794 } 795 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdhci), 0, 796 sc->memmap[ASPEED_DEV_SDHCI]); 797 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, 798 aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI)); 799 800 /* eMMC */ 801 if (!sysbus_realize(SYS_BUS_DEVICE(&s->emmc), errp)) { 802 return; 803 } 804 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->emmc), 0, 805 sc->memmap[ASPEED_DEV_EMMC]); 806 sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0, 807 aspeed_soc_get_irq(s, ASPEED_DEV_EMMC)); 808 809 /* Timer */ 810 object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu), 811 &error_abort); 812 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) { 813 return; 814 } 815 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->timerctrl), 0, 816 sc->memmap[ASPEED_DEV_TIMER1]); 817 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) { 818 irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i); 819 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); 820 } 821 822 /* HACE */ 823 object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(s->dram_mr), 824 &error_abort); 825 if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) { 826 return; 827 } 828 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->hace), 0, 829 sc->memmap[ASPEED_DEV_HACE]); 830 sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0, 831 aspeed_soc_get_irq(s, ASPEED_DEV_HACE)); 832 833 create_unimplemented_device("ast2700.dpmcu", 0x11000000, 0x40000); 834 create_unimplemented_device("ast2700.iomem0", 0x12000000, 0x01000000); 835 create_unimplemented_device("ast2700.iomem1", 0x14000000, 0x01000000); 836 create_unimplemented_device("ast2700.ltpi", 0x30000000, 0x1000000); 837 create_unimplemented_device("ast2700.io", 0x0, 0x4000000); 838 } 839 840 static void aspeed_soc_ast2700a0_class_init(ObjectClass *oc, void *data) 841 { 842 static const char * const valid_cpu_types[] = { 843 ARM_CPU_TYPE_NAME("cortex-a35"), 844 NULL 845 }; 846 DeviceClass *dc = DEVICE_CLASS(oc); 847 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); 848 849 /* Reason: The Aspeed SoC can only be instantiated from a board */ 850 dc->user_creatable = false; 851 dc->realize = aspeed_soc_ast2700_realize; 852 853 sc->valid_cpu_types = valid_cpu_types; 854 sc->silicon_rev = AST2700_A0_SILICON_REV; 855 sc->sram_size = 0x20000; 856 sc->spis_num = 3; 857 sc->wdts_num = 8; 858 sc->macs_num = 1; 859 sc->uarts_num = 13; 860 sc->num_cpus = 4; 861 sc->uarts_base = ASPEED_DEV_UART0; 862 sc->irqmap = aspeed_soc_ast2700a0_irqmap; 863 sc->memmap = aspeed_soc_ast2700_memmap; 864 sc->get_irq = aspeed_soc_ast2700_get_irq; 865 } 866 867 static const TypeInfo aspeed_soc_ast27x0_types[] = { 868 { 869 .name = TYPE_ASPEED27X0_SOC, 870 .parent = TYPE_ASPEED_SOC, 871 .instance_size = sizeof(Aspeed27x0SoCState), 872 .abstract = true, 873 }, { 874 .name = "ast2700-a0", 875 .parent = TYPE_ASPEED27X0_SOC, 876 .instance_init = aspeed_soc_ast2700_init, 877 .class_init = aspeed_soc_ast2700a0_class_init, 878 }, 879 }; 880 881 DEFINE_TYPES(aspeed_soc_ast27x0_types) 882