1 /* 2 * ASPEED SoC 27x0 family 3 * 4 * Copyright (C) 2024 ASPEED Technology Inc. 5 * 6 * This code is licensed under the GPL version 2 or later. See 7 * the COPYING file in the top-level directory. 8 * 9 * Implementation extracted from the AST2600 and adapted for AST27x0. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qapi/error.h" 14 #include "hw/misc/unimp.h" 15 #include "hw/arm/aspeed_soc.h" 16 #include "hw/arm/bsa.h" 17 #include "qemu/module.h" 18 #include "qemu/error-report.h" 19 #include "hw/i2c/aspeed_i2c.h" 20 #include "net/net.h" 21 #include "system/system.h" 22 #include "hw/intc/arm_gicv3.h" 23 #include "qobject/qlist.h" 24 #include "qemu/log.h" 25 26 static const hwaddr aspeed_soc_ast2700_memmap[] = { 27 [ASPEED_DEV_SPI_BOOT] = 0x400000000, 28 [ASPEED_DEV_SRAM] = 0x10000000, 29 [ASPEED_DEV_SDMC] = 0x12C00000, 30 [ASPEED_DEV_SCU] = 0x12C02000, 31 [ASPEED_DEV_SCUIO] = 0x14C02000, 32 [ASPEED_DEV_UART0] = 0X14C33000, 33 [ASPEED_DEV_UART1] = 0X14C33100, 34 [ASPEED_DEV_UART2] = 0X14C33200, 35 [ASPEED_DEV_UART3] = 0X14C33300, 36 [ASPEED_DEV_UART4] = 0X12C1A000, 37 [ASPEED_DEV_UART5] = 0X14C33400, 38 [ASPEED_DEV_UART6] = 0X14C33500, 39 [ASPEED_DEV_UART7] = 0X14C33600, 40 [ASPEED_DEV_UART8] = 0X14C33700, 41 [ASPEED_DEV_UART9] = 0X14C33800, 42 [ASPEED_DEV_UART10] = 0X14C33900, 43 [ASPEED_DEV_UART11] = 0X14C33A00, 44 [ASPEED_DEV_UART12] = 0X14C33B00, 45 [ASPEED_DEV_WDT] = 0x14C37000, 46 [ASPEED_DEV_VUART] = 0X14C30000, 47 [ASPEED_DEV_FMC] = 0x14000000, 48 [ASPEED_DEV_SPI0] = 0x14010000, 49 [ASPEED_DEV_SPI1] = 0x14020000, 50 [ASPEED_DEV_SPI2] = 0x14030000, 51 [ASPEED_DEV_SDRAM] = 0x400000000, 52 [ASPEED_DEV_MII1] = 0x14040000, 53 [ASPEED_DEV_MII2] = 0x14040008, 54 [ASPEED_DEV_MII3] = 0x14040010, 55 [ASPEED_DEV_ETH1] = 0x14050000, 56 [ASPEED_DEV_ETH2] = 0x14060000, 57 [ASPEED_DEV_ETH3] = 0x14070000, 58 [ASPEED_DEV_EMMC] = 0x12090000, 59 [ASPEED_DEV_INTC] = 0x12100000, 60 [ASPEED_DEV_SLI] = 0x12C17000, 61 [ASPEED_DEV_SLIIO] = 0x14C1E000, 62 [ASPEED_GIC_DIST] = 0x12200000, 63 [ASPEED_GIC_REDIST] = 0x12280000, 64 [ASPEED_DEV_ADC] = 0x14C00000, 65 [ASPEED_DEV_I2C] = 0x14C0F000, 66 [ASPEED_DEV_GPIO] = 0x14C0B000, 67 [ASPEED_DEV_RTC] = 0x12C0F000, 68 [ASPEED_DEV_SDHCI] = 0x14080000, 69 [ASPEED_DEV_TIMER1] = 0x12C10000, 70 }; 71 72 #define AST2700_MAX_IRQ 256 73 74 /* Shared Peripheral Interrupt values below are offset by -32 from datasheet */ 75 static const int aspeed_soc_ast2700_irqmap[] = { 76 [ASPEED_DEV_UART0] = 132, 77 [ASPEED_DEV_UART1] = 132, 78 [ASPEED_DEV_UART2] = 132, 79 [ASPEED_DEV_UART3] = 132, 80 [ASPEED_DEV_UART4] = 8, 81 [ASPEED_DEV_UART5] = 132, 82 [ASPEED_DEV_UART6] = 132, 83 [ASPEED_DEV_UART7] = 132, 84 [ASPEED_DEV_UART8] = 132, 85 [ASPEED_DEV_UART9] = 132, 86 [ASPEED_DEV_UART10] = 132, 87 [ASPEED_DEV_UART11] = 132, 88 [ASPEED_DEV_UART12] = 132, 89 [ASPEED_DEV_FMC] = 131, 90 [ASPEED_DEV_SDMC] = 0, 91 [ASPEED_DEV_SCU] = 12, 92 [ASPEED_DEV_ADC] = 130, 93 [ASPEED_DEV_XDMA] = 5, 94 [ASPEED_DEV_EMMC] = 15, 95 [ASPEED_DEV_GPIO] = 130, 96 [ASPEED_DEV_RTC] = 13, 97 [ASPEED_DEV_TIMER1] = 16, 98 [ASPEED_DEV_TIMER2] = 17, 99 [ASPEED_DEV_TIMER3] = 18, 100 [ASPEED_DEV_TIMER4] = 19, 101 [ASPEED_DEV_TIMER5] = 20, 102 [ASPEED_DEV_TIMER6] = 21, 103 [ASPEED_DEV_TIMER7] = 22, 104 [ASPEED_DEV_TIMER8] = 23, 105 [ASPEED_DEV_WDT] = 131, 106 [ASPEED_DEV_PWM] = 131, 107 [ASPEED_DEV_LPC] = 128, 108 [ASPEED_DEV_IBT] = 128, 109 [ASPEED_DEV_I2C] = 130, 110 [ASPEED_DEV_PECI] = 133, 111 [ASPEED_DEV_ETH1] = 132, 112 [ASPEED_DEV_ETH2] = 132, 113 [ASPEED_DEV_ETH3] = 132, 114 [ASPEED_DEV_HACE] = 4, 115 [ASPEED_DEV_KCS] = 128, 116 [ASPEED_DEV_DP] = 28, 117 [ASPEED_DEV_I3C] = 131, 118 [ASPEED_DEV_SDHCI] = 133, 119 }; 120 121 /* GICINT 128 */ 122 static const int aspeed_soc_ast2700_gic128_intcmap[] = { 123 [ASPEED_DEV_LPC] = 0, 124 [ASPEED_DEV_IBT] = 2, 125 [ASPEED_DEV_KCS] = 4, 126 }; 127 128 /* GICINT 130 */ 129 static const int aspeed_soc_ast2700_gic130_intcmap[] = { 130 [ASPEED_DEV_I2C] = 0, 131 [ASPEED_DEV_ADC] = 16, 132 [ASPEED_DEV_GPIO] = 18, 133 }; 134 135 /* GICINT 131 */ 136 static const int aspeed_soc_ast2700_gic131_intcmap[] = { 137 [ASPEED_DEV_I3C] = 0, 138 [ASPEED_DEV_WDT] = 16, 139 [ASPEED_DEV_FMC] = 25, 140 [ASPEED_DEV_PWM] = 29, 141 }; 142 143 /* GICINT 132 */ 144 static const int aspeed_soc_ast2700_gic132_intcmap[] = { 145 [ASPEED_DEV_ETH1] = 0, 146 [ASPEED_DEV_ETH2] = 1, 147 [ASPEED_DEV_ETH3] = 2, 148 [ASPEED_DEV_UART0] = 7, 149 [ASPEED_DEV_UART1] = 8, 150 [ASPEED_DEV_UART2] = 9, 151 [ASPEED_DEV_UART3] = 10, 152 [ASPEED_DEV_UART5] = 11, 153 [ASPEED_DEV_UART6] = 12, 154 [ASPEED_DEV_UART7] = 13, 155 [ASPEED_DEV_UART8] = 14, 156 [ASPEED_DEV_UART9] = 15, 157 [ASPEED_DEV_UART10] = 16, 158 [ASPEED_DEV_UART11] = 17, 159 [ASPEED_DEV_UART12] = 18, 160 }; 161 162 /* GICINT 133 */ 163 static const int aspeed_soc_ast2700_gic133_intcmap[] = { 164 [ASPEED_DEV_SDHCI] = 1, 165 [ASPEED_DEV_PECI] = 4, 166 }; 167 168 /* GICINT 128 ~ 136 */ 169 struct gic_intc_irq_info { 170 int irq; 171 const int *ptr; 172 }; 173 174 static const struct gic_intc_irq_info aspeed_soc_ast2700_gic_intcmap[] = { 175 {128, aspeed_soc_ast2700_gic128_intcmap}, 176 {129, NULL}, 177 {130, aspeed_soc_ast2700_gic130_intcmap}, 178 {131, aspeed_soc_ast2700_gic131_intcmap}, 179 {132, aspeed_soc_ast2700_gic132_intcmap}, 180 {133, aspeed_soc_ast2700_gic133_intcmap}, 181 {134, NULL}, 182 {135, NULL}, 183 {136, NULL}, 184 }; 185 186 static qemu_irq aspeed_soc_ast2700_get_irq(AspeedSoCState *s, int dev) 187 { 188 Aspeed27x0SoCState *a = ASPEED27X0_SOC(s); 189 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 190 int i; 191 192 for (i = 0; i < ARRAY_SIZE(aspeed_soc_ast2700_gic_intcmap); i++) { 193 if (sc->irqmap[dev] == aspeed_soc_ast2700_gic_intcmap[i].irq) { 194 assert(aspeed_soc_ast2700_gic_intcmap[i].ptr); 195 return qdev_get_gpio_in(DEVICE(&a->intc.orgates[i]), 196 aspeed_soc_ast2700_gic_intcmap[i].ptr[dev]); 197 } 198 } 199 200 return qdev_get_gpio_in(DEVICE(&a->gic), sc->irqmap[dev]); 201 } 202 203 static qemu_irq aspeed_soc_ast2700_get_irq_index(AspeedSoCState *s, int dev, 204 int index) 205 { 206 Aspeed27x0SoCState *a = ASPEED27X0_SOC(s); 207 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 208 int i; 209 210 for (i = 0; i < ARRAY_SIZE(aspeed_soc_ast2700_gic_intcmap); i++) { 211 if (sc->irqmap[dev] == aspeed_soc_ast2700_gic_intcmap[i].irq) { 212 assert(aspeed_soc_ast2700_gic_intcmap[i].ptr); 213 return qdev_get_gpio_in(DEVICE(&a->intc.orgates[i]), 214 aspeed_soc_ast2700_gic_intcmap[i].ptr[dev] + index); 215 } 216 } 217 218 /* 219 * Invalid orgate index, device irq should be 128 to 136. 220 */ 221 g_assert_not_reached(); 222 } 223 224 static uint64_t aspeed_ram_capacity_read(void *opaque, hwaddr addr, 225 unsigned int size) 226 { 227 qemu_log_mask(LOG_GUEST_ERROR, 228 "%s: DRAM read out of ram size, addr:0x%" PRIx64 "\n", 229 __func__, addr); 230 return 0; 231 } 232 233 static void aspeed_ram_capacity_write(void *opaque, hwaddr addr, uint64_t data, 234 unsigned int size) 235 { 236 AspeedSoCState *s = ASPEED_SOC(opaque); 237 ram_addr_t ram_size; 238 MemTxResult result; 239 240 ram_size = object_property_get_uint(OBJECT(&s->sdmc), "ram-size", 241 &error_abort); 242 243 assert(ram_size > 0); 244 245 /* 246 * Emulate ddr capacity hardware behavior. 247 * If writes the data to the address which is beyond the ram size, 248 * it would write the data to the "address % ram_size". 249 */ 250 result = address_space_write(&s->dram_as, addr % ram_size, 251 MEMTXATTRS_UNSPECIFIED, &data, 4); 252 if (result != MEMTX_OK) { 253 qemu_log_mask(LOG_GUEST_ERROR, 254 "%s: DRAM write failed, addr:0x%" HWADDR_PRIx 255 ", data :0x%" PRIx64 "\n", 256 __func__, addr % ram_size, data); 257 } 258 } 259 260 static const MemoryRegionOps aspeed_ram_capacity_ops = { 261 .read = aspeed_ram_capacity_read, 262 .write = aspeed_ram_capacity_write, 263 .endianness = DEVICE_LITTLE_ENDIAN, 264 .valid = { 265 .min_access_size = 1, 266 .max_access_size = 8, 267 }, 268 }; 269 270 /* 271 * SDMC should be realized first to get correct RAM size and max size 272 * values 273 */ 274 static bool aspeed_soc_ast2700_dram_init(DeviceState *dev, Error **errp) 275 { 276 ram_addr_t ram_size, max_ram_size; 277 Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev); 278 AspeedSoCState *s = ASPEED_SOC(dev); 279 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 280 281 ram_size = object_property_get_uint(OBJECT(&s->sdmc), "ram-size", 282 &error_abort); 283 max_ram_size = object_property_get_uint(OBJECT(&s->sdmc), "max-ram-size", 284 &error_abort); 285 286 memory_region_init(&s->dram_container, OBJECT(s), "ram-container", 287 ram_size); 288 memory_region_add_subregion(&s->dram_container, 0, s->dram_mr); 289 address_space_init(&s->dram_as, s->dram_mr, "dram"); 290 291 /* 292 * Add a memory region beyond the RAM region to emulate 293 * ddr capacity hardware behavior. 294 */ 295 if (ram_size < max_ram_size) { 296 memory_region_init_io(&a->dram_empty, OBJECT(s), 297 &aspeed_ram_capacity_ops, s, 298 "ram-empty", max_ram_size - ram_size); 299 300 memory_region_add_subregion(s->memory, 301 sc->memmap[ASPEED_DEV_SDRAM] + ram_size, 302 &a->dram_empty); 303 } 304 305 memory_region_add_subregion(s->memory, 306 sc->memmap[ASPEED_DEV_SDRAM], &s->dram_container); 307 return true; 308 } 309 310 static void aspeed_soc_ast2700_init(Object *obj) 311 { 312 Aspeed27x0SoCState *a = ASPEED27X0_SOC(obj); 313 AspeedSoCState *s = ASPEED_SOC(obj); 314 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 315 int i; 316 char socname[8]; 317 char typename[64]; 318 319 if (sscanf(sc->name, "%7s", socname) != 1) { 320 g_assert_not_reached(); 321 } 322 323 for (i = 0; i < sc->num_cpus; i++) { 324 object_initialize_child(obj, "cpu[*]", &a->cpu[i], 325 aspeed_soc_cpu_type(sc)); 326 } 327 328 object_initialize_child(obj, "gic", &a->gic, gicv3_class_name()); 329 330 object_initialize_child(obj, "scu", &s->scu, TYPE_ASPEED_2700_SCU); 331 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", 332 sc->silicon_rev); 333 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), 334 "hw-strap1"); 335 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), 336 "hw-strap2"); 337 object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu), 338 "hw-prot-key"); 339 340 object_initialize_child(obj, "scuio", &s->scuio, TYPE_ASPEED_2700_SCUIO); 341 qdev_prop_set_uint32(DEVICE(&s->scuio), "silicon-rev", 342 sc->silicon_rev); 343 344 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); 345 object_initialize_child(obj, "fmc", &s->fmc, typename); 346 347 for (i = 0; i < sc->spis_num; i++) { 348 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i, socname); 349 object_initialize_child(obj, "spi[*]", &s->spi[i], typename); 350 } 351 352 snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname); 353 object_initialize_child(obj, "sdmc", &s->sdmc, typename); 354 object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), 355 "ram-size"); 356 357 for (i = 0; i < sc->wdts_num; i++) { 358 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); 359 object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename); 360 } 361 362 for (i = 0; i < sc->macs_num; i++) { 363 object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i], 364 TYPE_FTGMAC100); 365 366 object_initialize_child(obj, "mii[*]", &s->mii[i], TYPE_ASPEED_MII); 367 } 368 369 for (i = 0; i < sc->uarts_num; i++) { 370 object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM); 371 } 372 373 object_initialize_child(obj, "sli", &s->sli, TYPE_ASPEED_2700_SLI); 374 object_initialize_child(obj, "sliio", &s->sliio, TYPE_ASPEED_2700_SLIIO); 375 object_initialize_child(obj, "intc", &a->intc, TYPE_ASPEED_2700_INTC); 376 377 snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname); 378 object_initialize_child(obj, "adc", &s->adc, typename); 379 380 snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); 381 object_initialize_child(obj, "i2c", &s->i2c, typename); 382 383 snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); 384 object_initialize_child(obj, "gpio", &s->gpio, typename); 385 386 object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC); 387 388 snprintf(typename, sizeof(typename), "aspeed.sdhci-%s", socname); 389 object_initialize_child(obj, "sd-controller", &s->sdhci, typename); 390 object_property_set_int(OBJECT(&s->sdhci), "num-slots", 1, &error_abort); 391 392 /* Init sd card slot class here so that they're under the correct parent */ 393 object_initialize_child(obj, "sd-controller.sdhci", 394 &s->sdhci.slots[0], TYPE_SYSBUS_SDHCI); 395 396 object_initialize_child(obj, "emmc-controller", &s->emmc, typename); 397 object_property_set_int(OBJECT(&s->emmc), "num-slots", 1, &error_abort); 398 399 object_initialize_child(obj, "emmc-controller.sdhci", &s->emmc.slots[0], 400 TYPE_SYSBUS_SDHCI); 401 402 snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname); 403 object_initialize_child(obj, "timerctrl", &s->timerctrl, typename); 404 } 405 406 /* 407 * ASPEED ast2700 has 0x0 as cluster ID 408 * 409 * https://developer.arm.com/documentation/100236/0100/register-descriptions/aarch64-system-registers/multiprocessor-affinity-register--el1 410 */ 411 static uint64_t aspeed_calc_affinity(int cpu) 412 { 413 return (0x0 << ARM_AFF1_SHIFT) | cpu; 414 } 415 416 static bool aspeed_soc_ast2700_gic_realize(DeviceState *dev, Error **errp) 417 { 418 Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev); 419 AspeedSoCState *s = ASPEED_SOC(dev); 420 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 421 SysBusDevice *gicbusdev; 422 DeviceState *gicdev; 423 QList *redist_region_count; 424 int i; 425 426 gicbusdev = SYS_BUS_DEVICE(&a->gic); 427 gicdev = DEVICE(&a->gic); 428 qdev_prop_set_uint32(gicdev, "revision", 3); 429 qdev_prop_set_uint32(gicdev, "num-cpu", sc->num_cpus); 430 qdev_prop_set_uint32(gicdev, "num-irq", AST2700_MAX_IRQ + GIC_INTERNAL); 431 432 redist_region_count = qlist_new(); 433 qlist_append_int(redist_region_count, sc->num_cpus); 434 qdev_prop_set_array(gicdev, "redist-region-count", redist_region_count); 435 436 if (!sysbus_realize(gicbusdev, errp)) { 437 return false; 438 } 439 sysbus_mmio_map(gicbusdev, 0, sc->memmap[ASPEED_GIC_DIST]); 440 sysbus_mmio_map(gicbusdev, 1, sc->memmap[ASPEED_GIC_REDIST]); 441 442 for (i = 0; i < sc->num_cpus; i++) { 443 DeviceState *cpudev = DEVICE(&a->cpu[i]); 444 int intidbase = AST2700_MAX_IRQ + i * GIC_INTERNAL; 445 446 const int timer_irq[] = { 447 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, 448 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, 449 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, 450 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, 451 }; 452 int j; 453 454 for (j = 0; j < ARRAY_SIZE(timer_irq); j++) { 455 qdev_connect_gpio_out(cpudev, j, 456 qdev_get_gpio_in(gicdev, intidbase + timer_irq[j])); 457 } 458 459 qemu_irq irq = qdev_get_gpio_in(gicdev, 460 intidbase + ARCH_GIC_MAINT_IRQ); 461 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 462 0, irq); 463 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, 464 qdev_get_gpio_in(gicdev, intidbase + VIRTUAL_PMU_IRQ)); 465 466 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 467 sysbus_connect_irq(gicbusdev, i + sc->num_cpus, 468 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 469 sysbus_connect_irq(gicbusdev, i + 2 * sc->num_cpus, 470 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 471 sysbus_connect_irq(gicbusdev, i + 3 * sc->num_cpus, 472 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 473 } 474 475 return true; 476 } 477 478 static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp) 479 { 480 int i; 481 Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev); 482 AspeedSoCState *s = ASPEED_SOC(dev); 483 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 484 AspeedINTCClass *ic = ASPEED_INTC_GET_CLASS(&a->intc); 485 g_autofree char *sram_name = NULL; 486 qemu_irq irq; 487 488 /* Default boot region (SPI memory or ROMs) */ 489 memory_region_init(&s->spi_boot_container, OBJECT(s), 490 "aspeed.spi_boot_container", 0x400000000); 491 memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SPI_BOOT], 492 &s->spi_boot_container); 493 494 /* CPU */ 495 for (i = 0; i < sc->num_cpus; i++) { 496 object_property_set_int(OBJECT(&a->cpu[i]), "mp-affinity", 497 aspeed_calc_affinity(i), &error_abort); 498 499 object_property_set_int(OBJECT(&a->cpu[i]), "cntfrq", 1125000000, 500 &error_abort); 501 object_property_set_link(OBJECT(&a->cpu[i]), "memory", 502 OBJECT(s->memory), &error_abort); 503 504 if (!qdev_realize(DEVICE(&a->cpu[i]), NULL, errp)) { 505 return; 506 } 507 } 508 509 /* GIC */ 510 if (!aspeed_soc_ast2700_gic_realize(dev, errp)) { 511 return; 512 } 513 514 /* INTC */ 515 if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc), errp)) { 516 return; 517 } 518 519 aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc), 0, 520 sc->memmap[ASPEED_DEV_INTC]); 521 522 /* GICINT orgates -> INTC -> GIC */ 523 for (i = 0; i < ic->num_ints; i++) { 524 qdev_connect_gpio_out(DEVICE(&a->intc.orgates[i]), 0, 525 qdev_get_gpio_in(DEVICE(&a->intc), i)); 526 sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc), i, 527 qdev_get_gpio_in(DEVICE(&a->gic), 528 aspeed_soc_ast2700_gic_intcmap[i].irq)); 529 } 530 531 /* SRAM */ 532 sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index); 533 if (!memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, 534 errp)) { 535 return; 536 } 537 memory_region_add_subregion(s->memory, 538 sc->memmap[ASPEED_DEV_SRAM], &s->sram); 539 540 /* SCU */ 541 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { 542 return; 543 } 544 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]); 545 546 /* SCU1 */ 547 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scuio), errp)) { 548 return; 549 } 550 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scuio), 0, 551 sc->memmap[ASPEED_DEV_SCUIO]); 552 553 /* UART */ 554 if (!aspeed_soc_uart_realize(s, errp)) { 555 return; 556 } 557 558 /* FMC, The number of CS is set at the board level */ 559 object_property_set_int(OBJECT(&s->fmc), "dram-base", 560 sc->memmap[ASPEED_DEV_SDRAM], 561 &error_abort); 562 object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr), 563 &error_abort); 564 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) { 565 return; 566 } 567 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]); 568 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 1, 569 ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base); 570 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, 571 aspeed_soc_get_irq(s, ASPEED_DEV_FMC)); 572 573 /* Set up an alias on the FMC CE0 region (boot default) */ 574 MemoryRegion *fmc0_mmio = &s->fmc.flashes[0].mmio; 575 memory_region_init_alias(&s->spi_boot, OBJECT(s), "aspeed.spi_boot", 576 fmc0_mmio, 0, memory_region_size(fmc0_mmio)); 577 memory_region_add_subregion(&s->spi_boot_container, 0x0, &s->spi_boot); 578 579 /* SPI */ 580 for (i = 0; i < sc->spis_num; i++) { 581 object_property_set_link(OBJECT(&s->spi[i]), "dram", 582 OBJECT(s->dram_mr), &error_abort); 583 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { 584 return; 585 } 586 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 0, 587 sc->memmap[ASPEED_DEV_SPI0 + i]); 588 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 1, 589 ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base); 590 } 591 592 /* 593 * SDMC - SDRAM Memory Controller 594 * The SDMC controller is unlocked at SPL stage. 595 * At present, only supports to emulate booting 596 * start from u-boot stage. Set SDMC controller 597 * unlocked by default. It is a temporarily solution. 598 */ 599 object_property_set_bool(OBJECT(&s->sdmc), "unlocked", true, 600 &error_abort); 601 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) { 602 return; 603 } 604 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdmc), 0, 605 sc->memmap[ASPEED_DEV_SDMC]); 606 607 /* RAM */ 608 if (!aspeed_soc_ast2700_dram_init(dev, errp)) { 609 return; 610 } 611 612 /* Net */ 613 for (i = 0; i < sc->macs_num; i++) { 614 object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true, 615 &error_abort); 616 object_property_set_bool(OBJECT(&s->ftgmac100[i]), "dma64", true, 617 &error_abort); 618 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) { 619 return; 620 } 621 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 622 sc->memmap[ASPEED_DEV_ETH1 + i]); 623 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 624 aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i)); 625 626 object_property_set_link(OBJECT(&s->mii[i]), "nic", 627 OBJECT(&s->ftgmac100[i]), &error_abort); 628 if (!sysbus_realize(SYS_BUS_DEVICE(&s->mii[i]), errp)) { 629 return; 630 } 631 632 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->mii[i]), 0, 633 sc->memmap[ASPEED_DEV_MII1 + i]); 634 } 635 636 /* Watch dog */ 637 for (i = 0; i < sc->wdts_num; i++) { 638 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); 639 hwaddr wdt_offset = sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize; 640 641 object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu), 642 &error_abort); 643 if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) { 644 return; 645 } 646 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offset); 647 } 648 649 /* SLI */ 650 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sli), errp)) { 651 return; 652 } 653 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sli), 0, sc->memmap[ASPEED_DEV_SLI]); 654 655 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sliio), errp)) { 656 return; 657 } 658 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sliio), 0, 659 sc->memmap[ASPEED_DEV_SLIIO]); 660 661 /* ADC */ 662 if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) { 663 return; 664 } 665 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]); 666 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0, 667 aspeed_soc_get_irq(s, ASPEED_DEV_ADC)); 668 669 /* I2C */ 670 object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr), 671 &error_abort); 672 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) { 673 return; 674 } 675 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]); 676 for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) { 677 /* 678 * The AST2700 I2C controller has one source INTC per bus. 679 * I2C buses interrupt are connected to GICINT130_INTC 680 * from bit 0 to bit 15. 681 * I2C bus 0 is connected to GICINT130_INTC at bit 0. 682 * I2C bus 15 is connected to GICINT130_INTC at bit 15. 683 */ 684 irq = aspeed_soc_ast2700_get_irq_index(s, ASPEED_DEV_I2C, i); 685 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq); 686 } 687 688 /* GPIO */ 689 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { 690 return; 691 } 692 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio), 0, 693 sc->memmap[ASPEED_DEV_GPIO]); 694 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, 695 aspeed_soc_get_irq(s, ASPEED_DEV_GPIO)); 696 697 /* RTC */ 698 if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) { 699 return; 700 } 701 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_RTC]); 702 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, 703 aspeed_soc_get_irq(s, ASPEED_DEV_RTC)); 704 705 /* SDHCI */ 706 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) { 707 return; 708 } 709 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdhci), 0, 710 sc->memmap[ASPEED_DEV_SDHCI]); 711 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, 712 aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI)); 713 714 /* eMMC */ 715 if (!sysbus_realize(SYS_BUS_DEVICE(&s->emmc), errp)) { 716 return; 717 } 718 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->emmc), 0, 719 sc->memmap[ASPEED_DEV_EMMC]); 720 sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0, 721 aspeed_soc_get_irq(s, ASPEED_DEV_EMMC)); 722 723 /* Timer */ 724 object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu), 725 &error_abort); 726 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) { 727 return; 728 } 729 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->timerctrl), 0, 730 sc->memmap[ASPEED_DEV_TIMER1]); 731 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) { 732 irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i); 733 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); 734 } 735 736 create_unimplemented_device("ast2700.dpmcu", 0x11000000, 0x40000); 737 create_unimplemented_device("ast2700.iomem0", 0x12000000, 0x01000000); 738 create_unimplemented_device("ast2700.iomem1", 0x14000000, 0x01000000); 739 create_unimplemented_device("ast2700.ltpi", 0x30000000, 0x1000000); 740 create_unimplemented_device("ast2700.io", 0x0, 0x4000000); 741 } 742 743 static void aspeed_soc_ast2700_class_init(ObjectClass *oc, void *data) 744 { 745 static const char * const valid_cpu_types[] = { 746 ARM_CPU_TYPE_NAME("cortex-a35"), 747 NULL 748 }; 749 DeviceClass *dc = DEVICE_CLASS(oc); 750 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); 751 752 /* Reason: The Aspeed SoC can only be instantiated from a board */ 753 dc->user_creatable = false; 754 dc->realize = aspeed_soc_ast2700_realize; 755 756 sc->name = "ast2700-a0"; 757 sc->valid_cpu_types = valid_cpu_types; 758 sc->silicon_rev = AST2700_A0_SILICON_REV; 759 sc->sram_size = 0x20000; 760 sc->spis_num = 3; 761 sc->wdts_num = 8; 762 sc->macs_num = 1; 763 sc->uarts_num = 13; 764 sc->num_cpus = 4; 765 sc->uarts_base = ASPEED_DEV_UART0; 766 sc->irqmap = aspeed_soc_ast2700_irqmap; 767 sc->memmap = aspeed_soc_ast2700_memmap; 768 sc->get_irq = aspeed_soc_ast2700_get_irq; 769 } 770 771 static const TypeInfo aspeed_soc_ast27x0_types[] = { 772 { 773 .name = TYPE_ASPEED27X0_SOC, 774 .parent = TYPE_ASPEED_SOC, 775 .instance_size = sizeof(Aspeed27x0SoCState), 776 .abstract = true, 777 }, { 778 .name = "ast2700-a0", 779 .parent = TYPE_ASPEED27X0_SOC, 780 .instance_init = aspeed_soc_ast2700_init, 781 .class_init = aspeed_soc_ast2700_class_init, 782 }, 783 }; 784 785 DEFINE_TYPES(aspeed_soc_ast27x0_types) 786