1 /* 2 * ASPEED SoC 27x0 family 3 * 4 * Copyright (C) 2024 ASPEED Technology Inc. 5 * 6 * This code is licensed under the GPL version 2 or later. See 7 * the COPYING file in the top-level directory. 8 * 9 * Implementation extracted from the AST2600 and adapted for AST27x0. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qapi/error.h" 14 #include "hw/misc/unimp.h" 15 #include "hw/arm/aspeed_soc.h" 16 #include "qemu/module.h" 17 #include "qemu/error-report.h" 18 #include "hw/i2c/aspeed_i2c.h" 19 #include "net/net.h" 20 #include "sysemu/sysemu.h" 21 #include "hw/intc/arm_gicv3.h" 22 #include "qapi/qmp/qlist.h" 23 24 static const hwaddr aspeed_soc_ast2700_memmap[] = { 25 [ASPEED_DEV_SPI_BOOT] = 0x400000000, 26 [ASPEED_DEV_SRAM] = 0x10000000, 27 [ASPEED_DEV_SDMC] = 0x12C00000, 28 [ASPEED_DEV_SCU] = 0x12C02000, 29 [ASPEED_DEV_SCUIO] = 0x14C02000, 30 [ASPEED_DEV_UART0] = 0X14C33000, 31 [ASPEED_DEV_UART1] = 0X14C33100, 32 [ASPEED_DEV_UART2] = 0X14C33200, 33 [ASPEED_DEV_UART3] = 0X14C33300, 34 [ASPEED_DEV_UART4] = 0X12C1A000, 35 [ASPEED_DEV_UART5] = 0X14C33400, 36 [ASPEED_DEV_UART6] = 0X14C33500, 37 [ASPEED_DEV_UART7] = 0X14C33600, 38 [ASPEED_DEV_UART8] = 0X14C33700, 39 [ASPEED_DEV_UART9] = 0X14C33800, 40 [ASPEED_DEV_UART10] = 0X14C33900, 41 [ASPEED_DEV_UART11] = 0X14C33A00, 42 [ASPEED_DEV_UART12] = 0X14C33B00, 43 [ASPEED_DEV_WDT] = 0x14C37000, 44 [ASPEED_DEV_VUART] = 0X14C30000, 45 [ASPEED_DEV_FMC] = 0x14000000, 46 [ASPEED_DEV_SPI0] = 0x14010000, 47 [ASPEED_DEV_SPI1] = 0x14020000, 48 [ASPEED_DEV_SPI2] = 0x14030000, 49 [ASPEED_DEV_SDRAM] = 0x400000000, 50 [ASPEED_DEV_MII1] = 0x14040000, 51 [ASPEED_DEV_MII2] = 0x14040008, 52 [ASPEED_DEV_MII3] = 0x14040010, 53 [ASPEED_DEV_ETH1] = 0x14050000, 54 [ASPEED_DEV_ETH2] = 0x14060000, 55 [ASPEED_DEV_ETH3] = 0x14070000, 56 [ASPEED_DEV_EMMC] = 0x12090000, 57 [ASPEED_DEV_INTC] = 0x12100000, 58 [ASPEED_DEV_SLI] = 0x12C17000, 59 [ASPEED_DEV_SLIIO] = 0x14C1E000, 60 [ASPEED_GIC_DIST] = 0x12200000, 61 [ASPEED_GIC_REDIST] = 0x12280000, 62 }; 63 64 #define AST2700_MAX_IRQ 288 65 66 /* Shared Peripheral Interrupt values below are offset by -32 from datasheet */ 67 static const int aspeed_soc_ast2700_irqmap[] = { 68 [ASPEED_DEV_UART0] = 132, 69 [ASPEED_DEV_UART1] = 132, 70 [ASPEED_DEV_UART2] = 132, 71 [ASPEED_DEV_UART3] = 132, 72 [ASPEED_DEV_UART4] = 8, 73 [ASPEED_DEV_UART5] = 132, 74 [ASPEED_DEV_UART6] = 132, 75 [ASPEED_DEV_UART7] = 132, 76 [ASPEED_DEV_UART8] = 132, 77 [ASPEED_DEV_UART9] = 132, 78 [ASPEED_DEV_UART10] = 132, 79 [ASPEED_DEV_UART11] = 132, 80 [ASPEED_DEV_UART12] = 132, 81 [ASPEED_DEV_FMC] = 131, 82 [ASPEED_DEV_SDMC] = 0, 83 [ASPEED_DEV_SCU] = 12, 84 [ASPEED_DEV_ADC] = 130, 85 [ASPEED_DEV_XDMA] = 5, 86 [ASPEED_DEV_EMMC] = 15, 87 [ASPEED_DEV_GPIO] = 11, 88 [ASPEED_DEV_GPIO_1_8V] = 130, 89 [ASPEED_DEV_RTC] = 13, 90 [ASPEED_DEV_TIMER1] = 16, 91 [ASPEED_DEV_TIMER2] = 17, 92 [ASPEED_DEV_TIMER3] = 18, 93 [ASPEED_DEV_TIMER4] = 19, 94 [ASPEED_DEV_TIMER5] = 20, 95 [ASPEED_DEV_TIMER6] = 21, 96 [ASPEED_DEV_TIMER7] = 22, 97 [ASPEED_DEV_TIMER8] = 23, 98 [ASPEED_DEV_WDT] = 131, 99 [ASPEED_DEV_PWM] = 131, 100 [ASPEED_DEV_LPC] = 128, 101 [ASPEED_DEV_IBT] = 128, 102 [ASPEED_DEV_I2C] = 130, 103 [ASPEED_DEV_PECI] = 133, 104 [ASPEED_DEV_ETH1] = 132, 105 [ASPEED_DEV_ETH2] = 132, 106 [ASPEED_DEV_ETH3] = 132, 107 [ASPEED_DEV_HACE] = 4, 108 [ASPEED_DEV_KCS] = 128, 109 [ASPEED_DEV_DP] = 28, 110 [ASPEED_DEV_I3C] = 131, 111 }; 112 113 /* GICINT 128 */ 114 static const int aspeed_soc_ast2700_gic128_intcmap[] = { 115 [ASPEED_DEV_LPC] = 0, 116 [ASPEED_DEV_IBT] = 2, 117 [ASPEED_DEV_KCS] = 4, 118 }; 119 120 /* GICINT 130 */ 121 static const int aspeed_soc_ast2700_gic130_intcmap[] = { 122 [ASPEED_DEV_I2C] = 0, 123 [ASPEED_DEV_ADC] = 16, 124 [ASPEED_DEV_GPIO_1_8V] = 18, 125 }; 126 127 /* GICINT 131 */ 128 static const int aspeed_soc_ast2700_gic131_intcmap[] = { 129 [ASPEED_DEV_I3C] = 0, 130 [ASPEED_DEV_WDT] = 16, 131 [ASPEED_DEV_FMC] = 25, 132 [ASPEED_DEV_PWM] = 29, 133 }; 134 135 /* GICINT 132 */ 136 static const int aspeed_soc_ast2700_gic132_intcmap[] = { 137 [ASPEED_DEV_ETH1] = 0, 138 [ASPEED_DEV_ETH2] = 1, 139 [ASPEED_DEV_ETH3] = 2, 140 [ASPEED_DEV_UART0] = 7, 141 [ASPEED_DEV_UART1] = 8, 142 [ASPEED_DEV_UART2] = 9, 143 [ASPEED_DEV_UART3] = 10, 144 [ASPEED_DEV_UART5] = 11, 145 [ASPEED_DEV_UART6] = 12, 146 [ASPEED_DEV_UART7] = 13, 147 [ASPEED_DEV_UART8] = 14, 148 [ASPEED_DEV_UART9] = 15, 149 [ASPEED_DEV_UART10] = 16, 150 [ASPEED_DEV_UART11] = 17, 151 [ASPEED_DEV_UART12] = 18, 152 }; 153 154 /* GICINT 133 */ 155 static const int aspeed_soc_ast2700_gic133_intcmap[] = { 156 [ASPEED_DEV_PECI] = 4, 157 }; 158 159 /* GICINT 128 ~ 136 */ 160 struct gic_intc_irq_info { 161 int irq; 162 const int *ptr; 163 }; 164 165 static const struct gic_intc_irq_info aspeed_soc_ast2700_gic_intcmap[] = { 166 {128, aspeed_soc_ast2700_gic128_intcmap}, 167 {129, NULL}, 168 {130, aspeed_soc_ast2700_gic130_intcmap}, 169 {131, aspeed_soc_ast2700_gic131_intcmap}, 170 {132, aspeed_soc_ast2700_gic132_intcmap}, 171 {133, aspeed_soc_ast2700_gic133_intcmap}, 172 {134, NULL}, 173 {135, NULL}, 174 {136, NULL}, 175 }; 176 177 static qemu_irq aspeed_soc_ast2700_get_irq(AspeedSoCState *s, int dev) 178 { 179 Aspeed27x0SoCState *a = ASPEED27X0_SOC(s); 180 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 181 int i; 182 183 for (i = 0; i < ARRAY_SIZE(aspeed_soc_ast2700_gic_intcmap); i++) { 184 if (sc->irqmap[dev] == aspeed_soc_ast2700_gic_intcmap[i].irq) { 185 assert(aspeed_soc_ast2700_gic_intcmap[i].ptr); 186 return qdev_get_gpio_in(DEVICE(&a->intc.orgates[i]), 187 aspeed_soc_ast2700_gic_intcmap[i].ptr[dev]); 188 } 189 } 190 191 return qdev_get_gpio_in(DEVICE(&a->gic), sc->irqmap[dev]); 192 } 193 194 static void aspeed_soc_ast2700_init(Object *obj) 195 { 196 Aspeed27x0SoCState *a = ASPEED27X0_SOC(obj); 197 AspeedSoCState *s = ASPEED_SOC(obj); 198 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 199 int i; 200 char socname[8]; 201 char typename[64]; 202 203 if (sscanf(sc->name, "%7s", socname) != 1) { 204 g_assert_not_reached(); 205 } 206 207 for (i = 0; i < sc->num_cpus; i++) { 208 object_initialize_child(obj, "cpu[*]", &a->cpu[i], 209 aspeed_soc_cpu_type(sc)); 210 } 211 212 object_initialize_child(obj, "gic", &a->gic, gicv3_class_name()); 213 214 object_initialize_child(obj, "scu", &s->scu, TYPE_ASPEED_2700_SCU); 215 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", 216 sc->silicon_rev); 217 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), 218 "hw-strap1"); 219 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), 220 "hw-strap2"); 221 object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu), 222 "hw-prot-key"); 223 224 object_initialize_child(obj, "scuio", &s->scuio, TYPE_ASPEED_2700_SCUIO); 225 qdev_prop_set_uint32(DEVICE(&s->scuio), "silicon-rev", 226 sc->silicon_rev); 227 228 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); 229 object_initialize_child(obj, "fmc", &s->fmc, typename); 230 231 for (i = 0; i < sc->spis_num; i++) { 232 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i, socname); 233 object_initialize_child(obj, "spi[*]", &s->spi[i], typename); 234 } 235 236 snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname); 237 object_initialize_child(obj, "sdmc", &s->sdmc, typename); 238 object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), 239 "ram-size"); 240 241 for (i = 0; i < sc->wdts_num; i++) { 242 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); 243 object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename); 244 } 245 246 for (i = 0; i < sc->macs_num; i++) { 247 object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i], 248 TYPE_FTGMAC100); 249 250 object_initialize_child(obj, "mii[*]", &s->mii[i], TYPE_ASPEED_MII); 251 } 252 253 for (i = 0; i < sc->uarts_num; i++) { 254 object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM); 255 } 256 257 object_initialize_child(obj, "sli", &s->sli, TYPE_ASPEED_2700_SLI); 258 object_initialize_child(obj, "sliio", &s->sliio, TYPE_ASPEED_2700_SLIIO); 259 object_initialize_child(obj, "intc", &a->intc, TYPE_ASPEED_2700_INTC); 260 } 261 262 /* 263 * ASPEED ast2700 has 0x0 as cluster ID 264 * 265 * https://developer.arm.com/documentation/100236/0100/register-descriptions/aarch64-system-registers/multiprocessor-affinity-register--el1 266 */ 267 static uint64_t aspeed_calc_affinity(int cpu) 268 { 269 return (0x0 << ARM_AFF1_SHIFT) | cpu; 270 } 271 272 static bool aspeed_soc_ast2700_gic_realize(DeviceState *dev, Error **errp) 273 { 274 Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev); 275 AspeedSoCState *s = ASPEED_SOC(dev); 276 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 277 SysBusDevice *gicbusdev; 278 DeviceState *gicdev; 279 QList *redist_region_count; 280 int i; 281 282 gicbusdev = SYS_BUS_DEVICE(&a->gic); 283 gicdev = DEVICE(&a->gic); 284 qdev_prop_set_uint32(gicdev, "revision", 3); 285 qdev_prop_set_uint32(gicdev, "num-cpu", sc->num_cpus); 286 qdev_prop_set_uint32(gicdev, "num-irq", AST2700_MAX_IRQ); 287 288 redist_region_count = qlist_new(); 289 qlist_append_int(redist_region_count, sc->num_cpus); 290 qdev_prop_set_array(gicdev, "redist-region-count", redist_region_count); 291 292 if (!sysbus_realize(gicbusdev, errp)) { 293 return false; 294 } 295 sysbus_mmio_map(gicbusdev, 0, sc->memmap[ASPEED_GIC_DIST]); 296 sysbus_mmio_map(gicbusdev, 1, sc->memmap[ASPEED_GIC_REDIST]); 297 298 for (i = 0; i < sc->num_cpus; i++) { 299 DeviceState *cpudev = DEVICE(&a->cpu[i]); 300 int NUM_IRQS = 256, ARCH_GIC_MAINT_IRQ = 9, VIRTUAL_PMU_IRQ = 7; 301 int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; 302 303 const int timer_irq[] = { 304 [GTIMER_PHYS] = 14, 305 [GTIMER_VIRT] = 11, 306 [GTIMER_HYP] = 10, 307 [GTIMER_SEC] = 13, 308 }; 309 int j; 310 311 for (j = 0; j < ARRAY_SIZE(timer_irq); j++) { 312 qdev_connect_gpio_out(cpudev, j, 313 qdev_get_gpio_in(gicdev, ppibase + timer_irq[j])); 314 } 315 316 qemu_irq irq = qdev_get_gpio_in(gicdev, 317 ppibase + ARCH_GIC_MAINT_IRQ); 318 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 319 0, irq); 320 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, 321 qdev_get_gpio_in(gicdev, ppibase + VIRTUAL_PMU_IRQ)); 322 323 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 324 sysbus_connect_irq(gicbusdev, i + sc->num_cpus, 325 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 326 sysbus_connect_irq(gicbusdev, i + 2 * sc->num_cpus, 327 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 328 sysbus_connect_irq(gicbusdev, i + 3 * sc->num_cpus, 329 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 330 } 331 332 return true; 333 } 334 335 static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp) 336 { 337 int i; 338 Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev); 339 AspeedSoCState *s = ASPEED_SOC(dev); 340 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 341 AspeedINTCClass *ic = ASPEED_INTC_GET_CLASS(&a->intc); 342 g_autofree char *sram_name = NULL; 343 344 /* Default boot region (SPI memory or ROMs) */ 345 memory_region_init(&s->spi_boot_container, OBJECT(s), 346 "aspeed.spi_boot_container", 0x400000000); 347 memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SPI_BOOT], 348 &s->spi_boot_container); 349 350 /* CPU */ 351 for (i = 0; i < sc->num_cpus; i++) { 352 object_property_set_int(OBJECT(&a->cpu[i]), "mp-affinity", 353 aspeed_calc_affinity(i), &error_abort); 354 355 object_property_set_int(OBJECT(&a->cpu[i]), "cntfrq", 1125000000, 356 &error_abort); 357 object_property_set_link(OBJECT(&a->cpu[i]), "memory", 358 OBJECT(s->memory), &error_abort); 359 360 if (!qdev_realize(DEVICE(&a->cpu[i]), NULL, errp)) { 361 return; 362 } 363 } 364 365 /* GIC */ 366 if (!aspeed_soc_ast2700_gic_realize(dev, errp)) { 367 return; 368 } 369 370 /* INTC */ 371 if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc), errp)) { 372 return; 373 } 374 375 aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc), 0, 376 sc->memmap[ASPEED_DEV_INTC]); 377 378 /* GICINT orgates -> INTC -> GIC */ 379 for (i = 0; i < ic->num_ints; i++) { 380 qdev_connect_gpio_out(DEVICE(&a->intc.orgates[i]), 0, 381 qdev_get_gpio_in(DEVICE(&a->intc), i)); 382 sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc), i, 383 qdev_get_gpio_in(DEVICE(&a->gic), 384 aspeed_soc_ast2700_gic_intcmap[i].irq)); 385 } 386 387 /* SRAM */ 388 sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index); 389 if (!memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, 390 errp)) { 391 return; 392 } 393 memory_region_add_subregion(s->memory, 394 sc->memmap[ASPEED_DEV_SRAM], &s->sram); 395 396 /* SCU */ 397 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { 398 return; 399 } 400 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]); 401 402 /* SCU1 */ 403 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scuio), errp)) { 404 return; 405 } 406 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scuio), 0, 407 sc->memmap[ASPEED_DEV_SCUIO]); 408 409 /* UART */ 410 if (!aspeed_soc_uart_realize(s, errp)) { 411 return; 412 } 413 414 /* FMC, The number of CS is set at the board level */ 415 object_property_set_int(OBJECT(&s->fmc), "dram-base", 416 sc->memmap[ASPEED_DEV_SDRAM], 417 &error_abort); 418 object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr), 419 &error_abort); 420 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) { 421 return; 422 } 423 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]); 424 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 1, 425 ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base); 426 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, 427 aspeed_soc_get_irq(s, ASPEED_DEV_FMC)); 428 429 /* Set up an alias on the FMC CE0 region (boot default) */ 430 MemoryRegion *fmc0_mmio = &s->fmc.flashes[0].mmio; 431 memory_region_init_alias(&s->spi_boot, OBJECT(s), "aspeed.spi_boot", 432 fmc0_mmio, 0, memory_region_size(fmc0_mmio)); 433 memory_region_add_subregion(&s->spi_boot_container, 0x0, &s->spi_boot); 434 435 /* SPI */ 436 for (i = 0; i < sc->spis_num; i++) { 437 object_property_set_link(OBJECT(&s->spi[i]), "dram", 438 OBJECT(s->dram_mr), &error_abort); 439 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { 440 return; 441 } 442 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 0, 443 sc->memmap[ASPEED_DEV_SPI0 + i]); 444 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 1, 445 ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base); 446 } 447 448 /* 449 * SDMC - SDRAM Memory Controller 450 * The SDMC controller is unlocked at SPL stage. 451 * At present, only supports to emulate booting 452 * start from u-boot stage. Set SDMC controller 453 * unlocked by default. It is a temporarily solution. 454 */ 455 object_property_set_bool(OBJECT(&s->sdmc), "unlocked", true, 456 &error_abort); 457 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) { 458 return; 459 } 460 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdmc), 0, 461 sc->memmap[ASPEED_DEV_SDMC]); 462 463 /* RAM */ 464 if (!aspeed_soc_dram_init(s, errp)) { 465 return; 466 } 467 468 for (i = 0; i < sc->macs_num; i++) { 469 object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true, 470 &error_abort); 471 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) { 472 return; 473 } 474 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 475 sc->memmap[ASPEED_DEV_ETH1 + i]); 476 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 477 aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i)); 478 479 object_property_set_link(OBJECT(&s->mii[i]), "nic", 480 OBJECT(&s->ftgmac100[i]), &error_abort); 481 if (!sysbus_realize(SYS_BUS_DEVICE(&s->mii[i]), errp)) { 482 return; 483 } 484 485 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->mii[i]), 0, 486 sc->memmap[ASPEED_DEV_MII1 + i]); 487 } 488 489 /* Watch dog */ 490 for (i = 0; i < sc->wdts_num; i++) { 491 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); 492 hwaddr wdt_offset = sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize; 493 494 object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu), 495 &error_abort); 496 if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) { 497 return; 498 } 499 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offset); 500 } 501 502 /* SLI */ 503 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sli), errp)) { 504 return; 505 } 506 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sli), 0, sc->memmap[ASPEED_DEV_SLI]); 507 508 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sliio), errp)) { 509 return; 510 } 511 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sliio), 0, 512 sc->memmap[ASPEED_DEV_SLIIO]); 513 514 create_unimplemented_device("ast2700.dpmcu", 0x11000000, 0x40000); 515 create_unimplemented_device("ast2700.iomem0", 0x12000000, 0x01000000); 516 create_unimplemented_device("ast2700.iomem1", 0x14000000, 0x01000000); 517 create_unimplemented_device("ast2700.ltpi", 0x30000000, 0x1000000); 518 create_unimplemented_device("ast2700.io", 0x0, 0x4000000); 519 } 520 521 static void aspeed_soc_ast2700_class_init(ObjectClass *oc, void *data) 522 { 523 static const char * const valid_cpu_types[] = { 524 ARM_CPU_TYPE_NAME("cortex-a35"), 525 NULL 526 }; 527 DeviceClass *dc = DEVICE_CLASS(oc); 528 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); 529 530 /* Reason: The Aspeed SoC can only be instantiated from a board */ 531 dc->user_creatable = false; 532 dc->realize = aspeed_soc_ast2700_realize; 533 534 sc->name = "ast2700-a0"; 535 sc->valid_cpu_types = valid_cpu_types; 536 sc->silicon_rev = AST2700_A0_SILICON_REV; 537 sc->sram_size = 0x20000; 538 sc->spis_num = 3; 539 sc->wdts_num = 8; 540 sc->macs_num = 1; 541 sc->uarts_num = 13; 542 sc->num_cpus = 4; 543 sc->uarts_base = ASPEED_DEV_UART0; 544 sc->irqmap = aspeed_soc_ast2700_irqmap; 545 sc->memmap = aspeed_soc_ast2700_memmap; 546 sc->get_irq = aspeed_soc_ast2700_get_irq; 547 } 548 549 static const TypeInfo aspeed_soc_ast27x0_types[] = { 550 { 551 .name = TYPE_ASPEED27X0_SOC, 552 .parent = TYPE_ASPEED_SOC, 553 .instance_size = sizeof(Aspeed27x0SoCState), 554 .abstract = true, 555 }, { 556 .name = "ast2700-a0", 557 .parent = TYPE_ASPEED27X0_SOC, 558 .instance_init = aspeed_soc_ast2700_init, 559 .class_init = aspeed_soc_ast2700_class_init, 560 }, 561 }; 562 563 DEFINE_TYPES(aspeed_soc_ast27x0_types) 564