1[ 2 { 3 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 1024 cycles.", 4 "Counter": "2,3,4,5,6,7,8,9", 5 "Data_LA": "1", 6 "EventCode": "0xcd", 7 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_1024", 8 "MSRIndex": "0x3F6", 9 "MSRValue": "0x400", 10 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 1024 cycles. Reported latency may be longer than just the memory latency. Available PDIST counters: 0", 11 "SampleAfterValue": "53", 12 "UMask": "0x1", 13 "Unit": "cpu_core" 14 }, 15 { 16 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.", 17 "Counter": "2,3,4,5,6,7,8,9", 18 "Data_LA": "1", 19 "EventCode": "0xcd", 20 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", 21 "MSRIndex": "0x3F6", 22 "MSRValue": "0x80", 23 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency. Available PDIST counters: 0", 24 "SampleAfterValue": "1009", 25 "UMask": "0x1", 26 "Unit": "cpu_core" 27 }, 28 { 29 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.", 30 "Counter": "2,3,4,5,6,7,8,9", 31 "Data_LA": "1", 32 "EventCode": "0xcd", 33 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", 34 "MSRIndex": "0x3F6", 35 "MSRValue": "0x10", 36 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency. Available PDIST counters: 0", 37 "SampleAfterValue": "20011", 38 "UMask": "0x1", 39 "Unit": "cpu_core" 40 }, 41 { 42 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 2048 cycles.", 43 "Counter": "2,3,4,5,6,7,8,9", 44 "Data_LA": "1", 45 "EventCode": "0xcd", 46 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_2048", 47 "MSRIndex": "0x3F6", 48 "MSRValue": "0x800", 49 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 2048 cycles. Reported latency may be longer than just the memory latency. Available PDIST counters: 0", 50 "SampleAfterValue": "23", 51 "UMask": "0x1", 52 "Unit": "cpu_core" 53 }, 54 { 55 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.", 56 "Counter": "2,3,4,5,6,7,8,9", 57 "Data_LA": "1", 58 "EventCode": "0xcd", 59 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", 60 "MSRIndex": "0x3F6", 61 "MSRValue": "0x100", 62 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency. Available PDIST counters: 0", 63 "SampleAfterValue": "503", 64 "UMask": "0x1", 65 "Unit": "cpu_core" 66 }, 67 { 68 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.", 69 "Counter": "2,3,4,5,6,7,8,9", 70 "Data_LA": "1", 71 "EventCode": "0xcd", 72 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", 73 "MSRIndex": "0x3F6", 74 "MSRValue": "0x20", 75 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency. Available PDIST counters: 0", 76 "SampleAfterValue": "100007", 77 "UMask": "0x1", 78 "Unit": "cpu_core" 79 }, 80 { 81 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.", 82 "Counter": "2,3,4,5,6,7,8,9", 83 "Data_LA": "1", 84 "EventCode": "0xcd", 85 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", 86 "MSRIndex": "0x3F6", 87 "MSRValue": "0x4", 88 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency. Available PDIST counters: 0", 89 "SampleAfterValue": "100003", 90 "UMask": "0x1", 91 "Unit": "cpu_core" 92 }, 93 { 94 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.", 95 "Counter": "2,3,4,5,6,7,8,9", 96 "Data_LA": "1", 97 "EventCode": "0xcd", 98 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", 99 "MSRIndex": "0x3F6", 100 "MSRValue": "0x200", 101 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency. Available PDIST counters: 0", 102 "SampleAfterValue": "101", 103 "UMask": "0x1", 104 "Unit": "cpu_core" 105 }, 106 { 107 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.", 108 "Counter": "2,3,4,5,6,7,8,9", 109 "Data_LA": "1", 110 "EventCode": "0xcd", 111 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", 112 "MSRIndex": "0x3F6", 113 "MSRValue": "0x40", 114 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency. Available PDIST counters: 0", 115 "SampleAfterValue": "2003", 116 "UMask": "0x1", 117 "Unit": "cpu_core" 118 }, 119 { 120 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.", 121 "Counter": "2,3,4,5,6,7,8,9", 122 "Data_LA": "1", 123 "EventCode": "0xcd", 124 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", 125 "MSRIndex": "0x3F6", 126 "MSRValue": "0x8", 127 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency. Available PDIST counters: 0", 128 "SampleAfterValue": "50021", 129 "UMask": "0x1", 130 "Unit": "cpu_core" 131 }, 132 { 133 "BriefDescription": "Retired memory store access operations. A PDist event for PEBS Store Latency Facility.", 134 "Counter": "0,1", 135 "Data_LA": "1", 136 "EventCode": "0xcd", 137 "EventName": "MEM_TRANS_RETIRED.STORE_SAMPLE", 138 "PublicDescription": "Counts Retired memory accesses with at least 1 store operation. This PEBS event is the precisely-distributed (PDist) trigger covering all stores uops for sampling by the PEBS Store Latency Facility. The facility is described in Intel SDM Volume 3 section 19.9.8 Available PDIST counters: 0", 139 "SampleAfterValue": "1000003", 140 "UMask": "0x2", 141 "Unit": "cpu_core" 142 }, 143 { 144 "BriefDescription": "Counts demand data reads that were supplied by DRAM.", 145 "Counter": "0,1,2,3,4,5,6,7", 146 "EventCode": "0xB7", 147 "EventName": "OCR.DEMAND_DATA_RD.DRAM", 148 "MSRIndex": "0x1a6,0x1a7", 149 "MSRValue": "0x7BC000001", 150 "PublicDescription": "Counts demand data reads that were supplied by DRAM. Available PDIST counters: 0", 151 "SampleAfterValue": "100003", 152 "UMask": "0x1", 153 "Unit": "cpu_atom" 154 }, 155 { 156 "BriefDescription": "Counts demand data reads that were supplied by DRAM.", 157 "Counter": "0,1,2,3", 158 "EventCode": "0x2A,0x2B", 159 "EventName": "OCR.DEMAND_DATA_RD.DRAM", 160 "MSRIndex": "0x1a6,0x1a7", 161 "MSRValue": "0x1E780000001", 162 "PublicDescription": "Counts demand data reads that were supplied by DRAM. Available PDIST counters: 0", 163 "SampleAfterValue": "100003", 164 "UMask": "0x1", 165 "Unit": "cpu_core" 166 }, 167 { 168 "BriefDescription": "Counts demand data reads that were not supplied by the L3 cache.", 169 "Counter": "0,1,2,3,4,5,6,7", 170 "EventCode": "0xB7", 171 "EventName": "OCR.DEMAND_DATA_RD.L3_MISS", 172 "MSRIndex": "0x1a6,0x1a7", 173 "MSRValue": "0x13FBFC00001", 174 "PublicDescription": "Counts demand data reads that were not supplied by the L3 cache. Available PDIST counters: 0", 175 "SampleAfterValue": "100003", 176 "UMask": "0x1", 177 "Unit": "cpu_atom" 178 }, 179 { 180 "BriefDescription": "Counts demand data reads that were not supplied by the L3 cache.", 181 "Counter": "0,1,2,3", 182 "EventCode": "0x2A,0x2B", 183 "EventName": "OCR.DEMAND_DATA_RD.L3_MISS", 184 "MSRIndex": "0x1a6,0x1a7", 185 "MSRValue": "0x9E7FA000001", 186 "PublicDescription": "Counts demand data reads that were not supplied by the L3 cache. Available PDIST counters: 0", 187 "SampleAfterValue": "100003", 188 "UMask": "0x1", 189 "Unit": "cpu_core" 190 }, 191 { 192 "BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.", 193 "Counter": "0,1,2,3,4,5,6,7", 194 "EventCode": "0xB7", 195 "EventName": "OCR.DEMAND_RFO.L3_MISS", 196 "MSRIndex": "0x1a6,0x1a7", 197 "MSRValue": "0x13FBFC00002", 198 "PublicDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache. Available PDIST counters: 0", 199 "SampleAfterValue": "100003", 200 "UMask": "0x1", 201 "Unit": "cpu_atom" 202 }, 203 { 204 "BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.", 205 "Counter": "0,1,2,3", 206 "EventCode": "0x2A,0x2B", 207 "EventName": "OCR.DEMAND_RFO.L3_MISS", 208 "MSRIndex": "0x1a6,0x1a7", 209 "MSRValue": "0x9E7FA000002", 210 "PublicDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache. Available PDIST counters: 0", 211 "SampleAfterValue": "100003", 212 "UMask": "0x1", 213 "Unit": "cpu_core" 214 } 215] 216