1[ 2 { 3 "BriefDescription": "Counts the number of cycles when any of the floating point dividers are active.", 4 "Counter": "0,1,2,3,4,5,6,7", 5 "CounterMask": "1", 6 "EventCode": "0xcd", 7 "EventName": "ARITH.FPDIV_ACTIVE", 8 "SampleAfterValue": "1000003", 9 "UMask": "0x2", 10 "Unit": "cpu_atom" 11 }, 12 { 13 "BriefDescription": "Cycles when floating-point divide unit is busy executing divide or square root operations.", 14 "Counter": "0,1,2,3,4,5,6,7,8,9", 15 "CounterMask": "1", 16 "EventCode": "0xb0", 17 "EventName": "ARITH.FPDIV_ACTIVE", 18 "PublicDescription": "Counts cycles when divide unit is busy executing divide or square root operations. Accounts for floating-point operations only.", 19 "SampleAfterValue": "1000003", 20 "UMask": "0x1", 21 "Unit": "cpu_core" 22 }, 23 { 24 "BriefDescription": "Counts the number of active floating point dividers per cycle in the loop stage.", 25 "Counter": "0,1,2,3,4,5,6,7", 26 "EventCode": "0xcd", 27 "EventName": "ARITH.FPDIV_OCCUPANCY", 28 "SampleAfterValue": "1000003", 29 "UMask": "0x2", 30 "Unit": "cpu_atom" 31 }, 32 { 33 "BriefDescription": "Counts the number of floating point divider uops executed per cycle.", 34 "Counter": "0,1,2,3,4,5,6,7", 35 "EventCode": "0xcd", 36 "EventName": "ARITH.FPDIV_UOPS", 37 "SampleAfterValue": "1000003", 38 "UMask": "0x8", 39 "Unit": "cpu_atom" 40 }, 41 { 42 "BriefDescription": "Counts all microcode FP assists.", 43 "Counter": "0,1,2,3,4,5,6,7,8,9", 44 "EventCode": "0xc1", 45 "EventName": "ASSISTS.FP", 46 "PublicDescription": "Counts all microcode Floating Point assists.", 47 "SampleAfterValue": "100003", 48 "UMask": "0x2", 49 "Unit": "cpu_core" 50 }, 51 { 52 "BriefDescription": "ASSISTS.SSE_AVX_MIX", 53 "Counter": "0,1,2,3,4,5,6,7,8,9", 54 "EventCode": "0xc1", 55 "EventName": "ASSISTS.SSE_AVX_MIX", 56 "SampleAfterValue": "1000003", 57 "UMask": "0x10", 58 "Unit": "cpu_core" 59 }, 60 { 61 "BriefDescription": "Number of FP-arith-uops dispatched on 1st VEC port (port 0). FP-arith-uops are of type ADD* / SUB* / MUL / FMA* / DPP.", 62 "Counter": "0,1,2,3,4,5,6,7,8,9", 63 "EventCode": "0xb3", 64 "EventName": "FP_ARITH_DISPATCHED.V0", 65 "SampleAfterValue": "2000003", 66 "UMask": "0x1", 67 "Unit": "cpu_core" 68 }, 69 { 70 "BriefDescription": "Number of FP-arith-uops dispatched on 2nd VEC port (port 1)", 71 "Counter": "0,1,2,3,4,5,6,7,8,9", 72 "EventCode": "0xb3", 73 "EventName": "FP_ARITH_DISPATCHED.V1", 74 "SampleAfterValue": "2000003", 75 "UMask": "0x2", 76 "Unit": "cpu_core" 77 }, 78 { 79 "BriefDescription": "Number of FP-arith-uops dispatched on 3rd VEC port (port 5)", 80 "Counter": "0,1,2,3,4,5,6,7,8,9", 81 "EventCode": "0xb3", 82 "EventName": "FP_ARITH_DISPATCHED.V2", 83 "SampleAfterValue": "2000003", 84 "UMask": "0x4", 85 "Unit": "cpu_core" 86 }, 87 { 88 "BriefDescription": "Number of FP-arith-uops dispatched on 4th VEC port", 89 "Counter": "0,1,2,3,4,5,6,7,8,9", 90 "EventCode": "0xb3", 91 "EventName": "FP_ARITH_DISPATCHED.V3", 92 "SampleAfterValue": "2000003", 93 "UMask": "0x8", 94 "Unit": "cpu_core" 95 }, 96 { 97 "BriefDescription": "This event is deprecated. Refer to new event FP_ARITH_OPS_RETIRED.128B_PACKED_DOUBLE", 98 "Counter": "0,1,2,3,4,5,6,7,8,9", 99 "Deprecated": "1", 100 "EventCode": "0xc7", 101 "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", 102 "SampleAfterValue": "100003", 103 "UMask": "0x4", 104 "Unit": "cpu_core" 105 }, 106 { 107 "BriefDescription": "This event is deprecated. Refer to new event FP_ARITH_OPS_RETIRED.128B_PACKED_SINGLE", 108 "Counter": "0,1,2,3,4,5,6,7,8,9", 109 "Deprecated": "1", 110 "EventCode": "0xc7", 111 "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", 112 "SampleAfterValue": "100003", 113 "UMask": "0x8", 114 "Unit": "cpu_core" 115 }, 116 { 117 "BriefDescription": "This event is deprecated. Refer to new event FP_ARITH_OPS_RETIRED.256B_PACKED_DOUBLE", 118 "Counter": "0,1,2,3,4,5,6,7,8,9", 119 "Deprecated": "1", 120 "EventCode": "0xc7", 121 "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", 122 "SampleAfterValue": "100003", 123 "UMask": "0x10", 124 "Unit": "cpu_core" 125 }, 126 { 127 "BriefDescription": "This event is deprecated. Refer to new event FP_ARITH_OPS_RETIRED.256B_PACKED_SINGLE", 128 "Counter": "0,1,2,3,4,5,6,7,8,9", 129 "Deprecated": "1", 130 "EventCode": "0xc7", 131 "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", 132 "SampleAfterValue": "100003", 133 "UMask": "0x20", 134 "Unit": "cpu_core" 135 }, 136 { 137 "BriefDescription": "This event is deprecated. Refer to new event FP_ARITH_OPS_RETIRED.4_FLOPS", 138 "Counter": "0,1,2,3,4,5,6,7,8,9", 139 "Deprecated": "1", 140 "EventCode": "0xc7", 141 "EventName": "FP_ARITH_INST_RETIRED.4_FLOPS", 142 "SampleAfterValue": "100003", 143 "UMask": "0x18", 144 "Unit": "cpu_core" 145 }, 146 { 147 "BriefDescription": "This event is deprecated. Refer to new event FP_ARITH_OPS_RETIRED.SCALAR", 148 "Counter": "0,1,2,3,4,5,6,7,8,9", 149 "Deprecated": "1", 150 "EventCode": "0xc7", 151 "EventName": "FP_ARITH_INST_RETIRED.SCALAR", 152 "SampleAfterValue": "1000003", 153 "UMask": "0x3", 154 "Unit": "cpu_core" 155 }, 156 { 157 "BriefDescription": "This event is deprecated. Refer to new event FP_ARITH_OPS_RETIRED.SCALAR_DOUBLE", 158 "Counter": "0,1,2,3,4,5,6,7,8,9", 159 "Deprecated": "1", 160 "EventCode": "0xc7", 161 "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", 162 "SampleAfterValue": "100003", 163 "UMask": "0x1", 164 "Unit": "cpu_core" 165 }, 166 { 167 "BriefDescription": "This event is deprecated. Refer to new event FP_ARITH_OPS_RETIRED.SCALAR_SINGLE", 168 "Counter": "0,1,2,3,4,5,6,7,8,9", 169 "Deprecated": "1", 170 "EventCode": "0xc7", 171 "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", 172 "SampleAfterValue": "100003", 173 "UMask": "0x2", 174 "Unit": "cpu_core" 175 }, 176 { 177 "BriefDescription": "This event is deprecated. Refer to new event FP_ARITH_OPS_RETIRED.VECTOR", 178 "Counter": "0,1,2,3,4,5,6,7,8,9", 179 "Deprecated": "1", 180 "EventCode": "0xc7", 181 "EventName": "FP_ARITH_INST_RETIRED.VECTOR", 182 "SampleAfterValue": "1000003", 183 "UMask": "0x3c", 184 "Unit": "cpu_core" 185 }, 186 { 187 "BriefDescription": "FP_ARITH_INST_RETIRED.VECTOR_128B [This event is alias to FP_ARITH_OPS_RETIRED.VECTOR_128B]", 188 "Counter": "0,1,2,3,4,5,6,7,8,9", 189 "EventCode": "0xc7", 190 "EventName": "FP_ARITH_INST_RETIRED.VECTOR_128B", 191 "SampleAfterValue": "100003", 192 "UMask": "0xc", 193 "Unit": "cpu_core" 194 }, 195 { 196 "BriefDescription": "FP_ARITH_INST_RETIRED.VECTOR_256B [This event is alias to FP_ARITH_OPS_RETIRED.VECTOR_256B]", 197 "Counter": "0,1,2,3,4,5,6,7,8,9", 198 "EventCode": "0xc7", 199 "EventName": "FP_ARITH_INST_RETIRED.VECTOR_256B", 200 "SampleAfterValue": "100003", 201 "UMask": "0x30", 202 "Unit": "cpu_core" 203 }, 204 { 205 "BriefDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 206 "Counter": "0,1,2,3,4,5,6,7,8,9", 207 "EventCode": "0xc7", 208 "EventName": "FP_ARITH_OPS_RETIRED.128B_PACKED_DOUBLE", 209 "PublicDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 210 "SampleAfterValue": "100003", 211 "UMask": "0x4", 212 "Unit": "cpu_core" 213 }, 214 { 215 "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 216 "Counter": "0,1,2,3,4,5,6,7,8,9", 217 "EventCode": "0xc7", 218 "EventName": "FP_ARITH_OPS_RETIRED.128B_PACKED_SINGLE", 219 "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 220 "SampleAfterValue": "100003", 221 "UMask": "0x8", 222 "Unit": "cpu_core" 223 }, 224 { 225 "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 226 "Counter": "0,1,2,3,4,5,6,7,8,9", 227 "EventCode": "0xc7", 228 "EventName": "FP_ARITH_OPS_RETIRED.256B_PACKED_DOUBLE", 229 "PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 230 "SampleAfterValue": "100003", 231 "UMask": "0x10", 232 "Unit": "cpu_core" 233 }, 234 { 235 "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 236 "Counter": "0,1,2,3,4,5,6,7,8,9", 237 "EventCode": "0xc7", 238 "EventName": "FP_ARITH_OPS_RETIRED.256B_PACKED_SINGLE", 239 "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 240 "SampleAfterValue": "100003", 241 "UMask": "0x20", 242 "Unit": "cpu_core" 243 }, 244 { 245 "BriefDescription": "Number of SSE/AVX computational 128-bit packed single and 256-bit packed double precision FP instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, 1 for each element. Applies to SSE* and AVX* packed single precision and packed double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element.", 246 "Counter": "0,1,2,3,4,5,6,7,8,9", 247 "EventCode": "0xc7", 248 "EventName": "FP_ARITH_OPS_RETIRED.4_FLOPS", 249 "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision and 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 250 "SampleAfterValue": "100003", 251 "UMask": "0x18", 252 "Unit": "cpu_core" 253 }, 254 { 255 "BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 RANGE SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", 256 "Counter": "0,1,2,3,4,5,6,7,8,9", 257 "EventCode": "0xc7", 258 "EventName": "FP_ARITH_OPS_RETIRED.SCALAR", 259 "PublicDescription": "Number of SSE/AVX computational scalar single precision and double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 260 "SampleAfterValue": "1000003", 261 "UMask": "0x3", 262 "Unit": "cpu_core" 263 }, 264 { 265 "BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 266 "Counter": "0,1,2,3,4,5,6,7,8,9", 267 "EventCode": "0xc7", 268 "EventName": "FP_ARITH_OPS_RETIRED.SCALAR_DOUBLE", 269 "PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 270 "SampleAfterValue": "100003", 271 "UMask": "0x1", 272 "Unit": "cpu_core" 273 }, 274 { 275 "BriefDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 276 "Counter": "0,1,2,3,4,5,6,7,8,9", 277 "EventCode": "0xc7", 278 "EventName": "FP_ARITH_OPS_RETIRED.SCALAR_SINGLE", 279 "PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 280 "SampleAfterValue": "100003", 281 "UMask": "0x2", 282 "Unit": "cpu_core" 283 }, 284 { 285 "BriefDescription": "Number of any Vector retired FP arithmetic instructions", 286 "Counter": "0,1,2,3,4,5,6,7,8,9", 287 "EventCode": "0xc7", 288 "EventName": "FP_ARITH_OPS_RETIRED.VECTOR", 289 "PublicDescription": "Number of any Vector retired FP arithmetic instructions. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 290 "SampleAfterValue": "1000003", 291 "UMask": "0x3c", 292 "Unit": "cpu_core" 293 }, 294 { 295 "BriefDescription": "FP_ARITH_OPS_RETIRED.VECTOR_128B [This event is alias to FP_ARITH_INST_RETIRED.VECTOR_128B]", 296 "Counter": "0,1,2,3,4,5,6,7,8,9", 297 "EventCode": "0xc7", 298 "EventName": "FP_ARITH_OPS_RETIRED.VECTOR_128B", 299 "SampleAfterValue": "100003", 300 "UMask": "0xc", 301 "Unit": "cpu_core" 302 }, 303 { 304 "BriefDescription": "FP_ARITH_OPS_RETIRED.VECTOR_256B [This event is alias to FP_ARITH_INST_RETIRED.VECTOR_256B]", 305 "Counter": "0,1,2,3,4,5,6,7,8,9", 306 "EventCode": "0xc7", 307 "EventName": "FP_ARITH_OPS_RETIRED.VECTOR_256B", 308 "SampleAfterValue": "100003", 309 "UMask": "0x30", 310 "Unit": "cpu_core" 311 }, 312 { 313 "BriefDescription": "Counts the number of all types of floating point operations per uop with all default weighting", 314 "Counter": "0,1,2,3,4,5,6,7", 315 "EventCode": "0xc8", 316 "EventName": "FP_FLOPS_RETIRED.ALL", 317 "SampleAfterValue": "1000003", 318 "UMask": "0x3", 319 "Unit": "cpu_atom" 320 }, 321 { 322 "BriefDescription": "Counts the number of floating point operations that produce 32 bit single precision results", 323 "Counter": "0,1,2,3,4,5,6,7", 324 "EventCode": "0xc8", 325 "EventName": "FP_FLOPS_RETIRED.FP32", 326 "SampleAfterValue": "1000003", 327 "UMask": "0x2", 328 "Unit": "cpu_atom" 329 }, 330 { 331 "BriefDescription": "Counts the number of floating point operations that produce 64 bit double precision results", 332 "Counter": "0,1,2,3,4,5,6,7", 333 "EventCode": "0xc8", 334 "EventName": "FP_FLOPS_RETIRED.FP64", 335 "SampleAfterValue": "1000003", 336 "UMask": "0x1", 337 "Unit": "cpu_atom" 338 }, 339 { 340 "BriefDescription": "Counts the number of retired instructions whose sources are a packed 128 bit double precision floating point. This may be SSE or AVX.128 operations.", 341 "Counter": "0,1,2,3,4,5,6,7", 342 "EventCode": "0xc7", 343 "EventName": "FP_INST_RETIRED.128B_DP", 344 "SampleAfterValue": "1000003", 345 "UMask": "0x8", 346 "Unit": "cpu_atom" 347 }, 348 { 349 "BriefDescription": "Counts the number of retired instructions whose sources are a packed 128 bit single precision floating point. This may be SSE or AVX.128 operations.", 350 "Counter": "0,1,2,3,4,5,6,7", 351 "EventCode": "0xc7", 352 "EventName": "FP_INST_RETIRED.128B_SP", 353 "SampleAfterValue": "1000003", 354 "UMask": "0x4", 355 "Unit": "cpu_atom" 356 }, 357 { 358 "BriefDescription": "Counts the number of retired instructions whose sources are a packed 256 bit double precision floating point.", 359 "Counter": "0,1,2,3,4,5,6,7", 360 "EventCode": "0xc7", 361 "EventName": "FP_INST_RETIRED.256B_DP", 362 "SampleAfterValue": "1000003", 363 "UMask": "0x20", 364 "Unit": "cpu_atom" 365 }, 366 { 367 "BriefDescription": "Counts the number of retired instructions whose sources are a packed 256 bit single precision floating point.", 368 "Counter": "0,1,2,3,4,5,6,7", 369 "EventCode": "0xc7", 370 "EventName": "FP_INST_RETIRED.256B_SP", 371 "SampleAfterValue": "1000003", 372 "UMask": "0x10", 373 "Unit": "cpu_atom" 374 }, 375 { 376 "BriefDescription": "Counts the number of retired instructions whose sources are a scalar 32bit single precision floating point", 377 "Counter": "0,1,2,3,4,5,6,7", 378 "EventCode": "0xc7", 379 "EventName": "FP_INST_RETIRED.32B_SP", 380 "SampleAfterValue": "1000003", 381 "UMask": "0x1", 382 "Unit": "cpu_atom" 383 }, 384 { 385 "BriefDescription": "Counts the number of retired instructions whose sources are a scalar 64 bit double precision floating point", 386 "Counter": "0,1,2,3,4,5,6,7", 387 "EventCode": "0xc7", 388 "EventName": "FP_INST_RETIRED.64B_DP", 389 "SampleAfterValue": "1000003", 390 "UMask": "0x2", 391 "Unit": "cpu_atom" 392 }, 393 { 394 "BriefDescription": "Counts the total number of floating point retired instructions.", 395 "Counter": "0,1,2,3,4,5,6,7", 396 "EventCode": "0xc7", 397 "EventName": "FP_INST_RETIRED.ALL", 398 "SampleAfterValue": "1000003", 399 "UMask": "0x3f", 400 "Unit": "cpu_atom" 401 }, 402 { 403 "BriefDescription": "Counts the number of uops executed on all floating point ports.", 404 "Counter": "0,1,2,3,4,5,6,7", 405 "EventCode": "0xb2", 406 "EventName": "FP_VINT_UOPS_EXECUTED.ALL", 407 "SampleAfterValue": "1000003", 408 "UMask": "0x1f", 409 "Unit": "cpu_atom" 410 }, 411 { 412 "BriefDescription": "Counts the number of uops executed on floating point and vector integer port 0.", 413 "Counter": "0,1,2,3,4,5,6,7", 414 "EventCode": "0xb2", 415 "EventName": "FP_VINT_UOPS_EXECUTED.P0", 416 "SampleAfterValue": "1000003", 417 "UMask": "0x2", 418 "Unit": "cpu_atom" 419 }, 420 { 421 "BriefDescription": "Counts the number of uops executed on floating point and vector integer port 1.", 422 "Counter": "0,1,2,3,4,5,6,7", 423 "EventCode": "0xb2", 424 "EventName": "FP_VINT_UOPS_EXECUTED.P1", 425 "SampleAfterValue": "1000003", 426 "UMask": "0x4", 427 "Unit": "cpu_atom" 428 }, 429 { 430 "BriefDescription": "Counts the number of uops executed on floating point and vector integer port 2.", 431 "Counter": "0,1,2,3,4,5,6,7", 432 "EventCode": "0xb2", 433 "EventName": "FP_VINT_UOPS_EXECUTED.P2", 434 "SampleAfterValue": "1000003", 435 "UMask": "0x8", 436 "Unit": "cpu_atom" 437 }, 438 { 439 "BriefDescription": "Counts the number of uops executed on floating point and vector integer port 3.", 440 "Counter": "0,1,2,3,4,5,6,7", 441 "EventCode": "0xb2", 442 "EventName": "FP_VINT_UOPS_EXECUTED.P3", 443 "SampleAfterValue": "1000003", 444 "UMask": "0x10", 445 "Unit": "cpu_atom" 446 }, 447 { 448 "BriefDescription": "Counts the number of uops executed on floating point and vector integer port 0, 1, 2, 3.", 449 "Counter": "0,1,2,3,4,5,6,7", 450 "EventCode": "0xb2", 451 "EventName": "FP_VINT_UOPS_EXECUTED.PRIMARY", 452 "SampleAfterValue": "1000003", 453 "UMask": "0x1e", 454 "Unit": "cpu_atom" 455 }, 456 { 457 "BriefDescription": "Counts the number of uops executed on floating point and vector integer store data port.", 458 "Counter": "0,1,2,3,4,5,6,7", 459 "EventCode": "0xb2", 460 "EventName": "FP_VINT_UOPS_EXECUTED.STD", 461 "SampleAfterValue": "1000003", 462 "UMask": "0x1", 463 "Unit": "cpu_atom" 464 }, 465 { 466 "BriefDescription": "Counts the number of floating point operations retired that required microcode assist.", 467 "Counter": "0,1,2,3,4,5,6,7", 468 "EventCode": "0xc3", 469 "EventName": "MACHINE_CLEARS.FP_ASSIST", 470 "PublicDescription": "Counts the number of floating point operations retired that required microcode assist, which is not a reflection of the number of FP operations, instructions or uops.", 471 "SampleAfterValue": "20003", 472 "UMask": "0x4", 473 "Unit": "cpu_atom" 474 }, 475 { 476 "BriefDescription": "Counts the number of floating point divide uops retired (x87 and sse, including x87 sqrt)", 477 "Counter": "0,1,2,3,4,5,6,7", 478 "EventCode": "0xc2", 479 "EventName": "UOPS_RETIRED.FPDIV", 480 "SampleAfterValue": "2000003", 481 "UMask": "0x8", 482 "Unit": "cpu_atom" 483 } 484] 485