1 /* 2 * ALSA SoC Synopsys I2S Audio Layer 3 * 4 * sound/soc/dwc/designware_i2s.c 5 * 6 * Copyright (C) 2010 ST Microelectronics 7 * Rajeev Kumar <rajeevkumar.linux@gmail.com> 8 * 9 * This file is licensed under the terms of the GNU General Public 10 * License version 2. This program is licensed "as is" without any 11 * warranty of any kind, whether express or implied. 12 */ 13 14 #include <linux/clk.h> 15 #include <linux/device.h> 16 #include <linux/init.h> 17 #include <linux/io.h> 18 #include <linux/interrupt.h> 19 #include <linux/mfd/syscon.h> 20 #include <linux/module.h> 21 #include <linux/reset.h> 22 #include <linux/slab.h> 23 #include <linux/pm_runtime.h> 24 #include <sound/designware_i2s.h> 25 #include <sound/pcm.h> 26 #include <sound/pcm_params.h> 27 #include <sound/soc.h> 28 #include <sound/dmaengine_pcm.h> 29 #include "local.h" 30 31 static inline void i2s_write_reg(void __iomem *io_base, int reg, u32 val) 32 { 33 writel(val, io_base + reg); 34 } 35 36 static inline u32 i2s_read_reg(void __iomem *io_base, int reg) 37 { 38 return readl(io_base + reg); 39 } 40 41 static inline void i2s_disable_channels(struct dw_i2s_dev *dev, u32 stream) 42 { 43 u32 i = 0; 44 45 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 46 for (i = 0; i < 4; i++) 47 i2s_write_reg(dev->i2s_base, TER(i), 0); 48 } else { 49 for (i = 0; i < 4; i++) 50 i2s_write_reg(dev->i2s_base, RER(i), 0); 51 } 52 } 53 54 static inline void i2s_clear_irqs(struct dw_i2s_dev *dev, u32 stream) 55 { 56 u32 i = 0; 57 58 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 59 for (i = 0; i < 4; i++) 60 i2s_read_reg(dev->i2s_base, TOR(i)); 61 } else { 62 for (i = 0; i < 4; i++) 63 i2s_read_reg(dev->i2s_base, ROR(i)); 64 } 65 } 66 67 static inline void i2s_disable_irqs(struct dw_i2s_dev *dev, u32 stream, 68 int chan_nr) 69 { 70 u32 i, irq; 71 72 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 73 for (i = 0; i < (chan_nr / 2); i++) { 74 irq = i2s_read_reg(dev->i2s_base, IMR(i)); 75 i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x30); 76 } 77 } else { 78 for (i = 0; i < (chan_nr / 2); i++) { 79 irq = i2s_read_reg(dev->i2s_base, IMR(i)); 80 i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x03); 81 } 82 } 83 } 84 85 static inline void i2s_enable_irqs(struct dw_i2s_dev *dev, u32 stream, 86 int chan_nr) 87 { 88 u32 i, irq; 89 90 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 91 for (i = 0; i < (chan_nr / 2); i++) { 92 irq = i2s_read_reg(dev->i2s_base, IMR(i)); 93 i2s_write_reg(dev->i2s_base, IMR(i), irq & ~0x30); 94 } 95 } else { 96 for (i = 0; i < (chan_nr / 2); i++) { 97 irq = i2s_read_reg(dev->i2s_base, IMR(i)); 98 i2s_write_reg(dev->i2s_base, IMR(i), irq & ~0x03); 99 } 100 } 101 } 102 103 static irqreturn_t i2s_irq_handler(int irq, void *dev_id) 104 { 105 struct dw_i2s_dev *dev = dev_id; 106 bool irq_valid = false; 107 u32 isr[4]; 108 int i; 109 110 for (i = 0; i < 4; i++) 111 isr[i] = i2s_read_reg(dev->i2s_base, ISR(i)); 112 113 i2s_clear_irqs(dev, SNDRV_PCM_STREAM_PLAYBACK); 114 i2s_clear_irqs(dev, SNDRV_PCM_STREAM_CAPTURE); 115 116 for (i = 0; i < 4; i++) { 117 /* 118 * Check if TX fifo is empty. If empty fill FIFO with samples 119 * NOTE: Only two channels supported 120 */ 121 if ((isr[i] & ISR_TXFE) && (i == 0) && dev->use_pio) { 122 dw_pcm_push_tx(dev); 123 irq_valid = true; 124 } 125 126 /* 127 * Data available. Retrieve samples from FIFO 128 * NOTE: Only two channels supported 129 */ 130 if ((isr[i] & ISR_RXDA) && (i == 0) && dev->use_pio) { 131 dw_pcm_pop_rx(dev); 132 irq_valid = true; 133 } 134 135 /* Error Handling: TX */ 136 if (isr[i] & ISR_TXFO) { 137 dev_err_ratelimited(dev->dev, "TX overrun (ch_id=%d)\n", i); 138 irq_valid = true; 139 } 140 141 /* Error Handling: TX */ 142 if (isr[i] & ISR_RXFO) { 143 dev_err_ratelimited(dev->dev, "RX overrun (ch_id=%d)\n", i); 144 irq_valid = true; 145 } 146 } 147 148 if (irq_valid) 149 return IRQ_HANDLED; 150 else 151 return IRQ_NONE; 152 } 153 154 static void i2s_enable_dma(struct dw_i2s_dev *dev, u32 stream) 155 { 156 u32 dma_reg = i2s_read_reg(dev->i2s_base, I2S_DMACR); 157 158 /* Enable DMA handshake for stream */ 159 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 160 dma_reg |= I2S_DMAEN_TXBLOCK; 161 else 162 dma_reg |= I2S_DMAEN_RXBLOCK; 163 164 i2s_write_reg(dev->i2s_base, I2S_DMACR, dma_reg); 165 } 166 167 static void i2s_disable_dma(struct dw_i2s_dev *dev, u32 stream) 168 { 169 u32 dma_reg = i2s_read_reg(dev->i2s_base, I2S_DMACR); 170 171 /* Disable DMA handshake for stream */ 172 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 173 dma_reg &= ~I2S_DMAEN_TXBLOCK; 174 i2s_write_reg(dev->i2s_base, I2S_RTXDMA, 1); 175 } else { 176 dma_reg &= ~I2S_DMAEN_RXBLOCK; 177 i2s_write_reg(dev->i2s_base, I2S_RRXDMA, 1); 178 } 179 i2s_write_reg(dev->i2s_base, I2S_DMACR, dma_reg); 180 } 181 182 static void i2s_start(struct dw_i2s_dev *dev, 183 struct snd_pcm_substream *substream) 184 { 185 struct i2s_clk_config_data *config = &dev->config; 186 187 u32 reg = IER_IEN; 188 189 if (dev->tdm_slots) { 190 reg |= (dev->tdm_slots - 1) << IER_TDM_SLOTS_SHIFT; 191 reg |= IER_INTF_TYPE; 192 reg |= dev->frame_offset << IER_FRAME_OFF_SHIFT; 193 } 194 195 i2s_write_reg(dev->i2s_base, IER, reg); 196 197 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 198 i2s_write_reg(dev->i2s_base, ITER, 1); 199 else 200 i2s_write_reg(dev->i2s_base, IRER, 1); 201 202 if (!(dev->use_pio || dev->is_jh7110)) 203 i2s_enable_dma(dev, substream->stream); 204 205 i2s_enable_irqs(dev, substream->stream, config->chan_nr); 206 i2s_write_reg(dev->i2s_base, CER, 1); 207 } 208 209 static void i2s_stop(struct dw_i2s_dev *dev, 210 struct snd_pcm_substream *substream) 211 { 212 213 i2s_clear_irqs(dev, substream->stream); 214 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 215 i2s_write_reg(dev->i2s_base, ITER, 0); 216 else 217 i2s_write_reg(dev->i2s_base, IRER, 0); 218 219 if (!(dev->use_pio || dev->is_jh7110)) 220 i2s_disable_dma(dev, substream->stream); 221 222 i2s_disable_irqs(dev, substream->stream, 8); 223 224 225 if (!dev->active) { 226 i2s_write_reg(dev->i2s_base, CER, 0); 227 i2s_write_reg(dev->i2s_base, IER, 0); 228 } 229 } 230 231 static int dw_i2s_startup(struct snd_pcm_substream *substream, 232 struct snd_soc_dai *cpu_dai) 233 { 234 struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(cpu_dai); 235 236 if (dev->is_jh7110) { 237 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); 238 struct snd_soc_dai_link *dai_link = rtd->dai_link; 239 240 dai_link->trigger_stop = SND_SOC_TRIGGER_ORDER_LDC; 241 } 242 243 return 0; 244 } 245 246 static void dw_i2s_config(struct dw_i2s_dev *dev, int stream) 247 { 248 u32 ch_reg; 249 struct i2s_clk_config_data *config = &dev->config; 250 251 252 i2s_disable_channels(dev, stream); 253 254 for (ch_reg = 0; ch_reg < (config->chan_nr / 2); ch_reg++) { 255 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 256 i2s_write_reg(dev->i2s_base, TCR(ch_reg), 257 dev->xfer_resolution); 258 i2s_write_reg(dev->i2s_base, TFCR(ch_reg), 259 dev->fifo_th - 1); 260 i2s_write_reg(dev->i2s_base, TER(ch_reg), TER_TXCHEN | 261 dev->tdm_mask << TER_TXSLOT_SHIFT); 262 } else { 263 i2s_write_reg(dev->i2s_base, RCR(ch_reg), 264 dev->xfer_resolution); 265 i2s_write_reg(dev->i2s_base, RFCR(ch_reg), 266 dev->fifo_th - 1); 267 i2s_write_reg(dev->i2s_base, RER(ch_reg), RER_RXCHEN | 268 dev->tdm_mask << RER_RXSLOT_SHIFT); 269 } 270 271 } 272 } 273 274 static int dw_i2s_hw_params(struct snd_pcm_substream *substream, 275 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 276 { 277 struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); 278 struct i2s_clk_config_data *config = &dev->config; 279 int ret; 280 281 switch (params_format(params)) { 282 case SNDRV_PCM_FORMAT_S16_LE: 283 config->data_width = 16; 284 dev->ccr = 0x00; 285 dev->xfer_resolution = 0x02; 286 break; 287 288 case SNDRV_PCM_FORMAT_S24_LE: 289 config->data_width = 24; 290 dev->ccr = 0x08; 291 dev->xfer_resolution = 0x04; 292 break; 293 294 case SNDRV_PCM_FORMAT_S32_LE: 295 config->data_width = 32; 296 dev->ccr = 0x10; 297 dev->xfer_resolution = 0x05; 298 break; 299 300 default: 301 dev_err(dev->dev, "designware-i2s: unsupported PCM fmt"); 302 return -EINVAL; 303 } 304 305 if (dev->tdm_slots) 306 config->data_width = 32; 307 308 config->chan_nr = params_channels(params); 309 310 switch (config->chan_nr) { 311 case EIGHT_CHANNEL_SUPPORT: 312 case SIX_CHANNEL_SUPPORT: 313 case FOUR_CHANNEL_SUPPORT: 314 case TWO_CHANNEL_SUPPORT: 315 break; 316 default: 317 dev_err(dev->dev, "channel not supported\n"); 318 return -EINVAL; 319 } 320 321 dw_i2s_config(dev, substream->stream); 322 323 i2s_write_reg(dev->i2s_base, CCR, dev->ccr); 324 325 config->sample_rate = params_rate(params); 326 327 if (dev->capability & DW_I2S_MASTER) { 328 if (dev->i2s_clk_cfg) { 329 ret = dev->i2s_clk_cfg(config); 330 if (ret < 0) { 331 dev_err(dev->dev, "runtime audio clk config fail\n"); 332 return ret; 333 } 334 } else { 335 u32 bitclk = config->sample_rate * 336 config->data_width * 2; 337 338 ret = clk_set_rate(dev->clk, bitclk); 339 if (ret) { 340 dev_err(dev->dev, "Can't set I2S clock rate: %d\n", 341 ret); 342 return ret; 343 } 344 } 345 } 346 return 0; 347 } 348 349 static int dw_i2s_prepare(struct snd_pcm_substream *substream, 350 struct snd_soc_dai *dai) 351 { 352 struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); 353 354 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 355 i2s_write_reg(dev->i2s_base, TXFFR, 1); 356 else 357 i2s_write_reg(dev->i2s_base, RXFFR, 1); 358 359 return 0; 360 } 361 362 static int dw_i2s_trigger(struct snd_pcm_substream *substream, 363 int cmd, struct snd_soc_dai *dai) 364 { 365 struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); 366 int ret = 0; 367 368 switch (cmd) { 369 case SNDRV_PCM_TRIGGER_START: 370 case SNDRV_PCM_TRIGGER_RESUME: 371 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 372 dev->active++; 373 i2s_start(dev, substream); 374 break; 375 376 case SNDRV_PCM_TRIGGER_STOP: 377 case SNDRV_PCM_TRIGGER_SUSPEND: 378 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 379 dev->active--; 380 i2s_stop(dev, substream); 381 break; 382 default: 383 ret = -EINVAL; 384 break; 385 } 386 return ret; 387 } 388 389 static int dw_i2s_set_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) 390 { 391 struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(cpu_dai); 392 int ret = 0; 393 394 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 395 case SND_SOC_DAIFMT_BC_FC: 396 if (dev->capability & DW_I2S_SLAVE) 397 ret = 0; 398 else 399 ret = -EINVAL; 400 break; 401 case SND_SOC_DAIFMT_BP_FP: 402 if (dev->capability & DW_I2S_MASTER) 403 ret = 0; 404 else 405 ret = -EINVAL; 406 break; 407 case SND_SOC_DAIFMT_BC_FP: 408 case SND_SOC_DAIFMT_BP_FC: 409 ret = -EINVAL; 410 break; 411 default: 412 dev_dbg(dev->dev, "dwc : Invalid clock provider format\n"); 413 ret = -EINVAL; 414 break; 415 } 416 417 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 418 case SND_SOC_DAIFMT_I2S: 419 case SND_SOC_DAIFMT_LEFT_J: 420 case SND_SOC_DAIFMT_RIGHT_J: 421 break; 422 case SND_SOC_DAIFMT_DSP_A: 423 dev->frame_offset = 1; 424 break; 425 case SND_SOC_DAIFMT_DSP_B: 426 dev->frame_offset = 0; 427 break; 428 default: 429 dev_err(dev->dev, "DAI format unsupported"); 430 return -EINVAL; 431 } 432 433 return ret; 434 } 435 436 static int dw_i2s_set_tdm_slot(struct snd_soc_dai *cpu_dai, unsigned int tx_mask, 437 unsigned int rx_mask, int slots, int slot_width) 438 { 439 struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(cpu_dai); 440 441 if (slot_width != 32) 442 return -EINVAL; 443 444 if (slots < 0 || slots > 16) 445 return -EINVAL; 446 447 if (rx_mask != tx_mask) 448 return -EINVAL; 449 450 if (!rx_mask) 451 return -EINVAL; 452 453 dev->tdm_slots = slots; 454 dev->tdm_mask = rx_mask; 455 456 dev->l_reg = RSLOT_TSLOT(ffs(rx_mask) - 1); 457 dev->r_reg = RSLOT_TSLOT(fls(rx_mask) - 1); 458 459 return 0; 460 } 461 462 static int dw_i2s_dai_probe(struct snd_soc_dai *dai) 463 { 464 struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); 465 466 snd_soc_dai_init_dma_data(dai, &dev->play_dma_data, &dev->capture_dma_data); 467 return 0; 468 } 469 470 static const struct snd_soc_dai_ops dw_i2s_dai_ops = { 471 .probe = dw_i2s_dai_probe, 472 .startup = dw_i2s_startup, 473 .hw_params = dw_i2s_hw_params, 474 .prepare = dw_i2s_prepare, 475 .trigger = dw_i2s_trigger, 476 .set_fmt = dw_i2s_set_fmt, 477 .set_tdm_slot = dw_i2s_set_tdm_slot, 478 }; 479 480 static int dw_i2s_runtime_suspend(struct device *dev) 481 { 482 struct dw_i2s_dev *dw_dev = dev_get_drvdata(dev); 483 484 if (dw_dev->capability & DW_I2S_MASTER) 485 clk_disable(dw_dev->clk); 486 return 0; 487 } 488 489 static int dw_i2s_runtime_resume(struct device *dev) 490 { 491 struct dw_i2s_dev *dw_dev = dev_get_drvdata(dev); 492 int ret; 493 494 if (dw_dev->capability & DW_I2S_MASTER) { 495 ret = clk_enable(dw_dev->clk); 496 if (ret) 497 return ret; 498 } 499 return 0; 500 } 501 502 #ifdef CONFIG_PM 503 static int dw_i2s_suspend(struct snd_soc_component *component) 504 { 505 struct dw_i2s_dev *dev = snd_soc_component_get_drvdata(component); 506 507 if (dev->capability & DW_I2S_MASTER) 508 clk_disable(dev->clk); 509 return 0; 510 } 511 512 static int dw_i2s_resume(struct snd_soc_component *component) 513 { 514 struct dw_i2s_dev *dev = snd_soc_component_get_drvdata(component); 515 struct snd_soc_dai *dai; 516 int stream, ret; 517 518 if (dev->capability & DW_I2S_MASTER) { 519 ret = clk_enable(dev->clk); 520 if (ret) 521 return ret; 522 } 523 524 for_each_component_dais(component, dai) { 525 for_each_pcm_streams(stream) 526 if (snd_soc_dai_stream_active(dai, stream)) 527 dw_i2s_config(dev, stream); 528 } 529 530 return 0; 531 } 532 533 #else 534 #define dw_i2s_suspend NULL 535 #define dw_i2s_resume NULL 536 #endif 537 538 static const struct snd_soc_component_driver dw_i2s_component = { 539 .name = "dw-i2s", 540 .suspend = dw_i2s_suspend, 541 .resume = dw_i2s_resume, 542 .legacy_dai_naming = 1, 543 }; 544 545 /* 546 * The following tables allow a direct lookup of various parameters 547 * defined in the I2S block's configuration in terms of sound system 548 * parameters. Each table is sized to the number of entries possible 549 * according to the number of configuration bits describing an I2S 550 * block parameter. 551 */ 552 553 /* Maximum bit resolution of a channel - not uniformly spaced */ 554 static const u32 fifo_width[COMP_MAX_WORDSIZE] = { 555 12, 16, 20, 24, 32, 0, 0, 0 556 }; 557 558 /* Width of (DMA) bus */ 559 static const u32 bus_widths[COMP_MAX_DATA_WIDTH] = { 560 DMA_SLAVE_BUSWIDTH_1_BYTE, 561 DMA_SLAVE_BUSWIDTH_2_BYTES, 562 DMA_SLAVE_BUSWIDTH_4_BYTES, 563 DMA_SLAVE_BUSWIDTH_UNDEFINED 564 }; 565 566 /* PCM format to support channel resolution */ 567 static const u32 formats[COMP_MAX_WORDSIZE] = { 568 SNDRV_PCM_FMTBIT_S16_LE, 569 SNDRV_PCM_FMTBIT_S16_LE, 570 SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE, 571 SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE, 572 SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, 573 0, 574 0, 575 0 576 }; 577 578 static int dw_configure_dai(struct dw_i2s_dev *dev, 579 struct snd_soc_dai_driver *dw_i2s_dai, 580 unsigned int rates) 581 { 582 /* 583 * Read component parameter registers to extract 584 * the I2S block's configuration. 585 */ 586 u32 comp1 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp1); 587 u32 comp2 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp2); 588 u32 fifo_depth = 1 << (1 + COMP1_FIFO_DEPTH_GLOBAL(comp1)); 589 u32 idx; 590 591 if (dev->capability & DWC_I2S_RECORD && 592 dev->quirks & DW_I2S_QUIRK_COMP_PARAM1) 593 comp1 = comp1 & ~BIT(5); 594 595 if (dev->capability & DWC_I2S_PLAY && 596 dev->quirks & DW_I2S_QUIRK_COMP_PARAM1) 597 comp1 = comp1 & ~BIT(6); 598 599 if (COMP1_TX_ENABLED(comp1)) { 600 dev_dbg(dev->dev, " designware: play supported\n"); 601 idx = COMP1_TX_WORDSIZE_0(comp1); 602 if (WARN_ON(idx >= ARRAY_SIZE(formats))) 603 return -EINVAL; 604 if (dev->quirks & DW_I2S_QUIRK_16BIT_IDX_OVERRIDE) 605 idx = 1; 606 dw_i2s_dai->playback.channels_min = MIN_CHANNEL_NUM; 607 dw_i2s_dai->playback.channels_max = 608 1 << (COMP1_TX_CHANNELS(comp1) + 1); 609 dw_i2s_dai->playback.formats = formats[idx]; 610 dw_i2s_dai->playback.rates = rates; 611 } 612 613 if (COMP1_RX_ENABLED(comp1)) { 614 dev_dbg(dev->dev, "designware: record supported\n"); 615 idx = COMP2_RX_WORDSIZE_0(comp2); 616 if (WARN_ON(idx >= ARRAY_SIZE(formats))) 617 return -EINVAL; 618 if (dev->quirks & DW_I2S_QUIRK_16BIT_IDX_OVERRIDE) 619 idx = 1; 620 dw_i2s_dai->capture.channels_min = MIN_CHANNEL_NUM; 621 dw_i2s_dai->capture.channels_max = 622 1 << (COMP1_RX_CHANNELS(comp1) + 1); 623 dw_i2s_dai->capture.formats = formats[idx]; 624 dw_i2s_dai->capture.rates = rates; 625 } 626 627 if (COMP1_MODE_EN(comp1)) { 628 dev_dbg(dev->dev, "designware: i2s master mode supported\n"); 629 dev->capability |= DW_I2S_MASTER; 630 } else { 631 dev_dbg(dev->dev, "designware: i2s slave mode supported\n"); 632 dev->capability |= DW_I2S_SLAVE; 633 } 634 635 dev->fifo_th = fifo_depth / 2; 636 return 0; 637 } 638 639 static int dw_configure_dai_by_pd(struct dw_i2s_dev *dev, 640 struct snd_soc_dai_driver *dw_i2s_dai, 641 struct resource *res, 642 const struct i2s_platform_data *pdata) 643 { 644 u32 comp1 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp1); 645 u32 idx = COMP1_APB_DATA_WIDTH(comp1); 646 int ret; 647 648 if (WARN_ON(idx >= ARRAY_SIZE(bus_widths))) 649 return -EINVAL; 650 651 ret = dw_configure_dai(dev, dw_i2s_dai, pdata->snd_rates); 652 if (ret < 0) 653 return ret; 654 655 if (dev->quirks & DW_I2S_QUIRK_16BIT_IDX_OVERRIDE) 656 idx = 1; 657 658 if (dev->is_jh7110) { 659 /* Use platform data and snd_dmaengine_dai_dma_data struct at the same time */ 660 u32 comp2 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_2); 661 u32 idx2; 662 663 if (COMP1_TX_ENABLED(comp1)) { 664 idx2 = COMP1_TX_WORDSIZE_0(comp1); 665 dev->play_dma_data.dt.addr = res->start + I2S_TXDMA; 666 dev->play_dma_data.dt.fifo_size = dev->fifo_th * 2 * 667 (fifo_width[idx2]) >> 8; 668 dev->play_dma_data.dt.maxburst = 16; 669 } 670 if (COMP1_RX_ENABLED(comp1)) { 671 idx2 = COMP2_RX_WORDSIZE_0(comp2); 672 dev->capture_dma_data.dt.addr = res->start + I2S_RXDMA; 673 dev->capture_dma_data.dt.fifo_size = dev->fifo_th * 2 * 674 (fifo_width[idx2] >> 8); 675 dev->capture_dma_data.dt.maxburst = 16; 676 } 677 } else { 678 /* Set DMA slaves info */ 679 dev->play_dma_data.pd.data = pdata->play_dma_data; 680 dev->capture_dma_data.pd.data = pdata->capture_dma_data; 681 dev->play_dma_data.pd.addr = res->start + I2S_TXDMA; 682 dev->capture_dma_data.pd.addr = res->start + I2S_RXDMA; 683 dev->play_dma_data.pd.max_burst = 16; 684 dev->capture_dma_data.pd.max_burst = 16; 685 dev->play_dma_data.pd.addr_width = bus_widths[idx]; 686 dev->capture_dma_data.pd.addr_width = bus_widths[idx]; 687 dev->play_dma_data.pd.filter = pdata->filter; 688 dev->capture_dma_data.pd.filter = pdata->filter; 689 } 690 691 return 0; 692 } 693 694 static int dw_configure_dai_by_dt(struct dw_i2s_dev *dev, 695 struct snd_soc_dai_driver *dw_i2s_dai, 696 struct resource *res) 697 { 698 u32 comp1 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_1); 699 u32 comp2 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_2); 700 u32 fifo_depth = 1 << (1 + COMP1_FIFO_DEPTH_GLOBAL(comp1)); 701 u32 idx2; 702 int ret; 703 704 ret = dw_configure_dai(dev, dw_i2s_dai, SNDRV_PCM_RATE_8000_192000); 705 if (ret < 0) 706 return ret; 707 708 if (COMP1_TX_ENABLED(comp1)) { 709 idx2 = COMP1_TX_WORDSIZE_0(comp1); 710 711 dev->capability |= DWC_I2S_PLAY; 712 dev->play_dma_data.dt.addr = res->start + I2S_TXDMA; 713 dev->play_dma_data.dt.fifo_size = fifo_depth * 714 (fifo_width[idx2]) >> 8; 715 dev->play_dma_data.dt.maxburst = 16; 716 } 717 if (COMP1_RX_ENABLED(comp1)) { 718 idx2 = COMP2_RX_WORDSIZE_0(comp2); 719 720 dev->capability |= DWC_I2S_RECORD; 721 dev->capture_dma_data.dt.addr = res->start + I2S_RXDMA; 722 dev->capture_dma_data.dt.fifo_size = fifo_depth * 723 (fifo_width[idx2] >> 8); 724 dev->capture_dma_data.dt.maxburst = 16; 725 } 726 727 return 0; 728 729 } 730 731 #ifdef CONFIG_OF 732 /* clocks initialization with master mode on JH7110 SoC */ 733 static int jh7110_i2s_crg_master_init(struct dw_i2s_dev *dev) 734 { 735 static struct clk_bulk_data clks[] = { 736 { .id = "mclk" }, 737 { .id = "mclk_ext" }, 738 { .id = "mclk_inner" }, 739 { .id = "apb" }, 740 { .id = "i2sclk" }, 741 }; 742 struct reset_control *resets = devm_reset_control_array_get_exclusive(dev->dev); 743 int ret; 744 struct clk *pclk; 745 struct clk *bclk_mst; 746 struct clk *mclk; 747 struct clk *mclk_ext; 748 struct clk *mclk_inner; 749 750 if (IS_ERR(resets)) 751 return dev_err_probe(dev->dev, PTR_ERR(resets), "failed to get i2s resets\n"); 752 753 ret = clk_bulk_get(dev->dev, ARRAY_SIZE(clks), clks); 754 if (ret) 755 return dev_err_probe(dev->dev, ret, "failed to get i2s clocks\n"); 756 757 mclk = clks[0].clk; 758 mclk_ext = clks[1].clk; 759 mclk_inner = clks[2].clk; 760 pclk = clks[3].clk; 761 bclk_mst = clks[4].clk; 762 763 ret = clk_prepare_enable(pclk); 764 if (ret) 765 goto exit; 766 767 /* Use inner mclk first and avoid uninitialized gpio for external mclk */ 768 ret = clk_set_parent(mclk, mclk_inner); 769 if (ret) 770 goto err_dis_pclk; 771 772 ret = clk_prepare_enable(bclk_mst); 773 if (ret) 774 goto err_dis_pclk; 775 776 /* deassert resets before set clock parent */ 777 ret = reset_control_deassert(resets); 778 if (ret) 779 goto err_dis_all; 780 781 /* external clock (12.288MHz) for Audio */ 782 ret = clk_set_parent(mclk, mclk_ext); 783 if (ret) 784 goto err_dis_all; 785 786 /* i2sclk will be got and enabled repeatedly later and should be disabled now. */ 787 clk_disable_unprepare(bclk_mst); 788 clk_bulk_put(ARRAY_SIZE(clks), clks); 789 dev->is_jh7110 = true; 790 791 return 0; 792 793 err_dis_all: 794 clk_disable_unprepare(bclk_mst); 795 err_dis_pclk: 796 clk_disable_unprepare(pclk); 797 exit: 798 clk_bulk_put(ARRAY_SIZE(clks), clks); 799 return ret; 800 } 801 802 /* clocks initialization with slave mode on JH7110 SoC */ 803 static int jh7110_i2s_crg_slave_init(struct dw_i2s_dev *dev) 804 { 805 static struct clk_bulk_data clks[] = { 806 { .id = "mclk" }, 807 { .id = "mclk_ext" }, 808 { .id = "apb" }, 809 { .id = "bclk_ext" }, 810 { .id = "lrck_ext" }, 811 { .id = "bclk" }, 812 { .id = "lrck" }, 813 { .id = "mclk_inner" }, 814 { .id = "i2sclk" }, 815 }; 816 struct reset_control *resets = devm_reset_control_array_get_exclusive(dev->dev); 817 int ret; 818 struct clk *pclk; 819 struct clk *bclk_mst; 820 struct clk *bclk_ext; 821 struct clk *lrck_ext; 822 struct clk *bclk; 823 struct clk *lrck; 824 struct clk *mclk; 825 struct clk *mclk_ext; 826 struct clk *mclk_inner; 827 828 if (IS_ERR(resets)) 829 return dev_err_probe(dev->dev, PTR_ERR(resets), "failed to get i2s resets\n"); 830 831 ret = clk_bulk_get(dev->dev, ARRAY_SIZE(clks), clks); 832 if (ret) 833 return dev_err_probe(dev->dev, ret, "failed to get i2s clocks\n"); 834 835 mclk = clks[0].clk; 836 mclk_ext = clks[1].clk; 837 pclk = clks[2].clk; 838 bclk_ext = clks[3].clk; 839 lrck_ext = clks[4].clk; 840 bclk = clks[5].clk; 841 lrck = clks[6].clk; 842 mclk_inner = clks[7].clk; 843 bclk_mst = clks[8].clk; 844 845 ret = clk_prepare_enable(pclk); 846 if (ret) 847 goto exit; 848 849 ret = clk_set_parent(mclk, mclk_inner); 850 if (ret) 851 goto err_dis_pclk; 852 853 ret = clk_prepare_enable(bclk_mst); 854 if (ret) 855 goto err_dis_pclk; 856 857 ret = reset_control_deassert(resets); 858 if (ret) 859 goto err_dis_all; 860 861 /* The sources of BCLK and LRCK are the external codec. */ 862 ret = clk_set_parent(bclk, bclk_ext); 863 if (ret) 864 goto err_dis_all; 865 866 ret = clk_set_parent(lrck, lrck_ext); 867 if (ret) 868 goto err_dis_all; 869 870 ret = clk_set_parent(mclk, mclk_ext); 871 if (ret) 872 goto err_dis_all; 873 874 /* The i2sclk will be got and enabled repeatedly later and should be disabled now. */ 875 clk_disable_unprepare(bclk_mst); 876 clk_bulk_put(ARRAY_SIZE(clks), clks); 877 dev->is_jh7110 = true; 878 879 return 0; 880 881 err_dis_all: 882 clk_disable_unprepare(bclk_mst); 883 err_dis_pclk: 884 clk_disable_unprepare(pclk); 885 exit: 886 clk_bulk_put(ARRAY_SIZE(clks), clks); 887 return ret; 888 } 889 890 /* Special syscon initialization about RX channel with slave mode on JH7110 SoC */ 891 static int jh7110_i2srx_crg_init(struct dw_i2s_dev *dev) 892 { 893 struct regmap *regmap; 894 unsigned int args[2]; 895 896 regmap = syscon_regmap_lookup_by_phandle_args(dev->dev->of_node, 897 "starfive,syscon", 898 2, args); 899 if (IS_ERR(regmap)) 900 return dev_err_probe(dev->dev, PTR_ERR(regmap), "getting the regmap failed\n"); 901 902 /* Enable I2Srx with syscon register, args[0]: offset, args[1]: mask */ 903 regmap_update_bits(regmap, args[0], args[1], args[1]); 904 905 return jh7110_i2s_crg_slave_init(dev); 906 } 907 908 static int jh7110_i2stx0_clk_cfg(struct i2s_clk_config_data *config) 909 { 910 struct dw_i2s_dev *dev = container_of(config, struct dw_i2s_dev, config); 911 u32 bclk_rate = config->sample_rate * 64; 912 913 return clk_set_rate(dev->clk, bclk_rate); 914 } 915 #endif /* CONFIG_OF */ 916 917 static int dw_i2s_probe(struct platform_device *pdev) 918 { 919 const struct i2s_platform_data *pdata = pdev->dev.platform_data; 920 struct dw_i2s_dev *dev; 921 struct resource *res; 922 int ret, irq; 923 struct snd_soc_dai_driver *dw_i2s_dai; 924 const char *clk_id; 925 926 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL); 927 if (!dev) 928 return -ENOMEM; 929 930 dw_i2s_dai = devm_kzalloc(&pdev->dev, sizeof(*dw_i2s_dai), GFP_KERNEL); 931 if (!dw_i2s_dai) 932 return -ENOMEM; 933 934 dw_i2s_dai->ops = &dw_i2s_dai_ops; 935 936 dev->i2s_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 937 if (IS_ERR(dev->i2s_base)) 938 return PTR_ERR(dev->i2s_base); 939 940 dev->dev = &pdev->dev; 941 dev->is_jh7110 = false; 942 if (pdata) { 943 if (pdata->i2s_pd_init) { 944 ret = pdata->i2s_pd_init(dev); 945 if (ret) 946 return ret; 947 } 948 } 949 950 if (!dev->is_jh7110) { 951 dev->reset = devm_reset_control_array_get_optional_shared(&pdev->dev); 952 if (IS_ERR(dev->reset)) 953 return PTR_ERR(dev->reset); 954 955 ret = reset_control_deassert(dev->reset); 956 if (ret) 957 return ret; 958 } 959 960 irq = platform_get_irq_optional(pdev, 0); 961 if (irq >= 0) { 962 ret = devm_request_irq(&pdev->dev, irq, i2s_irq_handler, 0, 963 pdev->name, dev); 964 if (ret < 0) { 965 dev_err(&pdev->dev, "failed to request irq\n"); 966 goto err_assert_reset; 967 } 968 } 969 970 dev->i2s_reg_comp1 = I2S_COMP_PARAM_1; 971 dev->i2s_reg_comp2 = I2S_COMP_PARAM_2; 972 if (pdata) { 973 dev->capability = pdata->cap; 974 clk_id = NULL; 975 dev->quirks = pdata->quirks; 976 if (dev->quirks & DW_I2S_QUIRK_COMP_REG_OFFSET) { 977 dev->i2s_reg_comp1 = pdata->i2s_reg_comp1; 978 dev->i2s_reg_comp2 = pdata->i2s_reg_comp2; 979 } 980 ret = dw_configure_dai_by_pd(dev, dw_i2s_dai, res, pdata); 981 } else { 982 clk_id = "i2sclk"; 983 ret = dw_configure_dai_by_dt(dev, dw_i2s_dai, res); 984 } 985 if (ret < 0) 986 goto err_assert_reset; 987 988 if (dev->capability & DW_I2S_MASTER) { 989 if (pdata) { 990 dev->i2s_clk_cfg = pdata->i2s_clk_cfg; 991 if (!dev->i2s_clk_cfg) { 992 dev_err(&pdev->dev, "no clock configure method\n"); 993 ret = -ENODEV; 994 goto err_assert_reset; 995 } 996 } 997 dev->clk = devm_clk_get_enabled(&pdev->dev, clk_id); 998 999 if (IS_ERR(dev->clk)) { 1000 ret = PTR_ERR(dev->clk); 1001 goto err_assert_reset; 1002 } 1003 } 1004 1005 dev_set_drvdata(&pdev->dev, dev); 1006 ret = devm_snd_soc_register_component(&pdev->dev, &dw_i2s_component, 1007 dw_i2s_dai, 1); 1008 if (ret != 0) { 1009 dev_err(&pdev->dev, "not able to register dai\n"); 1010 goto err_assert_reset; 1011 } 1012 1013 if (!pdata || dev->is_jh7110) { 1014 if (irq >= 0) { 1015 ret = dw_pcm_register(pdev); 1016 dev->use_pio = true; 1017 dev->l_reg = LRBR_LTHR(0); 1018 dev->r_reg = RRBR_RTHR(0); 1019 } else { 1020 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 1021 0); 1022 dev->use_pio = false; 1023 } 1024 1025 if (ret) { 1026 dev_err(&pdev->dev, "could not register pcm: %d\n", 1027 ret); 1028 goto err_assert_reset; 1029 } 1030 } 1031 1032 pm_runtime_enable(&pdev->dev); 1033 return 0; 1034 1035 err_assert_reset: 1036 reset_control_assert(dev->reset); 1037 return ret; 1038 } 1039 1040 static void dw_i2s_remove(struct platform_device *pdev) 1041 { 1042 struct dw_i2s_dev *dev = dev_get_drvdata(&pdev->dev); 1043 1044 reset_control_assert(dev->reset); 1045 pm_runtime_disable(&pdev->dev); 1046 } 1047 1048 #ifdef CONFIG_OF 1049 static const struct i2s_platform_data jh7110_i2stx0_data = { 1050 .cap = DWC_I2S_PLAY | DW_I2S_MASTER, 1051 .channel = TWO_CHANNEL_SUPPORT, 1052 .snd_fmts = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE, 1053 .snd_rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000, 1054 .i2s_clk_cfg = jh7110_i2stx0_clk_cfg, 1055 .i2s_pd_init = jh7110_i2s_crg_master_init, 1056 }; 1057 1058 static const struct i2s_platform_data jh7110_i2stx1_data = { 1059 .cap = DWC_I2S_PLAY | DW_I2S_SLAVE, 1060 .channel = TWO_CHANNEL_SUPPORT, 1061 .snd_fmts = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE, 1062 .snd_rates = SNDRV_PCM_RATE_8000_192000, 1063 .i2s_pd_init = jh7110_i2s_crg_slave_init, 1064 }; 1065 1066 static const struct i2s_platform_data jh7110_i2srx_data = { 1067 .cap = DWC_I2S_RECORD | DW_I2S_SLAVE, 1068 .channel = TWO_CHANNEL_SUPPORT, 1069 .snd_fmts = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE, 1070 .snd_rates = SNDRV_PCM_RATE_8000_192000, 1071 .i2s_pd_init = jh7110_i2srx_crg_init, 1072 }; 1073 1074 static const struct of_device_id dw_i2s_of_match[] = { 1075 { .compatible = "snps,designware-i2s", }, 1076 { .compatible = "starfive,jh7110-i2stx0", .data = &jh7110_i2stx0_data, }, 1077 { .compatible = "starfive,jh7110-i2stx1", .data = &jh7110_i2stx1_data,}, 1078 { .compatible = "starfive,jh7110-i2srx", .data = &jh7110_i2srx_data,}, 1079 {}, 1080 }; 1081 1082 MODULE_DEVICE_TABLE(of, dw_i2s_of_match); 1083 #endif 1084 1085 static const struct dev_pm_ops dwc_pm_ops = { 1086 RUNTIME_PM_OPS(dw_i2s_runtime_suspend, dw_i2s_runtime_resume, NULL) 1087 }; 1088 1089 static struct platform_driver dw_i2s_driver = { 1090 .probe = dw_i2s_probe, 1091 .remove = dw_i2s_remove, 1092 .driver = { 1093 .name = "designware-i2s", 1094 .of_match_table = of_match_ptr(dw_i2s_of_match), 1095 .pm = pm_ptr(&dwc_pm_ops), 1096 }, 1097 }; 1098 1099 module_platform_driver(dw_i2s_driver); 1100 1101 MODULE_AUTHOR("Rajeev Kumar <rajeevkumar.linux@gmail.com>"); 1102 MODULE_DESCRIPTION("DESIGNWARE I2S SoC Interface"); 1103 MODULE_LICENSE("GPL"); 1104 MODULE_ALIAS("platform:designware_i2s"); 1105