1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * AMD Common ACP header file for ACP6.3, ACP7.0 & ACP7.1 platforms 4 * 5 * Copyright (C) 2022, 2023, 2025 Advanced Micro Devices, Inc. All rights reserved. 6 */ 7 8 #include <linux/soundwire/sdw_amd.h> 9 #include <sound/acp63_chip_offset_byte.h> 10 11 #define ACP_DEVICE_ID 0x15E2 12 #define ACP63_REG_START 0x1240000 13 #define ACP63_REG_END 0x125C000 14 #define ACP63_PCI_REV 0x63 15 #define ACP70_PCI_REV 0x70 16 #define ACP71_PCI_REV 0x71 17 18 #define ACP_SOFT_RESET_SOFTRESET_AUDDONE_MASK 0x00010001 19 #define ACP63_PGFSM_CNTL_POWER_ON_MASK 1 20 #define ACP63_PGFSM_CNTL_POWER_OFF_MASK 0 21 #define ACP63_PGFSM_STATUS_MASK 3 22 #define ACP63_POWERED_ON 0 23 #define ACP63_POWER_ON_IN_PROGRESS 1 24 #define ACP63_POWERED_OFF 2 25 #define ACP63_POWER_OFF_IN_PROGRESS 3 26 27 #define ACP_ERROR_MASK 0x20000000 28 #define ACP_EXT_INTR_STAT_CLEAR_MASK 0xFFFFFFFF 29 #define PDM_DMA_STAT 0x10 30 31 #define PDM_DMA_INTR_MASK 0x10000 32 #define ACP_ERROR_STAT 29 33 #define PDM_DECIMATION_FACTOR 2 34 #define ACP_PDM_CLK_FREQ_MASK 7 35 #define ACP_WOV_GAIN_CONTROL GENMASK(4, 3) 36 #define ACP_PDM_ENABLE 1 37 #define ACP_PDM_DISABLE 0 38 #define ACP_PDM_DMA_EN_STATUS 2 39 #define TWO_CH 2 40 #define DELAY_US 5 41 #define ACP_COUNTER 20000 42 43 #define ACP_SRAM_PTE_OFFSET 0x03800000 44 #define PAGE_SIZE_4K_ENABLE 2 45 #define PDM_PTE_OFFSET 0 46 #define PDM_MEM_WINDOW_START 0x4000000 47 48 #define CAPTURE_MIN_NUM_PERIODS 4 49 #define CAPTURE_MAX_NUM_PERIODS 4 50 #define CAPTURE_MAX_PERIOD_SIZE 8192 51 #define CAPTURE_MIN_PERIOD_SIZE 4096 52 53 #define MAX_BUFFER (CAPTURE_MAX_PERIOD_SIZE * CAPTURE_MAX_NUM_PERIODS) 54 #define MIN_BUFFER MAX_BUFFER 55 56 /* time in ms for runtime suspend delay */ 57 #define ACP_SUSPEND_DELAY_MS 2000 58 59 #define ACP_DMIC_DEV 2 60 61 #define ACP63_DMIC_ADDR 2 62 #define ACP63_SDW_ADDR 5 63 #define AMD_SDW_MAX_MANAGERS 2 64 65 /* time in ms for acp timeout */ 66 #define ACP63_TIMEOUT 500 67 68 #define ACP_SDW0_STAT BIT(21) 69 #define ACP_SDW1_STAT BIT(2) 70 #define ACP_ERROR_IRQ BIT(29) 71 72 #define ACP_AUDIO0_TX_THRESHOLD 0x1c 73 #define ACP_AUDIO1_TX_THRESHOLD 0x1a 74 #define ACP_AUDIO2_TX_THRESHOLD 0x18 75 #define ACP_AUDIO0_RX_THRESHOLD 0x1b 76 #define ACP_AUDIO1_RX_THRESHOLD 0x19 77 #define ACP_AUDIO2_RX_THRESHOLD 0x17 78 #define ACP63_P1_AUDIO1_TX_THRESHOLD BIT(6) 79 #define ACP63_P1_AUDIO1_RX_THRESHOLD BIT(5) 80 #define ACP63_SDW_DMA_IRQ_MASK 0x1F800000 81 #define ACP63_P1_SDW_DMA_IRQ_MASK 0x60 82 #define ACP63_SDW0_DMA_MAX_STREAMS 6 83 #define ACP63_SDW1_DMA_MAX_STREAMS 2 84 #define ACP63_P1_AUDIO_TX_THRESHOLD 6 85 86 /* 87 * Below entries describes SDW0 instance DMA stream id and DMA irq bit mapping 88 * in ACP_EXTENAL_INTR_CNTL register. 89 * Stream id IRQ Bit 90 * 0 (SDW0_AUDIO0_TX) 28 91 * 1 (SDW0_AUDIO1_TX) 26 92 * 2 (SDW0_AUDIO2_TX) 24 93 * 3 (SDW0_AUDIO0_RX) 27 94 * 4 (SDW0_AUDIO1_RX) 25 95 * 5 (SDW0_AUDIO2_RX) 23 96 */ 97 #define ACP63_SDW0_DMA_TX_IRQ_MASK(i) (ACP_AUDIO0_TX_THRESHOLD - (2 * (i))) 98 #define ACP63_SDW0_DMA_RX_IRQ_MASK(i) (ACP_AUDIO0_RX_THRESHOLD - (2 * ((i) - 3))) 99 100 /* 101 * Below entries describes SDW1 instance DMA stream id and DMA irq bit mapping 102 * in ACP_EXTENAL_INTR_CNTL1 register. 103 * Stream id IRQ Bit 104 * 0 (SDW1_AUDIO1_TX) 6 105 * 1 (SDW1_AUDIO1_RX) 5 106 */ 107 #define ACP63_SDW1_DMA_IRQ_MASK(i) (ACP63_P1_AUDIO_TX_THRESHOLD - (i)) 108 109 #define ACP_DELAY_US 5 110 #define ACP_SDW_RING_BUFF_ADDR_OFFSET (128 * 1024) 111 #define SDW0_MEM_WINDOW_START 0x4800000 112 #define ACP_SDW_SRAM_PTE_OFFSET 0x03800400 113 #define SDW0_PTE_OFFSET 0x400 114 #define SDW_FIFO_SIZE 0x100 115 #define SDW_DMA_SIZE 0x40 116 #define ACP_SDW0_FIFO_OFFSET 0x100 117 #define ACP_SDW_PTE_OFFSET 0x100 118 #define SDW_FIFO_OFFSET 0x100 119 #define SDW_PTE_OFFSET(i) (SDW0_PTE_OFFSET + ((i) * 0x600)) 120 #define ACP_SDW_FIFO_OFFSET(i) (ACP_SDW0_FIFO_OFFSET + ((i) * 0x500)) 121 #define SDW_MEM_WINDOW_START(i) (SDW0_MEM_WINDOW_START + ((i) * 0xC0000)) 122 123 #define SDW_PLAYBACK_MIN_NUM_PERIODS 2 124 #define SDW_PLAYBACK_MAX_NUM_PERIODS 8 125 #define SDW_PLAYBACK_MAX_PERIOD_SIZE 8192 126 #define SDW_PLAYBACK_MIN_PERIOD_SIZE 1024 127 #define SDW_CAPTURE_MIN_NUM_PERIODS 2 128 #define SDW_CAPTURE_MAX_NUM_PERIODS 8 129 #define SDW_CAPTURE_MAX_PERIOD_SIZE 8192 130 #define SDW_CAPTURE_MIN_PERIOD_SIZE 1024 131 132 #define SDW_MAX_BUFFER (SDW_PLAYBACK_MAX_PERIOD_SIZE * SDW_PLAYBACK_MAX_NUM_PERIODS) 133 #define SDW_MIN_BUFFER SDW_MAX_BUFFER 134 135 #define ACP_HW_OPS(acp_data, cb) ((acp_data)->hw_ops->cb) 136 137 #define ACP70_PGFSM_CNTL_POWER_ON_MASK 0x1F 138 #define ACP70_PGFSM_CNTL_POWER_OFF_MASK 0 139 #define ACP70_PGFSM_STATUS_MASK 0xFF 140 #define ACP70_TIMEOUT 2000 141 #define ACP70_SDW_HOST_WAKE_MASK 0x0C00000 142 #define ACP70_SDW0_HOST_WAKE_STAT BIT(24) 143 #define ACP70_SDW1_HOST_WAKE_STAT BIT(25) 144 #define ACP70_SDW0_PME_STAT BIT(26) 145 #define ACP70_SDW1_PME_STAT BIT(27) 146 147 #define ACP70_SDW0_DMA_MAX_STREAMS 6 148 #define ACP70_SDW1_DMA_MAX_STREAMS ACP70_SDW0_DMA_MAX_STREAMS 149 #define ACP70_SDW_DMA_IRQ_MASK 0x1F800000 150 #define ACP70_P1_SDW_DMA_IRQ_MASK 0x1F8 151 152 #define ACP70_P1_AUDIO0_TX_THRESHOLD 0x8 153 #define ACP70_P1_AUDIO1_TX_THRESHOLD 0x6 154 #define ACP70_P1_AUDIO2_TX_THRESHOLD 0x4 155 #define ACP70_P1_AUDIO0_RX_THRESHOLD 0x7 156 #define ACP70_P1_AUDIO1_RX_THRESHOLD 0x5 157 #define ACP70_P1_AUDIO2_RX_THRESHOLD 0x3 158 159 #define ACP70_SDW0_DMA_TX_IRQ_MASK(i) (ACP_AUDIO0_TX_THRESHOLD - (2 * (i))) 160 #define ACP70_SDW0_DMA_RX_IRQ_MASK(i) (ACP_AUDIO0_RX_THRESHOLD - (2 * ((i) - 3))) 161 162 /* 163 * Below entries describes SDW1 instance DMA stream id and DMA irq bit mapping 164 * in ACP_EXTENAL_INTR_CNTL1 register for ACP70/ACP71 platforms 165 * Stream id IRQ Bit 166 * 0 (SDW1_AUDIO0_TX) 8 167 * 1 (SDW1_AUDIO1_TX) 6 168 * 2 (SDW1_AUDIO2_TX) 4 169 * 3 (SDW1_AUDIO0_RX) 7 170 * 4 (SDW1_AUDIO1_RX) 5 171 * 5 (SDW1_AUDIO2_RX) 3 172 */ 173 #define ACP70_SDW1_DMA_TX_IRQ_MASK(i) (ACP70_P1_AUDIO0_TX_THRESHOLD - (2 * (i))) 174 #define ACP70_SDW1_DMA_RX_IRQ_MASK(i) (ACP70_P1_AUDIO0_RX_THRESHOLD - (2 * ((i) - 3))) 175 176 #define ACP70_SW0_AUDIO0_TX_EN ACP_SW0_AUDIO0_TX_EN 177 #define ACP70_SW0_AUDIO1_TX_EN ACP_SW0_AUDIO1_TX_EN 178 #define ACP70_SW0_AUDIO2_TX_EN ACP_SW0_AUDIO2_TX_EN 179 #define ACP70_SW0_AUDIO0_RX_EN ACP_SW0_AUDIO0_RX_EN 180 #define ACP70_SW0_AUDIO1_RX_EN ACP_SW0_AUDIO1_RX_EN 181 #define ACP70_SW0_AUDIO2_RX_EN ACP_SW0_AUDIO2_RX_EN 182 183 #define ACP70_SW1_AUDIO0_TX_EN 0x0003C10 184 #define ACP70_SW1_AUDIO1_TX_EN 0x0003C50 185 #define ACP70_SW1_AUDIO2_TX_EN 0x0003C6C 186 #define ACP70_SW1_AUDIO0_RX_EN 0x0003C88 187 #define ACP70_SW1_AUDIO1_RX_EN 0x0003D28 188 #define ACP70_SW1_AUDIO2_RX_EN 0x0003D44 189 190 enum acp_config { 191 ACP_CONFIG_0 = 0, 192 ACP_CONFIG_1, 193 ACP_CONFIG_2, 194 ACP_CONFIG_3, 195 ACP_CONFIG_4, 196 ACP_CONFIG_5, 197 ACP_CONFIG_6, 198 ACP_CONFIG_7, 199 ACP_CONFIG_8, 200 ACP_CONFIG_9, 201 ACP_CONFIG_10, 202 ACP_CONFIG_11, 203 ACP_CONFIG_12, 204 ACP_CONFIG_13, 205 ACP_CONFIG_14, 206 ACP_CONFIG_15, 207 ACP_CONFIG_16, 208 ACP_CONFIG_17, 209 ACP_CONFIG_18, 210 ACP_CONFIG_19, 211 ACP_CONFIG_20, 212 }; 213 214 enum amd_acp63_sdw0_channel { 215 ACP63_SDW0_AUDIO0_TX = 0, 216 ACP63_SDW0_AUDIO1_TX, 217 ACP63_SDW0_AUDIO2_TX, 218 ACP63_SDW0_AUDIO0_RX, 219 ACP63_SDW0_AUDIO1_RX, 220 ACP63_SDW0_AUDIO2_RX, 221 }; 222 223 enum amd_acp63_sdw1_channel { 224 ACP63_SDW1_AUDIO1_TX, 225 ACP63_SDW1_AUDIO1_RX, 226 }; 227 228 enum amd_acp70_sdw_channel { 229 ACP70_SDW_AUDIO0_TX = 0, 230 ACP70_SDW_AUDIO1_TX, 231 ACP70_SDW_AUDIO2_TX, 232 ACP70_SDW_AUDIO0_RX, 233 ACP70_SDW_AUDIO1_RX, 234 ACP70_SDW_AUDIO2_RX, 235 }; 236 237 struct pdm_stream_instance { 238 u16 num_pages; 239 u16 channels; 240 dma_addr_t dma_addr; 241 u64 bytescount; 242 void __iomem *acp63_base; 243 }; 244 245 struct pdm_dev_data { 246 u32 pdm_irq; 247 void __iomem *acp63_base; 248 struct mutex *acp_lock; 249 struct snd_pcm_substream *capture_stream; 250 }; 251 252 struct sdw_dma_dev_data { 253 void __iomem *acp_base; 254 struct mutex *acp_lock; /* used to protect acp common register access */ 255 u32 acp_rev; 256 struct snd_pcm_substream *acp63_sdw0_dma_stream[ACP63_SDW0_DMA_MAX_STREAMS]; 257 struct snd_pcm_substream *acp63_sdw1_dma_stream[ACP63_SDW1_DMA_MAX_STREAMS]; 258 struct snd_pcm_substream *acp70_sdw0_dma_stream[ACP70_SDW0_DMA_MAX_STREAMS]; 259 struct snd_pcm_substream *acp70_sdw1_dma_stream[ACP70_SDW1_DMA_MAX_STREAMS]; 260 }; 261 262 struct acp_sdw_dma_stream { 263 u16 num_pages; 264 u16 channels; 265 u32 stream_id; 266 u32 instance; 267 dma_addr_t dma_addr; 268 u64 bytescount; 269 }; 270 271 union acp_sdw_dma_count { 272 struct { 273 u32 low; 274 u32 high; 275 } bcount; 276 u64 bytescount; 277 }; 278 279 struct sdw_dma_ring_buf_reg { 280 u32 reg_dma_size; 281 u32 reg_fifo_addr; 282 u32 reg_fifo_size; 283 u32 reg_ring_buf_size; 284 u32 reg_ring_buf_addr; 285 u32 water_mark_size_reg; 286 u32 pos_low_reg; 287 u32 pos_high_reg; 288 }; 289 290 struct acp63_dev_data; 291 292 /** 293 * struct acp_hw_ops - ACP PCI driver platform specific ops 294 * @acp_init: ACP initialization 295 * @acp_deinit: ACP de-initialization 296 * @acp_get_config: function to read the acp pin configuration 297 * @acp_sdw_dma_irq_thread: ACP SoundWire DMA interrupt thread 298 * acp_suspend: ACP system level suspend callback 299 * acp_resume: ACP system level resume callback 300 * acp_suspend_runtime: ACP runtime suspend callback 301 * acp_resume_runtime: ACP runtime resume callback 302 */ 303 struct acp_hw_ops { 304 int (*acp_init)(void __iomem *acp_base, struct device *dev); 305 int (*acp_deinit)(void __iomem *acp_base, struct device *dev); 306 void (*acp_get_config)(struct pci_dev *pci, struct acp63_dev_data *acp_data); 307 void (*acp_sdw_dma_irq_thread)(struct acp63_dev_data *acp_data); 308 int (*acp_suspend)(struct device *dev); 309 int (*acp_resume)(struct device *dev); 310 int (*acp_suspend_runtime)(struct device *dev); 311 int (*acp_resume_runtime)(struct device *dev); 312 }; 313 314 /** 315 * struct acp63_dev_data - acp pci driver context 316 * @acp63_base: acp mmio base 317 * @res: resource 318 * @hw_ops: ACP pci driver platform-specific ops 319 * @pdm_dev: ACP PDM controller platform device 320 * @dmic_codec: platform device for DMIC Codec 321 * sdw_dma_dev: platform device for SoundWire DMA controller 322 * @mach_dev: platform device for machine driver to support ACP PDM/SoundWire configuration 323 * @acp_lock: used to protect acp common registers 324 * @info: SoundWire AMD information found in ACPI tables 325 * @sdw: SoundWire context for all SoundWire manager instances 326 * @machine: ACPI machines for SoundWire interface 327 * @is_sdw_dev: flag set to true when any SoundWire manager instances are available 328 * @is_pdm_dev: flag set to true when ACP PDM controller exists 329 * @is_pdm_config: flat set to true when PDM configuration is selected from BIOS 330 * @is_sdw_config: flag set to true when SDW configuration is selected from BIOS 331 * @sdw_en_stat: flag set to true when any one of the SoundWire manager instance is enabled 332 * @acp70_sdw0_wake_event: flag set to true when wake irq asserted for SW0 instance 333 * @acp70_sdw1_wake_event: flag set to true when wake irq asserted for SW1 instance 334 * @addr: pci ioremap address 335 * @reg_range: ACP reigister range 336 * @acp_rev: ACP PCI revision id 337 * @acp63_sdw0-dma_intr_stat: DMA interrupt status array for ACP6.3 platform SoundWire 338 * manager-SW0 instance 339 * @acp63_sdw_dma_intr_stat: DMA interrupt status array for ACP6.3 platform SoundWire 340 * manager-SW1 instance 341 * @acp70_sdw0-dma_intr_stat: DMA interrupt status array for ACP7.0 platform SoundWire 342 * manager-SW0 instance 343 * @acp70_sdw_dma_intr_stat: DMA interrupt status array for ACP7.0 platform SoundWire 344 * manager-SW1 instance 345 */ 346 347 struct acp63_dev_data { 348 void __iomem *acp63_base; 349 struct resource *res; 350 struct acp_hw_ops *hw_ops; 351 struct platform_device *pdm_dev; 352 struct platform_device *dmic_codec_dev; 353 struct platform_device *sdw_dma_dev; 354 struct platform_device *mach_dev; 355 struct mutex acp_lock; /* protect shared registers */ 356 struct sdw_amd_acpi_info info; 357 /* sdw context allocated by SoundWire driver */ 358 struct sdw_amd_ctx *sdw; 359 struct snd_soc_acpi_mach *machines; 360 bool is_sdw_dev; 361 bool is_pdm_dev; 362 bool is_pdm_config; 363 bool is_sdw_config; 364 bool sdw_en_stat; 365 bool acp70_sdw0_wake_event; 366 bool acp70_sdw1_wake_event; 367 u32 addr; 368 u32 reg_range; 369 u32 acp_rev; 370 u16 acp63_sdw0_dma_intr_stat[ACP63_SDW0_DMA_MAX_STREAMS]; 371 u16 acp63_sdw1_dma_intr_stat[ACP63_SDW1_DMA_MAX_STREAMS]; 372 u16 acp70_sdw0_dma_intr_stat[ACP70_SDW0_DMA_MAX_STREAMS]; 373 u16 acp70_sdw1_dma_intr_stat[ACP70_SDW1_DMA_MAX_STREAMS]; 374 }; 375 376 void acp63_hw_init_ops(struct acp_hw_ops *hw_ops); 377 void acp70_hw_init_ops(struct acp_hw_ops *hw_ops); 378 379 static inline int acp_hw_init(struct acp63_dev_data *adata, struct device *dev) 380 { 381 if (adata && adata->hw_ops && adata->hw_ops->acp_init) 382 return ACP_HW_OPS(adata, acp_init)(adata->acp63_base, dev); 383 return -EOPNOTSUPP; 384 } 385 386 static inline int acp_hw_deinit(struct acp63_dev_data *adata, struct device *dev) 387 { 388 if (adata && adata->hw_ops && adata->hw_ops->acp_deinit) 389 return ACP_HW_OPS(adata, acp_deinit)(adata->acp63_base, dev); 390 return -EOPNOTSUPP; 391 } 392 393 static inline void acp_hw_get_config(struct pci_dev *pci, struct acp63_dev_data *adata) 394 { 395 if (adata && adata->hw_ops && adata->hw_ops->acp_get_config) 396 ACP_HW_OPS(adata, acp_get_config)(pci, adata); 397 } 398 399 static inline void acp_hw_sdw_dma_irq_thread(struct acp63_dev_data *adata) 400 { 401 if (adata && adata->hw_ops && adata->hw_ops->acp_sdw_dma_irq_thread) 402 ACP_HW_OPS(adata, acp_sdw_dma_irq_thread)(adata); 403 } 404 405 static inline int acp_hw_suspend(struct device *dev) 406 { 407 struct acp63_dev_data *adata = dev_get_drvdata(dev); 408 409 if (adata && adata->hw_ops && adata->hw_ops->acp_suspend) 410 return ACP_HW_OPS(adata, acp_suspend)(dev); 411 return -EOPNOTSUPP; 412 } 413 414 static inline int acp_hw_resume(struct device *dev) 415 { 416 struct acp63_dev_data *adata = dev_get_drvdata(dev); 417 418 if (adata && adata->hw_ops && adata->hw_ops->acp_resume) 419 return ACP_HW_OPS(adata, acp_resume)(dev); 420 return -EOPNOTSUPP; 421 } 422 423 static inline int acp_hw_suspend_runtime(struct device *dev) 424 { 425 struct acp63_dev_data *adata = dev_get_drvdata(dev); 426 427 if (adata && adata->hw_ops && adata->hw_ops->acp_suspend_runtime) 428 return ACP_HW_OPS(adata, acp_suspend_runtime)(dev); 429 return -EOPNOTSUPP; 430 } 431 432 static inline int acp_hw_runtime_resume(struct device *dev) 433 { 434 struct acp63_dev_data *adata = dev_get_drvdata(dev); 435 436 if (adata && adata->hw_ops && adata->hw_ops->acp_resume_runtime) 437 return ACP_HW_OPS(adata, acp_resume_runtime)(dev); 438 return -EOPNOTSUPP; 439 } 440 441 int snd_amd_acp_find_config(struct pci_dev *pci); 442