1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Sound driver for Nintendo 64. 4 * 5 * Copyright 2021 Lauri Kasanen 6 */ 7 8 #include <linux/dma-mapping.h> 9 #include <linux/init.h> 10 #include <linux/interrupt.h> 11 #include <linux/io.h> 12 #include <linux/log2.h> 13 #include <linux/module.h> 14 #include <linux/platform_device.h> 15 #include <linux/spinlock.h> 16 #include <linux/string.h> 17 18 #include <sound/control.h> 19 #include <sound/core.h> 20 #include <sound/initval.h> 21 #include <sound/pcm.h> 22 #include <sound/pcm_params.h> 23 24 MODULE_AUTHOR("Lauri Kasanen <cand@gmx.com>"); 25 MODULE_DESCRIPTION("N64 Audio"); 26 MODULE_LICENSE("GPL"); 27 28 #define AI_NTSC_DACRATE 48681812 29 #define AI_STATUS_BUSY (1 << 30) 30 #define AI_STATUS_FULL (1 << 31) 31 32 #define AI_ADDR_REG 0 33 #define AI_LEN_REG 1 34 #define AI_CONTROL_REG 2 35 #define AI_STATUS_REG 3 36 #define AI_RATE_REG 4 37 #define AI_BITCLOCK_REG 5 38 39 #define MI_INTR_REG 2 40 #define MI_MASK_REG 3 41 42 #define MI_INTR_AI 0x04 43 44 #define MI_MASK_CLR_AI 0x0010 45 #define MI_MASK_SET_AI 0x0020 46 47 48 struct n64audio { 49 u32 __iomem *ai_reg_base; 50 u32 __iomem *mi_reg_base; 51 52 void *ring_base; 53 dma_addr_t ring_base_dma; 54 55 struct snd_card *card; 56 57 struct { 58 struct snd_pcm_substream *substream; 59 int pos, nextpos; 60 u32 writesize; 61 u32 bufsize; 62 spinlock_t lock; 63 } chan; 64 }; 65 66 static void n64audio_write_reg(struct n64audio *priv, const u8 reg, const u32 value) 67 { 68 writel(value, priv->ai_reg_base + reg); 69 } 70 71 static void n64mi_write_reg(struct n64audio *priv, const u8 reg, const u32 value) 72 { 73 writel(value, priv->mi_reg_base + reg); 74 } 75 76 static u32 n64mi_read_reg(struct n64audio *priv, const u8 reg) 77 { 78 return readl(priv->mi_reg_base + reg); 79 } 80 81 static void n64audio_push(struct n64audio *priv) 82 { 83 struct snd_pcm_runtime *runtime = priv->chan.substream->runtime; 84 unsigned long flags; 85 u32 count; 86 87 spin_lock_irqsave(&priv->chan.lock, flags); 88 89 count = priv->chan.writesize; 90 91 memcpy(priv->ring_base + priv->chan.nextpos, 92 runtime->dma_area + priv->chan.nextpos, count); 93 94 /* 95 * The hw registers are double-buffered, and the IRQ fires essentially 96 * one period behind. The core only allows one period's distance, so we 97 * keep a private DMA buffer to afford two. 98 */ 99 n64audio_write_reg(priv, AI_ADDR_REG, priv->ring_base_dma + priv->chan.nextpos); 100 barrier(); 101 n64audio_write_reg(priv, AI_LEN_REG, count); 102 103 priv->chan.nextpos += count; 104 priv->chan.nextpos %= priv->chan.bufsize; 105 106 runtime->delay = runtime->period_size; 107 108 spin_unlock_irqrestore(&priv->chan.lock, flags); 109 } 110 111 static irqreturn_t n64audio_isr(int irq, void *dev_id) 112 { 113 struct n64audio *priv = dev_id; 114 const u32 intrs = n64mi_read_reg(priv, MI_INTR_REG); 115 unsigned long flags; 116 117 // Check it's ours 118 if (!(intrs & MI_INTR_AI)) 119 return IRQ_NONE; 120 121 n64audio_write_reg(priv, AI_STATUS_REG, 1); 122 123 if (priv->chan.substream && snd_pcm_running(priv->chan.substream)) { 124 spin_lock_irqsave(&priv->chan.lock, flags); 125 126 priv->chan.pos = priv->chan.nextpos; 127 128 spin_unlock_irqrestore(&priv->chan.lock, flags); 129 130 snd_pcm_period_elapsed(priv->chan.substream); 131 if (priv->chan.substream && snd_pcm_running(priv->chan.substream)) 132 n64audio_push(priv); 133 } 134 135 return IRQ_HANDLED; 136 } 137 138 static const struct snd_pcm_hardware n64audio_pcm_hw = { 139 .info = (SNDRV_PCM_INFO_MMAP | 140 SNDRV_PCM_INFO_MMAP_VALID | 141 SNDRV_PCM_INFO_INTERLEAVED | 142 SNDRV_PCM_INFO_BLOCK_TRANSFER), 143 .formats = SNDRV_PCM_FMTBIT_S16_BE, 144 .rates = SNDRV_PCM_RATE_8000_48000, 145 .rate_min = 8000, 146 .rate_max = 48000, 147 .channels_min = 2, 148 .channels_max = 2, 149 .buffer_bytes_max = 32768, 150 .period_bytes_min = 1024, 151 .period_bytes_max = 32768, 152 .periods_min = 3, 153 // 3 periods lets the double-buffering hw read one buffer behind safely 154 .periods_max = 128, 155 }; 156 157 static int hw_rule_period_size(struct snd_pcm_hw_params *params, 158 struct snd_pcm_hw_rule *rule) 159 { 160 struct snd_interval *c = hw_param_interval(params, 161 SNDRV_PCM_HW_PARAM_PERIOD_SIZE); 162 int changed = 0; 163 164 /* 165 * The DMA unit has errata on (start + len) & 0x3fff == 0x2000. 166 * This constraint makes sure that the period size is not a power of two, 167 * which combined with dma_alloc_coherent aligning the buffer to the largest 168 * PoT <= size guarantees it won't be hit. 169 */ 170 171 if (is_power_of_2(c->min)) { 172 c->min += 2; 173 changed = 1; 174 } 175 if (is_power_of_2(c->max)) { 176 c->max -= 2; 177 changed = 1; 178 } 179 if (snd_interval_checkempty(c)) { 180 c->empty = 1; 181 return -EINVAL; 182 } 183 184 return changed; 185 } 186 187 static int n64audio_pcm_open(struct snd_pcm_substream *substream) 188 { 189 struct snd_pcm_runtime *runtime = substream->runtime; 190 int err; 191 192 runtime->hw = n64audio_pcm_hw; 193 err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS); 194 if (err < 0) 195 return err; 196 197 err = snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2); 198 if (err < 0) 199 return err; 200 201 err = snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 202 hw_rule_period_size, NULL, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, -1); 203 if (err < 0) 204 return err; 205 206 return 0; 207 } 208 209 static int n64audio_pcm_prepare(struct snd_pcm_substream *substream) 210 { 211 struct snd_pcm_runtime *runtime = substream->runtime; 212 struct n64audio *priv = substream->pcm->private_data; 213 u32 rate; 214 215 rate = ((2 * AI_NTSC_DACRATE / runtime->rate) + 1) / 2 - 1; 216 217 n64audio_write_reg(priv, AI_RATE_REG, rate); 218 219 rate /= 66; 220 if (rate > 16) 221 rate = 16; 222 n64audio_write_reg(priv, AI_BITCLOCK_REG, rate - 1); 223 224 spin_lock_irq(&priv->chan.lock); 225 226 /* Setup the pseudo-dma transfer pointers. */ 227 priv->chan.pos = 0; 228 priv->chan.nextpos = 0; 229 priv->chan.substream = substream; 230 priv->chan.writesize = snd_pcm_lib_period_bytes(substream); 231 priv->chan.bufsize = snd_pcm_lib_buffer_bytes(substream); 232 233 spin_unlock_irq(&priv->chan.lock); 234 return 0; 235 } 236 237 static int n64audio_pcm_trigger(struct snd_pcm_substream *substream, 238 int cmd) 239 { 240 struct n64audio *priv = substream->pcm->private_data; 241 242 switch (cmd) { 243 case SNDRV_PCM_TRIGGER_START: 244 n64audio_push(substream->pcm->private_data); 245 n64audio_write_reg(priv, AI_CONTROL_REG, 1); 246 n64mi_write_reg(priv, MI_MASK_REG, MI_MASK_SET_AI); 247 break; 248 case SNDRV_PCM_TRIGGER_STOP: 249 n64audio_write_reg(priv, AI_CONTROL_REG, 0); 250 n64mi_write_reg(priv, MI_MASK_REG, MI_MASK_CLR_AI); 251 break; 252 default: 253 return -EINVAL; 254 } 255 return 0; 256 } 257 258 static snd_pcm_uframes_t n64audio_pcm_pointer(struct snd_pcm_substream *substream) 259 { 260 struct n64audio *priv = substream->pcm->private_data; 261 262 return bytes_to_frames(substream->runtime, 263 priv->chan.pos); 264 } 265 266 static int n64audio_pcm_close(struct snd_pcm_substream *substream) 267 { 268 struct n64audio *priv = substream->pcm->private_data; 269 270 priv->chan.substream = NULL; 271 272 return 0; 273 } 274 275 static const struct snd_pcm_ops n64audio_pcm_ops = { 276 .open = n64audio_pcm_open, 277 .prepare = n64audio_pcm_prepare, 278 .trigger = n64audio_pcm_trigger, 279 .pointer = n64audio_pcm_pointer, 280 .close = n64audio_pcm_close, 281 }; 282 283 /* 284 * The target device is embedded and RAM-constrained. We save RAM 285 * by initializing in __init code that gets dropped late in boot. 286 * For the same reason there is no module or unloading support. 287 */ 288 static int __init n64audio_probe(struct platform_device *pdev) 289 { 290 struct snd_card *card; 291 struct snd_pcm *pcm; 292 struct n64audio *priv; 293 int err, irq; 294 295 err = snd_card_new(&pdev->dev, SNDRV_DEFAULT_IDX1, 296 SNDRV_DEFAULT_STR1, 297 THIS_MODULE, sizeof(*priv), &card); 298 if (err < 0) 299 return err; 300 301 priv = card->private_data; 302 303 spin_lock_init(&priv->chan.lock); 304 305 priv->card = card; 306 307 priv->ring_base = dma_alloc_coherent(card->dev, 32 * 1024, &priv->ring_base_dma, 308 GFP_DMA|GFP_KERNEL); 309 if (!priv->ring_base) { 310 err = -ENOMEM; 311 goto fail_card; 312 } 313 314 priv->mi_reg_base = devm_platform_ioremap_resource(pdev, 0); 315 if (IS_ERR(priv->mi_reg_base)) { 316 err = PTR_ERR(priv->mi_reg_base); 317 goto fail_dma_alloc; 318 } 319 320 priv->ai_reg_base = devm_platform_ioremap_resource(pdev, 1); 321 if (IS_ERR(priv->ai_reg_base)) { 322 err = PTR_ERR(priv->ai_reg_base); 323 goto fail_dma_alloc; 324 } 325 326 err = snd_pcm_new(card, "N64 Audio", 0, 1, 0, &pcm); 327 if (err < 0) 328 goto fail_dma_alloc; 329 330 pcm->private_data = priv; 331 strscpy(pcm->name, "N64 Audio"); 332 333 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &n64audio_pcm_ops); 334 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_VMALLOC, card->dev, 0, 0); 335 336 strscpy(card->driver, "N64 Audio"); 337 strscpy(card->shortname, "N64 Audio"); 338 strscpy(card->longname, "N64 Audio"); 339 340 irq = platform_get_irq(pdev, 0); 341 if (irq < 0) { 342 err = -EINVAL; 343 goto fail_dma_alloc; 344 } 345 if (devm_request_irq(&pdev->dev, irq, n64audio_isr, 346 IRQF_SHARED, "N64 Audio", priv)) { 347 err = -EBUSY; 348 goto fail_dma_alloc; 349 } 350 351 err = snd_card_register(card); 352 if (err < 0) 353 goto fail_dma_alloc; 354 355 return 0; 356 357 fail_dma_alloc: 358 dma_free_coherent(card->dev, 32 * 1024, priv->ring_base, priv->ring_base_dma); 359 360 fail_card: 361 snd_card_free(card); 362 return err; 363 } 364 365 static struct platform_driver n64audio_driver = { 366 .driver = { 367 .name = "n64audio", 368 }, 369 }; 370 371 static int __init n64audio_init(void) 372 { 373 return platform_driver_probe(&n64audio_driver, n64audio_probe); 374 } 375 376 module_init(n64audio_init); 377