1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * HD-audio stream operations 4 */ 5 6 #include <linux/kernel.h> 7 #include <linux/delay.h> 8 #include <linux/export.h> 9 #include <linux/clocksource.h> 10 #include <sound/compress_driver.h> 11 #include <sound/core.h> 12 #include <sound/pcm.h> 13 #include <sound/hdaudio.h> 14 #include <sound/hda_register.h> 15 #include "trace.h" 16 17 /* 18 * the hdac_stream library is intended to be used with the following 19 * transitions. The states are not formally defined in the code but loosely 20 * inspired by boolean variables. Note that the 'prepared' field is not used 21 * in this library but by the callers during the hw_params/prepare transitions 22 * 23 * | 24 * stream_init() | 25 * v 26 * +--+-------+ 27 * | unused | 28 * +--+----+--+ 29 * | ^ 30 * stream_assign() | | stream_release() 31 * v | 32 * +--+----+--+ 33 * | opened | 34 * +--+----+--+ 35 * | ^ 36 * stream_reset() | | 37 * stream_setup() | | stream_cleanup() 38 * v | 39 * +--+----+--+ 40 * | prepared | 41 * +--+----+--+ 42 * | ^ 43 * stream_start() | | stream_stop() 44 * v | 45 * +--+----+--+ 46 * | running | 47 * +----------+ 48 */ 49 50 /** 51 * snd_hdac_get_stream_stripe_ctl - get stripe control value 52 * @bus: HD-audio core bus 53 * @substream: PCM substream 54 */ 55 int snd_hdac_get_stream_stripe_ctl(struct hdac_bus *bus, 56 struct snd_pcm_substream *substream) 57 { 58 struct snd_pcm_runtime *runtime = substream->runtime; 59 unsigned int channels = runtime->channels, 60 rate = runtime->rate, 61 bits_per_sample = runtime->sample_bits, 62 max_sdo_lines, value, sdo_line; 63 64 /* T_AZA_GCAP_NSDO is 1:2 bitfields in GCAP */ 65 max_sdo_lines = snd_hdac_chip_readl(bus, GCAP) & AZX_GCAP_NSDO; 66 67 /* following is from HD audio spec */ 68 for (sdo_line = max_sdo_lines; sdo_line > 0; sdo_line >>= 1) { 69 if (rate > 48000) 70 value = (channels * bits_per_sample * 71 (rate / 48000)) / sdo_line; 72 else 73 value = (channels * bits_per_sample) / sdo_line; 74 75 if (value >= bus->sdo_limit) 76 break; 77 } 78 79 /* stripe value: 0 for 1SDO, 1 for 2SDO, 2 for 4SDO lines */ 80 return sdo_line >> 1; 81 } 82 EXPORT_SYMBOL_GPL(snd_hdac_get_stream_stripe_ctl); 83 84 /** 85 * snd_hdac_stream_init - initialize each stream (aka device) 86 * @bus: HD-audio core bus 87 * @azx_dev: HD-audio core stream object to initialize 88 * @idx: stream index number 89 * @direction: stream direction (SNDRV_PCM_STREAM_PLAYBACK or SNDRV_PCM_STREAM_CAPTURE) 90 * @tag: the tag id to assign 91 * 92 * Assign the starting bdl address to each stream (device) and initialize. 93 */ 94 void snd_hdac_stream_init(struct hdac_bus *bus, struct hdac_stream *azx_dev, 95 int idx, int direction, int tag) 96 { 97 azx_dev->bus = bus; 98 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */ 99 azx_dev->sd_addr = bus->remap_addr + (0x20 * idx + 0x80); 100 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */ 101 azx_dev->sd_int_sta_mask = 1 << idx; 102 azx_dev->index = idx; 103 azx_dev->direction = direction; 104 azx_dev->stream_tag = tag; 105 snd_hdac_dsp_lock_init(azx_dev); 106 list_add_tail(&azx_dev->list, &bus->stream_list); 107 108 if (bus->spbcap) { 109 azx_dev->spib_addr = bus->spbcap + AZX_SPB_BASE + 110 AZX_SPB_INTERVAL * idx + 111 AZX_SPB_SPIB; 112 113 azx_dev->fifo_addr = bus->spbcap + AZX_SPB_BASE + 114 AZX_SPB_INTERVAL * idx + 115 AZX_SPB_MAXFIFO; 116 } 117 118 if (bus->drsmcap) 119 azx_dev->dpibr_addr = bus->drsmcap + AZX_DRSM_BASE + 120 AZX_DRSM_INTERVAL * idx; 121 } 122 EXPORT_SYMBOL_GPL(snd_hdac_stream_init); 123 124 /** 125 * snd_hdac_stream_start - start a stream 126 * @azx_dev: HD-audio core stream to start 127 * 128 * Start a stream, set start_wallclk and set the running flag. 129 */ 130 void snd_hdac_stream_start(struct hdac_stream *azx_dev) 131 { 132 struct hdac_bus *bus = azx_dev->bus; 133 int stripe_ctl; 134 135 trace_snd_hdac_stream_start(bus, azx_dev); 136 137 azx_dev->start_wallclk = snd_hdac_chip_readl(bus, WALLCLK); 138 139 /* enable SIE */ 140 snd_hdac_chip_updatel(bus, INTCTL, 141 1 << azx_dev->index, 142 1 << azx_dev->index); 143 /* set stripe control */ 144 if (azx_dev->stripe) { 145 if (azx_dev->substream) 146 stripe_ctl = snd_hdac_get_stream_stripe_ctl(bus, azx_dev->substream); 147 else 148 stripe_ctl = 0; 149 snd_hdac_stream_updateb(azx_dev, SD_CTL_3B, SD_CTL_STRIPE_MASK, 150 stripe_ctl); 151 } 152 /* set DMA start and interrupt mask */ 153 if (bus->access_sdnctl_in_dword) 154 snd_hdac_stream_updatel(azx_dev, SD_CTL, 155 0, SD_CTL_DMA_START | SD_INT_MASK); 156 else 157 snd_hdac_stream_updateb(azx_dev, SD_CTL, 158 0, SD_CTL_DMA_START | SD_INT_MASK); 159 azx_dev->running = true; 160 } 161 EXPORT_SYMBOL_GPL(snd_hdac_stream_start); 162 163 /** 164 * snd_hdac_stream_clear - helper to clear stream registers and stop DMA transfers 165 * @azx_dev: HD-audio core stream to stop 166 */ 167 static void snd_hdac_stream_clear(struct hdac_stream *azx_dev) 168 { 169 snd_hdac_stream_updateb(azx_dev, SD_CTL, 170 SD_CTL_DMA_START | SD_INT_MASK, 0); 171 snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */ 172 if (azx_dev->stripe) 173 snd_hdac_stream_updateb(azx_dev, SD_CTL_3B, SD_CTL_STRIPE_MASK, 0); 174 azx_dev->running = false; 175 } 176 177 /** 178 * snd_hdac_stream_stop - stop a stream 179 * @azx_dev: HD-audio core stream to stop 180 * 181 * Stop a stream DMA and disable stream interrupt 182 */ 183 void snd_hdac_stream_stop(struct hdac_stream *azx_dev) 184 { 185 trace_snd_hdac_stream_stop(azx_dev->bus, azx_dev); 186 187 snd_hdac_stream_clear(azx_dev); 188 /* disable SIE */ 189 snd_hdac_chip_updatel(azx_dev->bus, INTCTL, 1 << azx_dev->index, 0); 190 } 191 EXPORT_SYMBOL_GPL(snd_hdac_stream_stop); 192 193 /** 194 * snd_hdac_stop_streams - stop all streams 195 * @bus: HD-audio core bus 196 */ 197 void snd_hdac_stop_streams(struct hdac_bus *bus) 198 { 199 struct hdac_stream *stream; 200 201 list_for_each_entry(stream, &bus->stream_list, list) 202 snd_hdac_stream_stop(stream); 203 } 204 EXPORT_SYMBOL_GPL(snd_hdac_stop_streams); 205 206 /** 207 * snd_hdac_stop_streams_and_chip - stop all streams and chip if running 208 * @bus: HD-audio core bus 209 */ 210 void snd_hdac_stop_streams_and_chip(struct hdac_bus *bus) 211 { 212 213 if (bus->chip_init) { 214 snd_hdac_stop_streams(bus); 215 snd_hdac_bus_stop_chip(bus); 216 } 217 } 218 EXPORT_SYMBOL_GPL(snd_hdac_stop_streams_and_chip); 219 220 /** 221 * snd_hdac_stream_reset - reset a stream 222 * @azx_dev: HD-audio core stream to reset 223 */ 224 void snd_hdac_stream_reset(struct hdac_stream *azx_dev) 225 { 226 unsigned char val; 227 int dma_run_state; 228 229 snd_hdac_stream_clear(azx_dev); 230 231 dma_run_state = snd_hdac_stream_readb(azx_dev, SD_CTL) & SD_CTL_DMA_START; 232 233 snd_hdac_stream_updateb(azx_dev, SD_CTL, 0, SD_CTL_STREAM_RESET); 234 235 /* wait for hardware to report that the stream entered reset */ 236 snd_hdac_stream_readb_poll(azx_dev, SD_CTL, val, (val & SD_CTL_STREAM_RESET), 3, 300); 237 238 if (azx_dev->bus->dma_stop_delay && dma_run_state) 239 udelay(azx_dev->bus->dma_stop_delay); 240 241 snd_hdac_stream_updateb(azx_dev, SD_CTL, SD_CTL_STREAM_RESET, 0); 242 243 /* wait for hardware to report that the stream is out of reset */ 244 snd_hdac_stream_readb_poll(azx_dev, SD_CTL, val, !(val & SD_CTL_STREAM_RESET), 3, 300); 245 246 /* reset first position - may not be synced with hw at this time */ 247 if (azx_dev->posbuf) 248 *azx_dev->posbuf = 0; 249 } 250 EXPORT_SYMBOL_GPL(snd_hdac_stream_reset); 251 252 /** 253 * snd_hdac_stream_setup - set up the SD for streaming 254 * @azx_dev: HD-audio core stream to set up 255 * @code_loading: Whether the stream is for PCM or code-loading. 256 */ 257 int snd_hdac_stream_setup(struct hdac_stream *azx_dev, bool code_loading) 258 { 259 struct hdac_bus *bus = azx_dev->bus; 260 struct snd_pcm_runtime *runtime; 261 unsigned int val; 262 u16 reg; 263 int ret; 264 265 if (azx_dev->substream) 266 runtime = azx_dev->substream->runtime; 267 else 268 runtime = NULL; 269 /* make sure the run bit is zero for SD */ 270 snd_hdac_stream_clear(azx_dev); 271 /* program the stream_tag */ 272 val = snd_hdac_stream_readl(azx_dev, SD_CTL); 273 val = (val & ~SD_CTL_STREAM_TAG_MASK) | 274 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT); 275 if (!bus->snoop) 276 val |= SD_CTL_TRAFFIC_PRIO; 277 snd_hdac_stream_writel(azx_dev, SD_CTL, val); 278 279 /* program the length of samples in cyclic buffer */ 280 snd_hdac_stream_writel(azx_dev, SD_CBL, azx_dev->bufsize); 281 282 /* program the stream format */ 283 /* this value needs to be the same as the one programmed */ 284 snd_hdac_stream_writew(azx_dev, SD_FORMAT, azx_dev->format_val); 285 286 /* program the stream LVI (last valid index) of the BDL */ 287 snd_hdac_stream_writew(azx_dev, SD_LVI, azx_dev->frags - 1); 288 289 /* program the BDL address */ 290 /* lower BDL address */ 291 snd_hdac_stream_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr); 292 /* upper BDL address */ 293 snd_hdac_stream_writel(azx_dev, SD_BDLPU, 294 upper_32_bits(azx_dev->bdl.addr)); 295 296 /* enable the position buffer */ 297 if (bus->use_posbuf && bus->posbuf.addr) { 298 if (!(snd_hdac_chip_readl(bus, DPLBASE) & AZX_DPLBASE_ENABLE)) 299 snd_hdac_chip_writel(bus, DPLBASE, 300 (u32)bus->posbuf.addr | AZX_DPLBASE_ENABLE); 301 } 302 303 /* set the interrupt enable bits in the descriptor control register */ 304 snd_hdac_stream_updatel(azx_dev, SD_CTL, 0, SD_INT_MASK); 305 306 if (!code_loading) { 307 /* Once SDxFMT is set, the controller programs SDxFIFOS to non-zero value. */ 308 ret = snd_hdac_stream_readw_poll(azx_dev, SD_FIFOSIZE, reg, 309 reg & AZX_SD_FIFOSIZE_MASK, 3, 300); 310 if (ret) 311 dev_dbg(bus->dev, "polling SD_FIFOSIZE 0x%04x failed: %d\n", 312 AZX_REG_SD_FIFOSIZE, ret); 313 azx_dev->fifo_size = reg; 314 } 315 316 /* when LPIB delay correction gives a small negative value, 317 * we ignore it; currently set the threshold statically to 318 * 64 frames 319 */ 320 if (runtime && runtime->period_size > 64) 321 azx_dev->delay_negative_threshold = 322 -frames_to_bytes(runtime, 64); 323 else 324 azx_dev->delay_negative_threshold = 0; 325 326 /* wallclk has 24Mhz clock source */ 327 if (runtime) 328 azx_dev->period_wallclk = (((runtime->period_size * 24000) / 329 runtime->rate) * 1000); 330 331 return 0; 332 } 333 EXPORT_SYMBOL_GPL(snd_hdac_stream_setup); 334 335 /** 336 * snd_hdac_stream_cleanup - cleanup a stream 337 * @azx_dev: HD-audio core stream to clean up 338 */ 339 void snd_hdac_stream_cleanup(struct hdac_stream *azx_dev) 340 { 341 snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0); 342 snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0); 343 snd_hdac_stream_writel(azx_dev, SD_CTL, 0); 344 azx_dev->bufsize = 0; 345 azx_dev->period_bytes = 0; 346 azx_dev->format_val = 0; 347 } 348 EXPORT_SYMBOL_GPL(snd_hdac_stream_cleanup); 349 350 /** 351 * snd_hdac_stream_assign - assign a stream for the PCM 352 * @bus: HD-audio core bus 353 * @substream: PCM substream to assign 354 * 355 * Look for an unused stream for the given PCM substream, assign it 356 * and return the stream object. If no stream is free, returns NULL. 357 * The function tries to keep using the same stream object when it's used 358 * beforehand. Also, when bus->reverse_assign flag is set, the last free 359 * or matching entry is returned. This is needed for some strange codecs. 360 */ 361 struct hdac_stream *snd_hdac_stream_assign(struct hdac_bus *bus, 362 struct snd_pcm_substream *substream) 363 { 364 struct hdac_stream *azx_dev; 365 struct hdac_stream *res = NULL; 366 367 /* make a non-zero unique key for the substream */ 368 int key = (substream->number << 2) | (substream->stream + 1); 369 370 if (substream->pcm) 371 key |= (substream->pcm->device << 16); 372 373 spin_lock_irq(&bus->reg_lock); 374 list_for_each_entry(azx_dev, &bus->stream_list, list) { 375 if (azx_dev->direction != substream->stream) 376 continue; 377 if (azx_dev->opened) 378 continue; 379 if (azx_dev->assigned_key == key) { 380 res = azx_dev; 381 break; 382 } 383 if (!res || bus->reverse_assign) 384 res = azx_dev; 385 } 386 if (res) { 387 res->opened = 1; 388 res->running = 0; 389 res->assigned_key = key; 390 res->substream = substream; 391 } 392 spin_unlock_irq(&bus->reg_lock); 393 return res; 394 } 395 EXPORT_SYMBOL_GPL(snd_hdac_stream_assign); 396 397 /** 398 * snd_hdac_stream_release_locked - release the assigned stream 399 * @azx_dev: HD-audio core stream to release 400 * 401 * Release the stream that has been assigned by snd_hdac_stream_assign(). 402 * The bus->reg_lock needs to be taken at a higher level 403 */ 404 void snd_hdac_stream_release_locked(struct hdac_stream *azx_dev) 405 { 406 azx_dev->opened = 0; 407 azx_dev->running = 0; 408 azx_dev->substream = NULL; 409 } 410 EXPORT_SYMBOL_GPL(snd_hdac_stream_release_locked); 411 412 /** 413 * snd_hdac_stream_release - release the assigned stream 414 * @azx_dev: HD-audio core stream to release 415 * 416 * Release the stream that has been assigned by snd_hdac_stream_assign(). 417 */ 418 void snd_hdac_stream_release(struct hdac_stream *azx_dev) 419 { 420 struct hdac_bus *bus = azx_dev->bus; 421 422 spin_lock_irq(&bus->reg_lock); 423 snd_hdac_stream_release_locked(azx_dev); 424 spin_unlock_irq(&bus->reg_lock); 425 } 426 EXPORT_SYMBOL_GPL(snd_hdac_stream_release); 427 428 /** 429 * snd_hdac_get_stream - return hdac_stream based on stream_tag and 430 * direction 431 * 432 * @bus: HD-audio core bus 433 * @dir: direction for the stream to be found 434 * @stream_tag: stream tag for stream to be found 435 */ 436 struct hdac_stream *snd_hdac_get_stream(struct hdac_bus *bus, 437 int dir, int stream_tag) 438 { 439 struct hdac_stream *s; 440 441 list_for_each_entry(s, &bus->stream_list, list) { 442 if (s->direction == dir && s->stream_tag == stream_tag) 443 return s; 444 } 445 446 return NULL; 447 } 448 EXPORT_SYMBOL_GPL(snd_hdac_get_stream); 449 450 /* 451 * set up a BDL entry 452 */ 453 static int setup_bdle(struct hdac_bus *bus, 454 struct snd_dma_buffer *dmab, 455 struct hdac_stream *azx_dev, __le32 **bdlp, 456 int ofs, int size, int with_ioc) 457 { 458 __le32 *bdl = *bdlp; 459 460 while (size > 0) { 461 dma_addr_t addr; 462 int chunk; 463 464 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES) 465 return -EINVAL; 466 467 addr = snd_sgbuf_get_addr(dmab, ofs); 468 /* program the address field of the BDL entry */ 469 bdl[0] = cpu_to_le32((u32)addr); 470 bdl[1] = cpu_to_le32(upper_32_bits(addr)); 471 /* program the size field of the BDL entry */ 472 chunk = snd_sgbuf_get_chunk_size(dmab, ofs, size); 473 /* one BDLE cannot cross 4K boundary on CTHDA chips */ 474 if (bus->align_bdle_4k) { 475 u32 remain = 0x1000 - (ofs & 0xfff); 476 477 if (chunk > remain) 478 chunk = remain; 479 } 480 bdl[2] = cpu_to_le32(chunk); 481 /* program the IOC to enable interrupt 482 * only when the whole fragment is processed 483 */ 484 size -= chunk; 485 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01); 486 bdl += 4; 487 azx_dev->frags++; 488 ofs += chunk; 489 } 490 *bdlp = bdl; 491 return ofs; 492 } 493 494 /** 495 * snd_hdac_stream_setup_bdle - set up BDL entries 496 * @azx_dev: HD-audio core stream to set up 497 * @dmab: allocated DMA buffer 498 * @runtime: substream runtime, optional 499 * 500 * Set up the buffer descriptor table of the given stream based on the 501 * period and buffer sizes of the assigned PCM substream. 502 */ 503 static int snd_hdac_stream_setup_bdle(struct hdac_stream *azx_dev, struct snd_dma_buffer *dmab, 504 struct snd_pcm_runtime *runtime) 505 { 506 struct hdac_bus *bus = azx_dev->bus; 507 int i, ofs, periods, period_bytes; 508 int pos_adj, pos_align; 509 __le32 *bdl; 510 511 /* reset BDL address */ 512 snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0); 513 snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0); 514 515 period_bytes = azx_dev->period_bytes; 516 periods = azx_dev->bufsize / period_bytes; 517 518 /* program the initial BDL entries */ 519 bdl = (__le32 *)azx_dev->bdl.area; 520 ofs = 0; 521 azx_dev->frags = 0; 522 523 pos_adj = bus->bdl_pos_adj; 524 if (runtime && !azx_dev->no_period_wakeup && pos_adj > 0) { 525 pos_align = pos_adj; 526 pos_adj = DIV_ROUND_UP(pos_adj * runtime->rate, 48000); 527 if (!pos_adj) 528 pos_adj = pos_align; 529 else 530 pos_adj = roundup(pos_adj, pos_align); 531 pos_adj = frames_to_bytes(runtime, pos_adj); 532 if (pos_adj >= period_bytes) { 533 dev_warn(bus->dev, "Too big adjustment %d\n", 534 pos_adj); 535 pos_adj = 0; 536 } else { 537 ofs = setup_bdle(bus, dmab, azx_dev, 538 &bdl, ofs, pos_adj, true); 539 if (ofs < 0) 540 goto error; 541 } 542 } else 543 pos_adj = 0; 544 545 for (i = 0; i < periods; i++) { 546 if (i == periods - 1 && pos_adj) 547 ofs = setup_bdle(bus, dmab, azx_dev, 548 &bdl, ofs, period_bytes - pos_adj, 0); 549 else 550 ofs = setup_bdle(bus, dmab, azx_dev, 551 &bdl, ofs, period_bytes, 552 !azx_dev->no_period_wakeup); 553 if (ofs < 0) 554 goto error; 555 } 556 return 0; 557 558 error: 559 dev_dbg(bus->dev, "Too many BDL entries: buffer=%d, period=%d\n", 560 azx_dev->bufsize, period_bytes); 561 return -EINVAL; 562 } 563 564 /** 565 * snd_hdac_stream_setup_periods - set up BDL entries 566 * @azx_dev: HD-audio core stream to set up 567 * 568 * Set up the buffer descriptor table of the given stream based on the 569 * period and buffer sizes of the assigned PCM substream. 570 */ 571 int snd_hdac_stream_setup_periods(struct hdac_stream *azx_dev) 572 { 573 struct snd_pcm_substream *substream = azx_dev->substream; 574 struct snd_compr_stream *cstream = azx_dev->cstream; 575 struct snd_pcm_runtime *runtime = NULL; 576 struct snd_dma_buffer *dmab; 577 578 if (substream) { 579 runtime = substream->runtime; 580 dmab = snd_pcm_get_dma_buf(substream); 581 } else if (cstream) { 582 dmab = snd_pcm_get_dma_buf(cstream); 583 } else { 584 WARN(1, "No substream or cstream assigned\n"); 585 return -EINVAL; 586 } 587 588 return snd_hdac_stream_setup_bdle(azx_dev, dmab, runtime); 589 } 590 EXPORT_SYMBOL_GPL(snd_hdac_stream_setup_periods); 591 592 /** 593 * snd_hdac_stream_set_params - set stream parameters 594 * @azx_dev: HD-audio core stream for which parameters are to be set 595 * @format_val: format value parameter 596 * 597 * Setup the HD-audio core stream parameters from substream of the stream 598 * and passed format value 599 */ 600 int snd_hdac_stream_set_params(struct hdac_stream *azx_dev, 601 unsigned int format_val) 602 { 603 struct snd_pcm_substream *substream = azx_dev->substream; 604 struct snd_compr_stream *cstream = azx_dev->cstream; 605 unsigned int bufsize, period_bytes; 606 unsigned int no_period_wakeup; 607 int err; 608 609 if (substream) { 610 bufsize = snd_pcm_lib_buffer_bytes(substream); 611 period_bytes = snd_pcm_lib_period_bytes(substream); 612 no_period_wakeup = substream->runtime->no_period_wakeup; 613 } else if (cstream) { 614 bufsize = cstream->runtime->buffer_size; 615 period_bytes = cstream->runtime->fragment_size; 616 no_period_wakeup = 0; 617 } else { 618 return -EINVAL; 619 } 620 621 if (bufsize != azx_dev->bufsize || 622 period_bytes != azx_dev->period_bytes || 623 format_val != azx_dev->format_val || 624 no_period_wakeup != azx_dev->no_period_wakeup) { 625 azx_dev->bufsize = bufsize; 626 azx_dev->period_bytes = period_bytes; 627 azx_dev->format_val = format_val; 628 azx_dev->no_period_wakeup = no_period_wakeup; 629 err = snd_hdac_stream_setup_periods(azx_dev); 630 if (err < 0) 631 return err; 632 } 633 return 0; 634 } 635 EXPORT_SYMBOL_GPL(snd_hdac_stream_set_params); 636 637 static u64 azx_cc_read(const struct cyclecounter *cc) 638 { 639 struct hdac_stream *azx_dev = container_of(cc, struct hdac_stream, cc); 640 641 return snd_hdac_chip_readl(azx_dev->bus, WALLCLK); 642 } 643 644 static void azx_timecounter_init(struct hdac_stream *azx_dev, 645 bool force, u64 last) 646 { 647 struct timecounter *tc = &azx_dev->tc; 648 struct cyclecounter *cc = &azx_dev->cc; 649 u64 nsec; 650 651 cc->read = azx_cc_read; 652 cc->mask = CLOCKSOURCE_MASK(32); 653 654 /* 655 * Calculate the optimal mult/shift values. The counter wraps 656 * around after ~178.9 seconds. 657 */ 658 clocks_calc_mult_shift(&cc->mult, &cc->shift, 24000000, 659 NSEC_PER_SEC, 178); 660 661 nsec = 0; /* audio time is elapsed time since trigger */ 662 timecounter_init(tc, cc, nsec); 663 if (force) { 664 /* 665 * force timecounter to use predefined value, 666 * used for synchronized starts 667 */ 668 tc->cycle_last = last; 669 } 670 } 671 672 /** 673 * snd_hdac_stream_timecounter_init - initialize time counter 674 * @azx_dev: HD-audio core stream (master stream) 675 * @streams: bit flags of streams to set up 676 * @start: true for PCM trigger start, false for other cases 677 * 678 * Initializes the time counter of streams marked by the bit flags (each 679 * bit corresponds to the stream index). 680 * The trigger timestamp of PCM substream assigned to the given stream is 681 * updated accordingly, too. 682 */ 683 void snd_hdac_stream_timecounter_init(struct hdac_stream *azx_dev, 684 unsigned int streams, bool start) 685 { 686 struct hdac_bus *bus = azx_dev->bus; 687 struct snd_pcm_runtime *runtime = azx_dev->substream->runtime; 688 struct hdac_stream *s; 689 bool inited = false; 690 u64 cycle_last = 0; 691 692 if (!start) 693 goto skip; 694 695 list_for_each_entry(s, &bus->stream_list, list) { 696 if ((streams & (1 << s->index))) { 697 azx_timecounter_init(s, inited, cycle_last); 698 if (!inited) { 699 inited = true; 700 cycle_last = s->tc.cycle_last; 701 } 702 } 703 } 704 705 skip: 706 snd_pcm_gettime(runtime, &runtime->trigger_tstamp); 707 runtime->trigger_tstamp_latched = true; 708 } 709 EXPORT_SYMBOL_GPL(snd_hdac_stream_timecounter_init); 710 711 /** 712 * snd_hdac_stream_sync_trigger - turn on/off stream sync register 713 * @azx_dev: HD-audio core stream (master stream) 714 * @set: true = set, false = clear 715 * @streams: bit flags of streams to sync 716 * @reg: the stream sync register address 717 */ 718 void snd_hdac_stream_sync_trigger(struct hdac_stream *azx_dev, bool set, 719 unsigned int streams, unsigned int reg) 720 { 721 struct hdac_bus *bus = azx_dev->bus; 722 unsigned int val; 723 724 if (!reg) 725 reg = AZX_REG_SSYNC; 726 val = _snd_hdac_chip_readl(bus, reg); 727 if (set) 728 val |= streams; 729 else 730 val &= ~streams; 731 _snd_hdac_chip_writel(bus, reg, val); 732 } 733 EXPORT_SYMBOL_GPL(snd_hdac_stream_sync_trigger); 734 735 /** 736 * snd_hdac_stream_sync - sync with start/stop trigger operation 737 * @azx_dev: HD-audio core stream (master stream) 738 * @start: true = start, false = stop 739 * @streams: bit flags of streams to sync 740 * 741 * For @start = true, wait until all FIFOs get ready. 742 * For @start = false, wait until all RUN bits are cleared. 743 */ 744 void snd_hdac_stream_sync(struct hdac_stream *azx_dev, bool start, 745 unsigned int streams) 746 { 747 struct hdac_bus *bus = azx_dev->bus; 748 int nwait, timeout; 749 struct hdac_stream *s; 750 751 for (timeout = 5000; timeout; timeout--) { 752 nwait = 0; 753 list_for_each_entry(s, &bus->stream_list, list) { 754 if (!(streams & (1 << s->index))) 755 continue; 756 757 if (start) { 758 /* check FIFO gets ready */ 759 if (!(snd_hdac_stream_readb(s, SD_STS) & 760 SD_STS_FIFO_READY)) 761 nwait++; 762 } else { 763 /* check RUN bit is cleared */ 764 if (snd_hdac_stream_readb(s, SD_CTL) & 765 SD_CTL_DMA_START) { 766 nwait++; 767 /* 768 * Perform stream reset if DMA RUN 769 * bit not cleared within given timeout 770 */ 771 if (timeout == 1) 772 snd_hdac_stream_reset(s); 773 } 774 } 775 } 776 if (!nwait) 777 break; 778 cpu_relax(); 779 } 780 } 781 EXPORT_SYMBOL_GPL(snd_hdac_stream_sync); 782 783 /** 784 * snd_hdac_stream_spbcap_enable - enable SPIB for a stream 785 * @bus: HD-audio core bus 786 * @enable: flag to enable/disable SPIB 787 * @index: stream index for which SPIB need to be enabled 788 */ 789 void snd_hdac_stream_spbcap_enable(struct hdac_bus *bus, 790 bool enable, int index) 791 { 792 u32 mask = 0; 793 794 if (!bus->spbcap) { 795 dev_err(bus->dev, "Address of SPB capability is NULL\n"); 796 return; 797 } 798 799 mask |= (1 << index); 800 801 if (enable) 802 snd_hdac_updatel(bus->spbcap, AZX_REG_SPB_SPBFCCTL, mask, mask); 803 else 804 snd_hdac_updatel(bus->spbcap, AZX_REG_SPB_SPBFCCTL, mask, 0); 805 } 806 EXPORT_SYMBOL_GPL(snd_hdac_stream_spbcap_enable); 807 808 /** 809 * snd_hdac_stream_set_spib - sets the spib value of a stream 810 * @bus: HD-audio core bus 811 * @azx_dev: hdac_stream 812 * @value: spib value to set 813 */ 814 int snd_hdac_stream_set_spib(struct hdac_bus *bus, 815 struct hdac_stream *azx_dev, u32 value) 816 { 817 if (!bus->spbcap) { 818 dev_err(bus->dev, "Address of SPB capability is NULL\n"); 819 return -EINVAL; 820 } 821 822 writel(value, azx_dev->spib_addr); 823 824 return 0; 825 } 826 EXPORT_SYMBOL_GPL(snd_hdac_stream_set_spib); 827 828 /** 829 * snd_hdac_stream_drsm_enable - enable DMA resume for a stream 830 * @bus: HD-audio core bus 831 * @enable: flag to enable/disable DRSM 832 * @index: stream index for which DRSM need to be enabled 833 */ 834 void snd_hdac_stream_drsm_enable(struct hdac_bus *bus, 835 bool enable, int index) 836 { 837 u32 mask = 0; 838 839 if (!bus->drsmcap) { 840 dev_err(bus->dev, "Address of DRSM capability is NULL\n"); 841 return; 842 } 843 844 mask |= (1 << index); 845 846 if (enable) 847 snd_hdac_updatel(bus->drsmcap, AZX_REG_DRSM_CTL, mask, mask); 848 else 849 snd_hdac_updatel(bus->drsmcap, AZX_REG_DRSM_CTL, mask, 0); 850 } 851 EXPORT_SYMBOL_GPL(snd_hdac_stream_drsm_enable); 852 853 /* 854 * snd_hdac_stream_wait_drsm - wait for HW to clear RSM for a stream 855 * @azx_dev: HD-audio core stream to await RSM for 856 * 857 * Returns 0 on success and -ETIMEDOUT upon a timeout. 858 */ 859 int snd_hdac_stream_wait_drsm(struct hdac_stream *azx_dev) 860 { 861 struct hdac_bus *bus = azx_dev->bus; 862 u32 mask, reg; 863 int ret; 864 865 mask = 1 << azx_dev->index; 866 867 ret = read_poll_timeout(snd_hdac_reg_readl, reg, !(reg & mask), 250, 2000, false, bus, 868 bus->drsmcap + AZX_REG_DRSM_CTL); 869 if (ret) 870 dev_dbg(bus->dev, "polling RSM 0x%08x failed: %d\n", mask, ret); 871 return ret; 872 } 873 EXPORT_SYMBOL_GPL(snd_hdac_stream_wait_drsm); 874 875 /** 876 * snd_hdac_stream_set_dpibr - sets the dpibr value of a stream 877 * @bus: HD-audio core bus 878 * @azx_dev: hdac_stream 879 * @value: dpib value to set 880 */ 881 int snd_hdac_stream_set_dpibr(struct hdac_bus *bus, 882 struct hdac_stream *azx_dev, u32 value) 883 { 884 if (!bus->drsmcap) { 885 dev_err(bus->dev, "Address of DRSM capability is NULL\n"); 886 return -EINVAL; 887 } 888 889 writel(value, azx_dev->dpibr_addr); 890 891 return 0; 892 } 893 EXPORT_SYMBOL_GPL(snd_hdac_stream_set_dpibr); 894 895 /** 896 * snd_hdac_stream_set_lpib - sets the lpib value of a stream 897 * @azx_dev: hdac_stream 898 * @value: lpib value to set 899 */ 900 int snd_hdac_stream_set_lpib(struct hdac_stream *azx_dev, u32 value) 901 { 902 snd_hdac_stream_writel(azx_dev, SD_LPIB, value); 903 904 return 0; 905 } 906 EXPORT_SYMBOL_GPL(snd_hdac_stream_set_lpib); 907 908 #ifdef CONFIG_SND_HDA_DSP_LOADER 909 /** 910 * snd_hdac_dsp_prepare - prepare for DSP loading 911 * @azx_dev: HD-audio core stream used for DSP loading 912 * @format: HD-audio stream format 913 * @byte_size: data chunk byte size 914 * @bufp: allocated buffer 915 * 916 * Allocate the buffer for the given size and set up the given stream for 917 * DSP loading. Returns the stream tag (>= 0), or a negative error code. 918 */ 919 int snd_hdac_dsp_prepare(struct hdac_stream *azx_dev, unsigned int format, 920 unsigned int byte_size, struct snd_dma_buffer *bufp) 921 { 922 struct hdac_bus *bus = azx_dev->bus; 923 int err; 924 925 snd_hdac_dsp_lock(azx_dev); 926 spin_lock_irq(&bus->reg_lock); 927 if (azx_dev->running || azx_dev->locked) { 928 spin_unlock_irq(&bus->reg_lock); 929 err = -EBUSY; 930 goto unlock; 931 } 932 azx_dev->locked = true; 933 spin_unlock_irq(&bus->reg_lock); 934 935 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV_SG, bus->dev, 936 byte_size, bufp); 937 if (err < 0) 938 goto err_alloc; 939 940 azx_dev->substream = NULL; 941 azx_dev->bufsize = byte_size; 942 /* It is recommended to transfer the firmware in two or more chunks. */ 943 azx_dev->period_bytes = byte_size / 2; 944 azx_dev->format_val = format; 945 azx_dev->no_period_wakeup = 1; 946 947 snd_hdac_stream_reset(azx_dev); 948 949 err = snd_hdac_stream_setup_bdle(azx_dev, bufp, NULL); 950 if (err < 0) 951 goto error; 952 953 snd_hdac_stream_setup(azx_dev, true); 954 snd_hdac_dsp_unlock(azx_dev); 955 return azx_dev->stream_tag; 956 957 error: 958 snd_dma_free_pages(bufp); 959 err_alloc: 960 spin_lock_irq(&bus->reg_lock); 961 azx_dev->locked = false; 962 spin_unlock_irq(&bus->reg_lock); 963 unlock: 964 snd_hdac_dsp_unlock(azx_dev); 965 return err; 966 } 967 EXPORT_SYMBOL_GPL(snd_hdac_dsp_prepare); 968 969 /** 970 * snd_hdac_dsp_trigger - start / stop DSP loading 971 * @azx_dev: HD-audio core stream used for DSP loading 972 * @start: trigger start or stop 973 */ 974 void snd_hdac_dsp_trigger(struct hdac_stream *azx_dev, bool start) 975 { 976 if (start) 977 snd_hdac_stream_start(azx_dev); 978 else 979 snd_hdac_stream_stop(azx_dev); 980 } 981 EXPORT_SYMBOL_GPL(snd_hdac_dsp_trigger); 982 983 /** 984 * snd_hdac_dsp_cleanup - clean up the stream from DSP loading to normal 985 * @azx_dev: HD-audio core stream used for DSP loading 986 * @dmab: buffer used by DSP loading 987 */ 988 void snd_hdac_dsp_cleanup(struct hdac_stream *azx_dev, 989 struct snd_dma_buffer *dmab) 990 { 991 struct hdac_bus *bus = azx_dev->bus; 992 993 if (!dmab->area || !azx_dev->locked) 994 return; 995 996 snd_hdac_dsp_lock(azx_dev); 997 /* reset BDL address */ 998 snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0); 999 snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0); 1000 snd_hdac_stream_writel(azx_dev, SD_CTL, 0); 1001 azx_dev->bufsize = 0; 1002 azx_dev->period_bytes = 0; 1003 azx_dev->format_val = 0; 1004 1005 snd_dma_free_pages(dmab); 1006 dmab->area = NULL; 1007 1008 spin_lock_irq(&bus->reg_lock); 1009 azx_dev->locked = false; 1010 spin_unlock_irq(&bus->reg_lock); 1011 snd_hdac_dsp_unlock(azx_dev); 1012 } 1013 EXPORT_SYMBOL_GPL(snd_hdac_dsp_cleanup); 1014 #endif /* CONFIG_SND_HDA_DSP_LOADER */ 1015