1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Universal Flash Storage Host controller driver 4 * Copyright (C) 2011-2013 Samsung India Software Operations 5 * 6 * Authors: 7 * Santosh Yaraganavi <santosh.sy@samsung.com> 8 * Vinayak Holikatti <h.vinayak@samsung.com> 9 */ 10 11 #ifndef _UFSHCI_H 12 #define _UFSHCI_H 13 14 #include <linux/types.h> 15 #include <ufs/ufs.h> 16 17 enum { 18 TASK_REQ_UPIU_SIZE_DWORDS = 8, 19 TASK_RSP_UPIU_SIZE_DWORDS = 8, 20 ALIGNED_UPIU_SIZE = 512, 21 }; 22 23 /* UFSHCI Registers */ 24 enum { 25 REG_CONTROLLER_CAPABILITIES = 0x00, 26 REG_MCQCAP = 0x04, 27 REG_UFS_VERSION = 0x08, 28 REG_EXT_CONTROLLER_CAPABILITIES = 0x0C, 29 REG_CONTROLLER_PID = 0x10, 30 REG_CONTROLLER_MID = 0x14, 31 REG_AUTO_HIBERNATE_IDLE_TIMER = 0x18, 32 REG_INTERRUPT_STATUS = 0x20, 33 REG_INTERRUPT_ENABLE = 0x24, 34 REG_CONTROLLER_STATUS = 0x30, 35 REG_CONTROLLER_ENABLE = 0x34, 36 REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER = 0x38, 37 REG_UIC_ERROR_CODE_DATA_LINK_LAYER = 0x3C, 38 REG_UIC_ERROR_CODE_NETWORK_LAYER = 0x40, 39 REG_UIC_ERROR_CODE_TRANSPORT_LAYER = 0x44, 40 REG_UIC_ERROR_CODE_DME = 0x48, 41 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL = 0x4C, 42 REG_UTP_TRANSFER_REQ_LIST_BASE_L = 0x50, 43 REG_UTP_TRANSFER_REQ_LIST_BASE_H = 0x54, 44 REG_UTP_TRANSFER_REQ_DOOR_BELL = 0x58, 45 REG_UTP_TRANSFER_REQ_LIST_CLEAR = 0x5C, 46 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP = 0x60, 47 REG_UTP_TASK_REQ_LIST_BASE_L = 0x70, 48 REG_UTP_TASK_REQ_LIST_BASE_H = 0x74, 49 REG_UTP_TASK_REQ_DOOR_BELL = 0x78, 50 REG_UTP_TASK_REQ_LIST_CLEAR = 0x7C, 51 REG_UTP_TASK_REQ_LIST_RUN_STOP = 0x80, 52 REG_UIC_COMMAND = 0x90, 53 REG_UIC_COMMAND_ARG_1 = 0x94, 54 REG_UIC_COMMAND_ARG_2 = 0x98, 55 REG_UIC_COMMAND_ARG_3 = 0x9C, 56 57 UFSHCI_REG_SPACE_SIZE = 0xA0, 58 59 REG_UFS_CCAP = 0x100, 60 REG_UFS_CRYPTOCAP = 0x104, 61 62 REG_UFS_MEM_CFG = 0x300, 63 REG_UFS_MCQ_CFG = 0x380, 64 REG_UFS_ESILBA = 0x384, 65 REG_UFS_ESIUBA = 0x388, 66 UFSHCI_CRYPTO_REG_SPACE_SIZE = 0x400, 67 }; 68 69 /* Controller capability masks */ 70 enum { 71 MASK_TRANSFER_REQUESTS_SLOTS_SDB = 0x0000001F, 72 MASK_TRANSFER_REQUESTS_SLOTS_MCQ = 0x000000FF, 73 MASK_NUMBER_OUTSTANDING_RTT = 0x0000FF00, 74 MASK_TASK_MANAGEMENT_REQUEST_SLOTS = 0x00070000, 75 MASK_EHSLUTRD_SUPPORTED = 0x00400000, 76 MASK_AUTO_HIBERN8_SUPPORT = 0x00800000, 77 MASK_64_ADDRESSING_SUPPORT = 0x01000000, 78 MASK_OUT_OF_ORDER_DATA_DELIVERY_SUPPORT = 0x02000000, 79 MASK_UIC_DME_TEST_MODE_SUPPORT = 0x04000000, 80 MASK_CRYPTO_SUPPORT = 0x10000000, 81 MASK_LSDB_SUPPORT = 0x20000000, 82 MASK_MCQ_SUPPORT = 0x40000000, 83 }; 84 85 enum { 86 REG_SQATTR = 0x0, 87 REG_SQLBA = 0x4, 88 REG_SQUBA = 0x8, 89 REG_SQDAO = 0xC, 90 REG_SQISAO = 0x10, 91 92 REG_CQATTR = 0x20, 93 REG_CQLBA = 0x24, 94 REG_CQUBA = 0x28, 95 REG_CQDAO = 0x2C, 96 REG_CQISAO = 0x30, 97 }; 98 99 enum { 100 REG_SQHP = 0x0, 101 REG_SQTP = 0x4, 102 REG_SQRTC = 0x8, 103 REG_SQCTI = 0xC, 104 REG_SQRTS = 0x10, 105 }; 106 107 enum { 108 REG_CQHP = 0x0, 109 REG_CQTP = 0x4, 110 }; 111 112 enum { 113 REG_CQIS = 0x0, 114 REG_CQIE = 0x4, 115 }; 116 117 enum { 118 SQ_START = 0x0, 119 SQ_STOP = 0x1, 120 SQ_ICU = 0x2, 121 }; 122 123 enum { 124 SQ_STS = 0x1, 125 SQ_CUS = 0x2, 126 }; 127 128 #define SQ_ICU_ERR_CODE_MASK GENMASK(7, 4) 129 #define UFS_MASK(mask, offset) ((mask) << (offset)) 130 131 /* UFS Version 08h */ 132 #define MINOR_VERSION_NUM_MASK UFS_MASK(0xFFFF, 0) 133 #define MAJOR_VERSION_NUM_MASK UFS_MASK(0xFFFF, 16) 134 135 #define UFSHCD_NUM_RESERVED 1 136 /* 137 * Controller UFSHCI version 138 * - 2.x and newer use the following scheme: 139 * major << 8 + minor << 4 140 * - 1.x has been converted to match this in 141 * ufshcd_get_ufs_version() 142 */ 143 static inline u32 ufshci_version(u32 major, u32 minor) 144 { 145 return (major << 8) + (minor << 4); 146 } 147 148 /* 149 * HCDDID - Host Controller Identification Descriptor 150 * - Device ID and Device Class 10h 151 */ 152 #define DEVICE_CLASS UFS_MASK(0xFFFF, 0) 153 #define DEVICE_ID UFS_MASK(0xFF, 24) 154 155 /* 156 * HCPMID - Host Controller Identification Descriptor 157 * - Product/Manufacturer ID 14h 158 */ 159 #define MANUFACTURE_ID_MASK UFS_MASK(0xFFFF, 0) 160 #define PRODUCT_ID_MASK UFS_MASK(0xFFFF, 16) 161 162 /* AHIT - Auto-Hibernate Idle Timer */ 163 #define UFSHCI_AHIBERN8_TIMER_MASK GENMASK(9, 0) 164 #define UFSHCI_AHIBERN8_SCALE_MASK GENMASK(12, 10) 165 #define UFSHCI_AHIBERN8_SCALE_FACTOR 10 166 #define UFSHCI_AHIBERN8_MAX (1023 * 100000) 167 168 /* 169 * IS - Interrupt Status - 20h 170 */ 171 #define UTP_TRANSFER_REQ_COMPL 0x1 172 #define UIC_DME_END_PT_RESET 0x2 173 #define UIC_ERROR 0x4 174 #define UIC_TEST_MODE 0x8 175 #define UIC_POWER_MODE 0x10 176 #define UIC_HIBERNATE_EXIT 0x20 177 #define UIC_HIBERNATE_ENTER 0x40 178 #define UIC_LINK_LOST 0x80 179 #define UIC_LINK_STARTUP 0x100 180 #define UTP_TASK_REQ_COMPL 0x200 181 #define UIC_COMMAND_COMPL 0x400 182 #define DEVICE_FATAL_ERROR 0x800 183 #define CONTROLLER_FATAL_ERROR 0x10000 184 #define SYSTEM_BUS_FATAL_ERROR 0x20000 185 #define CRYPTO_ENGINE_FATAL_ERROR 0x40000 186 #define MCQ_CQ_EVENT_STATUS 0x100000 187 188 #define UFSHCD_UIC_HIBERN8_MASK (UIC_HIBERNATE_ENTER |\ 189 UIC_HIBERNATE_EXIT) 190 191 #define UFSHCD_UIC_PWR_MASK (UFSHCD_UIC_HIBERN8_MASK |\ 192 UIC_POWER_MODE) 193 194 #define UFSHCD_UIC_MASK (UIC_COMMAND_COMPL | UFSHCD_UIC_PWR_MASK) 195 196 #define UFSHCD_ERROR_MASK (UIC_ERROR | INT_FATAL_ERRORS) 197 198 #define INT_FATAL_ERRORS (DEVICE_FATAL_ERROR |\ 199 CONTROLLER_FATAL_ERROR |\ 200 SYSTEM_BUS_FATAL_ERROR |\ 201 CRYPTO_ENGINE_FATAL_ERROR |\ 202 UIC_LINK_LOST) 203 204 /* HCS - Host Controller Status 30h */ 205 #define DEVICE_PRESENT 0x1 206 #define UTP_TRANSFER_REQ_LIST_READY 0x2 207 #define UTP_TASK_REQ_LIST_READY 0x4 208 #define UIC_COMMAND_READY 0x8 209 #define HOST_ERROR_INDICATOR 0x10 210 #define DEVICE_ERROR_INDICATOR 0x20 211 #define UIC_POWER_MODE_CHANGE_REQ_STATUS_MASK UFS_MASK(0x7, 8) 212 213 #define UFSHCD_STATUS_READY (UTP_TRANSFER_REQ_LIST_READY |\ 214 UTP_TASK_REQ_LIST_READY |\ 215 UIC_COMMAND_READY) 216 217 enum { 218 PWR_OK = 0x0, 219 PWR_LOCAL = 0x01, 220 PWR_REMOTE = 0x02, 221 PWR_BUSY = 0x03, 222 PWR_ERROR_CAP = 0x04, 223 PWR_FATAL_ERROR = 0x05, 224 }; 225 226 /* HCE - Host Controller Enable 34h */ 227 #define CONTROLLER_ENABLE 0x1 228 #define CONTROLLER_DISABLE 0x0 229 #define CRYPTO_GENERAL_ENABLE 0x2 230 231 /* UECPA - Host UIC Error Code PHY Adapter Layer 38h */ 232 #define UIC_PHY_ADAPTER_LAYER_ERROR 0x80000000 233 #define UIC_PHY_ADAPTER_LAYER_ERROR_CODE_MASK 0x1F 234 #define UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK 0xF 235 #define UIC_PHY_ADAPTER_LAYER_GENERIC_ERROR 0x10 236 237 /* UECDL - Host UIC Error Code Data Link Layer 3Ch */ 238 #define UIC_DATA_LINK_LAYER_ERROR 0x80000000 239 #define UIC_DATA_LINK_LAYER_ERROR_CODE_MASK 0xFFFF 240 #define UIC_DATA_LINK_LAYER_ERROR_TCX_REP_TIMER_EXP 0x2 241 #define UIC_DATA_LINK_LAYER_ERROR_AFCX_REQ_TIMER_EXP 0x4 242 #define UIC_DATA_LINK_LAYER_ERROR_FCX_PRO_TIMER_EXP 0x8 243 #define UIC_DATA_LINK_LAYER_ERROR_RX_BUF_OF 0x20 244 #define UIC_DATA_LINK_LAYER_ERROR_PA_INIT 0x2000 245 #define UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED 0x0001 246 #define UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT 0x0002 247 248 /* UECN - Host UIC Error Code Network Layer 40h */ 249 #define UIC_NETWORK_LAYER_ERROR 0x80000000 250 #define UIC_NETWORK_LAYER_ERROR_CODE_MASK 0x7 251 #define UIC_NETWORK_UNSUPPORTED_HEADER_TYPE 0x1 252 #define UIC_NETWORK_BAD_DEVICEID_ENC 0x2 253 #define UIC_NETWORK_LHDR_TRAP_PACKET_DROPPING 0x4 254 255 /* UECT - Host UIC Error Code Transport Layer 44h */ 256 #define UIC_TRANSPORT_LAYER_ERROR 0x80000000 257 #define UIC_TRANSPORT_LAYER_ERROR_CODE_MASK 0x7F 258 #define UIC_TRANSPORT_UNSUPPORTED_HEADER_TYPE 0x1 259 #define UIC_TRANSPORT_UNKNOWN_CPORTID 0x2 260 #define UIC_TRANSPORT_NO_CONNECTION_RX 0x4 261 #define UIC_TRANSPORT_CONTROLLED_SEGMENT_DROPPING 0x8 262 #define UIC_TRANSPORT_BAD_TC 0x10 263 #define UIC_TRANSPORT_E2E_CREDIT_OVERFOW 0x20 264 #define UIC_TRANSPORT_SAFETY_VALUE_DROPPING 0x40 265 266 /* UECDME - Host UIC Error Code DME 48h */ 267 #define UIC_DME_ERROR 0x80000000 268 #define UIC_DME_ERROR_CODE_MASK 0x1 269 270 /* UTRIACR - Interrupt Aggregation control register - 0x4Ch */ 271 #define INT_AGGR_TIMEOUT_VAL_MASK 0xFF 272 #define INT_AGGR_COUNTER_THRESHOLD_MASK UFS_MASK(0x1F, 8) 273 #define INT_AGGR_COUNTER_AND_TIMER_RESET 0x10000 274 #define INT_AGGR_STATUS_BIT 0x100000 275 #define INT_AGGR_PARAM_WRITE 0x1000000 276 #define INT_AGGR_ENABLE 0x80000000 277 278 /* UTRLRSR - UTP Transfer Request Run-Stop Register 60h */ 279 #define UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT 0x1 280 281 /* UTMRLRSR - UTP Task Management Request Run-Stop Register 80h */ 282 #define UTP_TASK_REQ_LIST_RUN_STOP_BIT 0x1 283 284 /* REG_UFS_MEM_CFG - Global Config Registers 300h */ 285 #define MCQ_MODE_SELECT BIT(0) 286 287 /* CQISy - CQ y Interrupt Status Register */ 288 #define UFSHCD_MCQ_CQIS_TAIL_ENT_PUSH_STS 0x1 289 290 /* UICCMD - UIC Command */ 291 #define COMMAND_OPCODE_MASK 0xFF 292 #define GEN_SELECTOR_INDEX_MASK 0xFFFF 293 294 #define MIB_ATTRIBUTE_MASK UFS_MASK(0xFFFF, 16) 295 #define RESET_LEVEL 0xFF 296 297 #define ATTR_SET_TYPE_MASK UFS_MASK(0xFF, 16) 298 #define CONFIG_RESULT_CODE_MASK 0xFF 299 #define GENERIC_ERROR_CODE_MASK 0xFF 300 301 /* GenSelectorIndex calculation macros for M-PHY attributes */ 302 #define UIC_ARG_MPHY_TX_GEN_SEL_INDEX(lane) (lane) 303 #define UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane) (PA_MAXDATALANES + (lane)) 304 305 #define UIC_ARG_MIB_SEL(attr, sel) ((((attr) & 0xFFFF) << 16) |\ 306 ((sel) & 0xFFFF)) 307 #define UIC_ARG_MIB(attr) UIC_ARG_MIB_SEL(attr, 0) 308 #define UIC_ARG_ATTR_TYPE(t) (((t) & 0xFF) << 16) 309 #define UIC_GET_ATTR_ID(v) (((v) >> 16) & 0xFFFF) 310 311 /* Link Status*/ 312 enum link_status { 313 UFSHCD_LINK_IS_DOWN = 1, 314 UFSHCD_LINK_IS_UP = 2, 315 }; 316 317 /* UIC Commands */ 318 enum uic_cmd_dme { 319 UIC_CMD_DME_GET = 0x01, 320 UIC_CMD_DME_SET = 0x02, 321 UIC_CMD_DME_PEER_GET = 0x03, 322 UIC_CMD_DME_PEER_SET = 0x04, 323 UIC_CMD_DME_POWERON = 0x10, 324 UIC_CMD_DME_POWEROFF = 0x11, 325 UIC_CMD_DME_ENABLE = 0x12, 326 UIC_CMD_DME_RESET = 0x14, 327 UIC_CMD_DME_END_PT_RST = 0x15, 328 UIC_CMD_DME_LINK_STARTUP = 0x16, 329 UIC_CMD_DME_HIBER_ENTER = 0x17, 330 UIC_CMD_DME_HIBER_EXIT = 0x18, 331 UIC_CMD_DME_TEST_MODE = 0x1A, 332 }; 333 334 /* UIC Config result code / Generic error code */ 335 enum { 336 UIC_CMD_RESULT_SUCCESS = 0x00, 337 UIC_CMD_RESULT_INVALID_ATTR = 0x01, 338 UIC_CMD_RESULT_FAILURE = 0x01, 339 UIC_CMD_RESULT_INVALID_ATTR_VALUE = 0x02, 340 UIC_CMD_RESULT_READ_ONLY_ATTR = 0x03, 341 UIC_CMD_RESULT_WRITE_ONLY_ATTR = 0x04, 342 UIC_CMD_RESULT_BAD_INDEX = 0x05, 343 UIC_CMD_RESULT_LOCKED_ATTR = 0x06, 344 UIC_CMD_RESULT_BAD_TEST_FEATURE_INDEX = 0x07, 345 UIC_CMD_RESULT_PEER_COMM_FAILURE = 0x08, 346 UIC_CMD_RESULT_BUSY = 0x09, 347 UIC_CMD_RESULT_DME_FAILURE = 0x0A, 348 }; 349 350 #define MASK_UIC_COMMAND_RESULT 0xFF 351 352 #define INT_AGGR_COUNTER_THLD_VAL(c) (((c) & 0x1F) << 8) 353 #define INT_AGGR_TIMEOUT_VAL(t) (((t) & 0xFF) << 0) 354 355 /* Interrupt disable masks */ 356 enum { 357 /* Interrupt disable mask for UFSHCI v1.1 */ 358 INTERRUPT_MASK_ALL_VER_11 = 0x31FFF, 359 360 /* Interrupt disable mask for UFSHCI v2.1 */ 361 INTERRUPT_MASK_ALL_VER_21 = 0x71FFF, 362 }; 363 364 /* CCAP - Crypto Capability 100h */ 365 union ufs_crypto_capabilities { 366 __le32 reg_val; 367 struct { 368 u8 num_crypto_cap; 369 u8 config_count; 370 u8 reserved; 371 u8 config_array_ptr; 372 }; 373 }; 374 375 enum ufs_crypto_key_size { 376 UFS_CRYPTO_KEY_SIZE_INVALID = 0x0, 377 UFS_CRYPTO_KEY_SIZE_128 = 0x1, 378 UFS_CRYPTO_KEY_SIZE_192 = 0x2, 379 UFS_CRYPTO_KEY_SIZE_256 = 0x3, 380 UFS_CRYPTO_KEY_SIZE_512 = 0x4, 381 }; 382 383 enum ufs_crypto_alg { 384 UFS_CRYPTO_ALG_AES_XTS = 0x0, 385 UFS_CRYPTO_ALG_BITLOCKER_AES_CBC = 0x1, 386 UFS_CRYPTO_ALG_AES_ECB = 0x2, 387 UFS_CRYPTO_ALG_ESSIV_AES_CBC = 0x3, 388 }; 389 390 /* x-CRYPTOCAP - Crypto Capability X */ 391 union ufs_crypto_cap_entry { 392 __le32 reg_val; 393 struct { 394 u8 algorithm_id; 395 u8 sdus_mask; /* Supported data unit size mask */ 396 u8 key_size; 397 u8 reserved; 398 }; 399 }; 400 401 #define UFS_CRYPTO_CONFIGURATION_ENABLE (1 << 7) 402 #define UFS_CRYPTO_KEY_MAX_SIZE 64 403 /* x-CRYPTOCFG - Crypto Configuration X */ 404 union ufs_crypto_cfg_entry { 405 __le32 reg_val[32]; 406 struct { 407 u8 crypto_key[UFS_CRYPTO_KEY_MAX_SIZE]; 408 u8 data_unit_size; 409 u8 crypto_cap_idx; 410 u8 reserved_1; 411 u8 config_enable; 412 u8 reserved_multi_host; 413 u8 reserved_2; 414 u8 vsb[2]; 415 u8 reserved_3[56]; 416 }; 417 }; 418 419 /* 420 * Request Descriptor Definitions 421 */ 422 423 /* To accommodate UFS2.0 required Command type */ 424 enum { 425 UTP_CMD_TYPE_UFS_STORAGE = 0x1, 426 }; 427 428 enum { 429 UTP_SCSI_COMMAND = 0x00000000, 430 UTP_NATIVE_UFS_COMMAND = 0x10000000, 431 UTP_DEVICE_MANAGEMENT_FUNCTION = 0x20000000, 432 }; 433 434 /* UTP Transfer Request Data Direction (DD) */ 435 enum utp_data_direction { 436 UTP_NO_DATA_TRANSFER = 0, 437 UTP_HOST_TO_DEVICE = 1, 438 UTP_DEVICE_TO_HOST = 2, 439 }; 440 441 /* Overall command status values */ 442 enum utp_ocs { 443 OCS_SUCCESS = 0x0, 444 OCS_INVALID_CMD_TABLE_ATTR = 0x1, 445 OCS_INVALID_PRDT_ATTR = 0x2, 446 OCS_MISMATCH_DATA_BUF_SIZE = 0x3, 447 OCS_MISMATCH_RESP_UPIU_SIZE = 0x4, 448 OCS_PEER_COMM_FAILURE = 0x5, 449 OCS_ABORTED = 0x6, 450 OCS_FATAL_ERROR = 0x7, 451 OCS_DEVICE_FATAL_ERROR = 0x8, 452 OCS_INVALID_CRYPTO_CONFIG = 0x9, 453 OCS_GENERAL_CRYPTO_ERROR = 0xA, 454 OCS_INVALID_COMMAND_STATUS = 0x0F, 455 }; 456 457 enum { 458 MASK_OCS = 0x0F, 459 }; 460 461 /* The maximum length of the data byte count field in the PRDT is 256KB */ 462 #define PRDT_DATA_BYTE_COUNT_MAX SZ_256K 463 /* The granularity of the data byte count field in the PRDT is 32-bit */ 464 #define PRDT_DATA_BYTE_COUNT_PAD 4 465 466 /** 467 * struct ufshcd_sg_entry - UFSHCI PRD Entry 468 * @addr: Physical address; DW-0 and DW-1. 469 * @reserved: Reserved for future use DW-2 470 * @size: size of physical segment DW-3 471 */ 472 struct ufshcd_sg_entry { 473 __le64 addr; 474 __le32 reserved; 475 __le32 size; 476 /* 477 * followed by variant-specific fields if 478 * CONFIG_SCSI_UFS_VARIABLE_SG_ENTRY_SIZE has been defined. 479 */ 480 }; 481 482 /** 483 * struct utp_transfer_cmd_desc - UTP Command Descriptor (UCD) 484 * @command_upiu: Command UPIU Frame address 485 * @response_upiu: Response UPIU Frame address 486 * @prd_table: Physical Region Descriptor: an array of SG_ALL struct 487 * ufshcd_sg_entry's. Variant-specific fields may be present after each. 488 */ 489 struct utp_transfer_cmd_desc { 490 u8 command_upiu[ALIGNED_UPIU_SIZE]; 491 u8 response_upiu[ALIGNED_UPIU_SIZE]; 492 u8 prd_table[]; 493 }; 494 495 /** 496 * struct request_desc_header - Descriptor Header common to both UTRD and UTMRD 497 */ 498 struct request_desc_header { 499 u8 cci; 500 u8 ehs_length; 501 #if defined(__BIG_ENDIAN) 502 u8 enable_crypto:1; 503 u8 reserved2:7; 504 505 u8 command_type:4; 506 u8 reserved1:1; 507 u8 data_direction:2; 508 u8 interrupt:1; 509 #elif defined(__LITTLE_ENDIAN) 510 u8 reserved2:7; 511 u8 enable_crypto:1; 512 513 u8 interrupt:1; 514 u8 data_direction:2; 515 u8 reserved1:1; 516 u8 command_type:4; 517 #else 518 #error 519 #endif 520 521 __le32 dunl; 522 u8 ocs; 523 u8 cds; 524 __le16 ldbc; 525 __le32 dunu; 526 }; 527 528 static_assert(sizeof(struct request_desc_header) == 16); 529 530 /** 531 * struct utp_transfer_req_desc - UTP Transfer Request Descriptor (UTRD) 532 * @header: UTRD header DW-0 to DW-3 533 * @command_desc_base_addr: UCD base address DW 4-5 534 * @response_upiu_length: response UPIU length DW-6 535 * @response_upiu_offset: response UPIU offset DW-6 536 * @prd_table_length: Physical region descriptor length DW-7 537 * @prd_table_offset: Physical region descriptor offset DW-7 538 */ 539 struct utp_transfer_req_desc { 540 541 /* DW 0-3 */ 542 struct request_desc_header header; 543 544 /* DW 4-5*/ 545 __le64 command_desc_base_addr; 546 547 /* DW 6 */ 548 __le16 response_upiu_length; 549 __le16 response_upiu_offset; 550 551 /* DW 7 */ 552 __le16 prd_table_length; 553 __le16 prd_table_offset; 554 }; 555 556 /* MCQ Completion Queue Entry */ 557 struct cq_entry { 558 /* DW 0-1 */ 559 __le64 command_desc_base_addr; 560 561 /* DW 2 */ 562 __le16 response_upiu_length; 563 __le16 response_upiu_offset; 564 565 /* DW 3 */ 566 __le16 prd_table_length; 567 __le16 prd_table_offset; 568 569 /* DW 4 */ 570 __le32 status; 571 572 /* DW 5-7 */ 573 __le32 reserved[3]; 574 }; 575 576 static_assert(sizeof(struct cq_entry) == 32); 577 578 /* 579 * UTMRD structure. 580 */ 581 struct utp_task_req_desc { 582 /* DW 0-3 */ 583 struct request_desc_header header; 584 585 /* DW 4-11 - Task request UPIU structure */ 586 struct { 587 struct utp_upiu_header req_header; 588 __be32 input_param1; 589 __be32 input_param2; 590 __be32 input_param3; 591 __be32 __reserved1[2]; 592 } upiu_req; 593 594 /* DW 12-19 - Task Management Response UPIU structure */ 595 struct { 596 struct utp_upiu_header rsp_header; 597 __be32 output_param1; 598 __be32 output_param2; 599 __be32 __reserved2[3]; 600 } upiu_rsp; 601 }; 602 603 #endif /* End of Header */ 604