1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2014, The Linux Foundation. All rights reserved.
3  */
4 #include <linux/bits.h>
5 #include <linux/clk.h>
6 #include <linux/delay.h>
7 #include <linux/interrupt.h>
8 #include <linux/io.h>
9 #include <linux/kernel.h>
10 #include <linux/module.h>
11 #include <linux/of.h>
12 #include <linux/platform_device.h>
13 #include <linux/watchdog.h>
14 
15 enum wdt_reg {
16 	WDT_RST,
17 	WDT_EN,
18 	WDT_STS,
19 	WDT_BARK_TIME,
20 	WDT_BITE_TIME,
21 };
22 
23 #define QCOM_WDT_ENABLE		BIT(0)
24 
25 static const u32 reg_offset_data_apcs_tmr[] = {
26 	[WDT_RST] = 0x38,
27 	[WDT_EN] = 0x40,
28 	[WDT_STS] = 0x44,
29 	[WDT_BARK_TIME] = 0x4C,
30 	[WDT_BITE_TIME] = 0x5C,
31 };
32 
33 static const u32 reg_offset_data_kpss[] = {
34 	[WDT_RST] = 0x4,
35 	[WDT_EN] = 0x8,
36 	[WDT_STS] = 0xC,
37 	[WDT_BARK_TIME] = 0x10,
38 	[WDT_BITE_TIME] = 0x14,
39 };
40 
41 struct qcom_wdt_match_data {
42 	const u32 *offset;
43 	bool pretimeout;
44 	u32 max_tick_count;
45 };
46 
47 struct qcom_wdt {
48 	struct watchdog_device	wdd;
49 	unsigned long		rate;
50 	void __iomem		*base;
51 	const u32		*layout;
52 };
53 
54 static void __iomem *wdt_addr(struct qcom_wdt *wdt, enum wdt_reg reg)
55 {
56 	return wdt->base + wdt->layout[reg];
57 }
58 
59 static inline
60 struct qcom_wdt *to_qcom_wdt(struct watchdog_device *wdd)
61 {
62 	return container_of(wdd, struct qcom_wdt, wdd);
63 }
64 
65 static irqreturn_t qcom_wdt_isr(int irq, void *arg)
66 {
67 	struct watchdog_device *wdd = arg;
68 
69 	watchdog_notify_pretimeout(wdd);
70 
71 	return IRQ_HANDLED;
72 }
73 
74 static int qcom_wdt_start(struct watchdog_device *wdd)
75 {
76 	struct qcom_wdt *wdt = to_qcom_wdt(wdd);
77 	unsigned int bark = wdd->timeout - wdd->pretimeout;
78 
79 	writel(0, wdt_addr(wdt, WDT_EN));
80 	writel(1, wdt_addr(wdt, WDT_RST));
81 	writel(bark * wdt->rate, wdt_addr(wdt, WDT_BARK_TIME));
82 	writel(wdd->timeout * wdt->rate, wdt_addr(wdt, WDT_BITE_TIME));
83 	writel(QCOM_WDT_ENABLE, wdt_addr(wdt, WDT_EN));
84 	return 0;
85 }
86 
87 static int qcom_wdt_stop(struct watchdog_device *wdd)
88 {
89 	struct qcom_wdt *wdt = to_qcom_wdt(wdd);
90 
91 	writel(0, wdt_addr(wdt, WDT_EN));
92 	return 0;
93 }
94 
95 static int qcom_wdt_ping(struct watchdog_device *wdd)
96 {
97 	struct qcom_wdt *wdt = to_qcom_wdt(wdd);
98 
99 	writel(1, wdt_addr(wdt, WDT_RST));
100 	return 0;
101 }
102 
103 static int qcom_wdt_set_timeout(struct watchdog_device *wdd,
104 				unsigned int timeout)
105 {
106 	wdd->timeout = timeout;
107 	return qcom_wdt_start(wdd);
108 }
109 
110 static int qcom_wdt_set_pretimeout(struct watchdog_device *wdd,
111 				   unsigned int timeout)
112 {
113 	wdd->pretimeout = timeout;
114 	return qcom_wdt_start(wdd);
115 }
116 
117 static int qcom_wdt_restart(struct watchdog_device *wdd, unsigned long action,
118 			    void *data)
119 {
120 	struct qcom_wdt *wdt = to_qcom_wdt(wdd);
121 	u32 timeout;
122 
123 	/*
124 	 * Trigger watchdog bite:
125 	 *    Setup BITE_TIME to be 128ms, and enable WDT.
126 	 */
127 	timeout = 128 * wdt->rate / 1000;
128 
129 	writel(0, wdt_addr(wdt, WDT_EN));
130 	writel(1, wdt_addr(wdt, WDT_RST));
131 	writel(timeout, wdt_addr(wdt, WDT_BARK_TIME));
132 	writel(timeout, wdt_addr(wdt, WDT_BITE_TIME));
133 	writel(QCOM_WDT_ENABLE, wdt_addr(wdt, WDT_EN));
134 
135 	/*
136 	 * Actually make sure the above sequence hits hardware before sleeping.
137 	 */
138 	wmb();
139 
140 	mdelay(150);
141 	return 0;
142 }
143 
144 static int qcom_wdt_is_running(struct watchdog_device *wdd)
145 {
146 	struct qcom_wdt *wdt = to_qcom_wdt(wdd);
147 
148 	return (readl(wdt_addr(wdt, WDT_EN)) & QCOM_WDT_ENABLE);
149 }
150 
151 static const struct watchdog_ops qcom_wdt_ops = {
152 	.start		= qcom_wdt_start,
153 	.stop		= qcom_wdt_stop,
154 	.ping		= qcom_wdt_ping,
155 	.set_timeout	= qcom_wdt_set_timeout,
156 	.set_pretimeout	= qcom_wdt_set_pretimeout,
157 	.restart        = qcom_wdt_restart,
158 	.owner		= THIS_MODULE,
159 };
160 
161 static const struct watchdog_info qcom_wdt_info = {
162 	.options	= WDIOF_KEEPALIVEPING
163 			| WDIOF_MAGICCLOSE
164 			| WDIOF_SETTIMEOUT
165 			| WDIOF_CARDRESET,
166 	.identity	= KBUILD_MODNAME,
167 };
168 
169 static const struct watchdog_info qcom_wdt_pt_info = {
170 	.options	= WDIOF_KEEPALIVEPING
171 			| WDIOF_MAGICCLOSE
172 			| WDIOF_SETTIMEOUT
173 			| WDIOF_PRETIMEOUT
174 			| WDIOF_CARDRESET,
175 	.identity	= KBUILD_MODNAME,
176 };
177 
178 static const struct qcom_wdt_match_data match_data_apcs_tmr = {
179 	.offset = reg_offset_data_apcs_tmr,
180 	.pretimeout = false,
181 	.max_tick_count = 0x10000000U,
182 };
183 
184 static const struct qcom_wdt_match_data match_data_ipq5424 = {
185 	.offset = reg_offset_data_kpss,
186 	.pretimeout = true,
187 	.max_tick_count = 0xFFFFFU,
188 };
189 
190 static const struct qcom_wdt_match_data match_data_kpss = {
191 	.offset = reg_offset_data_kpss,
192 	.pretimeout = true,
193 	.max_tick_count = 0xFFFFFU,
194 };
195 
196 static int qcom_wdt_probe(struct platform_device *pdev)
197 {
198 	struct device *dev = &pdev->dev;
199 	struct qcom_wdt *wdt;
200 	struct resource *res;
201 	struct device_node *np = dev->of_node;
202 	const struct qcom_wdt_match_data *data;
203 	u32 percpu_offset;
204 	int irq, ret;
205 	struct clk *clk;
206 
207 	data = of_device_get_match_data(dev);
208 	if (!data) {
209 		dev_err(dev, "Unsupported QCOM WDT module\n");
210 		return -ENODEV;
211 	}
212 
213 	wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
214 	if (!wdt)
215 		return -ENOMEM;
216 
217 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
218 	if (!res)
219 		return -ENOMEM;
220 
221 	/* We use CPU0's DGT for the watchdog */
222 	if (of_property_read_u32(np, "cpu-offset", &percpu_offset))
223 		percpu_offset = 0;
224 
225 	res->start += percpu_offset;
226 	res->end += percpu_offset;
227 
228 	wdt->base = devm_ioremap_resource(dev, res);
229 	if (IS_ERR(wdt->base))
230 		return PTR_ERR(wdt->base);
231 
232 	clk = devm_clk_get_enabled(dev, NULL);
233 	if (IS_ERR(clk)) {
234 		dev_err(dev, "failed to get input clock\n");
235 		return PTR_ERR(clk);
236 	}
237 
238 	/*
239 	 * We use the clock rate to calculate the max timeout, so ensure it's
240 	 * not zero to avoid a divide-by-zero exception.
241 	 *
242 	 * WATCHDOG_CORE assumes units of seconds, if the WDT is clocked such
243 	 * that it would bite before a second elapses it's usefulness is
244 	 * limited.  Bail if this is the case.
245 	 */
246 	wdt->rate = clk_get_rate(clk);
247 	if (wdt->rate == 0 ||
248 	    wdt->rate > data->max_tick_count) {
249 		dev_err(dev, "invalid clock rate\n");
250 		return -EINVAL;
251 	}
252 
253 	/* check if there is pretimeout support */
254 	irq = platform_get_irq_optional(pdev, 0);
255 	if (data->pretimeout && irq > 0) {
256 		ret = devm_request_irq(dev, irq, qcom_wdt_isr, 0,
257 				       "wdt_bark", &wdt->wdd);
258 		if (ret)
259 			return ret;
260 
261 		wdt->wdd.info = &qcom_wdt_pt_info;
262 		wdt->wdd.pretimeout = 1;
263 	} else {
264 		if (irq == -EPROBE_DEFER)
265 			return -EPROBE_DEFER;
266 
267 		wdt->wdd.info = &qcom_wdt_info;
268 	}
269 
270 	wdt->wdd.ops = &qcom_wdt_ops;
271 	wdt->wdd.min_timeout = 1;
272 	wdt->wdd.max_timeout = data->max_tick_count / wdt->rate;
273 	wdt->wdd.parent = dev;
274 	wdt->layout = data->offset;
275 
276 	if (readl(wdt_addr(wdt, WDT_STS)) & 1)
277 		wdt->wdd.bootstatus = WDIOF_CARDRESET;
278 
279 	/*
280 	 * If 'timeout-sec' unspecified in devicetree, assume a 30 second
281 	 * default, unless the max timeout is less than 30 seconds, then use
282 	 * the max instead.
283 	 */
284 	wdt->wdd.timeout = min(wdt->wdd.max_timeout, 30U);
285 	watchdog_init_timeout(&wdt->wdd, 0, dev);
286 
287 	/*
288 	 * If WDT is already running, call WDT start which
289 	 * will stop the WDT, set timeouts as bootloader
290 	 * might use different ones and set running bit
291 	 * to inform the WDT subsystem to ping the WDT
292 	 */
293 	if (qcom_wdt_is_running(&wdt->wdd)) {
294 		qcom_wdt_start(&wdt->wdd);
295 		set_bit(WDOG_HW_RUNNING, &wdt->wdd.status);
296 	}
297 
298 	ret = devm_watchdog_register_device(dev, &wdt->wdd);
299 	if (ret)
300 		return ret;
301 
302 	platform_set_drvdata(pdev, wdt);
303 	return 0;
304 }
305 
306 static int __maybe_unused qcom_wdt_suspend(struct device *dev)
307 {
308 	struct qcom_wdt *wdt = dev_get_drvdata(dev);
309 
310 	if (watchdog_active(&wdt->wdd))
311 		qcom_wdt_stop(&wdt->wdd);
312 
313 	return 0;
314 }
315 
316 static int __maybe_unused qcom_wdt_resume(struct device *dev)
317 {
318 	struct qcom_wdt *wdt = dev_get_drvdata(dev);
319 
320 	if (watchdog_active(&wdt->wdd))
321 		qcom_wdt_start(&wdt->wdd);
322 
323 	return 0;
324 }
325 
326 static const struct dev_pm_ops qcom_wdt_pm_ops = {
327 	SET_LATE_SYSTEM_SLEEP_PM_OPS(qcom_wdt_suspend, qcom_wdt_resume)
328 };
329 
330 static const struct of_device_id qcom_wdt_of_table[] = {
331 	{ .compatible = "qcom,apss-wdt-ipq5424", .data = &match_data_ipq5424 },
332 	{ .compatible = "qcom,kpss-timer", .data = &match_data_apcs_tmr },
333 	{ .compatible = "qcom,scss-timer", .data = &match_data_apcs_tmr },
334 	{ .compatible = "qcom,kpss-wdt", .data = &match_data_kpss },
335 	{ },
336 };
337 MODULE_DEVICE_TABLE(of, qcom_wdt_of_table);
338 
339 static struct platform_driver qcom_watchdog_driver = {
340 	.probe	= qcom_wdt_probe,
341 	.driver	= {
342 		.name		= KBUILD_MODNAME,
343 		.of_match_table	= qcom_wdt_of_table,
344 		.pm		= &qcom_wdt_pm_ops,
345 	},
346 };
347 module_platform_driver(qcom_watchdog_driver);
348 
349 MODULE_DESCRIPTION("QCOM KPSS Watchdog Driver");
350 MODULE_LICENSE("GPL v2");
351