1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 /* 4 * xHCI host controller driver 5 * 6 * Copyright (C) 2008 Intel Corp. 7 * 8 * Author: Sarah Sharp 9 * Some code borrowed from the Linux EHCI driver. 10 */ 11 12 #ifndef __LINUX_XHCI_HCD_H 13 #define __LINUX_XHCI_HCD_H 14 15 #include <linux/usb.h> 16 #include <linux/timer.h> 17 #include <linux/kernel.h> 18 #include <linux/usb/hcd.h> 19 #include <linux/io-64-nonatomic-lo-hi.h> 20 #include <linux/io-64-nonatomic-hi-lo.h> 21 22 /* Code sharing between pci-quirks and xhci hcd */ 23 #include "xhci-ext-caps.h" 24 #include "pci-quirks.h" 25 26 #include "xhci-port.h" 27 #include "xhci-caps.h" 28 29 /* max buffer size for trace and debug messages */ 30 #define XHCI_MSG_MAX 500 31 32 /* xHCI PCI Configuration Registers */ 33 #define XHCI_SBRN_OFFSET (0x60) 34 35 /* Max number of USB devices for any host controller - limit in section 6.1 */ 36 #define MAX_HC_SLOTS 256 37 /* Section 5.3.3 - MaxPorts */ 38 #define MAX_HC_PORTS 127 39 40 /* 41 * xHCI register interface. 42 * This corresponds to the eXtensible Host Controller Interface (xHCI) 43 * Revision 0.95 specification 44 */ 45 46 /** 47 * struct xhci_cap_regs - xHCI Host Controller Capability Registers. 48 * @hc_capbase: length of the capabilities register and HC version number 49 * @hcs_params1: HCSPARAMS1 - Structural Parameters 1 50 * @hcs_params2: HCSPARAMS2 - Structural Parameters 2 51 * @hcs_params3: HCSPARAMS3 - Structural Parameters 3 52 * @hcc_params: HCCPARAMS - Capability Parameters 53 * @db_off: DBOFF - Doorbell array offset 54 * @run_regs_off: RTSOFF - Runtime register space offset 55 * @hcc_params2: HCCPARAMS2 Capability Parameters 2, xhci 1.1 only 56 */ 57 struct xhci_cap_regs { 58 __le32 hc_capbase; 59 __le32 hcs_params1; 60 __le32 hcs_params2; 61 __le32 hcs_params3; 62 __le32 hcc_params; 63 __le32 db_off; 64 __le32 run_regs_off; 65 __le32 hcc_params2; /* xhci 1.1 */ 66 /* Reserved up to (CAPLENGTH - 0x1C) */ 67 }; 68 69 /* Number of registers per port */ 70 #define NUM_PORT_REGS 4 71 72 #define PORTSC 0 73 #define PORTPMSC 1 74 #define PORTLI 2 75 #define PORTHLPMC 3 76 77 /** 78 * struct xhci_op_regs - xHCI Host Controller Operational Registers. 79 * @command: USBCMD - xHC command register 80 * @status: USBSTS - xHC status register 81 * @page_size: This indicates the page size that the host controller 82 * supports. If bit n is set, the HC supports a page size 83 * of 2^(n+12), up to a 128MB page size. 84 * 4K is the minimum page size. 85 * @cmd_ring: CRP - 64-bit Command Ring Pointer 86 * @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer 87 * @config_reg: CONFIG - Configure Register 88 * @port_status_base: PORTSCn - base address for Port Status and Control 89 * Each port has a Port Status and Control register, 90 * followed by a Port Power Management Status and Control 91 * register, a Port Link Info register, and a reserved 92 * register. 93 * @port_power_base: PORTPMSCn - base address for 94 * Port Power Management Status and Control 95 * @port_link_base: PORTLIn - base address for Port Link Info (current 96 * Link PM state and control) for USB 2.1 and USB 3.0 97 * devices. 98 */ 99 struct xhci_op_regs { 100 __le32 command; 101 __le32 status; 102 __le32 page_size; 103 __le32 reserved1; 104 __le32 reserved2; 105 __le32 dev_notification; 106 __le64 cmd_ring; 107 /* rsvd: offset 0x20-2F */ 108 __le32 reserved3[4]; 109 __le64 dcbaa_ptr; 110 __le32 config_reg; 111 /* rsvd: offset 0x3C-3FF */ 112 __le32 reserved4[241]; 113 /* port 1 registers, which serve as a base address for other ports */ 114 __le32 port_status_base; 115 __le32 port_power_base; 116 __le32 port_link_base; 117 __le32 reserved5; 118 /* registers for ports 2-255 */ 119 __le32 reserved6[NUM_PORT_REGS*254]; 120 }; 121 122 /* USBCMD - USB command - command bitmasks */ 123 /* start/stop HC execution - do not write unless HC is halted*/ 124 #define CMD_RUN XHCI_CMD_RUN 125 /* Reset HC - resets internal HC state machine and all registers (except 126 * PCI config regs). HC does NOT drive a USB reset on the downstream ports. 127 * The xHCI driver must reinitialize the xHC after setting this bit. 128 */ 129 #define CMD_RESET (1 << 1) 130 /* Event Interrupt Enable - a '1' allows interrupts from the host controller */ 131 #define CMD_EIE XHCI_CMD_EIE 132 /* Host System Error Interrupt Enable - get out-of-band signal for HC errors */ 133 #define CMD_HSEIE XHCI_CMD_HSEIE 134 /* bits 4:6 are reserved (and should be preserved on writes). */ 135 /* light reset (port status stays unchanged) - reset completed when this is 0 */ 136 #define CMD_LRESET (1 << 7) 137 /* host controller save/restore state. */ 138 #define CMD_CSS (1 << 8) 139 #define CMD_CRS (1 << 9) 140 /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */ 141 #define CMD_EWE XHCI_CMD_EWE 142 /* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root 143 * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off. 144 * '0' means the xHC can power it off if all ports are in the disconnect, 145 * disabled, or powered-off state. 146 */ 147 #define CMD_PM_INDEX (1 << 11) 148 /* bit 14 Extended TBC Enable, changes Isoc TRB fields to support larger TBC */ 149 #define CMD_ETE (1 << 14) 150 /* bits 15:31 are reserved (and should be preserved on writes). */ 151 152 #define XHCI_RESET_LONG_USEC (10 * 1000 * 1000) 153 #define XHCI_RESET_SHORT_USEC (250 * 1000) 154 155 /* USBSTS - USB status - status bitmasks */ 156 /* HC not running - set to 1 when run/stop bit is cleared. */ 157 #define STS_HALT XHCI_STS_HALT 158 /* serious error, e.g. PCI parity error. The HC will clear the run/stop bit. */ 159 #define STS_FATAL (1 << 2) 160 /* event interrupt - clear this prior to clearing any IP flags in IR set*/ 161 #define STS_EINT (1 << 3) 162 /* port change detect */ 163 #define STS_PORT (1 << 4) 164 /* bits 5:7 reserved and zeroed */ 165 /* save state status - '1' means xHC is saving state */ 166 #define STS_SAVE (1 << 8) 167 /* restore state status - '1' means xHC is restoring state */ 168 #define STS_RESTORE (1 << 9) 169 /* true: save or restore error */ 170 #define STS_SRE (1 << 10) 171 /* true: Controller Not Ready to accept doorbell or op reg writes after reset */ 172 #define STS_CNR XHCI_STS_CNR 173 /* true: internal Host Controller Error - SW needs to reset and reinitialize */ 174 #define STS_HCE (1 << 12) 175 /* bits 13:31 reserved and should be preserved */ 176 177 /* 178 * DNCTRL - Device Notification Control Register - dev_notification bitmasks 179 * Generate a device notification event when the HC sees a transaction with a 180 * notification type that matches a bit set in this bit field. 181 */ 182 #define DEV_NOTE_MASK (0xffff) 183 /* Most of the device notification types should only be used for debug. 184 * SW does need to pay attention to function wake notifications. 185 */ 186 #define DEV_NOTE_FWAKE (1 << 1) 187 188 /* CRCR - Command Ring Control Register - cmd_ring bitmasks */ 189 /* bit 0 - Cycle bit indicates the ownership of the command ring */ 190 #define CMD_RING_CYCLE (1 << 0) 191 /* stop ring operation after completion of the currently executing command */ 192 #define CMD_RING_PAUSE (1 << 1) 193 /* stop ring immediately - abort the currently executing command */ 194 #define CMD_RING_ABORT (1 << 2) 195 /* true: command ring is running */ 196 #define CMD_RING_RUNNING (1 << 3) 197 /* bits 63:6 - Command Ring pointer */ 198 #define CMD_RING_PTR_MASK GENMASK_ULL(63, 6) 199 200 /* CONFIG - Configure Register - config_reg bitmasks */ 201 /* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */ 202 #define MAX_DEVS(p) ((p) & 0xff) 203 /* bit 8: U3 Entry Enabled, assert PLC when root port enters U3, xhci 1.1 */ 204 #define CONFIG_U3E (1 << 8) 205 /* bit 9: Configuration Information Enable, xhci 1.1 */ 206 #define CONFIG_CIE (1 << 9) 207 /* bits 10:31 - reserved and should be preserved */ 208 209 /* bits 15:0 - HCD page shift bit */ 210 #define XHCI_PAGE_SIZE_MASK 0xffff 211 212 /** 213 * struct xhci_intr_reg - Interrupt Register Set, v1.2 section 5.5.2. 214 * @iman: IMAN - Interrupt Management Register. Used to enable 215 * interrupts and check for pending interrupts. 216 * @imod: IMOD - Interrupt Moderation Register. Used to throttle interrupts. 217 * @erst_size: ERSTSZ - Number of segments in the Event Ring Segment Table (ERST). 218 * @erst_base: ERSTBA - Event ring segment table base address. 219 * @erst_dequeue: ERDP - Event ring dequeue pointer. 220 * 221 * Each interrupter (defined by a MSI-X vector) has an event ring and an Event 222 * Ring Segment Table (ERST) associated with it. The event ring is comprised of 223 * multiple segments of the same size. The HC places events on the ring and 224 * "updates the Cycle bit in the TRBs to indicate to software the current 225 * position of the Enqueue Pointer." The HCD (Linux) processes those events and 226 * updates the dequeue pointer. 227 */ 228 struct xhci_intr_reg { 229 __le32 iman; 230 __le32 imod; 231 __le32 erst_size; 232 __le32 rsvd; 233 __le64 erst_base; 234 __le64 erst_dequeue; 235 }; 236 237 /* iman bitmasks */ 238 /* bit 0 - Interrupt Pending (IP), whether there is an interrupt pending. Write-1-to-clear. */ 239 #define IMAN_IP (1 << 0) 240 /* bit 1 - Interrupt Enable (IE), whether the interrupter is capable of generating an interrupt */ 241 #define IMAN_IE (1 << 1) 242 243 /* imod bitmasks */ 244 /* 245 * bits 15:0 - Interrupt Moderation Interval, the minimum interval between interrupts 246 * (in 250ns intervals). The interval between interrupts will be longer if there are no 247 * events on the event ring. Default is 4000 (1 ms). 248 */ 249 #define IMODI_MASK (0xffff) 250 /* bits 31:16 - Interrupt Moderation Counter, used to count down the time to the next interrupt */ 251 #define IMODC_MASK (0xffff << 16) 252 253 /* erst_size bitmasks */ 254 /* bits 15:0 - Event Ring Segment Table Size, number of ERST entries */ 255 #define ERST_SIZE_MASK (0xffff) 256 257 /* erst_base bitmasks */ 258 /* bits 63:6 - Event Ring Segment Table Base Address Register */ 259 #define ERST_BASE_ADDRESS_MASK GENMASK_ULL(63, 6) 260 261 /* erst_dequeue bitmasks */ 262 /* 263 * bits 2:0 - Dequeue ERST Segment Index (DESI), is the segment number (or alias) where the 264 * current dequeue pointer lies. This is an optional HW hint. 265 */ 266 #define ERST_DESI_MASK (0x7) 267 /* 268 * bit 3 - Event Handler Busy (EHB), whether the event ring is scheduled to be serviced by 269 * a work queue (or delayed service routine)? 270 */ 271 #define ERST_EHB (1 << 3) 272 /* bits 63:4 - Event Ring Dequeue Pointer */ 273 #define ERST_PTR_MASK GENMASK_ULL(63, 4) 274 275 /** 276 * struct xhci_run_regs 277 * @microframe_index: 278 * MFINDEX - current microframe number 279 * 280 * Section 5.5 Host Controller Runtime Registers: 281 * "Software should read and write these registers using only Dword (32 bit) 282 * or larger accesses" 283 */ 284 struct xhci_run_regs { 285 __le32 microframe_index; 286 __le32 rsvd[7]; 287 struct xhci_intr_reg ir_set[128]; 288 }; 289 290 /** 291 * struct doorbell_array 292 * 293 * Bits 0 - 7: Endpoint target 294 * Bits 8 - 15: RsvdZ 295 * Bits 16 - 31: Stream ID 296 * 297 * Section 5.6 298 */ 299 struct xhci_doorbell_array { 300 __le32 doorbell[256]; 301 }; 302 303 #define DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16)) 304 #define DB_VALUE_HOST 0x00000000 305 306 #define PLT_MASK (0x03 << 6) 307 #define PLT_SYM (0x00 << 6) 308 #define PLT_ASYM_RX (0x02 << 6) 309 #define PLT_ASYM_TX (0x03 << 6) 310 311 /** 312 * struct xhci_container_ctx 313 * @type: Type of context. Used to calculated offsets to contained contexts. 314 * @size: Size of the context data 315 * @bytes: The raw context data given to HW 316 * @dma: dma address of the bytes 317 * 318 * Represents either a Device or Input context. Holds a pointer to the raw 319 * memory used for the context (bytes) and dma address of it (dma). 320 */ 321 struct xhci_container_ctx { 322 unsigned type; 323 #define XHCI_CTX_TYPE_DEVICE 0x1 324 #define XHCI_CTX_TYPE_INPUT 0x2 325 326 int size; 327 328 u8 *bytes; 329 dma_addr_t dma; 330 }; 331 332 /** 333 * struct xhci_slot_ctx 334 * @dev_info: Route string, device speed, hub info, and last valid endpoint 335 * @dev_info2: Max exit latency for device number, root hub port number 336 * @tt_info: tt_info is used to construct split transaction tokens 337 * @dev_state: slot state and device address 338 * 339 * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context 340 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes 341 * reserved at the end of the slot context for HC internal use. 342 */ 343 struct xhci_slot_ctx { 344 __le32 dev_info; 345 __le32 dev_info2; 346 __le32 tt_info; 347 __le32 dev_state; 348 /* offset 0x10 to 0x1f reserved for HC internal use */ 349 __le32 reserved[4]; 350 }; 351 352 /* dev_info bitmasks */ 353 /* Route String - 0:19 */ 354 #define ROUTE_STRING_MASK (0xfffff) 355 /* Device speed - values defined by PORTSC Device Speed field - 20:23 */ 356 #define DEV_SPEED (0xf << 20) 357 #define GET_DEV_SPEED(n) (((n) & DEV_SPEED) >> 20) 358 /* bit 24 reserved */ 359 /* Is this LS/FS device connected through a HS hub? - bit 25 */ 360 #define DEV_MTT (0x1 << 25) 361 /* Set if the device is a hub - bit 26 */ 362 #define DEV_HUB (0x1 << 26) 363 /* Index of the last valid endpoint context in this device context - 27:31 */ 364 #define LAST_CTX_MASK (0x1f << 27) 365 #define LAST_CTX(p) ((p) << 27) 366 #define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1) 367 #define SLOT_FLAG (1 << 0) 368 #define EP0_FLAG (1 << 1) 369 370 /* dev_info2 bitmasks */ 371 /* Max Exit Latency (ms) - worst case time to wake up all links in dev path */ 372 #define MAX_EXIT (0xffff) 373 /* Root hub port number that is needed to access the USB device */ 374 #define ROOT_HUB_PORT(p) (((p) & 0xff) << 16) 375 #define DEVINFO_TO_ROOT_HUB_PORT(p) (((p) >> 16) & 0xff) 376 /* Maximum number of ports under a hub device */ 377 #define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24) 378 #define DEVINFO_TO_MAX_PORTS(p) (((p) & (0xff << 24)) >> 24) 379 380 /* tt_info bitmasks */ 381 /* 382 * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub 383 * The Slot ID of the hub that isolates the high speed signaling from 384 * this low or full-speed device. '0' if attached to root hub port. 385 */ 386 #define TT_SLOT (0xff) 387 /* 388 * The number of the downstream facing port of the high-speed hub 389 * '0' if the device is not low or full speed. 390 */ 391 #define TT_PORT (0xff << 8) 392 #define TT_THINK_TIME(p) (((p) & 0x3) << 16) 393 #define GET_TT_THINK_TIME(p) (((p) & (0x3 << 16)) >> 16) 394 395 /* dev_state bitmasks */ 396 /* USB device address - assigned by the HC */ 397 #define DEV_ADDR_MASK (0xff) 398 /* bits 8:26 reserved */ 399 /* Slot state */ 400 #define SLOT_STATE (0x1f << 27) 401 #define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27) 402 403 #define SLOT_STATE_DISABLED 0 404 #define SLOT_STATE_ENABLED SLOT_STATE_DISABLED 405 #define SLOT_STATE_DEFAULT 1 406 #define SLOT_STATE_ADDRESSED 2 407 #define SLOT_STATE_CONFIGURED 3 408 409 /** 410 * struct xhci_ep_ctx 411 * @ep_info: endpoint state, streams, mult, and interval information. 412 * @ep_info2: information on endpoint type, max packet size, max burst size, 413 * error count, and whether the HC will force an event for all 414 * transactions. 415 * @deq: 64-bit ring dequeue pointer address. If the endpoint only 416 * defines one stream, this points to the endpoint transfer ring. 417 * Otherwise, it points to a stream context array, which has a 418 * ring pointer for each flow. 419 * @tx_info: 420 * Average TRB lengths for the endpoint ring and 421 * max payload within an Endpoint Service Interval Time (ESIT). 422 * 423 * Endpoint Context - section 6.2.1.2. This assumes the HC uses 32-byte context 424 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes 425 * reserved at the end of the endpoint context for HC internal use. 426 */ 427 struct xhci_ep_ctx { 428 __le32 ep_info; 429 __le32 ep_info2; 430 __le64 deq; 431 __le32 tx_info; 432 /* offset 0x14 - 0x1f reserved for HC internal use */ 433 __le32 reserved[3]; 434 }; 435 436 /* ep_info bitmasks */ 437 /* 438 * Endpoint State - bits 0:2 439 * 0 - disabled 440 * 1 - running 441 * 2 - halted due to halt condition - ok to manipulate endpoint ring 442 * 3 - stopped 443 * 4 - TRB error 444 * 5-7 - reserved 445 */ 446 #define EP_STATE_MASK (0x7) 447 #define EP_STATE_DISABLED 0 448 #define EP_STATE_RUNNING 1 449 #define EP_STATE_HALTED 2 450 #define EP_STATE_STOPPED 3 451 #define EP_STATE_ERROR 4 452 #define GET_EP_CTX_STATE(ctx) (le32_to_cpu((ctx)->ep_info) & EP_STATE_MASK) 453 454 /* Mult - Max number of burtst within an interval, in EP companion desc. */ 455 #define EP_MULT(p) (((p) & 0x3) << 8) 456 #define CTX_TO_EP_MULT(p) (((p) >> 8) & 0x3) 457 /* bits 10:14 are Max Primary Streams */ 458 /* bit 15 is Linear Stream Array */ 459 /* Interval - period between requests to an endpoint - 125u increments. */ 460 #define EP_INTERVAL(p) (((p) & 0xff) << 16) 461 #define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff)) 462 #define CTX_TO_EP_INTERVAL(p) (((p) >> 16) & 0xff) 463 #define EP_MAXPSTREAMS_MASK (0x1f << 10) 464 #define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK) 465 #define CTX_TO_EP_MAXPSTREAMS(p) (((p) & EP_MAXPSTREAMS_MASK) >> 10) 466 /* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */ 467 #define EP_HAS_LSA (1 << 15) 468 /* hosts with LEC=1 use bits 31:24 as ESIT high bits. */ 469 #define CTX_TO_MAX_ESIT_PAYLOAD_HI(p) (((p) >> 24) & 0xff) 470 471 /* ep_info2 bitmasks */ 472 /* 473 * Force Event - generate transfer events for all TRBs for this endpoint 474 * This will tell the HC to ignore the IOC and ISP flags (for debugging only). 475 */ 476 #define FORCE_EVENT (0x1) 477 #define ERROR_COUNT(p) (((p) & 0x3) << 1) 478 #define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7) 479 #define EP_TYPE(p) ((p) << 3) 480 #define ISOC_OUT_EP 1 481 #define BULK_OUT_EP 2 482 #define INT_OUT_EP 3 483 #define CTRL_EP 4 484 #define ISOC_IN_EP 5 485 #define BULK_IN_EP 6 486 #define INT_IN_EP 7 487 /* bit 6 reserved */ 488 /* bit 7 is Host Initiate Disable - for disabling stream selection */ 489 #define MAX_BURST(p) (((p)&0xff) << 8) 490 #define CTX_TO_MAX_BURST(p) (((p) >> 8) & 0xff) 491 #define MAX_PACKET(p) (((p)&0xffff) << 16) 492 #define MAX_PACKET_MASK (0xffff << 16) 493 #define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff) 494 495 /* tx_info bitmasks */ 496 #define EP_AVG_TRB_LENGTH(p) ((p) & 0xffff) 497 #define EP_MAX_ESIT_PAYLOAD_LO(p) (((p) & 0xffff) << 16) 498 #define EP_MAX_ESIT_PAYLOAD_HI(p) ((((p) >> 16) & 0xff) << 24) 499 #define CTX_TO_MAX_ESIT_PAYLOAD(p) (((p) >> 16) & 0xffff) 500 501 /* deq bitmasks */ 502 #define EP_CTX_CYCLE_MASK (1 << 0) 503 #define SCTX_DEQ_MASK (~0xfL) 504 505 506 /** 507 * struct xhci_input_control_context 508 * Input control context; see section 6.2.5. 509 * 510 * @drop_context: set the bit of the endpoint context you want to disable 511 * @add_context: set the bit of the endpoint context you want to enable 512 */ 513 struct xhci_input_control_ctx { 514 __le32 drop_flags; 515 __le32 add_flags; 516 __le32 rsvd2[6]; 517 }; 518 519 #define EP_IS_ADDED(ctrl_ctx, i) \ 520 (le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1))) 521 #define EP_IS_DROPPED(ctrl_ctx, i) \ 522 (le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) 523 524 /* Represents everything that is needed to issue a command on the command ring. 525 * It's useful to pre-allocate these for commands that cannot fail due to 526 * out-of-memory errors, like freeing streams. 527 */ 528 struct xhci_command { 529 /* Input context for changing device state */ 530 struct xhci_container_ctx *in_ctx; 531 u32 status; 532 u32 comp_param; 533 int slot_id; 534 /* If completion is null, no one is waiting on this command 535 * and the structure can be freed after the command completes. 536 */ 537 struct completion *completion; 538 union xhci_trb *command_trb; 539 struct list_head cmd_list; 540 /* xHCI command response timeout in milliseconds */ 541 unsigned int timeout_ms; 542 }; 543 544 /* drop context bitmasks */ 545 #define DROP_EP(x) (0x1 << x) 546 /* add context bitmasks */ 547 #define ADD_EP(x) (0x1 << x) 548 549 struct xhci_stream_ctx { 550 /* 64-bit stream ring address, cycle state, and stream type */ 551 __le64 stream_ring; 552 /* offset 0x14 - 0x1f reserved for HC internal use */ 553 __le32 reserved[2]; 554 }; 555 556 /* Stream Context Types (section 6.4.1) - bits 3:1 of stream ctx deq ptr */ 557 #define SCT_FOR_CTX(p) (((p) & 0x7) << 1) 558 #define CTX_TO_SCT(p) (((p) >> 1) & 0x7) 559 /* Secondary stream array type, dequeue pointer is to a transfer ring */ 560 #define SCT_SEC_TR 0 561 /* Primary stream array type, dequeue pointer is to a transfer ring */ 562 #define SCT_PRI_TR 1 563 /* Dequeue pointer is for a secondary stream array (SSA) with 8 entries */ 564 #define SCT_SSA_8 2 565 #define SCT_SSA_16 3 566 #define SCT_SSA_32 4 567 #define SCT_SSA_64 5 568 #define SCT_SSA_128 6 569 #define SCT_SSA_256 7 570 571 /* Assume no secondary streams for now */ 572 struct xhci_stream_info { 573 struct xhci_ring **stream_rings; 574 /* Number of streams, including stream 0 (which drivers can't use) */ 575 unsigned int num_streams; 576 /* The stream context array may be bigger than 577 * the number of streams the driver asked for 578 */ 579 struct xhci_stream_ctx *stream_ctx_array; 580 unsigned int num_stream_ctxs; 581 dma_addr_t ctx_array_dma; 582 /* For mapping physical TRB addresses to segments in stream rings */ 583 struct radix_tree_root trb_address_map; 584 struct xhci_command *free_streams_command; 585 }; 586 587 #define SMALL_STREAM_ARRAY_SIZE 256 588 #define MEDIUM_STREAM_ARRAY_SIZE 1024 589 #define GET_PORT_BW_ARRAY_SIZE 256 590 591 /* Some Intel xHCI host controllers need software to keep track of the bus 592 * bandwidth. Keep track of endpoint info here. Each root port is allocated 593 * the full bus bandwidth. We must also treat TTs (including each port under a 594 * multi-TT hub) as a separate bandwidth domain. The direct memory interface 595 * (DMI) also limits the total bandwidth (across all domains) that can be used. 596 */ 597 struct xhci_bw_info { 598 /* ep_interval is zero-based */ 599 unsigned int ep_interval; 600 /* mult and num_packets are one-based */ 601 unsigned int mult; 602 unsigned int num_packets; 603 unsigned int max_packet_size; 604 unsigned int max_esit_payload; 605 unsigned int type; 606 }; 607 608 /* "Block" sizes in bytes the hardware uses for different device speeds. 609 * The logic in this part of the hardware limits the number of bits the hardware 610 * can use, so must represent bandwidth in a less precise manner to mimic what 611 * the scheduler hardware computes. 612 */ 613 #define FS_BLOCK 1 614 #define HS_BLOCK 4 615 #define SS_BLOCK 16 616 #define DMI_BLOCK 32 617 618 /* Each device speed has a protocol overhead (CRC, bit stuffing, etc) associated 619 * with each byte transferred. SuperSpeed devices have an initial overhead to 620 * set up bursts. These are in blocks, see above. LS overhead has already been 621 * translated into FS blocks. 622 */ 623 #define DMI_OVERHEAD 8 624 #define DMI_OVERHEAD_BURST 4 625 #define SS_OVERHEAD 8 626 #define SS_OVERHEAD_BURST 32 627 #define HS_OVERHEAD 26 628 #define FS_OVERHEAD 20 629 #define LS_OVERHEAD 128 630 /* The TTs need to claim roughly twice as much bandwidth (94 bytes per 631 * microframe ~= 24Mbps) of the HS bus as the devices can actually use because 632 * of overhead associated with split transfers crossing microframe boundaries. 633 * 31 blocks is pure protocol overhead. 634 */ 635 #define TT_HS_OVERHEAD (31 + 94) 636 #define TT_DMI_OVERHEAD (25 + 12) 637 638 /* Bandwidth limits in blocks */ 639 #define FS_BW_LIMIT 1285 640 #define TT_BW_LIMIT 1320 641 #define HS_BW_LIMIT 1607 642 #define SS_BW_LIMIT_IN 3906 643 #define DMI_BW_LIMIT_IN 3906 644 #define SS_BW_LIMIT_OUT 3906 645 #define DMI_BW_LIMIT_OUT 3906 646 647 /* Percentage of bus bandwidth reserved for non-periodic transfers */ 648 #define FS_BW_RESERVED 10 649 #define HS_BW_RESERVED 20 650 #define SS_BW_RESERVED 10 651 652 struct xhci_virt_ep { 653 struct xhci_virt_device *vdev; /* parent */ 654 unsigned int ep_index; 655 struct xhci_ring *ring; 656 /* Related to endpoints that are configured to use stream IDs only */ 657 struct xhci_stream_info *stream_info; 658 /* Temporary storage in case the configure endpoint command fails and we 659 * have to restore the device state to the previous state 660 */ 661 struct xhci_ring *new_ring; 662 unsigned int err_count; 663 unsigned int ep_state; 664 #define SET_DEQ_PENDING (1 << 0) 665 #define EP_HALTED (1 << 1) /* For stall handling */ 666 #define EP_STOP_CMD_PENDING (1 << 2) /* For URB cancellation */ 667 /* Transitioning the endpoint to using streams, don't enqueue URBs */ 668 #define EP_GETTING_STREAMS (1 << 3) 669 #define EP_HAS_STREAMS (1 << 4) 670 /* Transitioning the endpoint to not using streams, don't enqueue URBs */ 671 #define EP_GETTING_NO_STREAMS (1 << 5) 672 #define EP_HARD_CLEAR_TOGGLE (1 << 6) 673 #define EP_SOFT_CLEAR_TOGGLE (1 << 7) 674 /* usb_hub_clear_tt_buffer is in progress */ 675 #define EP_CLEARING_TT (1 << 8) 676 /* ---- Related to URB cancellation ---- */ 677 struct list_head cancelled_td_list; 678 struct xhci_hcd *xhci; 679 /* Dequeue pointer and dequeue segment for a submitted Set TR Dequeue 680 * command. We'll need to update the ring's dequeue segment and dequeue 681 * pointer after the command completes. 682 */ 683 struct xhci_segment *queued_deq_seg; 684 union xhci_trb *queued_deq_ptr; 685 /* 686 * Sometimes the xHC can not process isochronous endpoint ring quickly 687 * enough, and it will miss some isoc tds on the ring and generate 688 * a Missed Service Error Event. 689 * Set skip flag when receive a Missed Service Error Event and 690 * process the missed tds on the endpoint ring. 691 */ 692 bool skip; 693 /* Bandwidth checking storage */ 694 struct xhci_bw_info bw_info; 695 struct list_head bw_endpoint_list; 696 unsigned long stop_time; 697 /* Isoch Frame ID checking storage */ 698 int next_frame_id; 699 /* Use new Isoch TRB layout needed for extended TBC support */ 700 bool use_extended_tbc; 701 /* set if this endpoint is controlled via sideband access*/ 702 struct xhci_sideband *sideband; 703 }; 704 705 enum xhci_overhead_type { 706 LS_OVERHEAD_TYPE = 0, 707 FS_OVERHEAD_TYPE, 708 HS_OVERHEAD_TYPE, 709 }; 710 711 struct xhci_interval_bw { 712 unsigned int num_packets; 713 /* Sorted by max packet size. 714 * Head of the list is the greatest max packet size. 715 */ 716 struct list_head endpoints; 717 /* How many endpoints of each speed are present. */ 718 unsigned int overhead[3]; 719 }; 720 721 #define XHCI_MAX_INTERVAL 16 722 723 struct xhci_interval_bw_table { 724 unsigned int interval0_esit_payload; 725 struct xhci_interval_bw interval_bw[XHCI_MAX_INTERVAL]; 726 /* Includes reserved bandwidth for async endpoints */ 727 unsigned int bw_used; 728 unsigned int ss_bw_in; 729 unsigned int ss_bw_out; 730 }; 731 732 #define EP_CTX_PER_DEV 31 733 734 struct xhci_virt_device { 735 int slot_id; 736 struct usb_device *udev; 737 /* 738 * Commands to the hardware are passed an "input context" that 739 * tells the hardware what to change in its data structures. 740 * The hardware will return changes in an "output context" that 741 * software must allocate for the hardware. We need to keep 742 * track of input and output contexts separately because 743 * these commands might fail and we don't trust the hardware. 744 */ 745 struct xhci_container_ctx *out_ctx; 746 /* Used for addressing devices and configuration changes */ 747 struct xhci_container_ctx *in_ctx; 748 struct xhci_virt_ep eps[EP_CTX_PER_DEV]; 749 struct xhci_port *rhub_port; 750 struct xhci_interval_bw_table *bw_table; 751 struct xhci_tt_bw_info *tt_info; 752 /* 753 * flags for state tracking based on events and issued commands. 754 * Software can not rely on states from output contexts because of 755 * latency between events and xHC updating output context values. 756 * See xhci 1.1 section 4.8.3 for more details 757 */ 758 unsigned long flags; 759 #define VDEV_PORT_ERROR BIT(0) /* Port error, link inactive */ 760 761 /* The current max exit latency for the enabled USB3 link states. */ 762 u16 current_mel; 763 /* Used for the debugfs interfaces. */ 764 void *debugfs_private; 765 /* set if this endpoint is controlled via sideband access*/ 766 struct xhci_sideband *sideband; 767 }; 768 769 /* 770 * For each roothub, keep track of the bandwidth information for each periodic 771 * interval. 772 * 773 * If a high speed hub is attached to the roothub, each TT associated with that 774 * hub is a separate bandwidth domain. The interval information for the 775 * endpoints on the devices under that TT will appear in the TT structure. 776 */ 777 struct xhci_root_port_bw_info { 778 struct list_head tts; 779 unsigned int num_active_tts; 780 struct xhci_interval_bw_table bw_table; 781 }; 782 783 struct xhci_tt_bw_info { 784 struct list_head tt_list; 785 int slot_id; 786 int ttport; 787 struct xhci_interval_bw_table bw_table; 788 int active_eps; 789 }; 790 791 792 /** 793 * struct xhci_device_context_array 794 * @dev_context_ptr array of 64-bit DMA addresses for device contexts 795 */ 796 struct xhci_device_context_array { 797 /* 64-bit device addresses; we only write 32-bit addresses */ 798 __le64 dev_context_ptrs[MAX_HC_SLOTS]; 799 /* private xHCD pointers */ 800 dma_addr_t dma; 801 }; 802 /* TODO: write function to set the 64-bit device DMA address */ 803 /* 804 * TODO: change this to be dynamically sized at HC mem init time since the HC 805 * might not be able to handle the maximum number of devices possible. 806 */ 807 808 809 struct xhci_transfer_event { 810 /* 64-bit buffer address, or immediate data */ 811 __le64 buffer; 812 __le32 transfer_len; 813 /* This field is interpreted differently based on the type of TRB */ 814 __le32 flags; 815 }; 816 817 /* Transfer event flags bitfield, also for select command completion events */ 818 #define TRB_TO_SLOT_ID(p) (((p) >> 24) & 0xff) 819 #define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24) 820 821 #define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f) /* Endpoint ID 1 - 31 */ 822 #define EP_ID_FOR_TRB(p) (((p) & 0x1f) << 16) 823 824 #define TRB_TO_EP_INDEX(p) (TRB_TO_EP_ID(p) - 1) /* Endpoint index 0 - 30 */ 825 #define EP_INDEX_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16) 826 827 /* Transfer event TRB length bit mask */ 828 #define EVENT_TRB_LEN(p) ((p) & 0xffffff) 829 830 /* Completion Code - only applicable for some types of TRBs */ 831 #define COMP_CODE_MASK (0xff << 24) 832 #define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24) 833 #define COMP_INVALID 0 834 #define COMP_SUCCESS 1 835 #define COMP_DATA_BUFFER_ERROR 2 836 #define COMP_BABBLE_DETECTED_ERROR 3 837 #define COMP_USB_TRANSACTION_ERROR 4 838 #define COMP_TRB_ERROR 5 839 #define COMP_STALL_ERROR 6 840 #define COMP_RESOURCE_ERROR 7 841 #define COMP_BANDWIDTH_ERROR 8 842 #define COMP_NO_SLOTS_AVAILABLE_ERROR 9 843 #define COMP_INVALID_STREAM_TYPE_ERROR 10 844 #define COMP_SLOT_NOT_ENABLED_ERROR 11 845 #define COMP_ENDPOINT_NOT_ENABLED_ERROR 12 846 #define COMP_SHORT_PACKET 13 847 #define COMP_RING_UNDERRUN 14 848 #define COMP_RING_OVERRUN 15 849 #define COMP_VF_EVENT_RING_FULL_ERROR 16 850 #define COMP_PARAMETER_ERROR 17 851 #define COMP_BANDWIDTH_OVERRUN_ERROR 18 852 #define COMP_CONTEXT_STATE_ERROR 19 853 #define COMP_NO_PING_RESPONSE_ERROR 20 854 #define COMP_EVENT_RING_FULL_ERROR 21 855 #define COMP_INCOMPATIBLE_DEVICE_ERROR 22 856 #define COMP_MISSED_SERVICE_ERROR 23 857 #define COMP_COMMAND_RING_STOPPED 24 858 #define COMP_COMMAND_ABORTED 25 859 #define COMP_STOPPED 26 860 #define COMP_STOPPED_LENGTH_INVALID 27 861 #define COMP_STOPPED_SHORT_PACKET 28 862 #define COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR 29 863 #define COMP_ISOCH_BUFFER_OVERRUN 31 864 #define COMP_EVENT_LOST_ERROR 32 865 #define COMP_UNDEFINED_ERROR 33 866 #define COMP_INVALID_STREAM_ID_ERROR 34 867 #define COMP_SECONDARY_BANDWIDTH_ERROR 35 868 #define COMP_SPLIT_TRANSACTION_ERROR 36 869 870 static inline const char *xhci_trb_comp_code_string(u8 status) 871 { 872 switch (status) { 873 case COMP_INVALID: 874 return "Invalid"; 875 case COMP_SUCCESS: 876 return "Success"; 877 case COMP_DATA_BUFFER_ERROR: 878 return "Data Buffer Error"; 879 case COMP_BABBLE_DETECTED_ERROR: 880 return "Babble Detected"; 881 case COMP_USB_TRANSACTION_ERROR: 882 return "USB Transaction Error"; 883 case COMP_TRB_ERROR: 884 return "TRB Error"; 885 case COMP_STALL_ERROR: 886 return "Stall Error"; 887 case COMP_RESOURCE_ERROR: 888 return "Resource Error"; 889 case COMP_BANDWIDTH_ERROR: 890 return "Bandwidth Error"; 891 case COMP_NO_SLOTS_AVAILABLE_ERROR: 892 return "No Slots Available Error"; 893 case COMP_INVALID_STREAM_TYPE_ERROR: 894 return "Invalid Stream Type Error"; 895 case COMP_SLOT_NOT_ENABLED_ERROR: 896 return "Slot Not Enabled Error"; 897 case COMP_ENDPOINT_NOT_ENABLED_ERROR: 898 return "Endpoint Not Enabled Error"; 899 case COMP_SHORT_PACKET: 900 return "Short Packet"; 901 case COMP_RING_UNDERRUN: 902 return "Ring Underrun"; 903 case COMP_RING_OVERRUN: 904 return "Ring Overrun"; 905 case COMP_VF_EVENT_RING_FULL_ERROR: 906 return "VF Event Ring Full Error"; 907 case COMP_PARAMETER_ERROR: 908 return "Parameter Error"; 909 case COMP_BANDWIDTH_OVERRUN_ERROR: 910 return "Bandwidth Overrun Error"; 911 case COMP_CONTEXT_STATE_ERROR: 912 return "Context State Error"; 913 case COMP_NO_PING_RESPONSE_ERROR: 914 return "No Ping Response Error"; 915 case COMP_EVENT_RING_FULL_ERROR: 916 return "Event Ring Full Error"; 917 case COMP_INCOMPATIBLE_DEVICE_ERROR: 918 return "Incompatible Device Error"; 919 case COMP_MISSED_SERVICE_ERROR: 920 return "Missed Service Error"; 921 case COMP_COMMAND_RING_STOPPED: 922 return "Command Ring Stopped"; 923 case COMP_COMMAND_ABORTED: 924 return "Command Aborted"; 925 case COMP_STOPPED: 926 return "Stopped"; 927 case COMP_STOPPED_LENGTH_INVALID: 928 return "Stopped - Length Invalid"; 929 case COMP_STOPPED_SHORT_PACKET: 930 return "Stopped - Short Packet"; 931 case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR: 932 return "Max Exit Latency Too Large Error"; 933 case COMP_ISOCH_BUFFER_OVERRUN: 934 return "Isoch Buffer Overrun"; 935 case COMP_EVENT_LOST_ERROR: 936 return "Event Lost Error"; 937 case COMP_UNDEFINED_ERROR: 938 return "Undefined Error"; 939 case COMP_INVALID_STREAM_ID_ERROR: 940 return "Invalid Stream ID Error"; 941 case COMP_SECONDARY_BANDWIDTH_ERROR: 942 return "Secondary Bandwidth Error"; 943 case COMP_SPLIT_TRANSACTION_ERROR: 944 return "Split Transaction Error"; 945 default: 946 return "Unknown!!"; 947 } 948 } 949 950 struct xhci_link_trb { 951 /* 64-bit segment pointer*/ 952 __le64 segment_ptr; 953 __le32 intr_target; 954 __le32 control; 955 }; 956 957 /* control bitfields */ 958 #define LINK_TOGGLE (0x1<<1) 959 960 /* Command completion event TRB */ 961 struct xhci_event_cmd { 962 /* Pointer to command TRB, or the value passed by the event data trb */ 963 __le64 cmd_trb; 964 __le32 status; 965 __le32 flags; 966 }; 967 968 /* status bitmasks */ 969 #define COMP_PARAM(p) ((p) & 0xffffff) /* Command Completion Parameter */ 970 971 /* Address device - disable SetAddress */ 972 #define TRB_BSR (1<<9) 973 974 /* Configure Endpoint - Deconfigure */ 975 #define TRB_DC (1<<9) 976 977 /* Stop Ring - Transfer State Preserve */ 978 #define TRB_TSP (1<<9) 979 980 enum xhci_ep_reset_type { 981 EP_HARD_RESET, 982 EP_SOFT_RESET, 983 }; 984 985 /* Force Event */ 986 #define TRB_TO_VF_INTR_TARGET(p) (((p) & (0x3ff << 22)) >> 22) 987 #define TRB_TO_VF_ID(p) (((p) & (0xff << 16)) >> 16) 988 989 /* Set Latency Tolerance Value */ 990 #define TRB_TO_BELT(p) (((p) & (0xfff << 16)) >> 16) 991 992 /* Get Port Bandwidth */ 993 #define TRB_TO_DEV_SPEED(p) (((p) & (0xf << 16)) >> 16) 994 995 /* Force Header */ 996 #define TRB_TO_PACKET_TYPE(p) ((p) & 0x1f) 997 #define TRB_TO_ROOTHUB_PORT(p) (((p) & (0xff << 24)) >> 24) 998 999 enum xhci_setup_dev { 1000 SETUP_CONTEXT_ONLY, 1001 SETUP_CONTEXT_ADDRESS, 1002 }; 1003 1004 /* bits 16:23 are the virtual function ID */ 1005 /* bits 24:31 are the slot ID */ 1006 1007 /* bits 19:16 are the dev speed */ 1008 #define DEV_SPEED_FOR_TRB(p) ((p) << 16) 1009 1010 /* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */ 1011 #define SUSPEND_PORT_FOR_TRB(p) (((p) & 1) << 23) 1012 #define TRB_TO_SUSPEND_PORT(p) (((p) & (1 << 23)) >> 23) 1013 #define LAST_EP_INDEX 30 1014 1015 /* Set TR Dequeue Pointer command TRB fields, 6.4.3.9 */ 1016 #define TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16)) 1017 #define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16) 1018 #define SCT_FOR_TRB(p) (((p) & 0x7) << 1) 1019 1020 /* Link TRB specific fields */ 1021 #define TRB_TC (1<<1) 1022 1023 /* Port Status Change Event TRB fields */ 1024 /* Port ID - bits 31:24 */ 1025 #define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24) 1026 1027 #define EVENT_DATA (1 << 2) 1028 1029 /* Normal TRB fields */ 1030 /* transfer_len bitmasks - bits 0:16 */ 1031 #define TRB_LEN(p) ((p) & 0x1ffff) 1032 /* TD Size, packets remaining in this TD, bits 21:17 (5 bits, so max 31) */ 1033 #define TRB_TD_SIZE(p) (min((p), (u32)31) << 17) 1034 #define GET_TD_SIZE(p) (((p) & 0x3e0000) >> 17) 1035 /* xhci 1.1 uses the TD_SIZE field for TBC if Extended TBC is enabled (ETE) */ 1036 #define TRB_TD_SIZE_TBC(p) (min((p), (u32)31) << 17) 1037 /* Interrupter Target - which MSI-X vector to target the completion event at */ 1038 #define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22) 1039 #define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff) 1040 1041 /* Cycle bit - indicates TRB ownership by HC or HCD */ 1042 #define TRB_CYCLE (1<<0) 1043 /* 1044 * Force next event data TRB to be evaluated before task switch. 1045 * Used to pass OS data back after a TD completes. 1046 */ 1047 #define TRB_ENT (1<<1) 1048 /* Interrupt on short packet */ 1049 #define TRB_ISP (1<<2) 1050 /* Set PCIe no snoop attribute */ 1051 #define TRB_NO_SNOOP (1<<3) 1052 /* Chain multiple TRBs into a TD */ 1053 #define TRB_CHAIN (1<<4) 1054 /* Interrupt on completion */ 1055 #define TRB_IOC (1<<5) 1056 /* The buffer pointer contains immediate data */ 1057 #define TRB_IDT (1<<6) 1058 /* TDs smaller than this might use IDT */ 1059 #define TRB_IDT_MAX_SIZE 8 1060 1061 /* Block Event Interrupt */ 1062 #define TRB_BEI (1<<9) 1063 1064 /* Control transfer TRB specific fields */ 1065 #define TRB_DIR_IN (1<<16) 1066 #define TRB_TX_TYPE(p) ((p) << 16) 1067 #define TRB_DATA_OUT 2 1068 #define TRB_DATA_IN 3 1069 1070 /* Isochronous TRB specific fields */ 1071 #define TRB_SIA (1<<31) 1072 #define TRB_FRAME_ID(p) (((p) & 0x7ff) << 20) 1073 #define GET_FRAME_ID(p) (((p) >> 20) & 0x7ff) 1074 /* Total burst count field, Rsvdz on xhci 1.1 with Extended TBC enabled (ETE) */ 1075 #define TRB_TBC(p) (((p) & 0x3) << 7) 1076 #define GET_TBC(p) (((p) >> 7) & 0x3) 1077 #define TRB_TLBPC(p) (((p) & 0xf) << 16) 1078 #define GET_TLBPC(p) (((p) >> 16) & 0xf) 1079 1080 /* TRB cache size for xHC with TRB cache */ 1081 #define TRB_CACHE_SIZE_HS 8 1082 #define TRB_CACHE_SIZE_SS 16 1083 1084 struct xhci_generic_trb { 1085 __le32 field[4]; 1086 }; 1087 1088 union xhci_trb { 1089 struct xhci_link_trb link; 1090 struct xhci_transfer_event trans_event; 1091 struct xhci_event_cmd event_cmd; 1092 struct xhci_generic_trb generic; 1093 }; 1094 1095 /* TRB bit mask */ 1096 #define TRB_TYPE_BITMASK (0xfc00) 1097 #define TRB_TYPE(p) ((p) << 10) 1098 #define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10) 1099 /* TRB type IDs */ 1100 /* bulk, interrupt, isoc scatter/gather, and control data stage */ 1101 #define TRB_NORMAL 1 1102 /* setup stage for control transfers */ 1103 #define TRB_SETUP 2 1104 /* data stage for control transfers */ 1105 #define TRB_DATA 3 1106 /* status stage for control transfers */ 1107 #define TRB_STATUS 4 1108 /* isoc transfers */ 1109 #define TRB_ISOC 5 1110 /* TRB for linking ring segments */ 1111 #define TRB_LINK 6 1112 #define TRB_EVENT_DATA 7 1113 /* Transfer Ring No-op (not for the command ring) */ 1114 #define TRB_TR_NOOP 8 1115 /* Command TRBs */ 1116 /* Enable Slot Command */ 1117 #define TRB_ENABLE_SLOT 9 1118 /* Disable Slot Command */ 1119 #define TRB_DISABLE_SLOT 10 1120 /* Address Device Command */ 1121 #define TRB_ADDR_DEV 11 1122 /* Configure Endpoint Command */ 1123 #define TRB_CONFIG_EP 12 1124 /* Evaluate Context Command */ 1125 #define TRB_EVAL_CONTEXT 13 1126 /* Reset Endpoint Command */ 1127 #define TRB_RESET_EP 14 1128 /* Stop Transfer Ring Command */ 1129 #define TRB_STOP_RING 15 1130 /* Set Transfer Ring Dequeue Pointer Command */ 1131 #define TRB_SET_DEQ 16 1132 /* Reset Device Command */ 1133 #define TRB_RESET_DEV 17 1134 /* Force Event Command (opt) */ 1135 #define TRB_FORCE_EVENT 18 1136 /* Negotiate Bandwidth Command (opt) */ 1137 #define TRB_NEG_BANDWIDTH 19 1138 /* Set Latency Tolerance Value Command (opt) */ 1139 #define TRB_SET_LT 20 1140 /* Get port bandwidth Command */ 1141 #define TRB_GET_BW 21 1142 /* Force Header Command - generate a transaction or link management packet */ 1143 #define TRB_FORCE_HEADER 22 1144 /* No-op Command - not for transfer rings */ 1145 #define TRB_CMD_NOOP 23 1146 /* TRB IDs 24-31 reserved */ 1147 /* Event TRBS */ 1148 /* Transfer Event */ 1149 #define TRB_TRANSFER 32 1150 /* Command Completion Event */ 1151 #define TRB_COMPLETION 33 1152 /* Port Status Change Event */ 1153 #define TRB_PORT_STATUS 34 1154 /* Bandwidth Request Event (opt) */ 1155 #define TRB_BANDWIDTH_EVENT 35 1156 /* Doorbell Event (opt) */ 1157 #define TRB_DOORBELL 36 1158 /* Host Controller Event */ 1159 #define TRB_HC_EVENT 37 1160 /* Device Notification Event - device sent function wake notification */ 1161 #define TRB_DEV_NOTE 38 1162 /* MFINDEX Wrap Event - microframe counter wrapped */ 1163 #define TRB_MFINDEX_WRAP 39 1164 /* TRB IDs 40-47 reserved, 48-63 is vendor-defined */ 1165 #define TRB_VENDOR_DEFINED_LOW 48 1166 /* Nec vendor-specific command completion event. */ 1167 #define TRB_NEC_CMD_COMP 48 1168 /* Get NEC firmware revision. */ 1169 #define TRB_NEC_GET_FW 49 1170 1171 static inline const char *xhci_trb_type_string(u8 type) 1172 { 1173 switch (type) { 1174 case TRB_NORMAL: 1175 return "Normal"; 1176 case TRB_SETUP: 1177 return "Setup Stage"; 1178 case TRB_DATA: 1179 return "Data Stage"; 1180 case TRB_STATUS: 1181 return "Status Stage"; 1182 case TRB_ISOC: 1183 return "Isoch"; 1184 case TRB_LINK: 1185 return "Link"; 1186 case TRB_EVENT_DATA: 1187 return "Event Data"; 1188 case TRB_TR_NOOP: 1189 return "No-Op"; 1190 case TRB_ENABLE_SLOT: 1191 return "Enable Slot Command"; 1192 case TRB_DISABLE_SLOT: 1193 return "Disable Slot Command"; 1194 case TRB_ADDR_DEV: 1195 return "Address Device Command"; 1196 case TRB_CONFIG_EP: 1197 return "Configure Endpoint Command"; 1198 case TRB_EVAL_CONTEXT: 1199 return "Evaluate Context Command"; 1200 case TRB_RESET_EP: 1201 return "Reset Endpoint Command"; 1202 case TRB_STOP_RING: 1203 return "Stop Ring Command"; 1204 case TRB_SET_DEQ: 1205 return "Set TR Dequeue Pointer Command"; 1206 case TRB_RESET_DEV: 1207 return "Reset Device Command"; 1208 case TRB_FORCE_EVENT: 1209 return "Force Event Command"; 1210 case TRB_NEG_BANDWIDTH: 1211 return "Negotiate Bandwidth Command"; 1212 case TRB_SET_LT: 1213 return "Set Latency Tolerance Value Command"; 1214 case TRB_GET_BW: 1215 return "Get Port Bandwidth Command"; 1216 case TRB_FORCE_HEADER: 1217 return "Force Header Command"; 1218 case TRB_CMD_NOOP: 1219 return "No-Op Command"; 1220 case TRB_TRANSFER: 1221 return "Transfer Event"; 1222 case TRB_COMPLETION: 1223 return "Command Completion Event"; 1224 case TRB_PORT_STATUS: 1225 return "Port Status Change Event"; 1226 case TRB_BANDWIDTH_EVENT: 1227 return "Bandwidth Request Event"; 1228 case TRB_DOORBELL: 1229 return "Doorbell Event"; 1230 case TRB_HC_EVENT: 1231 return "Host Controller Event"; 1232 case TRB_DEV_NOTE: 1233 return "Device Notification Event"; 1234 case TRB_MFINDEX_WRAP: 1235 return "MFINDEX Wrap Event"; 1236 case TRB_NEC_CMD_COMP: 1237 return "NEC Command Completion Event"; 1238 case TRB_NEC_GET_FW: 1239 return "NET Get Firmware Revision Command"; 1240 default: 1241 return "UNKNOWN"; 1242 } 1243 } 1244 1245 #define TRB_TYPE_LINK(x) (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK)) 1246 /* Above, but for __le32 types -- can avoid work by swapping constants: */ 1247 #define TRB_TYPE_LINK_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \ 1248 cpu_to_le32(TRB_TYPE(TRB_LINK))) 1249 #define TRB_TYPE_NOOP_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \ 1250 cpu_to_le32(TRB_TYPE(TRB_TR_NOOP))) 1251 1252 #define NEC_FW_MINOR(p) (((p) >> 0) & 0xff) 1253 #define NEC_FW_MAJOR(p) (((p) >> 8) & 0xff) 1254 1255 /* 1256 * TRBS_PER_SEGMENT must be a multiple of 4, 1257 * since the command ring is 64-byte aligned. 1258 * It must also be greater than 16. 1259 */ 1260 #define TRBS_PER_SEGMENT 256 1261 /* Allow two commands + a link TRB, along with any reserved command TRBs */ 1262 #define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3) 1263 #define TRB_SEGMENT_SIZE (TRBS_PER_SEGMENT*16) 1264 #define TRB_SEGMENT_SHIFT (ilog2(TRB_SEGMENT_SIZE)) 1265 /* TRB buffer pointers can't cross 64KB boundaries */ 1266 #define TRB_MAX_BUFF_SHIFT 16 1267 #define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT) 1268 /* How much data is left before the 64KB boundary? */ 1269 #define TRB_BUFF_LEN_UP_TO_BOUNDARY(addr) (TRB_MAX_BUFF_SIZE - \ 1270 (addr & (TRB_MAX_BUFF_SIZE - 1))) 1271 #define MAX_SOFT_RETRY 3 1272 /* 1273 * Limits of consecutive isoc trbs that can Block Event Interrupt (BEI) if 1274 * XHCI_AVOID_BEI quirk is in use. 1275 */ 1276 #define AVOID_BEI_INTERVAL_MIN 8 1277 #define AVOID_BEI_INTERVAL_MAX 32 1278 1279 #define xhci_for_each_ring_seg(head, seg) \ 1280 for (seg = head; seg != NULL; seg = (seg->next != head ? seg->next : NULL)) 1281 1282 struct xhci_segment { 1283 union xhci_trb *trbs; 1284 /* private to HCD */ 1285 struct xhci_segment *next; 1286 unsigned int num; 1287 dma_addr_t dma; 1288 /* Max packet sized bounce buffer for td-fragmant alignment */ 1289 dma_addr_t bounce_dma; 1290 void *bounce_buf; 1291 unsigned int bounce_offs; 1292 unsigned int bounce_len; 1293 }; 1294 1295 enum xhci_cancelled_td_status { 1296 TD_DIRTY = 0, 1297 TD_HALTED, 1298 TD_CLEARING_CACHE, 1299 TD_CLEARING_CACHE_DEFERRED, 1300 TD_CLEARED, 1301 }; 1302 1303 struct xhci_td { 1304 struct list_head td_list; 1305 struct list_head cancelled_td_list; 1306 int status; 1307 enum xhci_cancelled_td_status cancel_status; 1308 struct urb *urb; 1309 struct xhci_segment *start_seg; 1310 union xhci_trb *start_trb; 1311 struct xhci_segment *end_seg; 1312 union xhci_trb *end_trb; 1313 struct xhci_segment *bounce_seg; 1314 /* actual_length of the URB has already been set */ 1315 bool urb_length_set; 1316 bool error_mid_td; 1317 }; 1318 1319 /* 1320 * xHCI command default timeout value in milliseconds. 1321 * USB 3.2 spec, section 9.2.6.1 1322 */ 1323 #define XHCI_CMD_DEFAULT_TIMEOUT 5000 1324 1325 /* command descriptor */ 1326 struct xhci_cd { 1327 struct xhci_command *command; 1328 union xhci_trb *cmd_trb; 1329 }; 1330 1331 enum xhci_ring_type { 1332 TYPE_CTRL = 0, 1333 TYPE_ISOC, 1334 TYPE_BULK, 1335 TYPE_INTR, 1336 TYPE_STREAM, 1337 TYPE_COMMAND, 1338 TYPE_EVENT, 1339 }; 1340 1341 static inline const char *xhci_ring_type_string(enum xhci_ring_type type) 1342 { 1343 switch (type) { 1344 case TYPE_CTRL: 1345 return "CTRL"; 1346 case TYPE_ISOC: 1347 return "ISOC"; 1348 case TYPE_BULK: 1349 return "BULK"; 1350 case TYPE_INTR: 1351 return "INTR"; 1352 case TYPE_STREAM: 1353 return "STREAM"; 1354 case TYPE_COMMAND: 1355 return "CMD"; 1356 case TYPE_EVENT: 1357 return "EVENT"; 1358 } 1359 1360 return "UNKNOWN"; 1361 } 1362 1363 struct xhci_ring { 1364 struct xhci_segment *first_seg; 1365 struct xhci_segment *last_seg; 1366 union xhci_trb *enqueue; 1367 struct xhci_segment *enq_seg; 1368 union xhci_trb *dequeue; 1369 struct xhci_segment *deq_seg; 1370 struct list_head td_list; 1371 /* 1372 * Write the cycle state into the TRB cycle field to give ownership of 1373 * the TRB to the host controller (if we are the producer), or to check 1374 * if we own the TRB (if we are the consumer). See section 4.9.1. 1375 */ 1376 u32 cycle_state; 1377 unsigned int stream_id; 1378 unsigned int num_segs; 1379 unsigned int num_trbs_free; /* used only by xhci DbC */ 1380 unsigned int bounce_buf_len; 1381 enum xhci_ring_type type; 1382 u32 old_trb_comp_code; 1383 struct radix_tree_root *trb_address_map; 1384 }; 1385 1386 struct xhci_erst_entry { 1387 /* 64-bit event ring segment address */ 1388 __le64 seg_addr; 1389 __le32 seg_size; 1390 /* Set to zero */ 1391 __le32 rsvd; 1392 }; 1393 1394 struct xhci_erst { 1395 struct xhci_erst_entry *entries; 1396 unsigned int num_entries; 1397 /* xhci->event_ring keeps track of segment dma addresses */ 1398 dma_addr_t erst_dma_addr; 1399 }; 1400 1401 struct xhci_scratchpad { 1402 u64 *sp_array; 1403 dma_addr_t sp_dma; 1404 void **sp_buffers; 1405 }; 1406 1407 struct urb_priv { 1408 int num_tds; 1409 int num_tds_done; 1410 struct xhci_td td[] __counted_by(num_tds); 1411 }; 1412 1413 /* Number of Event Ring segments to allocate, when amount is not specified. (spec allows 32k) */ 1414 #define ERST_DEFAULT_SEGS 2 1415 /* Poll every 60 seconds */ 1416 #define POLL_TIMEOUT 60 1417 /* Stop endpoint command timeout (secs) for URB cancellation watchdog timer */ 1418 #define XHCI_STOP_EP_CMD_TIMEOUT 5 1419 /* XXX: Make these module parameters */ 1420 1421 struct s3_save { 1422 u32 command; 1423 u32 dev_nt; 1424 u64 dcbaa_ptr; 1425 u32 config_reg; 1426 }; 1427 1428 /* Use for lpm */ 1429 struct dev_info { 1430 u32 dev_id; 1431 struct list_head list; 1432 }; 1433 1434 struct xhci_bus_state { 1435 unsigned long bus_suspended; 1436 unsigned long next_statechange; 1437 1438 /* Port suspend arrays are indexed by the portnum of the fake roothub */ 1439 /* ports suspend status arrays - max 31 ports for USB2, 15 for USB3 */ 1440 u32 port_c_suspend; 1441 u32 suspended_ports; 1442 u32 port_remote_wakeup; 1443 /* which ports have started to resume */ 1444 unsigned long resuming_ports; 1445 }; 1446 1447 struct xhci_interrupter { 1448 struct xhci_ring *event_ring; 1449 struct xhci_erst erst; 1450 struct xhci_intr_reg __iomem *ir_set; 1451 unsigned int intr_num; 1452 bool ip_autoclear; 1453 u32 isoc_bei_interval; 1454 /* For interrupter registers save and restore over suspend/resume */ 1455 u32 s3_iman; 1456 u32 s3_imod; 1457 u32 s3_erst_size; 1458 u64 s3_erst_base; 1459 u64 s3_erst_dequeue; 1460 }; 1461 /* 1462 * It can take up to 20 ms to transition from RExit to U0 on the 1463 * Intel Lynx Point LP xHCI host. 1464 */ 1465 #define XHCI_MAX_REXIT_TIMEOUT_MS 20 1466 struct xhci_port_cap { 1467 u32 *psi; /* array of protocol speed ID entries */ 1468 u8 psi_count; 1469 u8 psi_uid_count; 1470 u8 maj_rev; 1471 u8 min_rev; 1472 u32 protocol_caps; 1473 }; 1474 1475 struct xhci_port { 1476 __le32 __iomem *addr; 1477 int hw_portnum; 1478 int hcd_portnum; 1479 struct xhci_hub *rhub; 1480 struct xhci_port_cap *port_cap; 1481 unsigned int lpm_incapable:1; 1482 unsigned long resume_timestamp; 1483 bool rexit_active; 1484 /* Slot ID is the index of the device directly connected to the port */ 1485 int slot_id; 1486 struct completion rexit_done; 1487 struct completion u3exit_done; 1488 }; 1489 1490 struct xhci_hub { 1491 struct xhci_port **ports; 1492 unsigned int num_ports; 1493 struct usb_hcd *hcd; 1494 /* keep track of bus suspend info */ 1495 struct xhci_bus_state bus_state; 1496 /* supported prococol extended capabiliy values */ 1497 u8 maj_rev; 1498 u8 min_rev; 1499 }; 1500 1501 /* There is one xhci_hcd structure per controller */ 1502 struct xhci_hcd { 1503 struct usb_hcd *main_hcd; 1504 struct usb_hcd *shared_hcd; 1505 /* glue to PCI and HCD framework */ 1506 struct xhci_cap_regs __iomem *cap_regs; 1507 struct xhci_op_regs __iomem *op_regs; 1508 struct xhci_run_regs __iomem *run_regs; 1509 struct xhci_doorbell_array __iomem *dba; 1510 1511 /* Cached register copies of read-only HC data */ 1512 __u32 hcs_params1; 1513 __u32 hcs_params2; 1514 __u32 hcs_params3; 1515 __u32 hcc_params; 1516 __u32 hcc_params2; 1517 1518 spinlock_t lock; 1519 1520 /* packed release number */ 1521 u16 hci_version; 1522 u16 max_interrupters; 1523 /* imod_interval in ns (I * 250ns) */ 1524 u32 imod_interval; 1525 u32 page_size; 1526 /* MSI-X/MSI vectors */ 1527 int nvecs; 1528 /* optional clocks */ 1529 struct clk *clk; 1530 struct clk *reg_clk; 1531 /* optional reset controller */ 1532 struct reset_control *reset; 1533 /* data structures */ 1534 struct xhci_device_context_array *dcbaa; 1535 struct xhci_interrupter **interrupters; 1536 struct xhci_ring *cmd_ring; 1537 unsigned int cmd_ring_state; 1538 #define CMD_RING_STATE_RUNNING (1 << 0) 1539 #define CMD_RING_STATE_ABORTED (1 << 1) 1540 #define CMD_RING_STATE_STOPPED (1 << 2) 1541 struct list_head cmd_list; 1542 unsigned int cmd_ring_reserved_trbs; 1543 struct delayed_work cmd_timer; 1544 struct completion cmd_ring_stop_completion; 1545 struct xhci_command *current_cmd; 1546 1547 /* Scratchpad */ 1548 struct xhci_scratchpad *scratchpad; 1549 1550 /* slot enabling and address device helpers */ 1551 /* these are not thread safe so use mutex */ 1552 struct mutex mutex; 1553 /* Internal mirror of the HW's dcbaa */ 1554 struct xhci_virt_device *devs[MAX_HC_SLOTS]; 1555 /* For keeping track of bandwidth domains per roothub. */ 1556 struct xhci_root_port_bw_info *rh_bw; 1557 1558 /* DMA pools */ 1559 struct dma_pool *device_pool; 1560 struct dma_pool *segment_pool; 1561 struct dma_pool *small_streams_pool; 1562 struct dma_pool *port_bw_pool; 1563 struct dma_pool *medium_streams_pool; 1564 1565 /* Host controller watchdog timer structures */ 1566 unsigned int xhc_state; 1567 unsigned long run_graceperiod; 1568 struct s3_save s3; 1569 /* Host controller is dying - not responding to commands. "I'm not dead yet!" 1570 * 1571 * xHC interrupts have been disabled and a watchdog timer will (or has already) 1572 * halt the xHCI host, and complete all URBs with an -ESHUTDOWN code. Any code 1573 * that sees this status (other than the timer that set it) should stop touching 1574 * hardware immediately. Interrupt handlers should return immediately when 1575 * they see this status (any time they drop and re-acquire xhci->lock). 1576 * xhci_urb_dequeue() should call usb_hcd_check_unlink_urb() and return without 1577 * putting the TD on the canceled list, etc. 1578 * 1579 * There are no reports of xHCI host controllers that display this issue. 1580 */ 1581 #define XHCI_STATE_DYING (1 << 0) 1582 #define XHCI_STATE_HALTED (1 << 1) 1583 #define XHCI_STATE_REMOVING (1 << 2) 1584 unsigned long long quirks; 1585 #define XHCI_LINK_TRB_QUIRK BIT_ULL(0) 1586 #define XHCI_RESET_EP_QUIRK BIT_ULL(1) /* Deprecated */ 1587 #define XHCI_NEC_HOST BIT_ULL(2) 1588 #define XHCI_AMD_PLL_FIX BIT_ULL(3) 1589 #define XHCI_SPURIOUS_SUCCESS BIT_ULL(4) 1590 /* 1591 * Certain Intel host controllers have a limit to the number of endpoint 1592 * contexts they can handle. Ideally, they would signal that they can't handle 1593 * anymore endpoint contexts by returning a Resource Error for the Configure 1594 * Endpoint command, but they don't. Instead they expect software to keep track 1595 * of the number of active endpoints for them, across configure endpoint 1596 * commands, reset device commands, disable slot commands, and address device 1597 * commands. 1598 */ 1599 #define XHCI_EP_LIMIT_QUIRK BIT_ULL(5) 1600 #define XHCI_BROKEN_MSI BIT_ULL(6) 1601 #define XHCI_RESET_ON_RESUME BIT_ULL(7) 1602 #define XHCI_SW_BW_CHECKING BIT_ULL(8) 1603 #define XHCI_AMD_0x96_HOST BIT_ULL(9) 1604 #define XHCI_TRUST_TX_LENGTH BIT_ULL(10) /* Deprecated */ 1605 #define XHCI_LPM_SUPPORT BIT_ULL(11) 1606 #define XHCI_INTEL_HOST BIT_ULL(12) 1607 #define XHCI_SPURIOUS_REBOOT BIT_ULL(13) 1608 #define XHCI_COMP_MODE_QUIRK BIT_ULL(14) 1609 #define XHCI_AVOID_BEI BIT_ULL(15) 1610 #define XHCI_PLAT BIT_ULL(16) /* Deprecated */ 1611 #define XHCI_SLOW_SUSPEND BIT_ULL(17) 1612 #define XHCI_SPURIOUS_WAKEUP BIT_ULL(18) 1613 /* For controllers with a broken beyond repair streams implementation */ 1614 #define XHCI_BROKEN_STREAMS BIT_ULL(19) 1615 #define XHCI_PME_STUCK_QUIRK BIT_ULL(20) 1616 #define XHCI_MTK_HOST BIT_ULL(21) 1617 #define XHCI_SSIC_PORT_UNUSED BIT_ULL(22) 1618 #define XHCI_NO_64BIT_SUPPORT BIT_ULL(23) 1619 #define XHCI_MISSING_CAS BIT_ULL(24) 1620 /* For controller with a broken Port Disable implementation */ 1621 #define XHCI_BROKEN_PORT_PED BIT_ULL(25) 1622 #define XHCI_LIMIT_ENDPOINT_INTERVAL_7 BIT_ULL(26) 1623 #define XHCI_U2_DISABLE_WAKE BIT_ULL(27) 1624 #define XHCI_ASMEDIA_MODIFY_FLOWCONTROL BIT_ULL(28) 1625 #define XHCI_HW_LPM_DISABLE BIT_ULL(29) 1626 #define XHCI_SUSPEND_DELAY BIT_ULL(30) 1627 #define XHCI_INTEL_USB_ROLE_SW BIT_ULL(31) 1628 #define XHCI_ZERO_64B_REGS BIT_ULL(32) 1629 #define XHCI_DEFAULT_PM_RUNTIME_ALLOW BIT_ULL(33) 1630 #define XHCI_RESET_PLL_ON_DISCONNECT BIT_ULL(34) 1631 #define XHCI_SNPS_BROKEN_SUSPEND BIT_ULL(35) 1632 /* Reserved. It was XHCI_RENESAS_FW_QUIRK */ 1633 #define XHCI_SKIP_PHY_INIT BIT_ULL(37) 1634 #define XHCI_DISABLE_SPARSE BIT_ULL(38) 1635 #define XHCI_SG_TRB_CACHE_SIZE_QUIRK BIT_ULL(39) 1636 #define XHCI_NO_SOFT_RETRY BIT_ULL(40) 1637 #define XHCI_BROKEN_D3COLD_S2I BIT_ULL(41) 1638 #define XHCI_EP_CTX_BROKEN_DCS BIT_ULL(42) 1639 #define XHCI_SUSPEND_RESUME_CLKS BIT_ULL(43) 1640 #define XHCI_RESET_TO_DEFAULT BIT_ULL(44) 1641 #define XHCI_TRB_OVERFETCH BIT_ULL(45) 1642 #define XHCI_ZHAOXIN_HOST BIT_ULL(46) 1643 #define XHCI_WRITE_64_HI_LO BIT_ULL(47) 1644 #define XHCI_CDNS_SCTX_QUIRK BIT_ULL(48) 1645 #define XHCI_ETRON_HOST BIT_ULL(49) 1646 1647 unsigned int num_active_eps; 1648 unsigned int limit_active_eps; 1649 struct xhci_port *hw_ports; 1650 struct xhci_hub usb2_rhub; 1651 struct xhci_hub usb3_rhub; 1652 /* support xHCI 1.0 spec USB2 hardware LPM */ 1653 unsigned hw_lpm_support:1; 1654 /* Broken Suspend flag for SNPS Suspend resume issue */ 1655 unsigned broken_suspend:1; 1656 /* Indicates that omitting hcd is supported if root hub has no ports */ 1657 unsigned allow_single_roothub:1; 1658 /* cached extended protocol port capabilities */ 1659 struct xhci_port_cap *port_caps; 1660 unsigned int num_port_caps; 1661 /* Compliance Mode Recovery Data */ 1662 struct timer_list comp_mode_recovery_timer; 1663 u32 port_status_u0; 1664 u16 test_mode; 1665 /* Compliance Mode Timer Triggered every 2 seconds */ 1666 #define COMP_MODE_RCVRY_MSECS 2000 1667 1668 struct dentry *debugfs_root; 1669 struct dentry *debugfs_slots; 1670 struct list_head regset_list; 1671 1672 void *dbc; 1673 /* platform-specific data -- must come last */ 1674 unsigned long priv[] __aligned(sizeof(s64)); 1675 }; 1676 1677 /* Platform specific overrides to generic XHCI hc_driver ops */ 1678 struct xhci_driver_overrides { 1679 size_t extra_priv_size; 1680 int (*reset)(struct usb_hcd *hcd); 1681 int (*start)(struct usb_hcd *hcd); 1682 int (*add_endpoint)(struct usb_hcd *hcd, struct usb_device *udev, 1683 struct usb_host_endpoint *ep); 1684 int (*drop_endpoint)(struct usb_hcd *hcd, struct usb_device *udev, 1685 struct usb_host_endpoint *ep); 1686 int (*check_bandwidth)(struct usb_hcd *, struct usb_device *); 1687 void (*reset_bandwidth)(struct usb_hcd *, struct usb_device *); 1688 int (*update_hub_device)(struct usb_hcd *hcd, struct usb_device *hdev, 1689 struct usb_tt *tt, gfp_t mem_flags); 1690 int (*hub_control)(struct usb_hcd *hcd, u16 typeReq, u16 wValue, 1691 u16 wIndex, char *buf, u16 wLength); 1692 }; 1693 1694 #define XHCI_CFC_DELAY 10 1695 1696 /* convert between an HCD pointer and the corresponding EHCI_HCD */ 1697 static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd) 1698 { 1699 struct usb_hcd *primary_hcd; 1700 1701 if (usb_hcd_is_primary_hcd(hcd)) 1702 primary_hcd = hcd; 1703 else 1704 primary_hcd = hcd->primary_hcd; 1705 1706 return (struct xhci_hcd *) (primary_hcd->hcd_priv); 1707 } 1708 1709 static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci) 1710 { 1711 return xhci->main_hcd; 1712 } 1713 1714 static inline struct usb_hcd *xhci_get_usb3_hcd(struct xhci_hcd *xhci) 1715 { 1716 if (xhci->shared_hcd) 1717 return xhci->shared_hcd; 1718 1719 if (!xhci->usb2_rhub.num_ports) 1720 return xhci->main_hcd; 1721 1722 return NULL; 1723 } 1724 1725 static inline bool xhci_hcd_is_usb3(struct usb_hcd *hcd) 1726 { 1727 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 1728 1729 return hcd == xhci_get_usb3_hcd(xhci); 1730 } 1731 1732 static inline bool xhci_has_one_roothub(struct xhci_hcd *xhci) 1733 { 1734 return xhci->allow_single_roothub && 1735 (!xhci->usb2_rhub.num_ports || !xhci->usb3_rhub.num_ports); 1736 } 1737 1738 #define xhci_dbg(xhci, fmt, args...) \ 1739 dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1740 #define xhci_err(xhci, fmt, args...) \ 1741 dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1742 #define xhci_warn(xhci, fmt, args...) \ 1743 dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1744 #define xhci_info(xhci, fmt, args...) \ 1745 dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1746 1747 /* 1748 * Registers should always be accessed with double word or quad word accesses. 1749 * 1750 * Some xHCI implementations may support 64-bit address pointers. Registers 1751 * with 64-bit address pointers should be written to with dword accesses by 1752 * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second. 1753 * xHCI implementations that do not support 64-bit address pointers will ignore 1754 * the high dword, and write order is irrelevant. 1755 */ 1756 static inline u64 xhci_read_64(const struct xhci_hcd *xhci, 1757 __le64 __iomem *regs) 1758 { 1759 return lo_hi_readq(regs); 1760 } 1761 static inline void xhci_write_64(struct xhci_hcd *xhci, 1762 const u64 val, __le64 __iomem *regs) 1763 { 1764 lo_hi_writeq(val, regs); 1765 } 1766 1767 1768 /* 1769 * Reportedly, some chapters of v0.95 spec said that Link TRB always has its chain bit set. 1770 * Other chapters and later specs say that it should only be set if the link is inside a TD 1771 * which continues from the end of one segment to the next segment. 1772 * 1773 * Some 0.95 hardware was found to misbehave if any link TRB doesn't have the chain bit set. 1774 * 1775 * 0.96 hardware from AMD and NEC was found to ignore unchained isochronous link TRBs when 1776 * "resynchronizing the pipe" after a Missed Service Error. 1777 */ 1778 static inline bool xhci_link_chain_quirk(struct xhci_hcd *xhci, enum xhci_ring_type type) 1779 { 1780 return (xhci->quirks & XHCI_LINK_TRB_QUIRK) || 1781 (type == TYPE_ISOC && (xhci->quirks & (XHCI_AMD_0x96_HOST | XHCI_NEC_HOST))); 1782 } 1783 1784 /* xHCI debugging */ 1785 char *xhci_get_slot_state(struct xhci_hcd *xhci, 1786 struct xhci_container_ctx *ctx); 1787 void xhci_dbg_trace(struct xhci_hcd *xhci, void (*trace)(struct va_format *), 1788 const char *fmt, ...); 1789 1790 /* xHCI memory management */ 1791 void xhci_mem_cleanup(struct xhci_hcd *xhci); 1792 int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags); 1793 void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id); 1794 int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags); 1795 int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev); 1796 void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci, 1797 struct usb_device *udev); 1798 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc); 1799 unsigned int xhci_last_valid_endpoint(u32 added_ctxs); 1800 void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep); 1801 void xhci_update_tt_active_eps(struct xhci_hcd *xhci, 1802 struct xhci_virt_device *virt_dev, 1803 int old_active_eps); 1804 void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info); 1805 void xhci_update_bw_info(struct xhci_hcd *xhci, 1806 struct xhci_container_ctx *in_ctx, 1807 struct xhci_input_control_ctx *ctrl_ctx, 1808 struct xhci_virt_device *virt_dev); 1809 void xhci_endpoint_copy(struct xhci_hcd *xhci, 1810 struct xhci_container_ctx *in_ctx, 1811 struct xhci_container_ctx *out_ctx, 1812 unsigned int ep_index); 1813 void xhci_slot_copy(struct xhci_hcd *xhci, 1814 struct xhci_container_ctx *in_ctx, 1815 struct xhci_container_ctx *out_ctx); 1816 int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, 1817 struct usb_device *udev, struct usb_host_endpoint *ep, 1818 gfp_t mem_flags); 1819 struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci, unsigned int num_segs, 1820 enum xhci_ring_type type, unsigned int max_packet, gfp_t flags); 1821 void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring); 1822 int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring, 1823 unsigned int num_trbs, gfp_t flags); 1824 void xhci_initialize_ring_info(struct xhci_ring *ring); 1825 void xhci_free_endpoint_ring(struct xhci_hcd *xhci, 1826 struct xhci_virt_device *virt_dev, 1827 unsigned int ep_index); 1828 struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci, 1829 unsigned int num_stream_ctxs, 1830 unsigned int num_streams, 1831 unsigned int max_packet, gfp_t flags); 1832 void xhci_free_stream_info(struct xhci_hcd *xhci, 1833 struct xhci_stream_info *stream_info); 1834 void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci, 1835 struct xhci_ep_ctx *ep_ctx, 1836 struct xhci_stream_info *stream_info); 1837 void xhci_setup_no_streams_ep_input_ctx(struct xhci_ep_ctx *ep_ctx, 1838 struct xhci_virt_ep *ep); 1839 void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci, 1840 struct xhci_virt_device *virt_dev, bool drop_control_ep); 1841 struct xhci_ring *xhci_dma_to_transfer_ring( 1842 struct xhci_virt_ep *ep, 1843 u64 address); 1844 struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci, 1845 bool allocate_completion, gfp_t mem_flags); 1846 struct xhci_command *xhci_alloc_command_with_ctx(struct xhci_hcd *xhci, 1847 bool allocate_completion, gfp_t mem_flags); 1848 void xhci_urb_free_priv(struct urb_priv *urb_priv); 1849 void xhci_free_command(struct xhci_hcd *xhci, 1850 struct xhci_command *command); 1851 struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci, 1852 int type, gfp_t flags); 1853 void xhci_free_container_ctx(struct xhci_hcd *xhci, 1854 struct xhci_container_ctx *ctx); 1855 struct xhci_container_ctx *xhci_alloc_port_bw_ctx(struct xhci_hcd *xhci, 1856 gfp_t flags); 1857 void xhci_free_port_bw_ctx(struct xhci_hcd *xhci, 1858 struct xhci_container_ctx *ctx); 1859 struct xhci_interrupter * 1860 xhci_create_secondary_interrupter(struct usb_hcd *hcd, unsigned int segs, 1861 u32 imod_interval, unsigned int intr_num); 1862 void xhci_remove_secondary_interrupter(struct usb_hcd 1863 *hcd, struct xhci_interrupter *ir); 1864 void xhci_skip_sec_intr_events(struct xhci_hcd *xhci, 1865 struct xhci_ring *ring, 1866 struct xhci_interrupter *ir); 1867 1868 /* xHCI host controller glue */ 1869 typedef void (*xhci_get_quirks_t)(struct device *, struct xhci_hcd *); 1870 int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, u64 timeout_us); 1871 int xhci_handshake_check_state(struct xhci_hcd *xhci, void __iomem *ptr, 1872 u32 mask, u32 done, int usec, unsigned int exit_state); 1873 void xhci_quiesce(struct xhci_hcd *xhci); 1874 int xhci_halt(struct xhci_hcd *xhci); 1875 int xhci_start(struct xhci_hcd *xhci); 1876 int xhci_reset(struct xhci_hcd *xhci, u64 timeout_us); 1877 int xhci_run(struct usb_hcd *hcd); 1878 int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks); 1879 void xhci_shutdown(struct usb_hcd *hcd); 1880 void xhci_stop(struct usb_hcd *hcd); 1881 void xhci_init_driver(struct hc_driver *drv, 1882 const struct xhci_driver_overrides *over); 1883 int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev, 1884 struct usb_host_endpoint *ep); 1885 int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev, 1886 struct usb_host_endpoint *ep); 1887 int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev); 1888 void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev); 1889 int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev, 1890 struct usb_tt *tt, gfp_t mem_flags); 1891 int xhci_disable_slot(struct xhci_hcd *xhci, u32 slot_id); 1892 int xhci_ext_cap_init(struct xhci_hcd *xhci); 1893 1894 int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup); 1895 int xhci_resume(struct xhci_hcd *xhci, bool power_lost, bool is_auto_resume); 1896 1897 irqreturn_t xhci_irq(struct usb_hcd *hcd); 1898 irqreturn_t xhci_msi_irq(int irq, void *hcd); 1899 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev); 1900 int xhci_alloc_tt_info(struct xhci_hcd *xhci, 1901 struct xhci_virt_device *virt_dev, 1902 struct usb_device *hdev, 1903 struct usb_tt *tt, gfp_t mem_flags); 1904 int xhci_set_interrupter_moderation(struct xhci_interrupter *ir, 1905 u32 imod_interval); 1906 int xhci_enable_interrupter(struct xhci_interrupter *ir); 1907 int xhci_disable_interrupter(struct xhci_hcd *xhci, struct xhci_interrupter *ir); 1908 1909 /* xHCI ring, segment, TRB, and TD functions */ 1910 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb); 1911 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code); 1912 void xhci_ring_cmd_db(struct xhci_hcd *xhci); 1913 int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd, 1914 u32 trb_type, u32 slot_id); 1915 int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd, 1916 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev); 1917 int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd, 1918 u32 field1, u32 field2, u32 field3, u32 field4); 1919 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd, 1920 int slot_id, unsigned int ep_index, int suspend); 1921 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, 1922 int slot_id, unsigned int ep_index); 1923 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, 1924 int slot_id, unsigned int ep_index); 1925 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, 1926 int slot_id, unsigned int ep_index); 1927 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags, 1928 struct urb *urb, int slot_id, unsigned int ep_index); 1929 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, 1930 struct xhci_command *cmd, dma_addr_t in_ctx_ptr, u32 slot_id, 1931 bool command_must_succeed); 1932 int xhci_queue_get_port_bw(struct xhci_hcd *xhci, 1933 struct xhci_command *cmd, dma_addr_t in_ctx_ptr, 1934 u8 dev_speed, bool command_must_succeed); 1935 int xhci_get_port_bandwidth(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, 1936 u8 dev_speed); 1937 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd, 1938 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed); 1939 int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd, 1940 int slot_id, unsigned int ep_index, 1941 enum xhci_ep_reset_type reset_type); 1942 int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd, 1943 u32 slot_id); 1944 void xhci_handle_command_timeout(struct work_struct *work); 1945 1946 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, unsigned int slot_id, 1947 unsigned int ep_index, unsigned int stream_id); 1948 void xhci_ring_doorbell_for_active_rings(struct xhci_hcd *xhci, 1949 unsigned int slot_id, 1950 unsigned int ep_index); 1951 void xhci_cleanup_command_queue(struct xhci_hcd *xhci); 1952 void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring); 1953 unsigned int count_trbs(u64 addr, u64 len); 1954 int xhci_stop_endpoint_sync(struct xhci_hcd *xhci, struct xhci_virt_ep *ep, 1955 int suspend, gfp_t gfp_flags); 1956 void xhci_process_cancelled_tds(struct xhci_virt_ep *ep); 1957 void xhci_update_erst_dequeue(struct xhci_hcd *xhci, 1958 struct xhci_interrupter *ir, 1959 bool clear_ehb); 1960 void xhci_add_interrupter(struct xhci_hcd *xhci, unsigned int intr_num); 1961 1962 /* xHCI roothub code */ 1963 void xhci_set_link_state(struct xhci_hcd *xhci, struct xhci_port *port, 1964 u32 link_state); 1965 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, struct xhci_port *port, 1966 u32 port_bit); 1967 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex, 1968 char *buf, u16 wLength); 1969 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf); 1970 int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1); 1971 struct xhci_hub *xhci_get_rhub(struct usb_hcd *hcd); 1972 enum usb_link_tunnel_mode xhci_port_is_tunneled(struct xhci_hcd *xhci, 1973 struct xhci_port *port); 1974 void xhci_hc_died(struct xhci_hcd *xhci); 1975 1976 #ifdef CONFIG_PM 1977 int xhci_bus_suspend(struct usb_hcd *hcd); 1978 int xhci_bus_resume(struct usb_hcd *hcd); 1979 unsigned long xhci_get_resuming_ports(struct usb_hcd *hcd); 1980 #else 1981 #define xhci_bus_suspend NULL 1982 #define xhci_bus_resume NULL 1983 #define xhci_get_resuming_ports NULL 1984 #endif /* CONFIG_PM */ 1985 1986 u32 xhci_port_state_to_neutral(u32 state); 1987 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id); 1988 1989 /* xHCI contexts */ 1990 struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_container_ctx *ctx); 1991 struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx); 1992 struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index); 1993 1994 struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci, 1995 unsigned int slot_id, unsigned int ep_index, 1996 unsigned int stream_id); 1997 1998 static inline struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci, 1999 struct urb *urb) 2000 { 2001 return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id, 2002 xhci_get_endpoint_index(&urb->ep->desc), 2003 urb->stream_id); 2004 } 2005 2006 /* 2007 * TODO: As per spec Isochronous IDT transmissions are supported. We bypass 2008 * them anyways as we where unable to find a device that matches the 2009 * constraints. 2010 */ 2011 static inline bool xhci_urb_suitable_for_idt(struct urb *urb) 2012 { 2013 if (!usb_endpoint_xfer_isoc(&urb->ep->desc) && usb_urb_dir_out(urb) && 2014 usb_endpoint_maxp(&urb->ep->desc) >= TRB_IDT_MAX_SIZE && 2015 urb->transfer_buffer_length <= TRB_IDT_MAX_SIZE && 2016 !(urb->transfer_flags & URB_NO_TRANSFER_DMA_MAP) && 2017 !urb->num_sgs) 2018 return true; 2019 2020 return false; 2021 } 2022 2023 static inline char *xhci_slot_state_string(u32 state) 2024 { 2025 switch (state) { 2026 case SLOT_STATE_ENABLED: 2027 return "enabled/disabled"; 2028 case SLOT_STATE_DEFAULT: 2029 return "default"; 2030 case SLOT_STATE_ADDRESSED: 2031 return "addressed"; 2032 case SLOT_STATE_CONFIGURED: 2033 return "configured"; 2034 default: 2035 return "reserved"; 2036 } 2037 } 2038 2039 static inline const char *xhci_decode_trb(char *str, size_t size, 2040 u32 field0, u32 field1, u32 field2, u32 field3) 2041 { 2042 int type = TRB_FIELD_TO_TYPE(field3); 2043 2044 switch (type) { 2045 case TRB_LINK: 2046 snprintf(str, size, 2047 "LINK %08x%08x intr %d type '%s' flags %c:%c:%c:%c", 2048 field1, field0, GET_INTR_TARGET(field2), 2049 xhci_trb_type_string(type), 2050 field3 & TRB_IOC ? 'I' : 'i', 2051 field3 & TRB_CHAIN ? 'C' : 'c', 2052 field3 & TRB_TC ? 'T' : 't', 2053 field3 & TRB_CYCLE ? 'C' : 'c'); 2054 break; 2055 case TRB_TRANSFER: 2056 case TRB_COMPLETION: 2057 case TRB_PORT_STATUS: 2058 case TRB_BANDWIDTH_EVENT: 2059 case TRB_DOORBELL: 2060 case TRB_HC_EVENT: 2061 case TRB_DEV_NOTE: 2062 case TRB_MFINDEX_WRAP: 2063 snprintf(str, size, 2064 "TRB %08x%08x status '%s' len %d slot %d ep %d type '%s' flags %c:%c", 2065 field1, field0, 2066 xhci_trb_comp_code_string(GET_COMP_CODE(field2)), 2067 EVENT_TRB_LEN(field2), TRB_TO_SLOT_ID(field3), 2068 TRB_TO_EP_ID(field3), 2069 xhci_trb_type_string(type), 2070 field3 & EVENT_DATA ? 'E' : 'e', 2071 field3 & TRB_CYCLE ? 'C' : 'c'); 2072 2073 break; 2074 case TRB_SETUP: 2075 snprintf(str, size, 2076 "bRequestType %02x bRequest %02x wValue %02x%02x wIndex %02x%02x wLength %d length %d TD size %d intr %d type '%s' flags %c:%c:%c", 2077 field0 & 0xff, 2078 (field0 & 0xff00) >> 8, 2079 (field0 & 0xff000000) >> 24, 2080 (field0 & 0xff0000) >> 16, 2081 (field1 & 0xff00) >> 8, 2082 field1 & 0xff, 2083 (field1 & 0xff000000) >> 16 | 2084 (field1 & 0xff0000) >> 16, 2085 TRB_LEN(field2), GET_TD_SIZE(field2), 2086 GET_INTR_TARGET(field2), 2087 xhci_trb_type_string(type), 2088 field3 & TRB_IDT ? 'I' : 'i', 2089 field3 & TRB_IOC ? 'I' : 'i', 2090 field3 & TRB_CYCLE ? 'C' : 'c'); 2091 break; 2092 case TRB_DATA: 2093 snprintf(str, size, 2094 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c", 2095 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2), 2096 GET_INTR_TARGET(field2), 2097 xhci_trb_type_string(type), 2098 field3 & TRB_IDT ? 'I' : 'i', 2099 field3 & TRB_IOC ? 'I' : 'i', 2100 field3 & TRB_CHAIN ? 'C' : 'c', 2101 field3 & TRB_NO_SNOOP ? 'S' : 's', 2102 field3 & TRB_ISP ? 'I' : 'i', 2103 field3 & TRB_ENT ? 'E' : 'e', 2104 field3 & TRB_CYCLE ? 'C' : 'c'); 2105 break; 2106 case TRB_STATUS: 2107 snprintf(str, size, 2108 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c", 2109 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2), 2110 GET_INTR_TARGET(field2), 2111 xhci_trb_type_string(type), 2112 field3 & TRB_IOC ? 'I' : 'i', 2113 field3 & TRB_CHAIN ? 'C' : 'c', 2114 field3 & TRB_ENT ? 'E' : 'e', 2115 field3 & TRB_CYCLE ? 'C' : 'c'); 2116 break; 2117 case TRB_NORMAL: 2118 case TRB_EVENT_DATA: 2119 case TRB_TR_NOOP: 2120 snprintf(str, size, 2121 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c:%c", 2122 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2), 2123 GET_INTR_TARGET(field2), 2124 xhci_trb_type_string(type), 2125 field3 & TRB_BEI ? 'B' : 'b', 2126 field3 & TRB_IDT ? 'I' : 'i', 2127 field3 & TRB_IOC ? 'I' : 'i', 2128 field3 & TRB_CHAIN ? 'C' : 'c', 2129 field3 & TRB_NO_SNOOP ? 'S' : 's', 2130 field3 & TRB_ISP ? 'I' : 'i', 2131 field3 & TRB_ENT ? 'E' : 'e', 2132 field3 & TRB_CYCLE ? 'C' : 'c'); 2133 break; 2134 case TRB_ISOC: 2135 snprintf(str, size, 2136 "Buffer %08x%08x length %d TD size/TBC %d intr %d type '%s' TBC %u TLBPC %u frame_id %u flags %c:%c:%c:%c:%c:%c:%c:%c:%c", 2137 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2), 2138 GET_INTR_TARGET(field2), 2139 xhci_trb_type_string(type), 2140 GET_TBC(field3), 2141 GET_TLBPC(field3), 2142 GET_FRAME_ID(field3), 2143 field3 & TRB_SIA ? 'S' : 's', 2144 field3 & TRB_BEI ? 'B' : 'b', 2145 field3 & TRB_IDT ? 'I' : 'i', 2146 field3 & TRB_IOC ? 'I' : 'i', 2147 field3 & TRB_CHAIN ? 'C' : 'c', 2148 field3 & TRB_NO_SNOOP ? 'S' : 's', 2149 field3 & TRB_ISP ? 'I' : 'i', 2150 field3 & TRB_ENT ? 'E' : 'e', 2151 field3 & TRB_CYCLE ? 'C' : 'c'); 2152 break; 2153 case TRB_CMD_NOOP: 2154 case TRB_ENABLE_SLOT: 2155 snprintf(str, size, 2156 "%s: flags %c", 2157 xhci_trb_type_string(type), 2158 field3 & TRB_CYCLE ? 'C' : 'c'); 2159 break; 2160 case TRB_DISABLE_SLOT: 2161 case TRB_NEG_BANDWIDTH: 2162 snprintf(str, size, 2163 "%s: slot %d flags %c", 2164 xhci_trb_type_string(type), 2165 TRB_TO_SLOT_ID(field3), 2166 field3 & TRB_CYCLE ? 'C' : 'c'); 2167 break; 2168 case TRB_ADDR_DEV: 2169 snprintf(str, size, 2170 "%s: ctx %08x%08x slot %d flags %c:%c", 2171 xhci_trb_type_string(type), 2172 field1, field0, 2173 TRB_TO_SLOT_ID(field3), 2174 field3 & TRB_BSR ? 'B' : 'b', 2175 field3 & TRB_CYCLE ? 'C' : 'c'); 2176 break; 2177 case TRB_CONFIG_EP: 2178 snprintf(str, size, 2179 "%s: ctx %08x%08x slot %d flags %c:%c", 2180 xhci_trb_type_string(type), 2181 field1, field0, 2182 TRB_TO_SLOT_ID(field3), 2183 field3 & TRB_DC ? 'D' : 'd', 2184 field3 & TRB_CYCLE ? 'C' : 'c'); 2185 break; 2186 case TRB_EVAL_CONTEXT: 2187 snprintf(str, size, 2188 "%s: ctx %08x%08x slot %d flags %c", 2189 xhci_trb_type_string(type), 2190 field1, field0, 2191 TRB_TO_SLOT_ID(field3), 2192 field3 & TRB_CYCLE ? 'C' : 'c'); 2193 break; 2194 case TRB_RESET_EP: 2195 snprintf(str, size, 2196 "%s: ctx %08x%08x slot %d ep %d flags %c:%c", 2197 xhci_trb_type_string(type), 2198 field1, field0, 2199 TRB_TO_SLOT_ID(field3), 2200 TRB_TO_EP_ID(field3), 2201 field3 & TRB_TSP ? 'T' : 't', 2202 field3 & TRB_CYCLE ? 'C' : 'c'); 2203 break; 2204 case TRB_STOP_RING: 2205 snprintf(str, size, 2206 "%s: slot %d sp %d ep %d flags %c", 2207 xhci_trb_type_string(type), 2208 TRB_TO_SLOT_ID(field3), 2209 TRB_TO_SUSPEND_PORT(field3), 2210 TRB_TO_EP_ID(field3), 2211 field3 & TRB_CYCLE ? 'C' : 'c'); 2212 break; 2213 case TRB_SET_DEQ: 2214 snprintf(str, size, 2215 "%s: deq %08x%08x stream %d slot %d ep %d flags %c", 2216 xhci_trb_type_string(type), 2217 field1, field0, 2218 TRB_TO_STREAM_ID(field2), 2219 TRB_TO_SLOT_ID(field3), 2220 TRB_TO_EP_ID(field3), 2221 field3 & TRB_CYCLE ? 'C' : 'c'); 2222 break; 2223 case TRB_RESET_DEV: 2224 snprintf(str, size, 2225 "%s: slot %d flags %c", 2226 xhci_trb_type_string(type), 2227 TRB_TO_SLOT_ID(field3), 2228 field3 & TRB_CYCLE ? 'C' : 'c'); 2229 break; 2230 case TRB_FORCE_EVENT: 2231 snprintf(str, size, 2232 "%s: event %08x%08x vf intr %d vf id %d flags %c", 2233 xhci_trb_type_string(type), 2234 field1, field0, 2235 TRB_TO_VF_INTR_TARGET(field2), 2236 TRB_TO_VF_ID(field3), 2237 field3 & TRB_CYCLE ? 'C' : 'c'); 2238 break; 2239 case TRB_SET_LT: 2240 snprintf(str, size, 2241 "%s: belt %d flags %c", 2242 xhci_trb_type_string(type), 2243 TRB_TO_BELT(field3), 2244 field3 & TRB_CYCLE ? 'C' : 'c'); 2245 break; 2246 case TRB_GET_BW: 2247 snprintf(str, size, 2248 "%s: ctx %08x%08x slot %d speed %d flags %c", 2249 xhci_trb_type_string(type), 2250 field1, field0, 2251 TRB_TO_SLOT_ID(field3), 2252 TRB_TO_DEV_SPEED(field3), 2253 field3 & TRB_CYCLE ? 'C' : 'c'); 2254 break; 2255 case TRB_FORCE_HEADER: 2256 snprintf(str, size, 2257 "%s: info %08x%08x%08x pkt type %d roothub port %d flags %c", 2258 xhci_trb_type_string(type), 2259 field2, field1, field0 & 0xffffffe0, 2260 TRB_TO_PACKET_TYPE(field0), 2261 TRB_TO_ROOTHUB_PORT(field3), 2262 field3 & TRB_CYCLE ? 'C' : 'c'); 2263 break; 2264 default: 2265 snprintf(str, size, 2266 "type '%s' -> raw %08x %08x %08x %08x", 2267 xhci_trb_type_string(type), 2268 field0, field1, field2, field3); 2269 } 2270 2271 return str; 2272 } 2273 2274 static inline const char *xhci_decode_ctrl_ctx(char *str, 2275 unsigned long drop, unsigned long add) 2276 { 2277 unsigned int bit; 2278 int ret = 0; 2279 2280 str[0] = '\0'; 2281 2282 if (drop) { 2283 ret = sprintf(str, "Drop:"); 2284 for_each_set_bit(bit, &drop, 32) 2285 ret += sprintf(str + ret, " %d%s", 2286 bit / 2, 2287 bit % 2 ? "in":"out"); 2288 ret += sprintf(str + ret, ", "); 2289 } 2290 2291 if (add) { 2292 ret += sprintf(str + ret, "Add:%s%s", 2293 (add & SLOT_FLAG) ? " slot":"", 2294 (add & EP0_FLAG) ? " ep0":""); 2295 add &= ~(SLOT_FLAG | EP0_FLAG); 2296 for_each_set_bit(bit, &add, 32) 2297 ret += sprintf(str + ret, " %d%s", 2298 bit / 2, 2299 bit % 2 ? "in":"out"); 2300 } 2301 return str; 2302 } 2303 2304 static inline const char *xhci_decode_slot_context(char *str, 2305 u32 info, u32 info2, u32 tt_info, u32 state) 2306 { 2307 u32 speed; 2308 u32 hub; 2309 u32 mtt; 2310 int ret = 0; 2311 2312 speed = info & DEV_SPEED; 2313 hub = info & DEV_HUB; 2314 mtt = info & DEV_MTT; 2315 2316 ret = sprintf(str, "RS %05x %s%s%s Ctx Entries %d MEL %d us Port# %d/%d", 2317 info & ROUTE_STRING_MASK, 2318 ({ char *s; 2319 switch (speed) { 2320 case SLOT_SPEED_FS: 2321 s = "full-speed"; 2322 break; 2323 case SLOT_SPEED_LS: 2324 s = "low-speed"; 2325 break; 2326 case SLOT_SPEED_HS: 2327 s = "high-speed"; 2328 break; 2329 case SLOT_SPEED_SS: 2330 s = "super-speed"; 2331 break; 2332 case SLOT_SPEED_SSP: 2333 s = "super-speed plus"; 2334 break; 2335 default: 2336 s = "UNKNOWN speed"; 2337 } s; }), 2338 mtt ? " multi-TT" : "", 2339 hub ? " Hub" : "", 2340 (info & LAST_CTX_MASK) >> 27, 2341 info2 & MAX_EXIT, 2342 DEVINFO_TO_ROOT_HUB_PORT(info2), 2343 DEVINFO_TO_MAX_PORTS(info2)); 2344 2345 ret += sprintf(str + ret, " [TT Slot %d Port# %d TTT %d Intr %d] Addr %d State %s", 2346 tt_info & TT_SLOT, (tt_info & TT_PORT) >> 8, 2347 GET_TT_THINK_TIME(tt_info), GET_INTR_TARGET(tt_info), 2348 state & DEV_ADDR_MASK, 2349 xhci_slot_state_string(GET_SLOT_STATE(state))); 2350 2351 return str; 2352 } 2353 2354 2355 static inline const char *xhci_portsc_link_state_string(u32 portsc) 2356 { 2357 switch (portsc & PORT_PLS_MASK) { 2358 case XDEV_U0: 2359 return "U0"; 2360 case XDEV_U1: 2361 return "U1"; 2362 case XDEV_U2: 2363 return "U2"; 2364 case XDEV_U3: 2365 return "U3"; 2366 case XDEV_DISABLED: 2367 return "Disabled"; 2368 case XDEV_RXDETECT: 2369 return "RxDetect"; 2370 case XDEV_INACTIVE: 2371 return "Inactive"; 2372 case XDEV_POLLING: 2373 return "Polling"; 2374 case XDEV_RECOVERY: 2375 return "Recovery"; 2376 case XDEV_HOT_RESET: 2377 return "Hot Reset"; 2378 case XDEV_COMP_MODE: 2379 return "Compliance mode"; 2380 case XDEV_TEST_MODE: 2381 return "Test mode"; 2382 case XDEV_RESUME: 2383 return "Resume"; 2384 default: 2385 break; 2386 } 2387 return "Unknown"; 2388 } 2389 2390 static inline const char *xhci_decode_portsc(char *str, u32 portsc) 2391 { 2392 int ret; 2393 2394 ret = sprintf(str, "0x%08x ", portsc); 2395 2396 if (portsc == ~(u32)0) 2397 return str; 2398 2399 ret += sprintf(str + ret, "%s %s %s Link:%s PortSpeed:%d ", 2400 portsc & PORT_POWER ? "Powered" : "Powered-off", 2401 portsc & PORT_CONNECT ? "Connected" : "Not-connected", 2402 portsc & PORT_PE ? "Enabled" : "Disabled", 2403 xhci_portsc_link_state_string(portsc), 2404 DEV_PORT_SPEED(portsc)); 2405 2406 if (portsc & PORT_OC) 2407 ret += sprintf(str + ret, "OverCurrent "); 2408 if (portsc & PORT_RESET) 2409 ret += sprintf(str + ret, "In-Reset "); 2410 2411 ret += sprintf(str + ret, "Change: "); 2412 if (portsc & PORT_CSC) 2413 ret += sprintf(str + ret, "CSC "); 2414 if (portsc & PORT_PEC) 2415 ret += sprintf(str + ret, "PEC "); 2416 if (portsc & PORT_WRC) 2417 ret += sprintf(str + ret, "WRC "); 2418 if (portsc & PORT_OCC) 2419 ret += sprintf(str + ret, "OCC "); 2420 if (portsc & PORT_RC) 2421 ret += sprintf(str + ret, "PRC "); 2422 if (portsc & PORT_PLC) 2423 ret += sprintf(str + ret, "PLC "); 2424 if (portsc & PORT_CEC) 2425 ret += sprintf(str + ret, "CEC "); 2426 if (portsc & PORT_CAS) 2427 ret += sprintf(str + ret, "CAS "); 2428 2429 ret += sprintf(str + ret, "Wake: "); 2430 if (portsc & PORT_WKCONN_E) 2431 ret += sprintf(str + ret, "WCE "); 2432 if (portsc & PORT_WKDISC_E) 2433 ret += sprintf(str + ret, "WDE "); 2434 if (portsc & PORT_WKOC_E) 2435 ret += sprintf(str + ret, "WOE "); 2436 2437 return str; 2438 } 2439 2440 static inline const char *xhci_decode_usbsts(char *str, u32 usbsts) 2441 { 2442 int ret = 0; 2443 2444 ret = sprintf(str, " 0x%08x", usbsts); 2445 2446 if (usbsts == ~(u32)0) 2447 return str; 2448 2449 if (usbsts & STS_HALT) 2450 ret += sprintf(str + ret, " HCHalted"); 2451 if (usbsts & STS_FATAL) 2452 ret += sprintf(str + ret, " HSE"); 2453 if (usbsts & STS_EINT) 2454 ret += sprintf(str + ret, " EINT"); 2455 if (usbsts & STS_PORT) 2456 ret += sprintf(str + ret, " PCD"); 2457 if (usbsts & STS_SAVE) 2458 ret += sprintf(str + ret, " SSS"); 2459 if (usbsts & STS_RESTORE) 2460 ret += sprintf(str + ret, " RSS"); 2461 if (usbsts & STS_SRE) 2462 ret += sprintf(str + ret, " SRE"); 2463 if (usbsts & STS_CNR) 2464 ret += sprintf(str + ret, " CNR"); 2465 if (usbsts & STS_HCE) 2466 ret += sprintf(str + ret, " HCE"); 2467 2468 return str; 2469 } 2470 2471 static inline const char *xhci_decode_doorbell(char *str, u32 slot, u32 doorbell) 2472 { 2473 u8 ep; 2474 u16 stream; 2475 int ret; 2476 2477 ep = (doorbell & 0xff); 2478 stream = doorbell >> 16; 2479 2480 if (slot == 0) { 2481 sprintf(str, "Command Ring %d", doorbell); 2482 return str; 2483 } 2484 ret = sprintf(str, "Slot %d ", slot); 2485 if (ep > 0 && ep < 32) 2486 ret = sprintf(str + ret, "ep%d%s", 2487 ep / 2, 2488 ep % 2 ? "in" : "out"); 2489 else if (ep == 0 || ep < 248) 2490 ret = sprintf(str + ret, "Reserved %d", ep); 2491 else 2492 ret = sprintf(str + ret, "Vendor Defined %d", ep); 2493 if (stream) 2494 ret = sprintf(str + ret, " Stream %d", stream); 2495 2496 return str; 2497 } 2498 2499 static inline const char *xhci_ep_state_string(u8 state) 2500 { 2501 switch (state) { 2502 case EP_STATE_DISABLED: 2503 return "disabled"; 2504 case EP_STATE_RUNNING: 2505 return "running"; 2506 case EP_STATE_HALTED: 2507 return "halted"; 2508 case EP_STATE_STOPPED: 2509 return "stopped"; 2510 case EP_STATE_ERROR: 2511 return "error"; 2512 default: 2513 return "INVALID"; 2514 } 2515 } 2516 2517 static inline const char *xhci_ep_type_string(u8 type) 2518 { 2519 switch (type) { 2520 case ISOC_OUT_EP: 2521 return "Isoc OUT"; 2522 case BULK_OUT_EP: 2523 return "Bulk OUT"; 2524 case INT_OUT_EP: 2525 return "Int OUT"; 2526 case CTRL_EP: 2527 return "Ctrl"; 2528 case ISOC_IN_EP: 2529 return "Isoc IN"; 2530 case BULK_IN_EP: 2531 return "Bulk IN"; 2532 case INT_IN_EP: 2533 return "Int IN"; 2534 default: 2535 return "INVALID"; 2536 } 2537 } 2538 2539 static inline const char *xhci_decode_ep_context(char *str, u32 info, 2540 u32 info2, u64 deq, u32 tx_info) 2541 { 2542 int ret; 2543 2544 u32 esit; 2545 u16 maxp; 2546 u16 avg; 2547 2548 u8 max_pstr; 2549 u8 ep_state; 2550 u8 interval; 2551 u8 ep_type; 2552 u8 burst; 2553 u8 cerr; 2554 u8 mult; 2555 2556 bool lsa; 2557 bool hid; 2558 2559 esit = CTX_TO_MAX_ESIT_PAYLOAD_HI(info) << 16 | 2560 CTX_TO_MAX_ESIT_PAYLOAD(tx_info); 2561 2562 ep_state = info & EP_STATE_MASK; 2563 max_pstr = CTX_TO_EP_MAXPSTREAMS(info); 2564 interval = CTX_TO_EP_INTERVAL(info); 2565 mult = CTX_TO_EP_MULT(info) + 1; 2566 lsa = !!(info & EP_HAS_LSA); 2567 2568 cerr = (info2 & (3 << 1)) >> 1; 2569 ep_type = CTX_TO_EP_TYPE(info2); 2570 hid = !!(info2 & (1 << 7)); 2571 burst = CTX_TO_MAX_BURST(info2); 2572 maxp = MAX_PACKET_DECODED(info2); 2573 2574 avg = EP_AVG_TRB_LENGTH(tx_info); 2575 2576 ret = sprintf(str, "State %s mult %d max P. Streams %d %s", 2577 xhci_ep_state_string(ep_state), mult, 2578 max_pstr, lsa ? "LSA " : ""); 2579 2580 ret += sprintf(str + ret, "interval %d us max ESIT payload %d CErr %d ", 2581 (1 << interval) * 125, esit, cerr); 2582 2583 ret += sprintf(str + ret, "Type %s %sburst %d maxp %d deq %016llx ", 2584 xhci_ep_type_string(ep_type), hid ? "HID" : "", 2585 burst, maxp, deq); 2586 2587 ret += sprintf(str + ret, "avg trb len %d", avg); 2588 2589 return str; 2590 } 2591 2592 #endif /* __LINUX_XHCI_HCD_H */ 2593