1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * SuperH On-Chip RTC Support 4 * 5 * Copyright (C) 2006 - 2009 Paul Mundt 6 * Copyright (C) 2006 Jamie Lenehan 7 * Copyright (C) 2008 Angelo Castello 8 * Copyright (C) 2025 Wolfram Sang, Renesas Electronics Corporation 9 * 10 * Based on the old arch/sh/kernel/cpu/rtc.c by: 11 * 12 * Copyright (C) 2000 Philipp Rumpf <prumpf@tux.org> 13 * Copyright (C) 1999 Tetsuya Okada & Niibe Yutaka 14 */ 15 #include <linux/module.h> 16 #include <linux/mod_devicetable.h> 17 #include <linux/kernel.h> 18 #include <linux/bcd.h> 19 #include <linux/rtc.h> 20 #include <linux/init.h> 21 #include <linux/platform_device.h> 22 #include <linux/seq_file.h> 23 #include <linux/interrupt.h> 24 #include <linux/spinlock.h> 25 #include <linux/io.h> 26 #include <linux/log2.h> 27 #include <linux/clk.h> 28 #include <linux/slab.h> 29 #ifdef CONFIG_SUPERH 30 #include <asm/rtc.h> 31 #else 32 /* Default values for RZ/A RTC */ 33 #define rtc_reg_size sizeof(u16) 34 #define RTC_BIT_INVERTED 0 /* no chip bugs */ 35 #define RTC_CAP_4_DIGIT_YEAR BIT(0) 36 #define RTC_DEF_CAPABILITIES RTC_CAP_4_DIGIT_YEAR 37 #endif 38 39 #define DRV_NAME "sh-rtc" 40 41 #define RTC_REG(r) ((r) * rtc_reg_size) 42 43 #define R64CNT RTC_REG(0) 44 45 #define RSECCNT RTC_REG(1) /* RTC sec */ 46 #define RMINCNT RTC_REG(2) /* RTC min */ 47 #define RHRCNT RTC_REG(3) /* RTC hour */ 48 #define RWKCNT RTC_REG(4) /* RTC week */ 49 #define RDAYCNT RTC_REG(5) /* RTC day */ 50 #define RMONCNT RTC_REG(6) /* RTC month */ 51 #define RYRCNT RTC_REG(7) /* RTC year */ 52 #define RSECAR RTC_REG(8) /* ALARM sec */ 53 #define RMINAR RTC_REG(9) /* ALARM min */ 54 #define RHRAR RTC_REG(10) /* ALARM hour */ 55 #define RWKAR RTC_REG(11) /* ALARM week */ 56 #define RDAYAR RTC_REG(12) /* ALARM day */ 57 #define RMONAR RTC_REG(13) /* ALARM month */ 58 #define RCR1 RTC_REG(14) /* Control */ 59 #define RCR2 RTC_REG(15) /* Control */ 60 61 /* 62 * Note on RYRAR and RCR3: Up until this point most of the register 63 * definitions are consistent across all of the available parts. However, 64 * the placement of the optional RYRAR and RCR3 (the RYRAR control 65 * register used to control RYRCNT/RYRAR compare) varies considerably 66 * across various parts, occasionally being mapped in to a completely 67 * unrelated address space. For proper RYRAR support a separate resource 68 * would have to be handed off, but as this is purely optional in 69 * practice, we simply opt not to support it, thereby keeping the code 70 * quite a bit more simplified. 71 */ 72 73 /* ALARM Bits - or with BCD encoded value */ 74 #define AR_ENB BIT(7) /* Enable for alarm cmp */ 75 76 /* RCR1 Bits */ 77 #define RCR1_CF BIT(7) /* Carry Flag */ 78 #define RCR1_CIE BIT(4) /* Carry Interrupt Enable */ 79 #define RCR1_AIE BIT(3) /* Alarm Interrupt Enable */ 80 #define RCR1_AF BIT(0) /* Alarm Flag */ 81 82 /* RCR2 Bits */ 83 #define RCR2_RTCEN BIT(3) /* ENable RTC */ 84 #define RCR2_ADJ BIT(2) /* ADJustment (30-second) */ 85 #define RCR2_RESET BIT(1) /* Reset bit */ 86 #define RCR2_START BIT(0) /* Start bit */ 87 88 struct sh_rtc { 89 void __iomem *regbase; 90 int alarm_irq; 91 struct clk *clk; 92 struct rtc_device *rtc_dev; 93 spinlock_t lock; /* protecting register access */ 94 unsigned long capabilities; /* See asm/rtc.h for cap bits */ 95 }; 96 97 static irqreturn_t sh_rtc_alarm(int irq, void *dev_id) 98 { 99 struct sh_rtc *rtc = dev_id; 100 unsigned int tmp, pending; 101 102 spin_lock(&rtc->lock); 103 104 tmp = readb(rtc->regbase + RCR1); 105 pending = tmp & RCR1_AF; 106 tmp &= ~(RCR1_AF | RCR1_AIE); 107 writeb(tmp, rtc->regbase + RCR1); 108 109 if (pending) 110 rtc_update_irq(rtc->rtc_dev, 1, RTC_AF | RTC_IRQF); 111 112 spin_unlock(&rtc->lock); 113 114 return IRQ_RETVAL(pending); 115 } 116 117 static int sh_rtc_alarm_irq_enable(struct device *dev, unsigned int enable) 118 { 119 struct sh_rtc *rtc = dev_get_drvdata(dev); 120 unsigned int tmp; 121 122 spin_lock_irq(&rtc->lock); 123 124 tmp = readb(rtc->regbase + RCR1); 125 126 if (enable) 127 tmp |= RCR1_AIE; 128 else 129 tmp &= ~RCR1_AIE; 130 131 writeb(tmp, rtc->regbase + RCR1); 132 133 spin_unlock_irq(&rtc->lock); 134 135 return 0; 136 } 137 138 static int sh_rtc_read_time(struct device *dev, struct rtc_time *tm) 139 { 140 struct sh_rtc *rtc = dev_get_drvdata(dev); 141 unsigned int sec128, sec2, yr, yr100, cf_bit; 142 143 if (!(readb(rtc->regbase + RCR2) & RCR2_RTCEN)) 144 return -EINVAL; 145 146 do { 147 unsigned int tmp; 148 149 spin_lock_irq(&rtc->lock); 150 151 tmp = readb(rtc->regbase + RCR1); 152 tmp &= ~RCR1_CF; /* Clear CF-bit */ 153 tmp |= RCR1_CIE; 154 writeb(tmp, rtc->regbase + RCR1); 155 156 sec128 = readb(rtc->regbase + R64CNT); 157 158 tm->tm_sec = bcd2bin(readb(rtc->regbase + RSECCNT)); 159 tm->tm_min = bcd2bin(readb(rtc->regbase + RMINCNT)); 160 tm->tm_hour = bcd2bin(readb(rtc->regbase + RHRCNT)); 161 tm->tm_wday = bcd2bin(readb(rtc->regbase + RWKCNT)); 162 tm->tm_mday = bcd2bin(readb(rtc->regbase + RDAYCNT)); 163 tm->tm_mon = bcd2bin(readb(rtc->regbase + RMONCNT)) - 1; 164 165 if (rtc->capabilities & RTC_CAP_4_DIGIT_YEAR) { 166 yr = readw(rtc->regbase + RYRCNT); 167 yr100 = bcd2bin(yr >> 8); 168 yr &= 0xff; 169 } else { 170 yr = readb(rtc->regbase + RYRCNT); 171 yr100 = bcd2bin((yr == 0x99) ? 0x19 : 0x20); 172 } 173 174 tm->tm_year = (yr100 * 100 + bcd2bin(yr)) - 1900; 175 176 sec2 = readb(rtc->regbase + R64CNT); 177 cf_bit = readb(rtc->regbase + RCR1) & RCR1_CF; 178 179 spin_unlock_irq(&rtc->lock); 180 } while (cf_bit != 0 || ((sec128 ^ sec2) & RTC_BIT_INVERTED) != 0); 181 182 #if RTC_BIT_INVERTED != 0 183 if ((sec128 & RTC_BIT_INVERTED)) 184 tm->tm_sec--; 185 #endif 186 187 dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n", 188 __func__, tm->tm_sec, tm->tm_min, tm->tm_hour, 189 tm->tm_mday, tm->tm_mon + 1, tm->tm_year, tm->tm_wday); 190 191 return 0; 192 } 193 194 static int sh_rtc_set_time(struct device *dev, struct rtc_time *tm) 195 { 196 struct sh_rtc *rtc = dev_get_drvdata(dev); 197 unsigned int tmp; 198 int year; 199 200 spin_lock_irq(&rtc->lock); 201 202 /* Reset pre-scaler & stop RTC */ 203 tmp = readb(rtc->regbase + RCR2); 204 tmp |= RCR2_RESET; 205 tmp &= ~RCR2_START; 206 writeb(tmp, rtc->regbase + RCR2); 207 208 writeb(bin2bcd(tm->tm_sec), rtc->regbase + RSECCNT); 209 writeb(bin2bcd(tm->tm_min), rtc->regbase + RMINCNT); 210 writeb(bin2bcd(tm->tm_hour), rtc->regbase + RHRCNT); 211 writeb(bin2bcd(tm->tm_wday), rtc->regbase + RWKCNT); 212 writeb(bin2bcd(tm->tm_mday), rtc->regbase + RDAYCNT); 213 writeb(bin2bcd(tm->tm_mon + 1), rtc->regbase + RMONCNT); 214 215 if (rtc->capabilities & RTC_CAP_4_DIGIT_YEAR) { 216 year = (bin2bcd((tm->tm_year + 1900) / 100) << 8) | 217 bin2bcd(tm->tm_year % 100); 218 writew(year, rtc->regbase + RYRCNT); 219 } else { 220 year = tm->tm_year % 100; 221 writeb(bin2bcd(year), rtc->regbase + RYRCNT); 222 } 223 224 /* Start RTC */ 225 tmp = readb(rtc->regbase + RCR2); 226 tmp &= ~RCR2_RESET; 227 tmp |= RCR2_RTCEN | RCR2_START; 228 writeb(tmp, rtc->regbase + RCR2); 229 230 spin_unlock_irq(&rtc->lock); 231 232 return 0; 233 } 234 235 static inline int sh_rtc_read_alarm_value(struct sh_rtc *rtc, int reg_off) 236 { 237 unsigned int byte; 238 int value = -1; /* return -1 for ignored values */ 239 240 byte = readb(rtc->regbase + reg_off); 241 if (byte & AR_ENB) { 242 byte &= ~AR_ENB; /* strip the enable bit */ 243 value = bcd2bin(byte); 244 } 245 246 return value; 247 } 248 249 static int sh_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *wkalrm) 250 { 251 struct sh_rtc *rtc = dev_get_drvdata(dev); 252 struct rtc_time *tm = &wkalrm->time; 253 254 spin_lock_irq(&rtc->lock); 255 256 tm->tm_sec = sh_rtc_read_alarm_value(rtc, RSECAR); 257 tm->tm_min = sh_rtc_read_alarm_value(rtc, RMINAR); 258 tm->tm_hour = sh_rtc_read_alarm_value(rtc, RHRAR); 259 tm->tm_wday = sh_rtc_read_alarm_value(rtc, RWKAR); 260 tm->tm_mday = sh_rtc_read_alarm_value(rtc, RDAYAR); 261 tm->tm_mon = sh_rtc_read_alarm_value(rtc, RMONAR); 262 if (tm->tm_mon > 0) 263 tm->tm_mon -= 1; /* RTC is 1-12, tm_mon is 0-11 */ 264 265 wkalrm->enabled = (readb(rtc->regbase + RCR1) & RCR1_AIE) ? 1 : 0; 266 267 spin_unlock_irq(&rtc->lock); 268 269 return 0; 270 } 271 272 static inline void sh_rtc_write_alarm_value(struct sh_rtc *rtc, 273 int value, int reg_off) 274 { 275 /* < 0 for a value that is ignored */ 276 if (value < 0) 277 writeb(0, rtc->regbase + reg_off); 278 else 279 writeb(bin2bcd(value) | AR_ENB, rtc->regbase + reg_off); 280 } 281 282 static int sh_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *wkalrm) 283 { 284 struct sh_rtc *rtc = dev_get_drvdata(dev); 285 unsigned int rcr1; 286 struct rtc_time *tm = &wkalrm->time; 287 int mon; 288 289 spin_lock_irq(&rtc->lock); 290 291 /* disable alarm interrupt and clear the alarm flag */ 292 rcr1 = readb(rtc->regbase + RCR1); 293 rcr1 &= ~(RCR1_AF | RCR1_AIE); 294 writeb(rcr1, rtc->regbase + RCR1); 295 296 /* set alarm time */ 297 sh_rtc_write_alarm_value(rtc, tm->tm_sec, RSECAR); 298 sh_rtc_write_alarm_value(rtc, tm->tm_min, RMINAR); 299 sh_rtc_write_alarm_value(rtc, tm->tm_hour, RHRAR); 300 sh_rtc_write_alarm_value(rtc, tm->tm_wday, RWKAR); 301 sh_rtc_write_alarm_value(rtc, tm->tm_mday, RDAYAR); 302 mon = tm->tm_mon; 303 if (mon >= 0) 304 mon += 1; 305 sh_rtc_write_alarm_value(rtc, mon, RMONAR); 306 307 if (wkalrm->enabled) { 308 rcr1 |= RCR1_AIE; 309 writeb(rcr1, rtc->regbase + RCR1); 310 } 311 312 spin_unlock_irq(&rtc->lock); 313 314 return 0; 315 } 316 317 static const struct rtc_class_ops sh_rtc_ops = { 318 .read_time = sh_rtc_read_time, 319 .set_time = sh_rtc_set_time, 320 .read_alarm = sh_rtc_read_alarm, 321 .set_alarm = sh_rtc_set_alarm, 322 .alarm_irq_enable = sh_rtc_alarm_irq_enable, 323 }; 324 325 static int __init sh_rtc_probe(struct platform_device *pdev) 326 { 327 struct sh_rtc *rtc; 328 struct resource *res, *req_res; 329 char clk_name[14]; 330 int clk_id, ret; 331 unsigned int tmp; 332 resource_size_t regsize; 333 334 rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL); 335 if (unlikely(!rtc)) 336 return -ENOMEM; 337 338 spin_lock_init(&rtc->lock); 339 340 ret = platform_get_irq(pdev, 0); 341 if (unlikely(ret <= 0)) { 342 dev_err(&pdev->dev, "No IRQ resource\n"); 343 return -ENOENT; 344 } 345 346 if (!pdev->dev.of_node) 347 rtc->alarm_irq = platform_get_irq(pdev, 2); 348 else 349 rtc->alarm_irq = ret; 350 351 res = platform_get_resource(pdev, IORESOURCE_IO, 0); 352 if (!res) 353 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 354 if (!res) { 355 dev_err(&pdev->dev, "No IO resource\n"); 356 return -ENOENT; 357 } 358 359 regsize = resource_size(res); 360 req_res = devm_request_mem_region(&pdev->dev, res->start, regsize, pdev->name); 361 if (!req_res) 362 return -EBUSY; 363 364 rtc->regbase = devm_ioremap(&pdev->dev, req_res->start, regsize); 365 if (!rtc->regbase) 366 return -EINVAL; 367 368 if (!pdev->dev.of_node) { 369 clk_id = pdev->id; 370 /* With a single device, the clock id is still "rtc0" */ 371 if (clk_id < 0) 372 clk_id = 0; 373 374 snprintf(clk_name, sizeof(clk_name), "rtc%d", clk_id); 375 } else { 376 snprintf(clk_name, sizeof(clk_name), "fck"); 377 } 378 379 rtc->clk = devm_clk_get(&pdev->dev, clk_name); 380 if (IS_ERR(rtc->clk)) { 381 /* 382 * No error handling for rtc->clk intentionally, not all 383 * platforms will have a unique clock for the RTC, and 384 * the clk API can handle the struct clk pointer being 385 * NULL. 386 */ 387 rtc->clk = NULL; 388 } 389 390 rtc->rtc_dev = devm_rtc_allocate_device(&pdev->dev); 391 if (IS_ERR(rtc->rtc_dev)) 392 return PTR_ERR(rtc->rtc_dev); 393 394 clk_enable(rtc->clk); 395 396 rtc->capabilities = RTC_DEF_CAPABILITIES; 397 398 #ifdef CONFIG_SUPERH 399 if (dev_get_platdata(&pdev->dev)) { 400 struct sh_rtc_platform_info *pinfo = 401 dev_get_platdata(&pdev->dev); 402 403 /* 404 * Some CPUs have special capabilities in addition to the 405 * default set. Add those in here. 406 */ 407 rtc->capabilities |= pinfo->capabilities; 408 } 409 #endif 410 411 ret = devm_request_irq(&pdev->dev, rtc->alarm_irq, sh_rtc_alarm, 0, "sh-rtc", rtc); 412 if (ret) { 413 dev_err(&pdev->dev, "request alarm IRQ failed with %d, IRQ %d\n", 414 ret, rtc->alarm_irq); 415 goto err_unmap; 416 } 417 418 platform_set_drvdata(pdev, rtc); 419 420 /* everything disabled by default */ 421 tmp = readb(rtc->regbase + RCR1); 422 tmp &= ~(RCR1_CIE | RCR1_AIE); 423 writeb(tmp, rtc->regbase + RCR1); 424 425 rtc->rtc_dev->ops = &sh_rtc_ops; 426 rtc->rtc_dev->max_user_freq = 256; 427 428 if (rtc->capabilities & RTC_CAP_4_DIGIT_YEAR) { 429 rtc->rtc_dev->range_min = RTC_TIMESTAMP_BEGIN_1900; 430 rtc->rtc_dev->range_max = RTC_TIMESTAMP_END_9999; 431 } else { 432 rtc->rtc_dev->range_min = mktime64(1999, 1, 1, 0, 0, 0); 433 rtc->rtc_dev->range_max = mktime64(2098, 12, 31, 23, 59, 59); 434 } 435 436 ret = devm_rtc_register_device(rtc->rtc_dev); 437 if (ret) 438 goto err_unmap; 439 440 device_init_wakeup(&pdev->dev, true); 441 return 0; 442 443 err_unmap: 444 clk_disable(rtc->clk); 445 446 return ret; 447 } 448 449 static void __exit sh_rtc_remove(struct platform_device *pdev) 450 { 451 struct sh_rtc *rtc = platform_get_drvdata(pdev); 452 453 sh_rtc_alarm_irq_enable(&pdev->dev, 0); 454 455 clk_disable(rtc->clk); 456 } 457 458 static int __maybe_unused sh_rtc_suspend(struct device *dev) 459 { 460 struct sh_rtc *rtc = dev_get_drvdata(dev); 461 462 if (device_may_wakeup(dev)) 463 irq_set_irq_wake(rtc->alarm_irq, 1); 464 465 return 0; 466 } 467 468 static int __maybe_unused sh_rtc_resume(struct device *dev) 469 { 470 struct sh_rtc *rtc = dev_get_drvdata(dev); 471 472 if (device_may_wakeup(dev)) 473 irq_set_irq_wake(rtc->alarm_irq, 0); 474 475 return 0; 476 } 477 478 static SIMPLE_DEV_PM_OPS(sh_rtc_pm_ops, sh_rtc_suspend, sh_rtc_resume); 479 480 static const struct of_device_id sh_rtc_of_match[] = { 481 { .compatible = "renesas,sh-rtc", }, 482 { /* sentinel */ } 483 }; 484 MODULE_DEVICE_TABLE(of, sh_rtc_of_match); 485 486 /* 487 * sh_rtc_remove() lives in .exit.text. For drivers registered via 488 * module_platform_driver_probe() this is ok because they cannot get unbound at 489 * runtime. So mark the driver struct with __refdata to prevent modpost 490 * triggering a section mismatch warning. 491 */ 492 static struct platform_driver sh_rtc_platform_driver __refdata = { 493 .driver = { 494 .name = DRV_NAME, 495 .pm = &sh_rtc_pm_ops, 496 .of_match_table = sh_rtc_of_match, 497 }, 498 .remove = __exit_p(sh_rtc_remove), 499 }; 500 501 module_platform_driver_probe(sh_rtc_platform_driver, sh_rtc_probe); 502 503 MODULE_DESCRIPTION("SuperH on-chip RTC driver"); 504 MODULE_AUTHOR("Paul Mundt <lethal@linux-sh.org>"); 505 MODULE_AUTHOR("Jamie Lenehan <lenehan@twibble.org>"); 506 MODULE_AUTHOR("Angelo Castello <angelo.castello@st.com>"); 507 MODULE_LICENSE("GPL v2"); 508 MODULE_ALIAS("platform:" DRV_NAME); 509