1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Copyright 2025 NXP
4  */
5 
6 #include <linux/bitfield.h>
7 #include <linux/clk.h>
8 #include <linux/iopoll.h>
9 #include <linux/of_irq.h>
10 #include <linux/platform_device.h>
11 #include <linux/rtc.h>
12 
13 #define RTCC_OFFSET	0x4ul
14 #define RTCS_OFFSET	0x8ul
15 #define APIVAL_OFFSET	0x10ul
16 
17 /* RTCC fields */
18 #define RTCC_CNTEN				BIT(31)
19 #define RTCC_APIEN				BIT(15)
20 #define RTCC_APIIE				BIT(14)
21 #define RTCC_CLKSEL_MASK		GENMASK(13, 12)
22 #define RTCC_DIV512EN			BIT(11)
23 #define RTCC_DIV32EN			BIT(10)
24 
25 /* RTCS fields */
26 #define RTCS_INV_API	BIT(17)
27 #define RTCS_APIF		BIT(13)
28 
29 #define APIVAL_MAX_VAL		GENMASK(31, 0)
30 #define RTC_SYNCH_TIMEOUT	(100 * USEC_PER_MSEC)
31 
32 /*
33  * S32G2 and S32G3 SoCs have RTC clock source1 reserved and
34  * should not be used.
35  */
36 #define RTC_CLK_SRC1_RESERVED		BIT(1)
37 
38 /*
39  * S32G RTC module has a 512 value and a 32 value hardware frequency
40  * divisors (DIV512 and DIV32) which could be used to achieve higher
41  * counter ranges by lowering the RTC frequency.
42  */
43 enum {
44 	DIV1 = 1,
45 	DIV32 = 32,
46 	DIV512 = 512,
47 	DIV512_32 = 16384
48 };
49 
50 static const char *const rtc_clk_src[] = {
51 	"source0",
52 	"source1",
53 	"source2",
54 	"source3"
55 };
56 
57 struct rtc_priv {
58 	struct rtc_device *rdev;
59 	void __iomem *rtc_base;
60 	struct clk *ipg;
61 	struct clk *clk_src;
62 	const struct rtc_soc_data *rtc_data;
63 	u64 rtc_hz;
64 	time64_t sleep_sec;
65 	int irq;
66 	u32 clk_src_idx;
67 };
68 
69 struct rtc_soc_data {
70 	u32 clk_div;
71 	u32 reserved_clk_mask;
72 };
73 
74 static const struct rtc_soc_data rtc_s32g2_data = {
75 	.clk_div = DIV512_32,
76 	.reserved_clk_mask = RTC_CLK_SRC1_RESERVED,
77 };
78 
79 static irqreturn_t s32g_rtc_handler(int irq, void *dev)
80 {
81 	struct rtc_priv *priv = platform_get_drvdata(dev);
82 	u32 status;
83 
84 	status = readl(priv->rtc_base + RTCS_OFFSET);
85 
86 	if (status & RTCS_APIF) {
87 		writel(0x0, priv->rtc_base + APIVAL_OFFSET);
88 		writel(status | RTCS_APIF, priv->rtc_base + RTCS_OFFSET);
89 	}
90 
91 	rtc_update_irq(priv->rdev, 1, RTC_IRQF | RTC_AF);
92 
93 	return IRQ_HANDLED;
94 }
95 
96 /*
97  * The function is not really getting time from the RTC since the S32G RTC
98  * has several limitations. Thus, to setup alarm use system time.
99  */
100 static int s32g_rtc_read_time(struct device *dev,
101 			      struct rtc_time *tm)
102 {
103 	struct rtc_priv *priv = dev_get_drvdata(dev);
104 	time64_t sec;
105 
106 	if (check_add_overflow(ktime_get_real_seconds(),
107 			       priv->sleep_sec, &sec))
108 		return -ERANGE;
109 
110 	rtc_time64_to_tm(sec, tm);
111 
112 	return 0;
113 }
114 
115 static int s32g_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
116 {
117 	struct rtc_priv *priv = dev_get_drvdata(dev);
118 	u32 rtcc, rtcs;
119 
120 	rtcc = readl(priv->rtc_base + RTCC_OFFSET);
121 	rtcs = readl(priv->rtc_base + RTCS_OFFSET);
122 
123 	alrm->enabled = rtcc & RTCC_APIIE;
124 	if (alrm->enabled)
125 		alrm->pending = !(rtcs & RTCS_APIF);
126 
127 	return 0;
128 }
129 
130 static int s32g_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
131 {
132 	struct rtc_priv *priv = dev_get_drvdata(dev);
133 	u32 rtcc;
134 
135 	/* RTC API functionality is used both for triggering interrupts
136 	 * and as a wakeup event. Hence it should always be enabled.
137 	 */
138 	rtcc = readl(priv->rtc_base + RTCC_OFFSET);
139 	rtcc |= RTCC_APIEN | RTCC_APIIE;
140 	writel(rtcc, priv->rtc_base + RTCC_OFFSET);
141 
142 	return 0;
143 }
144 
145 static int s32g_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
146 {
147 	struct rtc_priv *priv = dev_get_drvdata(dev);
148 	unsigned long long cycles;
149 	long long t_offset;
150 	time64_t alrm_time;
151 	u32 rtcs;
152 	int ret;
153 
154 	alrm_time = rtc_tm_to_time64(&alrm->time);
155 	t_offset = alrm_time - ktime_get_real_seconds() - priv->sleep_sec;
156 	if (t_offset < 0)
157 		return -ERANGE;
158 
159 	cycles = t_offset * priv->rtc_hz;
160 	if (cycles > APIVAL_MAX_VAL)
161 		return -ERANGE;
162 
163 	/* APIVAL could have been reset from the IRQ handler.
164 	 * Hence, we wait in case there is a synchronization process.
165 	 */
166 	ret = read_poll_timeout(readl, rtcs, !(rtcs & RTCS_INV_API),
167 				0, RTC_SYNCH_TIMEOUT, false, priv->rtc_base + RTCS_OFFSET);
168 	if (ret)
169 		return ret;
170 
171 	writel(cycles, priv->rtc_base + APIVAL_OFFSET);
172 
173 	return read_poll_timeout(readl, rtcs, !(rtcs & RTCS_INV_API),
174 				0, RTC_SYNCH_TIMEOUT, false, priv->rtc_base + RTCS_OFFSET);
175 }
176 
177 /*
178  * Disable the 32-bit free running counter.
179  * This allows Clock Source and Divisors selection
180  * to be performed without causing synchronization issues.
181  */
182 static void s32g_rtc_disable(struct rtc_priv *priv)
183 {
184 	u32 rtcc = readl(priv->rtc_base + RTCC_OFFSET);
185 
186 	rtcc &= ~RTCC_CNTEN;
187 	writel(rtcc, priv->rtc_base + RTCC_OFFSET);
188 }
189 
190 static void s32g_rtc_enable(struct rtc_priv *priv)
191 {
192 	u32 rtcc = readl(priv->rtc_base + RTCC_OFFSET);
193 
194 	rtcc |= RTCC_CNTEN;
195 	writel(rtcc, priv->rtc_base + RTCC_OFFSET);
196 }
197 
198 static int rtc_clk_src_setup(struct rtc_priv *priv)
199 {
200 	u32 rtcc;
201 
202 	rtcc = FIELD_PREP(RTCC_CLKSEL_MASK, priv->clk_src_idx);
203 
204 	switch (priv->rtc_data->clk_div) {
205 	case DIV512_32:
206 		rtcc |= RTCC_DIV512EN;
207 		rtcc |= RTCC_DIV32EN;
208 		break;
209 	case DIV512:
210 		rtcc |= RTCC_DIV512EN;
211 		break;
212 	case DIV32:
213 		rtcc |= RTCC_DIV32EN;
214 		break;
215 	case DIV1:
216 		break;
217 	default:
218 		return -EINVAL;
219 	}
220 
221 	rtcc |= RTCC_APIEN | RTCC_APIIE;
222 	/*
223 	 * Make sure the CNTEN is 0 before we configure
224 	 * the clock source and dividers.
225 	 */
226 	s32g_rtc_disable(priv);
227 	writel(rtcc, priv->rtc_base + RTCC_OFFSET);
228 	s32g_rtc_enable(priv);
229 
230 	return 0;
231 }
232 
233 static const struct rtc_class_ops rtc_ops = {
234 	.read_time = s32g_rtc_read_time,
235 	.read_alarm = s32g_rtc_read_alarm,
236 	.set_alarm = s32g_rtc_set_alarm,
237 	.alarm_irq_enable = s32g_rtc_alarm_irq_enable,
238 };
239 
240 static int rtc_clk_dts_setup(struct rtc_priv *priv,
241 			     struct device *dev)
242 {
243 	u32 i;
244 
245 	priv->ipg = devm_clk_get_enabled(dev, "ipg");
246 	if (IS_ERR(priv->ipg))
247 		return dev_err_probe(dev, PTR_ERR(priv->ipg),
248 				"Failed to get 'ipg' clock\n");
249 
250 	for (i = 0; i < ARRAY_SIZE(rtc_clk_src); i++) {
251 		if (priv->rtc_data->reserved_clk_mask & BIT(i))
252 			return -EOPNOTSUPP;
253 
254 		priv->clk_src = devm_clk_get_enabled(dev, rtc_clk_src[i]);
255 		if (!IS_ERR(priv->clk_src)) {
256 			priv->clk_src_idx = i;
257 			break;
258 		}
259 	}
260 
261 	if (IS_ERR(priv->clk_src))
262 		return dev_err_probe(dev, PTR_ERR(priv->clk_src),
263 				"Failed to get rtc module clock source\n");
264 
265 	return 0;
266 }
267 
268 static int s32g_rtc_probe(struct platform_device *pdev)
269 {
270 	struct device *dev = &pdev->dev;
271 	struct rtc_priv *priv;
272 	unsigned long rtc_hz;
273 	int ret;
274 
275 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
276 	if (!priv)
277 		return -ENOMEM;
278 
279 	priv->rtc_data = of_device_get_match_data(dev);
280 	if (!priv->rtc_data)
281 		return -ENODEV;
282 
283 	priv->rtc_base = devm_platform_ioremap_resource(pdev, 0);
284 	if (IS_ERR(priv->rtc_base))
285 		return PTR_ERR(priv->rtc_base);
286 
287 	device_init_wakeup(dev, true);
288 
289 	ret = rtc_clk_dts_setup(priv, dev);
290 	if (ret)
291 		return ret;
292 
293 	priv->rdev = devm_rtc_allocate_device(dev);
294 	if (IS_ERR(priv->rdev))
295 		return PTR_ERR(priv->rdev);
296 
297 	ret = rtc_clk_src_setup(priv);
298 	if (ret)
299 		return ret;
300 
301 	priv->irq = platform_get_irq(pdev, 0);
302 	if (priv->irq < 0) {
303 		ret = priv->irq;
304 		goto disable_rtc;
305 	}
306 
307 	rtc_hz = clk_get_rate(priv->clk_src);
308 	if (!rtc_hz) {
309 		dev_err(dev, "Failed to get RTC frequency\n");
310 		ret = -EINVAL;
311 		goto disable_rtc;
312 	}
313 
314 	priv->rtc_hz = DIV_ROUND_UP(rtc_hz, priv->rtc_data->clk_div);
315 
316 	platform_set_drvdata(pdev, priv);
317 	priv->rdev->ops = &rtc_ops;
318 
319 	ret = devm_request_irq(dev, priv->irq,
320 			       s32g_rtc_handler, 0, dev_name(dev), pdev);
321 	if (ret) {
322 		dev_err(dev, "Request interrupt %d failed, error: %d\n",
323 			priv->irq, ret);
324 		goto disable_rtc;
325 	}
326 
327 	ret = devm_rtc_register_device(priv->rdev);
328 	if (ret)
329 		goto disable_rtc;
330 
331 	return 0;
332 
333 disable_rtc:
334 	s32g_rtc_disable(priv);
335 	return ret;
336 }
337 
338 static int s32g_rtc_suspend(struct device *dev)
339 {
340 	struct rtc_priv *priv = dev_get_drvdata(dev);
341 	u32 apival = readl(priv->rtc_base + APIVAL_OFFSET);
342 
343 	if (check_add_overflow(priv->sleep_sec, div64_u64(apival, priv->rtc_hz),
344 			       &priv->sleep_sec)) {
345 		dev_warn(dev, "Overflow on sleep cycles occurred. Resetting to 0.\n");
346 		priv->sleep_sec = 0;
347 	}
348 
349 	return 0;
350 }
351 
352 static int s32g_rtc_resume(struct device *dev)
353 {
354 	struct rtc_priv *priv = dev_get_drvdata(dev);
355 
356 	/* The transition from resume to run is a reset event.
357 	 * This leads to the RTC registers being reset after resume from
358 	 * suspend. It is uncommon, but this behaviour has been observed
359 	 * on S32G RTC after issuing a Suspend to RAM operation.
360 	 * Thus, reconfigure RTC registers on the resume path.
361 	 */
362 	return rtc_clk_src_setup(priv);
363 }
364 
365 static const struct of_device_id rtc_dt_ids[] = {
366 	{ .compatible = "nxp,s32g2-rtc", .data = &rtc_s32g2_data },
367 	{ /* sentinel */ },
368 };
369 
370 static DEFINE_SIMPLE_DEV_PM_OPS(s32g_rtc_pm_ops,
371 			 s32g_rtc_suspend, s32g_rtc_resume);
372 
373 static struct platform_driver s32g_rtc_driver = {
374 	.driver = {
375 		.name = "s32g-rtc",
376 		.pm = pm_sleep_ptr(&s32g_rtc_pm_ops),
377 		.of_match_table = rtc_dt_ids,
378 	},
379 	.probe = s32g_rtc_probe,
380 };
381 module_platform_driver(s32g_rtc_driver);
382 
383 MODULE_AUTHOR("NXP");
384 MODULE_DESCRIPTION("NXP RTC driver for S32G2/S32G3");
385 MODULE_LICENSE("GPL");
386