1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * RTC driver for the interal RTC block in the Amlogic Meson6, Meson8,
4  * Meson8b and Meson8m2 SoCs.
5  *
6  * The RTC is split in to two parts, the AHB front end and a simple serial
7  * connection to the actual registers. This driver manages both parts.
8  *
9  * Copyright (c) 2018 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
10  * Copyright (c) 2015 Ben Dooks <ben.dooks@codethink.co.uk> for Codethink Ltd
11  * Based on origin by Carlo Caione <carlo@endlessm.com>
12  */
13 
14 #include <linux/bitfield.h>
15 #include <linux/delay.h>
16 #include <linux/io.h>
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/nvmem-provider.h>
20 #include <linux/of.h>
21 #include <linux/platform_device.h>
22 #include <linux/regmap.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/reset.h>
25 #include <linux/rtc.h>
26 
27 /* registers accessed from cpu bus */
28 #define RTC_ADDR0				0x00
29 	#define RTC_ADDR0_LINE_SCLK		BIT(0)
30 	#define RTC_ADDR0_LINE_SEN		BIT(1)
31 	#define RTC_ADDR0_LINE_SDI		BIT(2)
32 	#define RTC_ADDR0_START_SER		BIT(17)
33 	#define RTC_ADDR0_WAIT_SER		BIT(22)
34 	#define RTC_ADDR0_DATA			GENMASK(31, 24)
35 
36 #define RTC_ADDR1				0x04
37 	#define RTC_ADDR1_SDO			BIT(0)
38 	#define RTC_ADDR1_S_READY		BIT(1)
39 
40 #define RTC_ADDR2				0x08
41 #define RTC_ADDR3				0x0c
42 
43 #define RTC_REG4				0x10
44 	#define RTC_REG4_STATIC_VALUE		GENMASK(7, 0)
45 
46 /* rtc registers accessed via rtc-serial interface */
47 #define RTC_COUNTER		(0)
48 #define RTC_SEC_ADJ		(2)
49 #define RTC_REGMEM_0		(4)
50 #define RTC_REGMEM_1		(5)
51 #define RTC_REGMEM_2		(6)
52 #define RTC_REGMEM_3		(7)
53 
54 #define RTC_ADDR_BITS		(3)	/* number of address bits to send */
55 #define RTC_DATA_BITS		(32)	/* number of data bits to tx/rx */
56 
57 #define MESON_STATIC_BIAS_CUR	(0x5 << 1)
58 #define MESON_STATIC_VOLTAGE	(0x3 << 11)
59 #define MESON_STATIC_DEFAULT    (MESON_STATIC_BIAS_CUR | MESON_STATIC_VOLTAGE)
60 
61 struct meson_rtc {
62 	struct device		*dev;		/* device we bound from */
63 	struct reset_control	*reset;		/* reset source */
64 	struct regulator	*vdd;		/* voltage input */
65 	struct regmap		*peripheral;	/* peripheral registers */
66 	struct regmap		*serial;	/* serial registers */
67 };
68 
69 static const struct regmap_config meson_rtc_peripheral_regmap_config = {
70 	.name		= "peripheral-registers",
71 	.reg_bits	= 8,
72 	.val_bits	= 32,
73 	.reg_stride	= 4,
74 	.max_register	= RTC_REG4,
75 	.fast_io	= true,
76 };
77 
78 /* RTC front-end serialiser controls */
79 
80 static void meson_rtc_sclk_pulse(struct meson_rtc *rtc)
81 {
82 	udelay(5);
83 	regmap_update_bits(rtc->peripheral, RTC_ADDR0, RTC_ADDR0_LINE_SCLK, 0);
84 	udelay(5);
85 	regmap_update_bits(rtc->peripheral, RTC_ADDR0, RTC_ADDR0_LINE_SCLK,
86 			   RTC_ADDR0_LINE_SCLK);
87 }
88 
89 static void meson_rtc_send_bit(struct meson_rtc *rtc, unsigned int bit)
90 {
91 	regmap_update_bits(rtc->peripheral, RTC_ADDR0, RTC_ADDR0_LINE_SDI,
92 			   bit ? RTC_ADDR0_LINE_SDI : 0);
93 	meson_rtc_sclk_pulse(rtc);
94 }
95 
96 static void meson_rtc_send_bits(struct meson_rtc *rtc, u32 data,
97 				unsigned int nr)
98 {
99 	u32 bit = 1 << (nr - 1);
100 
101 	while (bit) {
102 		meson_rtc_send_bit(rtc, data & bit);
103 		bit >>= 1;
104 	}
105 }
106 
107 static void meson_rtc_set_dir(struct meson_rtc *rtc, u32 mode)
108 {
109 	regmap_update_bits(rtc->peripheral, RTC_ADDR0, RTC_ADDR0_LINE_SEN, 0);
110 	regmap_update_bits(rtc->peripheral, RTC_ADDR0, RTC_ADDR0_LINE_SDI, 0);
111 	meson_rtc_send_bit(rtc, mode);
112 	regmap_update_bits(rtc->peripheral, RTC_ADDR0, RTC_ADDR0_LINE_SDI, 0);
113 }
114 
115 static u32 meson_rtc_get_data(struct meson_rtc *rtc)
116 {
117 	u32 tmp, val = 0;
118 	int bit;
119 
120 	for (bit = 0; bit < RTC_DATA_BITS; bit++) {
121 		meson_rtc_sclk_pulse(rtc);
122 		val <<= 1;
123 
124 		regmap_read(rtc->peripheral, RTC_ADDR1, &tmp);
125 		val |= tmp & RTC_ADDR1_SDO;
126 	}
127 
128 	return val;
129 }
130 
131 static int meson_rtc_get_bus(struct meson_rtc *rtc)
132 {
133 	int ret, retries;
134 	u32 val;
135 
136 	/* prepare bus for transfers, set all lines low */
137 	val = RTC_ADDR0_LINE_SDI | RTC_ADDR0_LINE_SEN | RTC_ADDR0_LINE_SCLK;
138 	regmap_update_bits(rtc->peripheral, RTC_ADDR0, val, 0);
139 
140 	for (retries = 0; retries < 3; retries++) {
141 		/* wait for the bus to be ready */
142 		if (!regmap_read_poll_timeout(rtc->peripheral, RTC_ADDR1, val,
143 					      val & RTC_ADDR1_S_READY, 10,
144 					      10000))
145 			return 0;
146 
147 		dev_warn(rtc->dev, "failed to get bus, resetting RTC\n");
148 
149 		ret = reset_control_reset(rtc->reset);
150 		if (ret)
151 			return ret;
152 	}
153 
154 	dev_err(rtc->dev, "bus is not ready\n");
155 	return -ETIMEDOUT;
156 }
157 
158 static int meson_rtc_serial_bus_reg_read(void *context, unsigned int reg,
159 					 unsigned int *data)
160 {
161 	struct meson_rtc *rtc = context;
162 	int ret;
163 
164 	ret = meson_rtc_get_bus(rtc);
165 	if (ret)
166 		return ret;
167 
168 	regmap_update_bits(rtc->peripheral, RTC_ADDR0, RTC_ADDR0_LINE_SEN,
169 			   RTC_ADDR0_LINE_SEN);
170 	meson_rtc_send_bits(rtc, reg, RTC_ADDR_BITS);
171 	meson_rtc_set_dir(rtc, 0);
172 	*data = meson_rtc_get_data(rtc);
173 
174 	return 0;
175 }
176 
177 static int meson_rtc_serial_bus_reg_write(void *context, unsigned int reg,
178 					  unsigned int data)
179 {
180 	struct meson_rtc *rtc = context;
181 	int ret;
182 
183 	ret = meson_rtc_get_bus(rtc);
184 	if (ret)
185 		return ret;
186 
187 	regmap_update_bits(rtc->peripheral, RTC_ADDR0, RTC_ADDR0_LINE_SEN,
188 			   RTC_ADDR0_LINE_SEN);
189 	meson_rtc_send_bits(rtc, data, RTC_DATA_BITS);
190 	meson_rtc_send_bits(rtc, reg, RTC_ADDR_BITS);
191 	meson_rtc_set_dir(rtc, 1);
192 
193 	return 0;
194 }
195 
196 static const struct regmap_bus meson_rtc_serial_bus = {
197 	.reg_read	= meson_rtc_serial_bus_reg_read,
198 	.reg_write	= meson_rtc_serial_bus_reg_write,
199 };
200 
201 static const struct regmap_config meson_rtc_serial_regmap_config = {
202 	.name		= "serial-registers",
203 	.reg_bits	= 4,
204 	.reg_stride	= 1,
205 	.val_bits	= 32,
206 	.max_register	= RTC_REGMEM_3,
207 	.fast_io	= false,
208 };
209 
210 static int meson_rtc_write_static(struct meson_rtc *rtc, u32 data)
211 {
212 	u32 tmp;
213 
214 	regmap_write(rtc->peripheral, RTC_REG4,
215 		     FIELD_PREP(RTC_REG4_STATIC_VALUE, (data >> 8)));
216 
217 	/* write the static value and start the auto serializer */
218 	tmp = FIELD_PREP(RTC_ADDR0_DATA, (data & 0xff)) | RTC_ADDR0_START_SER;
219 	regmap_update_bits(rtc->peripheral, RTC_ADDR0,
220 			   RTC_ADDR0_DATA | RTC_ADDR0_START_SER, tmp);
221 
222 	/* wait for the auto serializer to complete */
223 	return regmap_read_poll_timeout(rtc->peripheral, RTC_REG4, tmp,
224 					!(tmp & RTC_ADDR0_WAIT_SER), 10,
225 					10000);
226 }
227 
228 /* RTC interface layer functions */
229 
230 static int meson_rtc_gettime(struct device *dev, struct rtc_time *tm)
231 {
232 	struct meson_rtc *rtc = dev_get_drvdata(dev);
233 	u32 time;
234 	int ret;
235 
236 	ret = regmap_read(rtc->serial, RTC_COUNTER, &time);
237 	if (!ret)
238 		rtc_time64_to_tm(time, tm);
239 
240 	return ret;
241 }
242 
243 static int meson_rtc_settime(struct device *dev, struct rtc_time *tm)
244 {
245 	struct meson_rtc *rtc = dev_get_drvdata(dev);
246 
247 	return regmap_write(rtc->serial, RTC_COUNTER, rtc_tm_to_time64(tm));
248 }
249 
250 static const struct rtc_class_ops meson_rtc_ops = {
251 	.read_time	= meson_rtc_gettime,
252 	.set_time	= meson_rtc_settime,
253 };
254 
255 /* NVMEM interface layer functions */
256 
257 static int meson_rtc_regmem_read(void *context, unsigned int offset,
258 				 void *buf, size_t bytes)
259 {
260 	struct meson_rtc *rtc = context;
261 	unsigned int read_offset, read_size;
262 
263 	read_offset = RTC_REGMEM_0 + (offset / 4);
264 	read_size = bytes / 4;
265 
266 	return regmap_bulk_read(rtc->serial, read_offset, buf, read_size);
267 }
268 
269 static int meson_rtc_regmem_write(void *context, unsigned int offset,
270 				  void *buf, size_t bytes)
271 {
272 	struct meson_rtc *rtc = context;
273 	unsigned int write_offset, write_size;
274 
275 	write_offset = RTC_REGMEM_0 + (offset / 4);
276 	write_size = bytes / 4;
277 
278 	return regmap_bulk_write(rtc->serial, write_offset, buf, write_size);
279 }
280 
281 static int meson_rtc_probe(struct platform_device *pdev)
282 {
283 	struct nvmem_config meson_rtc_nvmem_config = {
284 		.name = "meson-rtc-regmem",
285 		.type = NVMEM_TYPE_BATTERY_BACKED,
286 		.word_size = 4,
287 		.stride = 4,
288 		.size = 4 * 4,
289 		.reg_read = meson_rtc_regmem_read,
290 		.reg_write = meson_rtc_regmem_write,
291 	};
292 	struct device *dev = &pdev->dev;
293 	struct meson_rtc *rtc;
294 	struct rtc_device *rtc_dev;
295 	void __iomem *base;
296 	int ret;
297 	u32 tm;
298 
299 	rtc = devm_kzalloc(dev, sizeof(struct meson_rtc), GFP_KERNEL);
300 	if (!rtc)
301 		return -ENOMEM;
302 
303 	rtc_dev = devm_rtc_allocate_device(dev);
304 	if (IS_ERR(rtc_dev))
305 		return PTR_ERR(rtc_dev);
306 
307 	platform_set_drvdata(pdev, rtc);
308 
309 	rtc->dev = dev;
310 
311 	rtc_dev->ops = &meson_rtc_ops;
312 	rtc_dev->range_max = U32_MAX;
313 
314 	base = devm_platform_ioremap_resource(pdev, 0);
315 	if (IS_ERR(base))
316 		return PTR_ERR(base);
317 
318 	rtc->peripheral = devm_regmap_init_mmio(dev, base,
319 					&meson_rtc_peripheral_regmap_config);
320 	if (IS_ERR(rtc->peripheral)) {
321 		dev_err(dev, "failed to create peripheral regmap\n");
322 		return PTR_ERR(rtc->peripheral);
323 	}
324 
325 	rtc->reset = devm_reset_control_get(dev, NULL);
326 	if (IS_ERR(rtc->reset)) {
327 		dev_err(dev, "missing reset line\n");
328 		return PTR_ERR(rtc->reset);
329 	}
330 
331 	rtc->vdd = devm_regulator_get(dev, "vdd");
332 	if (IS_ERR(rtc->vdd)) {
333 		dev_err(dev, "failed to get the vdd-supply\n");
334 		return PTR_ERR(rtc->vdd);
335 	}
336 
337 	ret = regulator_enable(rtc->vdd);
338 	if (ret) {
339 		dev_err(dev, "failed to enable vdd-supply\n");
340 		return ret;
341 	}
342 
343 	ret = meson_rtc_write_static(rtc, MESON_STATIC_DEFAULT);
344 	if (ret) {
345 		dev_err(dev, "failed to set static values\n");
346 		goto out_disable_vdd;
347 	}
348 
349 	rtc->serial = devm_regmap_init(dev, &meson_rtc_serial_bus, rtc,
350 				       &meson_rtc_serial_regmap_config);
351 	if (IS_ERR(rtc->serial)) {
352 		dev_err(dev, "failed to create serial regmap\n");
353 		ret = PTR_ERR(rtc->serial);
354 		goto out_disable_vdd;
355 	}
356 
357 	/*
358 	 * check if we can read RTC counter, if not then the RTC is probably
359 	 * not functional. If it isn't probably best to not bind.
360 	 */
361 	ret = regmap_read(rtc->serial, RTC_COUNTER, &tm);
362 	if (ret) {
363 		dev_err(dev, "cannot read RTC counter, RTC not functional\n");
364 		goto out_disable_vdd;
365 	}
366 
367 	meson_rtc_nvmem_config.priv = rtc;
368 	ret = devm_rtc_nvmem_register(rtc_dev, &meson_rtc_nvmem_config);
369 	if (ret)
370 		goto out_disable_vdd;
371 
372 	ret = devm_rtc_register_device(rtc_dev);
373 	if (ret)
374 		goto out_disable_vdd;
375 
376 	return 0;
377 
378 out_disable_vdd:
379 	regulator_disable(rtc->vdd);
380 	return ret;
381 }
382 
383 static const __maybe_unused struct of_device_id meson_rtc_dt_match[] = {
384 	{ .compatible = "amlogic,meson6-rtc", },
385 	{ .compatible = "amlogic,meson8-rtc", },
386 	{ .compatible = "amlogic,meson8b-rtc", },
387 	{ .compatible = "amlogic,meson8m2-rtc", },
388 	{ },
389 };
390 MODULE_DEVICE_TABLE(of, meson_rtc_dt_match);
391 
392 static struct platform_driver meson_rtc_driver = {
393 	.probe		= meson_rtc_probe,
394 	.driver		= {
395 		.name		= "meson-rtc",
396 		.of_match_table	= of_match_ptr(meson_rtc_dt_match),
397 	},
398 };
399 module_platform_driver(meson_rtc_driver);
400 
401 MODULE_DESCRIPTION("Amlogic Meson RTC Driver");
402 MODULE_AUTHOR("Ben Dooks <ben.dooks@codethink.co.uk>");
403 MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
404 MODULE_LICENSE("GPL v2");
405 MODULE_ALIAS("platform:meson-rtc");
406