1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright 2024 NXP. 4 * NXP PF9453 pmic driver 5 */ 6 7 #include <linux/bits.h> 8 #include <linux/err.h> 9 #include <linux/gpio/consumer.h> 10 #include <linux/i2c.h> 11 #include <linux/interrupt.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/platform_device.h> 16 #include <linux/regmap.h> 17 #include <linux/regulator/driver.h> 18 #include <linux/regulator/machine.h> 19 #include <linux/regulator/of_regulator.h> 20 21 struct pf9453_dvs_config { 22 unsigned int run_reg; /* dvs0 */ 23 unsigned int run_mask; 24 unsigned int standby_reg; /* dvs1 */ 25 unsigned int standby_mask; 26 }; 27 28 struct pf9453_regulator_desc { 29 struct regulator_desc desc; 30 const struct pf9453_dvs_config dvs; 31 }; 32 33 struct pf9453 { 34 struct device *dev; 35 struct regmap *regmap; 36 struct gpio_desc *sd_vsel_gpio; 37 int irq; 38 }; 39 40 enum { 41 PF9453_BUCK1 = 0, 42 PF9453_BUCK2, 43 PF9453_BUCK3, 44 PF9453_BUCK4, 45 PF9453_LDO1, 46 PF9453_LDO2, 47 PF9453_LDOSNVS, 48 PF9453_REGULATOR_CNT 49 }; 50 51 enum { 52 PF9453_DVS_LEVEL_RUN = 0, 53 PF9453_DVS_LEVEL_STANDBY, 54 PF9453_DVS_LEVEL_DPSTANDBY, 55 PF9453_DVS_LEVEL_MAX 56 }; 57 58 #define PF9453_BUCK1_VOLTAGE_NUM 0x80 59 #define PF9453_BUCK2_VOLTAGE_NUM 0x80 60 #define PF9453_BUCK3_VOLTAGE_NUM 0x80 61 #define PF9453_BUCK4_VOLTAGE_NUM 0x80 62 63 #define PF9453_LDO1_VOLTAGE_NUM 0x65 64 #define PF9453_LDO2_VOLTAGE_NUM 0x3b 65 #define PF9453_LDOSNVS_VOLTAGE_NUM 0x59 66 67 enum { 68 PF9453_REG_DEV_ID = 0x00, 69 PF9453_REG_OTP_VER = 0x01, 70 PF9453_REG_INT1 = 0x02, 71 PF9453_REG_INT1_MASK = 0x03, 72 PF9453_REG_INT1_STATUS = 0x04, 73 PF9453_REG_VRFLT1_INT = 0x05, 74 PF9453_REG_VRFLT1_MASK = 0x06, 75 PF9453_REG_PWRON_STAT = 0x07, 76 PF9453_REG_RESET_CTRL = 0x08, 77 PF9453_REG_SW_RST = 0x09, 78 PF9453_REG_PWR_CTRL = 0x0a, 79 PF9453_REG_CONFIG1 = 0x0b, 80 PF9453_REG_CONFIG2 = 0x0c, 81 PF9453_REG_32K_CONFIG = 0x0d, 82 PF9453_REG_BUCK1CTRL = 0x10, 83 PF9453_REG_BUCK1OUT = 0x11, 84 PF9453_REG_BUCK2CTRL = 0x14, 85 PF9453_REG_BUCK2OUT = 0x15, 86 PF9453_REG_BUCK2OUT_STBY = 0x1d, 87 PF9453_REG_BUCK2OUT_MAX_LIMIT = 0x1f, 88 PF9453_REG_BUCK2OUT_MIN_LIMIT = 0x20, 89 PF9453_REG_BUCK3CTRL = 0x21, 90 PF9453_REG_BUCK3OUT = 0x22, 91 PF9453_REG_BUCK4CTRL = 0x2e, 92 PF9453_REG_BUCK4OUT = 0x2f, 93 PF9453_REG_LDO1OUT_L = 0x36, 94 PF9453_REG_LDO1CFG = 0x37, 95 PF9453_REG_LDO1OUT_H = 0x38, 96 PF9453_REG_LDOSNVS_CFG1 = 0x39, 97 PF9453_REG_LDOSNVS_CFG2 = 0x3a, 98 PF9453_REG_LDO2CFG = 0x3b, 99 PF9453_REG_LDO2OUT = 0x3c, 100 PF9453_REG_BUCK_POK = 0x3d, 101 PF9453_REG_LSW_CTRL1 = 0x40, 102 PF9453_REG_LSW_CTRL2 = 0x41, 103 PF9453_REG_LOCK = 0x4e, 104 PF9453_MAX_REG 105 }; 106 107 #define PF9453_UNLOCK_KEY 0x5c 108 #define PF9453_LOCK_KEY 0x0 109 110 /* PF9453 BUCK ENMODE bits */ 111 #define BUCK_ENMODE_OFF 0x00 112 #define BUCK_ENMODE_ONREQ 0x01 113 #define BUCK_ENMODE_ONREQ_STBY 0x02 114 #define BUCK_ENMODE_ONREQ_STBY_DPSTBY 0x03 115 116 /* PF9453 BUCK ENMODE bits */ 117 #define LDO_ENMODE_OFF 0x00 118 #define LDO_ENMODE_ONREQ 0x01 119 #define LDO_ENMODE_ONREQ_STBY 0x02 120 #define LDO_ENMODE_ONREQ_STBY_DPSTBY 0x03 121 122 /* PF9453_REG_BUCK1_CTRL bits */ 123 #define BUCK1_LPMODE 0x30 124 #define BUCK1_AD 0x08 125 #define BUCK1_FPWM 0x04 126 #define BUCK1_ENMODE_MASK GENMASK(1, 0) 127 128 /* PF9453_REG_BUCK2_CTRL bits */ 129 #define BUCK2_RAMP_MASK GENMASK(7, 6) 130 #define BUCK2_RAMP_25MV 0x0 131 #define BUCK2_RAMP_12P5MV 0x1 132 #define BUCK2_RAMP_6P25MV 0x2 133 #define BUCK2_RAMP_3P125MV 0x3 134 #define BUCK2_LPMODE 0x30 135 #define BUCK2_AD 0x08 136 #define BUCK2_FPWM 0x04 137 #define BUCK2_ENMODE_MASK GENMASK(1, 0) 138 139 /* PF9453_REG_BUCK3_CTRL bits */ 140 #define BUCK3_LPMODE 0x30 141 #define BUCK3_AD 0x08 142 #define BUCK3_FPWM 0x04 143 #define BUCK3_ENMODE_MASK GENMASK(1, 0) 144 145 /* PF9453_REG_BUCK4_CTRL bits */ 146 #define BUCK4_LPMODE 0x30 147 #define BUCK4_AD 0x08 148 #define BUCK4_FPWM 0x04 149 #define BUCK4_ENMODE_MASK GENMASK(1, 0) 150 151 /* PF9453_REG_BUCK123_PRESET_EN bit */ 152 #define BUCK123_PRESET_EN 0x80 153 154 /* PF9453_BUCK1OUT bits */ 155 #define BUCK1OUT_MASK GENMASK(6, 0) 156 157 /* PF9453_BUCK2OUT bits */ 158 #define BUCK2OUT_MASK GENMASK(6, 0) 159 #define BUCK2OUT_STBY_MASK GENMASK(6, 0) 160 161 /* PF9453_REG_BUCK3OUT bits */ 162 #define BUCK3OUT_MASK GENMASK(6, 0) 163 164 /* PF9453_REG_BUCK4OUT bits */ 165 #define BUCK4OUT_MASK GENMASK(6, 0) 166 167 /* PF9453_REG_LDO1_VOLT bits */ 168 #define LDO1_EN_MASK GENMASK(1, 0) 169 #define LDO1OUT_MASK GENMASK(6, 0) 170 171 /* PF9453_REG_LDO2_VOLT bits */ 172 #define LDO2_EN_MASK GENMASK(1, 0) 173 #define LDO2OUT_MASK GENMASK(6, 0) 174 175 /* PF9453_REG_LDOSNVS_VOLT bits */ 176 #define LDOSNVS_EN_MASK GENMASK(0, 0) 177 #define LDOSNVSCFG1_MASK GENMASK(6, 0) 178 179 /* PF9453_REG_IRQ bits */ 180 #define IRQ_RSVD 0x80 181 #define IRQ_RSTB 0x40 182 #define IRQ_ONKEY 0x20 183 #define IRQ_RESETKEY 0x10 184 #define IRQ_VR_FLT1 0x08 185 #define IRQ_LOWVSYS 0x04 186 #define IRQ_THERM_100 0x02 187 #define IRQ_THERM_80 0x01 188 189 /* PF9453_REG_RESET_CTRL bits */ 190 #define WDOG_B_CFG_MASK GENMASK(7, 6) 191 #define WDOG_B_CFG_NONE 0x00 192 #define WDOG_B_CFG_WARM 0x40 193 #define WDOG_B_CFG_COLD 0x80 194 195 /* PF9453_REG_CONFIG2 bits */ 196 #define I2C_LT_MASK GENMASK(1, 0) 197 #define I2C_LT_FORCE_DISABLE 0x00 198 #define I2C_LT_ON_STANDBY_RUN 0x01 199 #define I2C_LT_ON_RUN 0x02 200 #define I2C_LT_FORCE_ENABLE 0x03 201 202 static const struct regmap_range pf9453_status_range = { 203 .range_min = PF9453_REG_INT1, 204 .range_max = PF9453_REG_PWRON_STAT, 205 }; 206 207 static const struct regmap_access_table pf9453_volatile_regs = { 208 .yes_ranges = &pf9453_status_range, 209 .n_yes_ranges = 1, 210 }; 211 212 static const struct regmap_config pf9453_regmap_config = { 213 .reg_bits = 8, 214 .val_bits = 8, 215 .volatile_table = &pf9453_volatile_regs, 216 .max_register = PF9453_MAX_REG - 1, 217 .cache_type = REGCACHE_MAPLE, 218 }; 219 220 /* 221 * BUCK2 222 * BUCK2RAM[1:0] BUCK2 DVS ramp rate setting 223 * 00: 25mV/1usec 224 * 01: 25mV/2usec 225 * 10: 25mV/4usec 226 * 11: 25mV/8usec 227 */ 228 static const unsigned int pf9453_dvs_buck_ramp_table[] = { 229 25000, 12500, 6250, 3125 230 }; 231 232 static bool is_reg_protect(uint reg) 233 { 234 switch (reg) { 235 case PF9453_REG_BUCK1OUT: 236 case PF9453_REG_BUCK2OUT: 237 case PF9453_REG_BUCK3OUT: 238 case PF9453_REG_BUCK4OUT: 239 case PF9453_REG_LDO1OUT_L: 240 case PF9453_REG_LDO1OUT_H: 241 case PF9453_REG_LDO2OUT: 242 case PF9453_REG_LDOSNVS_CFG1: 243 case PF9453_REG_BUCK2OUT_MAX_LIMIT: 244 case PF9453_REG_BUCK2OUT_MIN_LIMIT: 245 return true; 246 default: 247 return false; 248 } 249 } 250 251 static int pf9453_pmic_write(struct pf9453 *pf9453, unsigned int reg, u8 mask, unsigned int val) 252 { 253 int ret = -EINVAL; 254 u8 data, key; 255 u32 rxBuf; 256 257 /* If not updating entire register, perform a read-mod-write */ 258 data = val; 259 key = PF9453_UNLOCK_KEY; 260 261 if (mask != 0xffU) { 262 /* Read data */ 263 ret = regmap_read(pf9453->regmap, reg, &rxBuf); 264 if (ret) { 265 dev_err(pf9453->dev, "Read reg=%0x error!\n", reg); 266 return ret; 267 } 268 data = (val & mask) | (rxBuf & (~mask)); 269 } 270 271 if (reg < PF9453_MAX_REG) { 272 if (is_reg_protect(reg)) { 273 ret = regmap_raw_write(pf9453->regmap, PF9453_REG_LOCK, &key, 1U); 274 if (ret) { 275 dev_err(pf9453->dev, "Write reg=%0x error!\n", reg); 276 return ret; 277 } 278 279 ret = regmap_raw_write(pf9453->regmap, reg, &data, 1U); 280 if (ret) { 281 dev_err(pf9453->dev, "Write reg=%0x error!\n", reg); 282 return ret; 283 } 284 285 key = PF9453_LOCK_KEY; 286 ret = regmap_raw_write(pf9453->regmap, PF9453_REG_LOCK, &key, 1U); 287 if (ret) { 288 dev_err(pf9453->dev, "Write reg=%0x error!\n", reg); 289 return ret; 290 } 291 } else { 292 ret = regmap_raw_write(pf9453->regmap, reg, &data, 1U); 293 if (ret) { 294 dev_err(pf9453->dev, "Write reg=%0x error!\n", reg); 295 return ret; 296 } 297 } 298 } 299 300 return ret; 301 } 302 303 /** 304 * pf9453_regulator_enable_regmap for regmap users 305 * 306 * @rdev: regulator to operate on 307 * 308 * Regulators that use regmap for their register I/O can set the 309 * enable_reg and enable_mask fields in their descriptor and then use 310 * this as their enable() operation, saving some code. 311 */ 312 static int pf9453_regulator_enable_regmap(struct regulator_dev *rdev) 313 { 314 struct pf9453 *pf9453 = dev_get_drvdata(rdev->dev.parent); 315 unsigned int val; 316 317 if (rdev->desc->enable_is_inverted) { 318 val = rdev->desc->disable_val; 319 } else { 320 val = rdev->desc->enable_val; 321 if (!val) 322 val = rdev->desc->enable_mask; 323 } 324 325 return pf9453_pmic_write(pf9453, rdev->desc->enable_reg, rdev->desc->enable_mask, val); 326 } 327 328 /** 329 * pf9453_regulator_disable_regmap for regmap users 330 * 331 * @rdev: regulator to operate on 332 * 333 * Regulators that use regmap for their register I/O can set the 334 * enable_reg and enable_mask fields in their descriptor and then use 335 * this as their disable() operation, saving some code. 336 */ 337 static int pf9453_regulator_disable_regmap(struct regulator_dev *rdev) 338 { 339 struct pf9453 *pf9453 = dev_get_drvdata(rdev->dev.parent); 340 unsigned int val; 341 342 if (rdev->desc->enable_is_inverted) { 343 val = rdev->desc->enable_val; 344 if (!val) 345 val = rdev->desc->enable_mask; 346 } else { 347 val = rdev->desc->disable_val; 348 } 349 350 return pf9453_pmic_write(pf9453, rdev->desc->enable_reg, rdev->desc->enable_mask, val); 351 } 352 353 /** 354 * pf9453_regulator_set_voltage_sel_regmap for regmap users 355 * 356 * @rdev: regulator to operate on 357 * @sel: Selector to set 358 * 359 * Regulators that use regmap for their register I/O can set the 360 * vsel_reg and vsel_mask fields in their descriptor and then use this 361 * as their set_voltage_vsel operation, saving some code. 362 */ 363 static int pf9453_regulator_set_voltage_sel_regmap(struct regulator_dev *rdev, unsigned int sel) 364 { 365 struct pf9453 *pf9453 = dev_get_drvdata(rdev->dev.parent); 366 int ret; 367 368 sel <<= ffs(rdev->desc->vsel_mask) - 1; 369 ret = pf9453_pmic_write(pf9453, rdev->desc->vsel_reg, rdev->desc->vsel_mask, sel); 370 if (ret) 371 return ret; 372 373 if (rdev->desc->apply_bit) 374 ret = pf9453_pmic_write(pf9453, rdev->desc->apply_reg, 375 rdev->desc->apply_bit, rdev->desc->apply_bit); 376 return ret; 377 } 378 379 static int find_closest_bigger(unsigned int target, const unsigned int *table, 380 unsigned int num_sel, unsigned int *sel) 381 { 382 unsigned int s, tmp, max, maxsel = 0; 383 bool found = false; 384 385 max = table[0]; 386 387 for (s = 0; s < num_sel; s++) { 388 if (table[s] > max) { 389 max = table[s]; 390 maxsel = s; 391 } 392 if (table[s] >= target) { 393 if (!found || table[s] - target < tmp - target) { 394 tmp = table[s]; 395 *sel = s; 396 found = true; 397 if (tmp == target) 398 break; 399 } 400 } 401 } 402 403 if (!found) { 404 *sel = maxsel; 405 return -EINVAL; 406 } 407 408 return 0; 409 } 410 411 /** 412 * pf9453_regulator_set_ramp_delay_regmap 413 * 414 * @rdev: regulator to operate on 415 * @ramp_delay: desired ramp delay value in microseconds 416 * 417 * Regulators that use regmap for their register I/O can set the ramp_reg 418 * and ramp_mask fields in their descriptor and then use this as their 419 * set_ramp_delay operation, saving some code. 420 */ 421 static int pf9453_regulator_set_ramp_delay_regmap(struct regulator_dev *rdev, int ramp_delay) 422 { 423 struct pf9453 *pf9453 = dev_get_drvdata(rdev->dev.parent); 424 unsigned int sel; 425 int ret; 426 427 if (WARN_ON(!rdev->desc->n_ramp_values || !rdev->desc->ramp_delay_table)) 428 return -EINVAL; 429 430 ret = find_closest_bigger(ramp_delay, rdev->desc->ramp_delay_table, 431 rdev->desc->n_ramp_values, &sel); 432 433 if (ret) { 434 dev_warn(rdev_get_dev(rdev), 435 "Can't set ramp-delay %u, setting %u\n", ramp_delay, 436 rdev->desc->ramp_delay_table[sel]); 437 } 438 439 sel <<= ffs(rdev->desc->ramp_mask) - 1; 440 441 return pf9453_pmic_write(pf9453, rdev->desc->ramp_reg, 442 rdev->desc->ramp_mask, sel); 443 } 444 445 static const struct regulator_ops pf9453_dvs_buck_regulator_ops = { 446 .enable = pf9453_regulator_enable_regmap, 447 .disable = pf9453_regulator_disable_regmap, 448 .is_enabled = regulator_is_enabled_regmap, 449 .list_voltage = regulator_list_voltage_linear_range, 450 .set_voltage_sel = pf9453_regulator_set_voltage_sel_regmap, 451 .get_voltage_sel = regulator_get_voltage_sel_regmap, 452 .set_voltage_time_sel = regulator_set_voltage_time_sel, 453 .set_ramp_delay = pf9453_regulator_set_ramp_delay_regmap, 454 }; 455 456 static const struct regulator_ops pf9453_buck_regulator_ops = { 457 .enable = pf9453_regulator_enable_regmap, 458 .disable = pf9453_regulator_disable_regmap, 459 .is_enabled = regulator_is_enabled_regmap, 460 .list_voltage = regulator_list_voltage_linear_range, 461 .set_voltage_sel = pf9453_regulator_set_voltage_sel_regmap, 462 .get_voltage_sel = regulator_get_voltage_sel_regmap, 463 .set_voltage_time_sel = regulator_set_voltage_time_sel, 464 }; 465 466 static const struct regulator_ops pf9453_ldo_regulator_ops = { 467 .enable = pf9453_regulator_enable_regmap, 468 .disable = pf9453_regulator_disable_regmap, 469 .is_enabled = regulator_is_enabled_regmap, 470 .list_voltage = regulator_list_voltage_linear_range, 471 .set_voltage_sel = pf9453_regulator_set_voltage_sel_regmap, 472 .get_voltage_sel = regulator_get_voltage_sel_regmap, 473 }; 474 475 /* 476 * BUCK1/3/4 477 * 0.60 to 3.775V (25mV step) 478 */ 479 static const struct linear_range pf9453_buck134_volts[] = { 480 REGULATOR_LINEAR_RANGE(600000, 0x00, 0x7F, 25000), 481 }; 482 483 /* 484 * BUCK2 485 * 0.60 to 2.1875V (12.5mV step) 486 */ 487 static const struct linear_range pf9453_buck2_volts[] = { 488 REGULATOR_LINEAR_RANGE(600000, 0x00, 0x7F, 12500), 489 }; 490 491 /* 492 * LDO1 493 * 0.8 to 3.3V (25mV step) 494 */ 495 static const struct linear_range pf9453_ldo1_volts[] = { 496 REGULATOR_LINEAR_RANGE(800000, 0x00, 0x64, 25000), 497 }; 498 499 /* 500 * LDO2 501 * 0.5 to 1.95V (25mV step) 502 */ 503 static const struct linear_range pf9453_ldo2_volts[] = { 504 REGULATOR_LINEAR_RANGE(500000, 0x00, 0x3A, 25000), 505 }; 506 507 /* 508 * LDOSNVS 509 * 1.2 to 3.4V (25mV step) 510 */ 511 static const struct linear_range pf9453_ldosnvs_volts[] = { 512 REGULATOR_LINEAR_RANGE(1200000, 0x00, 0x58, 25000), 513 }; 514 515 static int buck_set_dvs(const struct regulator_desc *desc, 516 struct device_node *np, struct pf9453 *pf9453, 517 char *prop, unsigned int reg, unsigned int mask) 518 { 519 int ret, i; 520 u32 uv; 521 522 ret = of_property_read_u32(np, prop, &uv); 523 if (ret == -EINVAL) 524 return 0; 525 else if (ret) 526 return ret; 527 528 for (i = 0; i < desc->n_voltages; i++) { 529 ret = regulator_desc_list_voltage_linear_range(desc, i); 530 if (ret < 0) 531 continue; 532 if (ret == uv) { 533 i <<= ffs(desc->vsel_mask) - 1; 534 ret = pf9453_pmic_write(pf9453, reg, mask, i); 535 break; 536 } 537 } 538 539 if (ret == 0) { 540 struct pf9453_regulator_desc *regulator = container_of(desc, 541 struct pf9453_regulator_desc, desc); 542 543 /* Enable DVS control through PMIC_STBY_REQ for this BUCK */ 544 ret = pf9453_pmic_write(pf9453, regulator->desc.enable_reg, 545 BUCK2_LPMODE, BUCK2_LPMODE); 546 } 547 return ret; 548 } 549 550 static int pf9453_set_dvs_levels(struct device_node *np, const struct regulator_desc *desc, 551 struct regulator_config *cfg) 552 { 553 struct pf9453_regulator_desc *data = container_of(desc, struct pf9453_regulator_desc, desc); 554 struct pf9453 *pf9453 = dev_get_drvdata(cfg->dev); 555 const struct pf9453_dvs_config *dvs = &data->dvs; 556 unsigned int reg, mask; 557 int i, ret = 0; 558 char *prop; 559 560 for (i = 0; i < PF9453_DVS_LEVEL_MAX; i++) { 561 switch (i) { 562 case PF9453_DVS_LEVEL_RUN: 563 prop = "nxp,dvs-run-voltage"; 564 reg = dvs->run_reg; 565 mask = dvs->run_mask; 566 break; 567 case PF9453_DVS_LEVEL_DPSTANDBY: 568 case PF9453_DVS_LEVEL_STANDBY: 569 prop = "nxp,dvs-standby-voltage"; 570 reg = dvs->standby_reg; 571 mask = dvs->standby_mask; 572 break; 573 default: 574 return -EINVAL; 575 } 576 577 ret = buck_set_dvs(desc, np, pf9453, prop, reg, mask); 578 if (ret) 579 break; 580 } 581 582 return ret; 583 } 584 585 static const struct pf9453_regulator_desc pf9453_regulators[] = { 586 { 587 .desc = { 588 .name = "buck1", 589 .of_match = of_match_ptr("BUCK1"), 590 .regulators_node = of_match_ptr("regulators"), 591 .id = PF9453_BUCK1, 592 .ops = &pf9453_buck_regulator_ops, 593 .type = REGULATOR_VOLTAGE, 594 .n_voltages = PF9453_BUCK1_VOLTAGE_NUM, 595 .linear_ranges = pf9453_buck134_volts, 596 .n_linear_ranges = ARRAY_SIZE(pf9453_buck134_volts), 597 .vsel_reg = PF9453_REG_BUCK1OUT, 598 .vsel_mask = BUCK1OUT_MASK, 599 .enable_reg = PF9453_REG_BUCK1CTRL, 600 .enable_mask = BUCK1_ENMODE_MASK, 601 .enable_val = BUCK_ENMODE_ONREQ, 602 .owner = THIS_MODULE, 603 }, 604 }, 605 { 606 .desc = { 607 .name = "buck2", 608 .of_match = of_match_ptr("BUCK2"), 609 .regulators_node = of_match_ptr("regulators"), 610 .id = PF9453_BUCK2, 611 .ops = &pf9453_dvs_buck_regulator_ops, 612 .type = REGULATOR_VOLTAGE, 613 .n_voltages = PF9453_BUCK2_VOLTAGE_NUM, 614 .linear_ranges = pf9453_buck2_volts, 615 .n_linear_ranges = ARRAY_SIZE(pf9453_buck2_volts), 616 .vsel_reg = PF9453_REG_BUCK2OUT, 617 .vsel_mask = BUCK2OUT_MASK, 618 .enable_reg = PF9453_REG_BUCK2CTRL, 619 .enable_mask = BUCK2_ENMODE_MASK, 620 .enable_val = BUCK_ENMODE_ONREQ, 621 .ramp_reg = PF9453_REG_BUCK2CTRL, 622 .ramp_mask = BUCK2_RAMP_MASK, 623 .ramp_delay_table = pf9453_dvs_buck_ramp_table, 624 .n_ramp_values = ARRAY_SIZE(pf9453_dvs_buck_ramp_table), 625 .owner = THIS_MODULE, 626 .of_parse_cb = pf9453_set_dvs_levels, 627 }, 628 .dvs = { 629 .run_reg = PF9453_REG_BUCK2OUT, 630 .run_mask = BUCK2OUT_MASK, 631 .standby_reg = PF9453_REG_BUCK2OUT_STBY, 632 .standby_mask = BUCK2OUT_STBY_MASK, 633 }, 634 }, 635 { 636 .desc = { 637 .name = "buck3", 638 .of_match = of_match_ptr("BUCK3"), 639 .regulators_node = of_match_ptr("regulators"), 640 .id = PF9453_BUCK3, 641 .ops = &pf9453_buck_regulator_ops, 642 .type = REGULATOR_VOLTAGE, 643 .n_voltages = PF9453_BUCK3_VOLTAGE_NUM, 644 .linear_ranges = pf9453_buck134_volts, 645 .n_linear_ranges = ARRAY_SIZE(pf9453_buck134_volts), 646 .vsel_reg = PF9453_REG_BUCK3OUT, 647 .vsel_mask = BUCK3OUT_MASK, 648 .enable_reg = PF9453_REG_BUCK3CTRL, 649 .enable_mask = BUCK3_ENMODE_MASK, 650 .enable_val = BUCK_ENMODE_ONREQ, 651 .owner = THIS_MODULE, 652 }, 653 }, 654 { 655 .desc = { 656 .name = "buck4", 657 .of_match = of_match_ptr("BUCK4"), 658 .regulators_node = of_match_ptr("regulators"), 659 .id = PF9453_BUCK4, 660 .ops = &pf9453_buck_regulator_ops, 661 .type = REGULATOR_VOLTAGE, 662 .n_voltages = PF9453_BUCK4_VOLTAGE_NUM, 663 .linear_ranges = pf9453_buck134_volts, 664 .n_linear_ranges = ARRAY_SIZE(pf9453_buck134_volts), 665 .vsel_reg = PF9453_REG_BUCK4OUT, 666 .vsel_mask = BUCK4OUT_MASK, 667 .enable_reg = PF9453_REG_BUCK4CTRL, 668 .enable_mask = BUCK4_ENMODE_MASK, 669 .enable_val = BUCK_ENMODE_ONREQ, 670 .owner = THIS_MODULE, 671 }, 672 }, 673 { 674 .desc = { 675 .name = "ldo1", 676 .of_match = of_match_ptr("LDO1"), 677 .regulators_node = of_match_ptr("regulators"), 678 .id = PF9453_LDO1, 679 .ops = &pf9453_ldo_regulator_ops, 680 .type = REGULATOR_VOLTAGE, 681 .n_voltages = PF9453_LDO1_VOLTAGE_NUM, 682 .linear_ranges = pf9453_ldo1_volts, 683 .n_linear_ranges = ARRAY_SIZE(pf9453_ldo1_volts), 684 .vsel_reg = PF9453_REG_LDO1OUT_H, 685 .vsel_mask = LDO1OUT_MASK, 686 .enable_reg = PF9453_REG_LDO1CFG, 687 .enable_mask = LDO1_EN_MASK, 688 .enable_val = LDO_ENMODE_ONREQ, 689 .owner = THIS_MODULE, 690 }, 691 }, 692 { 693 .desc = { 694 .name = "ldo2", 695 .of_match = of_match_ptr("LDO2"), 696 .regulators_node = of_match_ptr("regulators"), 697 .id = PF9453_LDO2, 698 .ops = &pf9453_ldo_regulator_ops, 699 .type = REGULATOR_VOLTAGE, 700 .n_voltages = PF9453_LDO2_VOLTAGE_NUM, 701 .linear_ranges = pf9453_ldo2_volts, 702 .n_linear_ranges = ARRAY_SIZE(pf9453_ldo2_volts), 703 .vsel_reg = PF9453_REG_LDO2OUT, 704 .vsel_mask = LDO2OUT_MASK, 705 .enable_reg = PF9453_REG_LDO2CFG, 706 .enable_mask = LDO2_EN_MASK, 707 .enable_val = LDO_ENMODE_ONREQ, 708 .owner = THIS_MODULE, 709 }, 710 }, 711 { 712 .desc = { 713 .name = "ldosnvs", 714 .of_match = of_match_ptr("LDO-SNVS"), 715 .regulators_node = of_match_ptr("regulators"), 716 .id = PF9453_LDOSNVS, 717 .ops = &pf9453_ldo_regulator_ops, 718 .type = REGULATOR_VOLTAGE, 719 .n_voltages = PF9453_LDOSNVS_VOLTAGE_NUM, 720 .linear_ranges = pf9453_ldosnvs_volts, 721 .n_linear_ranges = ARRAY_SIZE(pf9453_ldosnvs_volts), 722 .vsel_reg = PF9453_REG_LDOSNVS_CFG1, 723 .vsel_mask = LDOSNVSCFG1_MASK, 724 .enable_reg = PF9453_REG_LDOSNVS_CFG2, 725 .enable_mask = LDOSNVS_EN_MASK, 726 .owner = THIS_MODULE, 727 }, 728 }, 729 { } 730 }; 731 732 static irqreturn_t pf9453_irq_handler(int irq, void *data) 733 { 734 struct pf9453 *pf9453 = data; 735 struct regmap *regmap = pf9453->regmap; 736 unsigned int status; 737 int ret; 738 739 ret = regmap_read(regmap, PF9453_REG_INT1, &status); 740 if (ret < 0) { 741 dev_err(pf9453->dev, "Failed to read INT1(%d)\n", ret); 742 return IRQ_NONE; 743 } 744 745 if (status & IRQ_RSTB) 746 dev_warn(pf9453->dev, "IRQ_RSTB interrupt.\n"); 747 748 if (status & IRQ_ONKEY) 749 dev_warn(pf9453->dev, "IRQ_ONKEY interrupt.\n"); 750 751 if (status & IRQ_VR_FLT1) 752 dev_warn(pf9453->dev, "VRFLT1 interrupt.\n"); 753 754 if (status & IRQ_RESETKEY) 755 dev_warn(pf9453->dev, "IRQ_RESETKEY interrupt.\n"); 756 757 if (status & IRQ_LOWVSYS) 758 dev_warn(pf9453->dev, "LOWVSYS interrupt.\n"); 759 760 if (status & IRQ_THERM_100) 761 dev_warn(pf9453->dev, "IRQ_THERM_100 interrupt.\n"); 762 763 if (status & IRQ_THERM_80) 764 dev_warn(pf9453->dev, "IRQ_THERM_80 interrupt.\n"); 765 766 return IRQ_HANDLED; 767 } 768 769 static int pf9453_i2c_probe(struct i2c_client *i2c) 770 { 771 const struct pf9453_regulator_desc *regulator_desc = of_device_get_match_data(&i2c->dev); 772 struct regulator_config config = { }; 773 unsigned int reset_ctrl; 774 unsigned int device_id; 775 struct pf9453 *pf9453; 776 int ret; 777 778 if (!i2c->irq) 779 return dev_err_probe(&i2c->dev, -EINVAL, "No IRQ configured?\n"); 780 781 pf9453 = devm_kzalloc(&i2c->dev, sizeof(struct pf9453), GFP_KERNEL); 782 if (!pf9453) 783 return -ENOMEM; 784 785 pf9453->regmap = devm_regmap_init_i2c(i2c, &pf9453_regmap_config); 786 if (IS_ERR(pf9453->regmap)) 787 return dev_err_probe(&i2c->dev, PTR_ERR(pf9453->regmap), 788 "regmap initialization failed\n"); 789 790 pf9453->irq = i2c->irq; 791 pf9453->dev = &i2c->dev; 792 793 dev_set_drvdata(&i2c->dev, pf9453); 794 795 ret = regmap_read(pf9453->regmap, PF9453_REG_DEV_ID, &device_id); 796 if (ret) 797 return dev_err_probe(&i2c->dev, ret, "Read device id error\n"); 798 799 /* Check your board and dts for match the right pmic */ 800 if ((device_id >> 4) != 0xb) 801 return dev_err_probe(&i2c->dev, -EINVAL, "Device id(%x) mismatched\n", 802 device_id >> 4); 803 804 while (regulator_desc->desc.name) { 805 const struct regulator_desc *desc; 806 struct regulator_dev *rdev; 807 808 desc = ®ulator_desc->desc; 809 810 config.regmap = pf9453->regmap; 811 config.dev = pf9453->dev; 812 813 rdev = devm_regulator_register(pf9453->dev, desc, &config); 814 if (IS_ERR(rdev)) 815 return dev_err_probe(pf9453->dev, PTR_ERR(rdev), 816 "Failed to register regulator(%s)\n", desc->name); 817 818 regulator_desc++; 819 } 820 821 ret = devm_request_threaded_irq(pf9453->dev, pf9453->irq, NULL, pf9453_irq_handler, 822 (IRQF_TRIGGER_FALLING | IRQF_ONESHOT), 823 "pf9453-irq", pf9453); 824 if (ret) 825 return dev_err_probe(pf9453->dev, ret, "Failed to request IRQ: %d\n", pf9453->irq); 826 827 /* Unmask all interrupt except PWRON/WDOG/RSVD */ 828 ret = pf9453_pmic_write(pf9453, PF9453_REG_INT1_MASK, 829 IRQ_ONKEY | IRQ_RESETKEY | IRQ_RSTB | IRQ_VR_FLT1 830 | IRQ_LOWVSYS | IRQ_THERM_100 | IRQ_THERM_80, IRQ_RSVD); 831 if (ret) 832 return dev_err_probe(&i2c->dev, ret, "Unmask irq error\n"); 833 834 if (of_property_read_bool(i2c->dev.of_node, "nxp,wdog_b-warm-reset")) 835 reset_ctrl = WDOG_B_CFG_WARM; 836 else 837 reset_ctrl = WDOG_B_CFG_COLD; 838 839 /* Set reset behavior on assertion of WDOG_B signal */ 840 ret = pf9453_pmic_write(pf9453, PF9453_REG_RESET_CTRL, WDOG_B_CFG_MASK, reset_ctrl); 841 if (ret) 842 return dev_err_probe(&i2c->dev, ret, "Failed to set WDOG_B reset behavior\n"); 843 844 /* 845 * The driver uses the LDO1OUT_H register to control the LDO1 regulator. 846 * This is only valid if the SD_VSEL input of the PMIC is high. Let's 847 * check if the pin is available as GPIO and set it to high. 848 */ 849 pf9453->sd_vsel_gpio = gpiod_get_optional(pf9453->dev, "sd-vsel", GPIOD_OUT_HIGH); 850 851 if (IS_ERR(pf9453->sd_vsel_gpio)) 852 return dev_err_probe(&i2c->dev, PTR_ERR(pf9453->sd_vsel_gpio), 853 "Failed to get SD_VSEL GPIO\n"); 854 855 return 0; 856 } 857 858 static const struct of_device_id pf9453_of_match[] = { 859 { 860 .compatible = "nxp,pf9453", 861 .data = pf9453_regulators, 862 }, 863 { } 864 }; 865 MODULE_DEVICE_TABLE(of, pf9453_of_match); 866 867 static struct i2c_driver pf9453_i2c_driver = { 868 .driver = { 869 .name = "nxp-pf9453", 870 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 871 .of_match_table = pf9453_of_match, 872 }, 873 .probe = pf9453_i2c_probe, 874 }; 875 876 module_i2c_driver(pf9453_i2c_driver); 877 878 MODULE_AUTHOR("Joy Zou <joy.zou@nxp.com>"); 879 MODULE_DESCRIPTION("NXP PF9453 Power Management IC driver"); 880 MODULE_LICENSE("GPL"); 881