1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) STMicroelectronics 2016 4 * 5 * Author: Gerald Baeza <gerald.baeza@st.com> 6 * 7 * Inspired by timer-stm32.c from Maxime Coquelin 8 * pwm-atmel.c from Bo Shen 9 */ 10 11 #include <linux/bitfield.h> 12 #include <linux/mfd/stm32-timers.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/pinctrl/consumer.h> 16 #include <linux/platform_device.h> 17 #include <linux/pwm.h> 18 19 #define CCMR_CHANNEL_SHIFT 8 20 #define CCMR_CHANNEL_MASK 0xFF 21 #define MAX_BREAKINPUT 2 22 23 struct stm32_breakinput { 24 u32 index; 25 u32 level; 26 u32 filter; 27 }; 28 29 struct stm32_pwm { 30 struct mutex lock; /* protect pwm config/enable */ 31 struct clk *clk; 32 struct regmap *regmap; 33 u32 max_arr; 34 bool have_complementary_output; 35 struct stm32_breakinput breakinputs[MAX_BREAKINPUT]; 36 unsigned int num_breakinputs; 37 u32 capture[4] ____cacheline_aligned; /* DMA'able buffer */ 38 }; 39 40 static inline struct stm32_pwm *to_stm32_pwm_dev(struct pwm_chip *chip) 41 { 42 return pwmchip_get_drvdata(chip); 43 } 44 45 static u32 active_channels(struct stm32_pwm *dev) 46 { 47 u32 ccer; 48 49 regmap_read(dev->regmap, TIM_CCER, &ccer); 50 51 return ccer & TIM_CCER_CCXE; 52 } 53 54 struct stm32_pwm_waveform { 55 u32 ccer; 56 u32 psc; 57 u32 arr; 58 u32 ccr; 59 }; 60 61 static int stm32_pwm_round_waveform_tohw(struct pwm_chip *chip, 62 struct pwm_device *pwm, 63 const struct pwm_waveform *wf, 64 void *_wfhw) 65 { 66 struct stm32_pwm_waveform *wfhw = _wfhw; 67 struct stm32_pwm *priv = to_stm32_pwm_dev(chip); 68 unsigned int ch = pwm->hwpwm; 69 unsigned long rate; 70 u64 ccr, duty; 71 int ret; 72 73 if (wf->period_length_ns == 0) { 74 *wfhw = (struct stm32_pwm_waveform){ 75 .ccer = 0, 76 }; 77 78 return 0; 79 } 80 81 ret = clk_enable(priv->clk); 82 if (ret) 83 return ret; 84 85 wfhw->ccer = TIM_CCER_CCxE(ch + 1); 86 if (priv->have_complementary_output) 87 wfhw->ccer |= TIM_CCER_CCxNE(ch + 1); 88 89 rate = clk_get_rate(priv->clk); 90 91 if (active_channels(priv) & ~TIM_CCER_CCxE(ch + 1)) { 92 u64 arr; 93 94 /* 95 * Other channels are already enabled, so the configured PSC and 96 * ARR must be used for this channel, too. 97 */ 98 ret = regmap_read(priv->regmap, TIM_PSC, &wfhw->psc); 99 if (ret) 100 goto out; 101 102 ret = regmap_read(priv->regmap, TIM_ARR, &wfhw->arr); 103 if (ret) 104 goto out; 105 106 arr = mul_u64_u64_div_u64(wf->period_length_ns, rate, 107 (u64)NSEC_PER_SEC * (wfhw->psc + 1)); 108 if (arr <= wfhw->arr) { 109 /* 110 * requested period is smaller than the currently 111 * configured and unchangable period, report back the smallest 112 * possible period, i.e. the current state and return 1 113 * to indicate the wrong rounding direction. 114 */ 115 ret = 1; 116 } 117 118 } else { 119 /* 120 * .probe() asserted that clk_get_rate() is not bigger than 1 GHz, so 121 * the calculations here won't overflow. 122 * First we need to find the minimal value for prescaler such that 123 * 124 * period_ns * clkrate 125 * ------------------------------ < max_arr + 1 126 * NSEC_PER_SEC * (prescaler + 1) 127 * 128 * This equation is equivalent to 129 * 130 * period_ns * clkrate 131 * ---------------------------- < prescaler + 1 132 * NSEC_PER_SEC * (max_arr + 1) 133 * 134 * Using integer division and knowing that the right hand side is 135 * integer, this is further equivalent to 136 * 137 * (period_ns * clkrate) // (NSEC_PER_SEC * (max_arr + 1)) ≤ prescaler 138 */ 139 u64 psc = mul_u64_u64_div_u64(wf->period_length_ns, rate, 140 (u64)NSEC_PER_SEC * ((u64)priv->max_arr + 1)); 141 u64 arr; 142 143 wfhw->psc = min_t(u64, psc, MAX_TIM_PSC); 144 145 arr = mul_u64_u64_div_u64(wf->period_length_ns, rate, 146 (u64)NSEC_PER_SEC * (wfhw->psc + 1)); 147 if (!arr) { 148 /* 149 * requested period is too small, report back the smallest 150 * possible period, i.e. ARR = 0. The only valid CCR 151 * value is then zero, too. 152 */ 153 wfhw->arr = 0; 154 wfhw->ccr = 0; 155 ret = 1; 156 goto out; 157 } 158 159 /* 160 * ARR is limited intentionally to values less than 161 * priv->max_arr to allow 100% duty cycle. 162 */ 163 wfhw->arr = min_t(u64, arr, priv->max_arr) - 1; 164 } 165 166 duty = mul_u64_u64_div_u64(wf->duty_length_ns, rate, 167 (u64)NSEC_PER_SEC * (wfhw->psc + 1)); 168 duty = min_t(u64, duty, wfhw->arr + 1); 169 170 if (wf->duty_length_ns && wf->duty_offset_ns && 171 wf->duty_length_ns + wf->duty_offset_ns >= wf->period_length_ns) { 172 wfhw->ccer |= TIM_CCER_CCxP(ch + 1); 173 if (priv->have_complementary_output) 174 wfhw->ccer |= TIM_CCER_CCxNP(ch + 1); 175 176 ccr = wfhw->arr + 1 - duty; 177 } else { 178 ccr = duty; 179 } 180 181 wfhw->ccr = min_t(u64, ccr, wfhw->arr + 1); 182 183 out: 184 dev_dbg(&chip->dev, "pwm#%u: %lld/%lld [+%lld] @%lu -> CCER: %08x, PSC: %08x, ARR: %08x, CCR: %08x\n", 185 pwm->hwpwm, wf->duty_length_ns, wf->period_length_ns, wf->duty_offset_ns, 186 rate, wfhw->ccer, wfhw->psc, wfhw->arr, wfhw->ccr); 187 188 clk_disable(priv->clk); 189 190 return ret; 191 } 192 193 /* 194 * This should be moved to lib/math/div64.c. Currently there are some changes 195 * pending to mul_u64_u64_div_u64. Uwe will care for that when the dust settles. 196 */ 197 static u64 stm32_pwm_mul_u64_u64_div_u64_roundup(u64 a, u64 b, u64 c) 198 { 199 u64 res = mul_u64_u64_div_u64(a, b, c); 200 /* Those multiplications might overflow but it doesn't matter */ 201 u64 rem = a * b - c * res; 202 203 if (rem) 204 res += 1; 205 206 return res; 207 } 208 209 static int stm32_pwm_round_waveform_fromhw(struct pwm_chip *chip, 210 struct pwm_device *pwm, 211 const void *_wfhw, 212 struct pwm_waveform *wf) 213 { 214 const struct stm32_pwm_waveform *wfhw = _wfhw; 215 struct stm32_pwm *priv = to_stm32_pwm_dev(chip); 216 unsigned long rate = clk_get_rate(priv->clk); 217 unsigned int ch = pwm->hwpwm; 218 219 if (wfhw->ccer & TIM_CCER_CCxE(ch + 1)) { 220 u64 ccr_ns; 221 222 /* The result doesn't overflow for rate >= 15259 */ 223 wf->period_length_ns = stm32_pwm_mul_u64_u64_div_u64_roundup(((u64)wfhw->psc + 1) * (wfhw->arr + 1), 224 NSEC_PER_SEC, rate); 225 226 ccr_ns = stm32_pwm_mul_u64_u64_div_u64_roundup(((u64)wfhw->psc + 1) * wfhw->ccr, 227 NSEC_PER_SEC, rate); 228 229 if (wfhw->ccer & TIM_CCER_CCxP(ch + 1)) { 230 wf->duty_length_ns = 231 stm32_pwm_mul_u64_u64_div_u64_roundup(((u64)wfhw->psc + 1) * (wfhw->arr + 1 - wfhw->ccr), 232 NSEC_PER_SEC, rate); 233 234 wf->duty_offset_ns = ccr_ns; 235 } else { 236 wf->duty_length_ns = ccr_ns; 237 wf->duty_offset_ns = 0; 238 } 239 } else { 240 *wf = (struct pwm_waveform){ 241 .period_length_ns = 0, 242 }; 243 } 244 245 dev_dbg(&chip->dev, "pwm#%u: CCER: %08x, PSC: %08x, ARR: %08x, CCR: %08x @%lu -> %lld/%lld [+%lld]\n", 246 pwm->hwpwm, wfhw->ccer, wfhw->psc, wfhw->arr, wfhw->ccr, rate, 247 wf->duty_length_ns, wf->period_length_ns, wf->duty_offset_ns); 248 249 return 0; 250 } 251 252 static int stm32_pwm_read_waveform(struct pwm_chip *chip, 253 struct pwm_device *pwm, 254 void *_wfhw) 255 { 256 struct stm32_pwm_waveform *wfhw = _wfhw; 257 struct stm32_pwm *priv = to_stm32_pwm_dev(chip); 258 unsigned int ch = pwm->hwpwm; 259 int ret; 260 261 ret = clk_enable(priv->clk); 262 if (ret) 263 return ret; 264 265 ret = regmap_read(priv->regmap, TIM_CCER, &wfhw->ccer); 266 if (ret) 267 goto out; 268 269 if (wfhw->ccer & TIM_CCER_CCxE(ch + 1)) { 270 ret = regmap_read(priv->regmap, TIM_PSC, &wfhw->psc); 271 if (ret) 272 goto out; 273 274 ret = regmap_read(priv->regmap, TIM_ARR, &wfhw->arr); 275 if (ret) 276 goto out; 277 278 if (wfhw->arr == U32_MAX) 279 wfhw->arr -= 1; 280 281 ret = regmap_read(priv->regmap, TIM_CCRx(ch + 1), &wfhw->ccr); 282 if (ret) 283 goto out; 284 285 if (wfhw->ccr > wfhw->arr + 1) 286 wfhw->ccr = wfhw->arr + 1; 287 } 288 289 out: 290 clk_disable(priv->clk); 291 292 return ret; 293 } 294 295 static int stm32_pwm_write_waveform(struct pwm_chip *chip, 296 struct pwm_device *pwm, 297 const void *_wfhw) 298 { 299 const struct stm32_pwm_waveform *wfhw = _wfhw; 300 struct stm32_pwm *priv = to_stm32_pwm_dev(chip); 301 unsigned int ch = pwm->hwpwm; 302 int ret; 303 304 ret = clk_enable(priv->clk); 305 if (ret) 306 return ret; 307 308 if (wfhw->ccer & TIM_CCER_CCxE(ch + 1)) { 309 u32 ccer, mask; 310 unsigned int shift; 311 u32 ccmr; 312 313 ret = regmap_read(priv->regmap, TIM_CCER, &ccer); 314 if (ret) 315 goto out; 316 317 /* If there are other channels enabled, don't update PSC and ARR */ 318 if (ccer & ~TIM_CCER_CCxE(ch + 1) & TIM_CCER_CCXE) { 319 u32 psc, arr; 320 321 ret = regmap_read(priv->regmap, TIM_PSC, &psc); 322 if (ret) 323 goto out; 324 325 if (psc != wfhw->psc) { 326 ret = -EBUSY; 327 goto out; 328 } 329 330 ret = regmap_read(priv->regmap, TIM_ARR, &arr); 331 if (ret) 332 goto out; 333 334 if (arr != wfhw->arr) { 335 ret = -EBUSY; 336 goto out; 337 } 338 } else { 339 ret = regmap_write(priv->regmap, TIM_PSC, wfhw->psc); 340 if (ret) 341 goto out; 342 343 ret = regmap_write(priv->regmap, TIM_ARR, wfhw->arr); 344 if (ret) 345 goto out; 346 347 ret = regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE); 348 if (ret) 349 goto out; 350 351 } 352 353 /* set polarity */ 354 mask = TIM_CCER_CCxP(ch + 1) | TIM_CCER_CCxNP(ch + 1); 355 ret = regmap_update_bits(priv->regmap, TIM_CCER, mask, wfhw->ccer); 356 if (ret) 357 goto out; 358 359 ret = regmap_write(priv->regmap, TIM_CCRx(ch + 1), wfhw->ccr); 360 if (ret) 361 goto out; 362 363 /* Configure output mode */ 364 shift = (ch & 0x1) * CCMR_CHANNEL_SHIFT; 365 ccmr = (TIM_CCMR_PE | TIM_CCMR_M1) << shift; 366 mask = CCMR_CHANNEL_MASK << shift; 367 368 if (ch < 2) 369 ret = regmap_update_bits(priv->regmap, TIM_CCMR1, mask, ccmr); 370 else 371 ret = regmap_update_bits(priv->regmap, TIM_CCMR2, mask, ccmr); 372 if (ret) 373 goto out; 374 375 ret = regmap_set_bits(priv->regmap, TIM_BDTR, TIM_BDTR_MOE); 376 if (ret) 377 goto out; 378 379 if (!(ccer & TIM_CCER_CCxE(ch + 1))) { 380 mask = TIM_CCER_CCxE(ch + 1) | TIM_CCER_CCxNE(ch + 1); 381 382 ret = clk_enable(priv->clk); 383 if (ret) 384 goto out; 385 386 ccer = (ccer & ~mask) | (wfhw->ccer & mask); 387 regmap_write(priv->regmap, TIM_CCER, ccer); 388 389 /* Make sure that registers are updated */ 390 regmap_set_bits(priv->regmap, TIM_EGR, TIM_EGR_UG); 391 392 /* Enable controller */ 393 regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN); 394 } 395 396 } else { 397 /* disable channel */ 398 u32 mask, ccer; 399 400 mask = TIM_CCER_CCxE(ch + 1); 401 if (priv->have_complementary_output) 402 mask |= TIM_CCER_CCxNE(ch + 1); 403 404 ret = regmap_read(priv->regmap, TIM_CCER, &ccer); 405 if (ret) 406 goto out; 407 408 if (ccer & mask) { 409 ccer = ccer & ~mask; 410 411 ret = regmap_write(priv->regmap, TIM_CCER, ccer); 412 if (ret) 413 goto out; 414 415 if (!(ccer & TIM_CCER_CCXE)) { 416 /* When all channels are disabled, we can disable the controller */ 417 ret = regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN); 418 if (ret) 419 goto out; 420 } 421 422 clk_disable(priv->clk); 423 } 424 } 425 426 out: 427 clk_disable(priv->clk); 428 429 return ret; 430 } 431 432 #define TIM_CCER_CC12P (TIM_CCER_CC1P | TIM_CCER_CC2P) 433 #define TIM_CCER_CC12E (TIM_CCER_CC1E | TIM_CCER_CC2E) 434 #define TIM_CCER_CC34P (TIM_CCER_CC3P | TIM_CCER_CC4P) 435 #define TIM_CCER_CC34E (TIM_CCER_CC3E | TIM_CCER_CC4E) 436 437 /* 438 * Capture using PWM input mode: 439 * ___ ___ 440 * TI[1, 2, 3 or 4]: ........._| |________| 441 * ^0 ^1 ^2 442 * . . . 443 * . . XXXXX 444 * . . XXXXX | 445 * . XXXXX . | 446 * XXXXX . . | 447 * COUNTER: ______XXXXX . . . |_XXX 448 * start^ . . . ^stop 449 * . . . . 450 * v v . v 451 * v 452 * CCR1/CCR3: tx..........t0...........t2 453 * CCR2/CCR4: tx..............t1......... 454 * 455 * DMA burst transfer: | | 456 * v v 457 * DMA buffer: { t0, tx } { t2, t1 } 458 * DMA done: ^ 459 * 460 * 0: IC1/3 snapchot on rising edge: counter value -> CCR1/CCR3 461 * + DMA transfer CCR[1/3] & CCR[2/4] values (t0, tx: doesn't care) 462 * 1: IC2/4 snapchot on falling edge: counter value -> CCR2/CCR4 463 * 2: IC1/3 snapchot on rising edge: counter value -> CCR1/CCR3 464 * + DMA transfer CCR[1/3] & CCR[2/4] values (t2, t1) 465 * 466 * DMA done, compute: 467 * - Period = t2 - t0 468 * - Duty cycle = t1 - t0 469 */ 470 static int stm32_pwm_raw_capture(struct pwm_chip *chip, struct pwm_device *pwm, 471 unsigned long tmo_ms, u32 *raw_prd, 472 u32 *raw_dty) 473 { 474 struct stm32_pwm *priv = to_stm32_pwm_dev(chip); 475 struct device *parent = pwmchip_parent(chip)->parent; 476 enum stm32_timers_dmas dma_id; 477 u32 ccen, ccr; 478 int ret; 479 480 /* Ensure registers have been updated, enable counter and capture */ 481 regmap_set_bits(priv->regmap, TIM_EGR, TIM_EGR_UG); 482 regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN); 483 484 /* Use cc1 or cc3 DMA resp for PWM input channels 1 & 2 or 3 & 4 */ 485 dma_id = pwm->hwpwm < 2 ? STM32_TIMERS_DMA_CH1 : STM32_TIMERS_DMA_CH3; 486 ccen = pwm->hwpwm < 2 ? TIM_CCER_CC12E : TIM_CCER_CC34E; 487 ccr = pwm->hwpwm < 2 ? TIM_CCR1 : TIM_CCR3; 488 regmap_set_bits(priv->regmap, TIM_CCER, ccen); 489 490 /* 491 * Timer DMA burst mode. Request 2 registers, 2 bursts, to get both 492 * CCR1 & CCR2 (or CCR3 & CCR4) on each capture event. 493 * We'll get two capture snapchots: { CCR1, CCR2 }, { CCR1, CCR2 } 494 * or { CCR3, CCR4 }, { CCR3, CCR4 } 495 */ 496 ret = stm32_timers_dma_burst_read(parent, priv->capture, dma_id, ccr, 2, 497 2, tmo_ms); 498 if (ret) 499 goto stop; 500 501 /* Period: t2 - t0 (take care of counter overflow) */ 502 if (priv->capture[0] <= priv->capture[2]) 503 *raw_prd = priv->capture[2] - priv->capture[0]; 504 else 505 *raw_prd = priv->max_arr - priv->capture[0] + priv->capture[2]; 506 507 /* Duty cycle capture requires at least two capture units */ 508 if (pwm->chip->npwm < 2) 509 *raw_dty = 0; 510 else if (priv->capture[0] <= priv->capture[3]) 511 *raw_dty = priv->capture[3] - priv->capture[0]; 512 else 513 *raw_dty = priv->max_arr - priv->capture[0] + priv->capture[3]; 514 515 if (*raw_dty > *raw_prd) { 516 /* 517 * Race beetween PWM input and DMA: it may happen 518 * falling edge triggers new capture on TI2/4 before DMA 519 * had a chance to read CCR2/4. It means capture[1] 520 * contains period + duty_cycle. So, subtract period. 521 */ 522 *raw_dty -= *raw_prd; 523 } 524 525 stop: 526 regmap_clear_bits(priv->regmap, TIM_CCER, ccen); 527 regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN); 528 529 return ret; 530 } 531 532 static int stm32_pwm_capture(struct pwm_chip *chip, struct pwm_device *pwm, 533 struct pwm_capture *result, unsigned long tmo_ms) 534 { 535 struct stm32_pwm *priv = to_stm32_pwm_dev(chip); 536 unsigned long long prd, div, dty; 537 unsigned long rate; 538 unsigned int psc = 0, icpsc, scale; 539 u32 raw_prd = 0, raw_dty = 0; 540 int ret = 0; 541 542 mutex_lock(&priv->lock); 543 544 if (active_channels(priv)) { 545 ret = -EBUSY; 546 goto unlock; 547 } 548 549 ret = clk_enable(priv->clk); 550 if (ret) { 551 dev_err(pwmchip_parent(chip), "failed to enable counter clock\n"); 552 goto unlock; 553 } 554 555 rate = clk_get_rate(priv->clk); 556 if (!rate) { 557 ret = -EINVAL; 558 goto clk_dis; 559 } 560 561 /* prescaler: fit timeout window provided by upper layer */ 562 div = (unsigned long long)rate * (unsigned long long)tmo_ms; 563 do_div(div, MSEC_PER_SEC); 564 prd = div; 565 while ((div > priv->max_arr) && (psc < MAX_TIM_PSC)) { 566 psc++; 567 div = prd; 568 do_div(div, psc + 1); 569 } 570 regmap_write(priv->regmap, TIM_ARR, priv->max_arr); 571 regmap_write(priv->regmap, TIM_PSC, psc); 572 573 /* Reset input selector to its default input and disable slave mode */ 574 regmap_write(priv->regmap, TIM_TISEL, 0x0); 575 regmap_write(priv->regmap, TIM_SMCR, 0x0); 576 577 /* Map TI1 or TI2 PWM input to IC1 & IC2 (or TI3/4 to IC3 & IC4) */ 578 regmap_update_bits(priv->regmap, 579 pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2, 580 TIM_CCMR_CC1S | TIM_CCMR_CC2S, pwm->hwpwm & 0x1 ? 581 TIM_CCMR_CC1S_TI2 | TIM_CCMR_CC2S_TI2 : 582 TIM_CCMR_CC1S_TI1 | TIM_CCMR_CC2S_TI1); 583 584 /* Capture period on IC1/3 rising edge, duty cycle on IC2/4 falling. */ 585 regmap_update_bits(priv->regmap, TIM_CCER, pwm->hwpwm < 2 ? 586 TIM_CCER_CC12P : TIM_CCER_CC34P, pwm->hwpwm < 2 ? 587 TIM_CCER_CC2P : TIM_CCER_CC4P); 588 589 ret = stm32_pwm_raw_capture(chip, pwm, tmo_ms, &raw_prd, &raw_dty); 590 if (ret) 591 goto stop; 592 593 /* 594 * Got a capture. Try to improve accuracy at high rates: 595 * - decrease counter clock prescaler, scale up to max rate. 596 * - use input prescaler, capture once every /2 /4 or /8 edges. 597 */ 598 if (raw_prd) { 599 u32 max_arr = priv->max_arr - 0x1000; /* arbitrary margin */ 600 601 scale = max_arr / min(max_arr, raw_prd); 602 } else { 603 scale = priv->max_arr; /* below resolution, use max scale */ 604 } 605 606 if (psc && scale > 1) { 607 /* 2nd measure with new scale */ 608 psc /= scale; 609 regmap_write(priv->regmap, TIM_PSC, psc); 610 ret = stm32_pwm_raw_capture(chip, pwm, tmo_ms, &raw_prd, 611 &raw_dty); 612 if (ret) 613 goto stop; 614 } 615 616 /* Compute intermediate period not to exceed timeout at low rates */ 617 prd = (unsigned long long)raw_prd * (psc + 1) * NSEC_PER_SEC; 618 do_div(prd, rate); 619 620 for (icpsc = 0; icpsc < MAX_TIM_ICPSC ; icpsc++) { 621 /* input prescaler: also keep arbitrary margin */ 622 if (raw_prd >= (priv->max_arr - 0x1000) >> (icpsc + 1)) 623 break; 624 if (prd >= (tmo_ms * NSEC_PER_MSEC) >> (icpsc + 2)) 625 break; 626 } 627 628 if (!icpsc) 629 goto done; 630 631 /* Last chance to improve period accuracy, using input prescaler */ 632 regmap_update_bits(priv->regmap, 633 pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2, 634 TIM_CCMR_IC1PSC | TIM_CCMR_IC2PSC, 635 FIELD_PREP(TIM_CCMR_IC1PSC, icpsc) | 636 FIELD_PREP(TIM_CCMR_IC2PSC, icpsc)); 637 638 ret = stm32_pwm_raw_capture(chip, pwm, tmo_ms, &raw_prd, &raw_dty); 639 if (ret) 640 goto stop; 641 642 if (raw_dty >= (raw_prd >> icpsc)) { 643 /* 644 * We may fall here using input prescaler, when input 645 * capture starts on high side (before falling edge). 646 * Example with icpsc to capture on each 4 events: 647 * 648 * start 1st capture 2nd capture 649 * v v v 650 * ___ _____ _____ _____ _____ ____ 651 * TI1..4 |__| |__| |__| |__| |__| 652 * v v . . . . . v v 653 * icpsc1/3: . 0 . 1 . 2 . 3 . 0 654 * icpsc2/4: 0 1 2 3 0 655 * v v v v 656 * CCR1/3 ......t0..............................t2 657 * CCR2/4 ..t1..............................t1'... 658 * . . . 659 * Capture0: .<----------------------------->. 660 * Capture1: .<-------------------------->. . 661 * . . . 662 * Period: .<------> . . 663 * Low side: .<>. 664 * 665 * Result: 666 * - Period = Capture0 / icpsc 667 * - Duty = Period - Low side = Period - (Capture0 - Capture1) 668 */ 669 raw_dty = (raw_prd >> icpsc) - (raw_prd - raw_dty); 670 } 671 672 done: 673 prd = (unsigned long long)raw_prd * (psc + 1) * NSEC_PER_SEC; 674 result->period = DIV_ROUND_UP_ULL(prd, rate << icpsc); 675 dty = (unsigned long long)raw_dty * (psc + 1) * NSEC_PER_SEC; 676 result->duty_cycle = DIV_ROUND_UP_ULL(dty, rate); 677 stop: 678 regmap_write(priv->regmap, TIM_CCER, 0); 679 regmap_write(priv->regmap, pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2, 0); 680 regmap_write(priv->regmap, TIM_PSC, 0); 681 clk_dis: 682 clk_disable(priv->clk); 683 unlock: 684 mutex_unlock(&priv->lock); 685 686 return ret; 687 } 688 689 static const struct pwm_ops stm32pwm_ops = { 690 .sizeof_wfhw = sizeof(struct stm32_pwm_waveform), 691 .round_waveform_tohw = stm32_pwm_round_waveform_tohw, 692 .round_waveform_fromhw = stm32_pwm_round_waveform_fromhw, 693 .read_waveform = stm32_pwm_read_waveform, 694 .write_waveform = stm32_pwm_write_waveform, 695 696 .capture = IS_ENABLED(CONFIG_DMA_ENGINE) ? stm32_pwm_capture : NULL, 697 }; 698 699 static int stm32_pwm_set_breakinput(struct stm32_pwm *priv, 700 const struct stm32_breakinput *bi) 701 { 702 u32 shift = TIM_BDTR_BKF_SHIFT(bi->index); 703 u32 bke = TIM_BDTR_BKE(bi->index); 704 u32 bkp = TIM_BDTR_BKP(bi->index); 705 u32 bkf = TIM_BDTR_BKF(bi->index); 706 u32 mask = bkf | bkp | bke; 707 u32 bdtr; 708 709 bdtr = (bi->filter & TIM_BDTR_BKF_MASK) << shift | bke; 710 711 if (bi->level) 712 bdtr |= bkp; 713 714 regmap_update_bits(priv->regmap, TIM_BDTR, mask, bdtr); 715 716 regmap_read(priv->regmap, TIM_BDTR, &bdtr); 717 718 return (bdtr & bke) ? 0 : -EINVAL; 719 } 720 721 static int stm32_pwm_apply_breakinputs(struct stm32_pwm *priv) 722 { 723 unsigned int i; 724 int ret; 725 726 for (i = 0; i < priv->num_breakinputs; i++) { 727 ret = stm32_pwm_set_breakinput(priv, &priv->breakinputs[i]); 728 if (ret < 0) 729 return ret; 730 } 731 732 return 0; 733 } 734 735 static int stm32_pwm_probe_breakinputs(struct stm32_pwm *priv, 736 struct device_node *np) 737 { 738 int nb, ret, array_size; 739 unsigned int i; 740 741 nb = of_property_count_elems_of_size(np, "st,breakinput", 742 sizeof(struct stm32_breakinput)); 743 744 /* 745 * Because "st,breakinput" parameter is optional do not make probe 746 * failed if it doesn't exist. 747 */ 748 if (nb <= 0) 749 return 0; 750 751 if (nb > MAX_BREAKINPUT) 752 return -EINVAL; 753 754 priv->num_breakinputs = nb; 755 array_size = nb * sizeof(struct stm32_breakinput) / sizeof(u32); 756 ret = of_property_read_u32_array(np, "st,breakinput", 757 (u32 *)priv->breakinputs, array_size); 758 if (ret) 759 return ret; 760 761 for (i = 0; i < priv->num_breakinputs; i++) { 762 if (priv->breakinputs[i].index > 1 || 763 priv->breakinputs[i].level > 1 || 764 priv->breakinputs[i].filter > 15) 765 return -EINVAL; 766 } 767 768 return stm32_pwm_apply_breakinputs(priv); 769 } 770 771 static void stm32_pwm_detect_complementary(struct stm32_pwm *priv) 772 { 773 u32 ccer; 774 775 /* 776 * If complementary bit doesn't exist writing 1 will have no 777 * effect so we can detect it. 778 */ 779 regmap_set_bits(priv->regmap, TIM_CCER, TIM_CCER_CC1NE); 780 regmap_read(priv->regmap, TIM_CCER, &ccer); 781 regmap_clear_bits(priv->regmap, TIM_CCER, TIM_CCER_CC1NE); 782 783 priv->have_complementary_output = (ccer != 0); 784 } 785 786 static unsigned int stm32_pwm_detect_channels(struct regmap *regmap, 787 unsigned int *num_enabled) 788 { 789 u32 ccer, ccer_backup; 790 791 /* 792 * If channels enable bits don't exist writing 1 will have no 793 * effect so we can detect and count them. 794 */ 795 regmap_read(regmap, TIM_CCER, &ccer_backup); 796 regmap_set_bits(regmap, TIM_CCER, TIM_CCER_CCXE); 797 regmap_read(regmap, TIM_CCER, &ccer); 798 regmap_write(regmap, TIM_CCER, ccer_backup); 799 800 *num_enabled = hweight32(ccer_backup & TIM_CCER_CCXE); 801 802 return hweight32(ccer & TIM_CCER_CCXE); 803 } 804 805 static int stm32_pwm_probe(struct platform_device *pdev) 806 { 807 struct device *dev = &pdev->dev; 808 struct device_node *np = dev->of_node; 809 struct stm32_timers *ddata = dev_get_drvdata(pdev->dev.parent); 810 struct pwm_chip *chip; 811 struct stm32_pwm *priv; 812 unsigned int npwm, num_enabled; 813 unsigned int i; 814 int ret; 815 816 npwm = stm32_pwm_detect_channels(ddata->regmap, &num_enabled); 817 818 chip = devm_pwmchip_alloc(dev, npwm, sizeof(*priv)); 819 if (IS_ERR(chip)) 820 return PTR_ERR(chip); 821 priv = to_stm32_pwm_dev(chip); 822 823 mutex_init(&priv->lock); 824 priv->regmap = ddata->regmap; 825 priv->clk = ddata->clk; 826 priv->max_arr = ddata->max_arr; 827 828 if (!priv->regmap || !priv->clk) 829 return dev_err_probe(dev, -EINVAL, "Failed to get %s\n", 830 priv->regmap ? "clk" : "regmap"); 831 832 ret = stm32_pwm_probe_breakinputs(priv, np); 833 if (ret) 834 return dev_err_probe(dev, ret, 835 "Failed to configure breakinputs\n"); 836 837 stm32_pwm_detect_complementary(priv); 838 839 ret = devm_clk_rate_exclusive_get(dev, priv->clk); 840 if (ret) 841 return dev_err_probe(dev, ret, "Failed to lock clock\n"); 842 843 /* 844 * With the clk running with not more than 1 GHz the calculations in 845 * .apply() won't overflow. 846 */ 847 if (clk_get_rate(priv->clk) > 1000000000) 848 return dev_err_probe(dev, -EINVAL, "Clock freq too high (%lu)\n", 849 clk_get_rate(priv->clk)); 850 851 chip->ops = &stm32pwm_ops; 852 853 /* Initialize clock refcount to number of enabled PWM channels. */ 854 for (i = 0; i < num_enabled; i++) { 855 ret = clk_enable(priv->clk); 856 if (ret) 857 return ret; 858 } 859 860 ret = devm_pwmchip_add(dev, chip); 861 if (ret < 0) 862 return dev_err_probe(dev, ret, 863 "Failed to register pwmchip\n"); 864 865 platform_set_drvdata(pdev, chip); 866 867 return 0; 868 } 869 870 static int stm32_pwm_suspend(struct device *dev) 871 { 872 struct pwm_chip *chip = dev_get_drvdata(dev); 873 struct stm32_pwm *priv = to_stm32_pwm_dev(chip); 874 unsigned int i; 875 u32 ccer, mask; 876 877 /* Look for active channels */ 878 ccer = active_channels(priv); 879 880 for (i = 0; i < chip->npwm; i++) { 881 mask = TIM_CCER_CCxE(i + 1); 882 if (ccer & mask) { 883 dev_err(dev, "PWM %u still in use by consumer %s\n", 884 i, chip->pwms[i].label); 885 return -EBUSY; 886 } 887 } 888 889 return pinctrl_pm_select_sleep_state(dev); 890 } 891 892 static int stm32_pwm_resume(struct device *dev) 893 { 894 struct pwm_chip *chip = dev_get_drvdata(dev); 895 struct stm32_pwm *priv = to_stm32_pwm_dev(chip); 896 int ret; 897 898 ret = pinctrl_pm_select_default_state(dev); 899 if (ret) 900 return ret; 901 902 /* restore breakinput registers that may have been lost in low power */ 903 return stm32_pwm_apply_breakinputs(priv); 904 } 905 906 static DEFINE_SIMPLE_DEV_PM_OPS(stm32_pwm_pm_ops, stm32_pwm_suspend, stm32_pwm_resume); 907 908 static const struct of_device_id stm32_pwm_of_match[] = { 909 { .compatible = "st,stm32-pwm", }, 910 { /* end node */ }, 911 }; 912 MODULE_DEVICE_TABLE(of, stm32_pwm_of_match); 913 914 static struct platform_driver stm32_pwm_driver = { 915 .probe = stm32_pwm_probe, 916 .driver = { 917 .name = "stm32-pwm", 918 .of_match_table = stm32_pwm_of_match, 919 .pm = pm_ptr(&stm32_pwm_pm_ops), 920 }, 921 }; 922 module_platform_driver(stm32_pwm_driver); 923 924 MODULE_ALIAS("platform:stm32-pwm"); 925 MODULE_DESCRIPTION("STMicroelectronics STM32 PWM driver"); 926 MODULE_LICENSE("GPL v2"); 927