1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * STM32 Low-Power Timer PWM driver 4 * 5 * Copyright (C) STMicroelectronics 2017 6 * 7 * Author: Gerald Baeza <gerald.baeza@st.com> 8 * 9 * Inspired by Gerald Baeza's pwm-stm32 driver 10 */ 11 12 #include <linux/bitfield.h> 13 #include <linux/mfd/stm32-lptimer.h> 14 #include <linux/module.h> 15 #include <linux/of.h> 16 #include <linux/pinctrl/consumer.h> 17 #include <linux/platform_device.h> 18 #include <linux/pwm.h> 19 20 struct stm32_pwm_lp { 21 struct clk *clk; 22 struct regmap *regmap; 23 unsigned int num_cc_chans; 24 }; 25 26 static inline struct stm32_pwm_lp *to_stm32_pwm_lp(struct pwm_chip *chip) 27 { 28 return pwmchip_get_drvdata(chip); 29 } 30 31 /* STM32 Low-Power Timer is preceded by a configurable power-of-2 prescaler */ 32 #define STM32_LPTIM_MAX_PRESCALER 128 33 34 static int stm32_pwm_lp_update_allowed(struct stm32_pwm_lp *priv, int channel) 35 { 36 int ret; 37 u32 ccmr1; 38 unsigned long ccmr; 39 40 /* Only one PWM on this LPTIMER: enable, prescaler and reload value can be changed */ 41 if (!priv->num_cc_chans) 42 return true; 43 44 ret = regmap_read(priv->regmap, STM32_LPTIM_CCMR1, &ccmr1); 45 if (ret) 46 return ret; 47 ccmr = ccmr1 & (STM32_LPTIM_CC1E | STM32_LPTIM_CC2E); 48 49 /* More than one channel enabled: enable, prescaler or ARR value can't be changed */ 50 if (bitmap_weight(&ccmr, sizeof(u32) * BITS_PER_BYTE) > 1) 51 return false; 52 53 /* 54 * Only one channel is enabled (or none): check status on the other channel, to 55 * report if enable, prescaler or ARR value can be changed. 56 */ 57 if (channel) 58 return !(ccmr1 & STM32_LPTIM_CC1E); 59 else 60 return !(ccmr1 & STM32_LPTIM_CC2E); 61 } 62 63 static int stm32_pwm_lp_compare_channel_apply(struct stm32_pwm_lp *priv, int channel, 64 bool enable, enum pwm_polarity polarity) 65 { 66 u32 ccmr1, val, mask; 67 bool reenable; 68 int ret; 69 70 /* No dedicated CC channel: nothing to do */ 71 if (!priv->num_cc_chans) 72 return 0; 73 74 ret = regmap_read(priv->regmap, STM32_LPTIM_CCMR1, &ccmr1); 75 if (ret) 76 return ret; 77 78 if (channel) { 79 /* Must disable CC channel (CCxE) to modify polarity (CCxP), then re-enable */ 80 reenable = (enable && FIELD_GET(STM32_LPTIM_CC2E, ccmr1)) && 81 (polarity != FIELD_GET(STM32_LPTIM_CC2P, ccmr1)); 82 83 mask = STM32_LPTIM_CC2SEL | STM32_LPTIM_CC2E | STM32_LPTIM_CC2P; 84 val = FIELD_PREP(STM32_LPTIM_CC2P, polarity); 85 val |= FIELD_PREP(STM32_LPTIM_CC2E, enable); 86 } else { 87 reenable = (enable && FIELD_GET(STM32_LPTIM_CC1E, ccmr1)) && 88 (polarity != FIELD_GET(STM32_LPTIM_CC1P, ccmr1)); 89 90 mask = STM32_LPTIM_CC1SEL | STM32_LPTIM_CC1E | STM32_LPTIM_CC1P; 91 val = FIELD_PREP(STM32_LPTIM_CC1P, polarity); 92 val |= FIELD_PREP(STM32_LPTIM_CC1E, enable); 93 } 94 95 if (reenable) { 96 u32 cfgr, presc; 97 unsigned long rate; 98 unsigned int delay_us; 99 100 ret = regmap_update_bits(priv->regmap, STM32_LPTIM_CCMR1, 101 channel ? STM32_LPTIM_CC2E : STM32_LPTIM_CC1E, 0); 102 if (ret) 103 return ret; 104 /* 105 * After a write to the LPTIM_CCMRx register, a new write operation can only be 106 * performed after a delay of at least (PRESC × 3) clock cycles 107 */ 108 ret = regmap_read(priv->regmap, STM32_LPTIM_CFGR, &cfgr); 109 if (ret) 110 return ret; 111 presc = FIELD_GET(STM32_LPTIM_PRESC, cfgr); 112 rate = clk_get_rate(priv->clk) >> presc; 113 if (!rate) 114 return -EINVAL; 115 delay_us = 3 * DIV_ROUND_UP(USEC_PER_SEC, rate); 116 usleep_range(delay_us, delay_us * 2); 117 } 118 119 return regmap_update_bits(priv->regmap, STM32_LPTIM_CCMR1, mask, val); 120 } 121 122 static int stm32_pwm_lp_apply(struct pwm_chip *chip, struct pwm_device *pwm, 123 const struct pwm_state *state) 124 { 125 struct stm32_pwm_lp *priv = to_stm32_pwm_lp(chip); 126 unsigned long long prd, div, dty; 127 struct pwm_state cstate; 128 u32 arr, val, mask, cfgr, presc = 0; 129 bool reenable; 130 int ret; 131 132 pwm_get_state(pwm, &cstate); 133 reenable = !cstate.enabled; 134 135 if (!state->enabled) { 136 if (cstate.enabled) { 137 /* Disable CC channel if any */ 138 ret = stm32_pwm_lp_compare_channel_apply(priv, pwm->hwpwm, false, 139 state->polarity); 140 if (ret) 141 return ret; 142 ret = regmap_write(priv->regmap, pwm->hwpwm ? 143 STM32_LPTIM_CCR2 : STM32_LPTIM_CMP, 0); 144 if (ret) 145 return ret; 146 147 /* Check if the timer can be disabled */ 148 ret = stm32_pwm_lp_update_allowed(priv, pwm->hwpwm); 149 if (ret < 0) 150 return ret; 151 152 if (ret) { 153 /* Disable LP timer */ 154 ret = regmap_write(priv->regmap, STM32_LPTIM_CR, 0); 155 if (ret) 156 return ret; 157 } 158 159 /* disable clock to PWM counter */ 160 clk_disable(priv->clk); 161 } 162 return 0; 163 } 164 165 /* Calculate the period and prescaler value */ 166 div = (unsigned long long)clk_get_rate(priv->clk) * state->period; 167 do_div(div, NSEC_PER_SEC); 168 if (!div) { 169 /* Clock is too slow to achieve requested period. */ 170 dev_dbg(pwmchip_parent(chip), "Can't reach %llu ns\n", state->period); 171 return -EINVAL; 172 } 173 174 prd = div; 175 while (div > STM32_LPTIM_MAX_ARR) { 176 presc++; 177 if ((1 << presc) > STM32_LPTIM_MAX_PRESCALER) { 178 dev_err(pwmchip_parent(chip), "max prescaler exceeded\n"); 179 return -EINVAL; 180 } 181 div = prd >> presc; 182 } 183 prd = div; 184 185 /* Calculate the duty cycle */ 186 dty = prd * state->duty_cycle; 187 do_div(dty, state->period); 188 189 ret = regmap_read(priv->regmap, STM32_LPTIM_CFGR, &cfgr); 190 if (ret) 191 return ret; 192 193 /* 194 * When there are several channels, they share the same prescaler and reload value. 195 * Check if this can be changed, or the values are the same for all channels. 196 */ 197 if (!stm32_pwm_lp_update_allowed(priv, pwm->hwpwm)) { 198 ret = regmap_read(priv->regmap, STM32_LPTIM_ARR, &arr); 199 if (ret) 200 return ret; 201 202 if ((FIELD_GET(STM32_LPTIM_PRESC, cfgr) != presc) || (arr != prd - 1)) 203 return -EBUSY; 204 } 205 206 if (!cstate.enabled) { 207 /* enable clock to drive PWM counter */ 208 ret = clk_enable(priv->clk); 209 if (ret) 210 return ret; 211 } 212 213 if ((FIELD_GET(STM32_LPTIM_PRESC, cfgr) != presc) || 214 ((FIELD_GET(STM32_LPTIM_WAVPOL, cfgr) != state->polarity) && !priv->num_cc_chans)) { 215 val = FIELD_PREP(STM32_LPTIM_PRESC, presc); 216 mask = STM32_LPTIM_PRESC; 217 218 if (!priv->num_cc_chans) { 219 /* 220 * WAVPOL bit is only available when no capature compare channel is used, 221 * e.g. on LPTIMER instances that have only one output channel. CCMR1 is 222 * used otherwise. 223 */ 224 val |= FIELD_PREP(STM32_LPTIM_WAVPOL, state->polarity); 225 mask |= STM32_LPTIM_WAVPOL; 226 } 227 228 /* Must disable LP timer to modify CFGR */ 229 reenable = true; 230 ret = regmap_write(priv->regmap, STM32_LPTIM_CR, 0); 231 if (ret) 232 goto err; 233 234 ret = regmap_update_bits(priv->regmap, STM32_LPTIM_CFGR, mask, 235 val); 236 if (ret) 237 goto err; 238 } 239 240 if (reenable) { 241 /* Must (re)enable LP timer to modify CMP & ARR */ 242 ret = regmap_write(priv->regmap, STM32_LPTIM_CR, 243 STM32_LPTIM_ENABLE); 244 if (ret) 245 goto err; 246 } 247 248 ret = regmap_write(priv->regmap, STM32_LPTIM_ARR, prd - 1); 249 if (ret) 250 goto err; 251 252 /* Write CMP/CCRx register and ensure it's been properly written */ 253 ret = regmap_write(priv->regmap, pwm->hwpwm ? STM32_LPTIM_CCR2 : STM32_LPTIM_CMP, 254 prd - (1 + dty)); 255 if (ret) 256 goto err; 257 258 /* ensure ARR and CMP/CCRx registers are properly written */ 259 ret = regmap_read_poll_timeout(priv->regmap, STM32_LPTIM_ISR, val, pwm->hwpwm ? 260 (val & STM32_LPTIM_CMP2_ARROK) == STM32_LPTIM_CMP2_ARROK : 261 (val & STM32_LPTIM_CMPOK_ARROK) == STM32_LPTIM_CMPOK_ARROK, 262 100, 1000); 263 if (ret) { 264 dev_err(pwmchip_parent(chip), "ARR/CMP registers write issue\n"); 265 goto err; 266 } 267 ret = regmap_write(priv->regmap, STM32_LPTIM_ICR, pwm->hwpwm ? 268 STM32_LPTIM_CMP2OKCF_ARROKCF : STM32_LPTIM_CMPOKCF_ARROKCF); 269 if (ret) 270 goto err; 271 272 ret = stm32_pwm_lp_compare_channel_apply(priv, pwm->hwpwm, true, state->polarity); 273 if (ret) 274 goto err; 275 276 if (reenable) { 277 /* Start LP timer in continuous mode */ 278 ret = regmap_set_bits(priv->regmap, STM32_LPTIM_CR, 279 STM32_LPTIM_CNTSTRT); 280 if (ret) { 281 regmap_write(priv->regmap, STM32_LPTIM_CR, 0); 282 goto err; 283 } 284 } 285 286 return 0; 287 err: 288 if (!cstate.enabled) 289 clk_disable(priv->clk); 290 291 return ret; 292 } 293 294 static int stm32_pwm_lp_get_state(struct pwm_chip *chip, 295 struct pwm_device *pwm, 296 struct pwm_state *state) 297 { 298 struct stm32_pwm_lp *priv = to_stm32_pwm_lp(chip); 299 unsigned long rate = clk_get_rate(priv->clk); 300 u32 val, presc, prd, ccmr1; 301 bool enabled; 302 u64 tmp; 303 304 regmap_read(priv->regmap, STM32_LPTIM_CR, &val); 305 enabled = !!FIELD_GET(STM32_LPTIM_ENABLE, val); 306 if (priv->num_cc_chans) { 307 /* There's a CC chan, need to also check if it's enabled */ 308 regmap_read(priv->regmap, STM32_LPTIM_CCMR1, &ccmr1); 309 if (pwm->hwpwm) 310 enabled &= !!FIELD_GET(STM32_LPTIM_CC2E, ccmr1); 311 else 312 enabled &= !!FIELD_GET(STM32_LPTIM_CC1E, ccmr1); 313 } 314 state->enabled = enabled; 315 316 /* Keep PWM counter clock refcount in sync with PWM initial state */ 317 if (state->enabled) { 318 int ret = clk_enable(priv->clk); 319 320 if (ret) 321 return ret; 322 } 323 324 regmap_read(priv->regmap, STM32_LPTIM_CFGR, &val); 325 presc = FIELD_GET(STM32_LPTIM_PRESC, val); 326 if (priv->num_cc_chans) { 327 if (pwm->hwpwm) 328 state->polarity = FIELD_GET(STM32_LPTIM_CC2P, ccmr1); 329 else 330 state->polarity = FIELD_GET(STM32_LPTIM_CC1P, ccmr1); 331 } else { 332 state->polarity = FIELD_GET(STM32_LPTIM_WAVPOL, val); 333 } 334 335 regmap_read(priv->regmap, STM32_LPTIM_ARR, &prd); 336 tmp = prd + 1; 337 tmp = (tmp << presc) * NSEC_PER_SEC; 338 state->period = DIV_ROUND_CLOSEST_ULL(tmp, rate); 339 340 regmap_read(priv->regmap, pwm->hwpwm ? STM32_LPTIM_CCR2 : STM32_LPTIM_CMP, &val); 341 tmp = prd - val; 342 tmp = (tmp << presc) * NSEC_PER_SEC; 343 state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, rate); 344 345 return 0; 346 } 347 348 static const struct pwm_ops stm32_pwm_lp_ops = { 349 .apply = stm32_pwm_lp_apply, 350 .get_state = stm32_pwm_lp_get_state, 351 }; 352 353 static int stm32_pwm_lp_probe(struct platform_device *pdev) 354 { 355 struct stm32_lptimer *ddata = dev_get_drvdata(pdev->dev.parent); 356 struct stm32_pwm_lp *priv; 357 struct pwm_chip *chip; 358 unsigned int npwm; 359 int ret; 360 361 if (!ddata->num_cc_chans) { 362 /* No dedicated CC channel, so there's only one PWM channel */ 363 npwm = 1; 364 } else { 365 /* There are dedicated CC channels, each with one PWM output */ 366 npwm = ddata->num_cc_chans; 367 } 368 369 chip = devm_pwmchip_alloc(&pdev->dev, npwm, sizeof(*priv)); 370 if (IS_ERR(chip)) 371 return PTR_ERR(chip); 372 priv = to_stm32_pwm_lp(chip); 373 374 priv->regmap = ddata->regmap; 375 priv->clk = ddata->clk; 376 priv->num_cc_chans = ddata->num_cc_chans; 377 chip->ops = &stm32_pwm_lp_ops; 378 379 ret = devm_pwmchip_add(&pdev->dev, chip); 380 if (ret < 0) 381 return ret; 382 383 platform_set_drvdata(pdev, chip); 384 385 return 0; 386 } 387 388 static int stm32_pwm_lp_suspend(struct device *dev) 389 { 390 struct pwm_chip *chip = dev_get_drvdata(dev); 391 struct pwm_state state; 392 unsigned int i; 393 394 for (i = 0; i < chip->npwm; i++) { 395 pwm_get_state(&chip->pwms[i], &state); 396 if (state.enabled) { 397 dev_err(dev, "The consumer didn't stop us (%s)\n", 398 chip->pwms[i].label); 399 return -EBUSY; 400 } 401 } 402 403 return pinctrl_pm_select_sleep_state(dev); 404 } 405 406 static int stm32_pwm_lp_resume(struct device *dev) 407 { 408 return pinctrl_pm_select_default_state(dev); 409 } 410 411 static DEFINE_SIMPLE_DEV_PM_OPS(stm32_pwm_lp_pm_ops, stm32_pwm_lp_suspend, 412 stm32_pwm_lp_resume); 413 414 static const struct of_device_id stm32_pwm_lp_of_match[] = { 415 { .compatible = "st,stm32-pwm-lp", }, 416 {}, 417 }; 418 MODULE_DEVICE_TABLE(of, stm32_pwm_lp_of_match); 419 420 static struct platform_driver stm32_pwm_lp_driver = { 421 .probe = stm32_pwm_lp_probe, 422 .driver = { 423 .name = "stm32-pwm-lp", 424 .of_match_table = stm32_pwm_lp_of_match, 425 .pm = pm_ptr(&stm32_pwm_lp_pm_ops), 426 }, 427 }; 428 module_platform_driver(stm32_pwm_lp_driver); 429 430 MODULE_ALIAS("platform:stm32-pwm-lp"); 431 MODULE_DESCRIPTION("STMicroelectronics STM32 PWM LP driver"); 432 MODULE_LICENSE("GPL v2"); 433