1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * MediaTek Pulse Width Modulator driver 4 * 5 * Copyright (C) 2015 John Crispin <blogic@openwrt.org> 6 * Copyright (C) 2017 Zhi Mao <zhi.mao@mediatek.com> 7 * 8 */ 9 10 #include <linux/err.h> 11 #include <linux/io.h> 12 #include <linux/ioport.h> 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/clk.h> 16 #include <linux/of.h> 17 #include <linux/platform_device.h> 18 #include <linux/pwm.h> 19 #include <linux/slab.h> 20 #include <linux/types.h> 21 22 /* PWM registers and bits definitions */ 23 #define PWMCON 0x00 24 #define PWMHDUR 0x04 25 #define PWMLDUR 0x08 26 #define PWMGDUR 0x0c 27 #define PWMWAVENUM 0x28 28 #define PWMDWIDTH 0x2c 29 #define PWM45DWIDTH_FIXUP 0x30 30 #define PWMTHRES 0x30 31 #define PWM45THRES_FIXUP 0x34 32 #define PWM_CK_26M_SEL 0x210 33 34 #define PWM_CLK_DIV_MAX 7 35 36 struct pwm_mediatek_of_data { 37 unsigned int num_pwms; 38 bool pwm45_fixup; 39 bool has_ck_26m_sel; 40 const unsigned int *reg_offset; 41 }; 42 43 /** 44 * struct pwm_mediatek_chip - struct representing PWM chip 45 * @regs: base address of PWM chip 46 * @clk_top: the top clock generator 47 * @clk_main: the clock used by PWM core 48 * @clk_pwms: the clock used by each PWM channel 49 * @soc: pointer to chip's platform data 50 */ 51 struct pwm_mediatek_chip { 52 void __iomem *regs; 53 struct clk *clk_top; 54 struct clk *clk_main; 55 struct clk **clk_pwms; 56 const struct pwm_mediatek_of_data *soc; 57 }; 58 59 static const unsigned int mtk_pwm_reg_offset_v1[] = { 60 0x0010, 0x0050, 0x0090, 0x00d0, 0x0110, 0x0150, 0x0190, 0x0220 61 }; 62 63 static const unsigned int mtk_pwm_reg_offset_v2[] = { 64 0x0080, 0x00c0, 0x0100, 0x0140, 0x0180, 0x01c0, 0x0200, 0x0240 65 }; 66 67 static inline struct pwm_mediatek_chip * 68 to_pwm_mediatek_chip(struct pwm_chip *chip) 69 { 70 return pwmchip_get_drvdata(chip); 71 } 72 73 static int pwm_mediatek_clk_enable(struct pwm_chip *chip, 74 struct pwm_device *pwm) 75 { 76 struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip); 77 int ret; 78 79 ret = clk_prepare_enable(pc->clk_top); 80 if (ret < 0) 81 return ret; 82 83 ret = clk_prepare_enable(pc->clk_main); 84 if (ret < 0) 85 goto disable_clk_top; 86 87 ret = clk_prepare_enable(pc->clk_pwms[pwm->hwpwm]); 88 if (ret < 0) 89 goto disable_clk_main; 90 91 return 0; 92 93 disable_clk_main: 94 clk_disable_unprepare(pc->clk_main); 95 disable_clk_top: 96 clk_disable_unprepare(pc->clk_top); 97 98 return ret; 99 } 100 101 static void pwm_mediatek_clk_disable(struct pwm_chip *chip, 102 struct pwm_device *pwm) 103 { 104 struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip); 105 106 clk_disable_unprepare(pc->clk_pwms[pwm->hwpwm]); 107 clk_disable_unprepare(pc->clk_main); 108 clk_disable_unprepare(pc->clk_top); 109 } 110 111 static inline void pwm_mediatek_writel(struct pwm_mediatek_chip *chip, 112 unsigned int num, unsigned int offset, 113 u32 value) 114 { 115 writel(value, chip->regs + chip->soc->reg_offset[num] + offset); 116 } 117 118 static int pwm_mediatek_config(struct pwm_chip *chip, struct pwm_device *pwm, 119 int duty_ns, int period_ns) 120 { 121 struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip); 122 u32 clkdiv = 0, cnt_period, cnt_duty, reg_width = PWMDWIDTH, 123 reg_thres = PWMTHRES; 124 unsigned long clk_rate; 125 u64 resolution; 126 int ret; 127 128 ret = pwm_mediatek_clk_enable(chip, pwm); 129 if (ret < 0) 130 return ret; 131 132 clk_rate = clk_get_rate(pc->clk_pwms[pwm->hwpwm]); 133 if (!clk_rate) 134 return -EINVAL; 135 136 /* Make sure we use the bus clock and not the 26MHz clock */ 137 if (pc->soc->has_ck_26m_sel) 138 writel(0, pc->regs + PWM_CK_26M_SEL); 139 140 /* Using resolution in picosecond gets accuracy higher */ 141 resolution = (u64)NSEC_PER_SEC * 1000; 142 do_div(resolution, clk_rate); 143 144 cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000, resolution); 145 while (cnt_period > 8191) { 146 resolution *= 2; 147 clkdiv++; 148 cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000, 149 resolution); 150 } 151 152 if (clkdiv > PWM_CLK_DIV_MAX) { 153 pwm_mediatek_clk_disable(chip, pwm); 154 dev_err(pwmchip_parent(chip), "period of %d ns not supported\n", period_ns); 155 return -EINVAL; 156 } 157 158 if (pc->soc->pwm45_fixup && pwm->hwpwm > 2) { 159 /* 160 * PWM[4,5] has distinct offset for PWMDWIDTH and PWMTHRES 161 * from the other PWMs on MT7623. 162 */ 163 reg_width = PWM45DWIDTH_FIXUP; 164 reg_thres = PWM45THRES_FIXUP; 165 } 166 167 cnt_duty = DIV_ROUND_CLOSEST_ULL((u64)duty_ns * 1000, resolution); 168 pwm_mediatek_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | clkdiv); 169 pwm_mediatek_writel(pc, pwm->hwpwm, reg_width, cnt_period); 170 pwm_mediatek_writel(pc, pwm->hwpwm, reg_thres, cnt_duty); 171 172 pwm_mediatek_clk_disable(chip, pwm); 173 174 return 0; 175 } 176 177 static int pwm_mediatek_enable(struct pwm_chip *chip, struct pwm_device *pwm) 178 { 179 struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip); 180 u32 value; 181 int ret; 182 183 ret = pwm_mediatek_clk_enable(chip, pwm); 184 if (ret < 0) 185 return ret; 186 187 value = readl(pc->regs); 188 value |= BIT(pwm->hwpwm); 189 writel(value, pc->regs); 190 191 return 0; 192 } 193 194 static void pwm_mediatek_disable(struct pwm_chip *chip, struct pwm_device *pwm) 195 { 196 struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip); 197 u32 value; 198 199 value = readl(pc->regs); 200 value &= ~BIT(pwm->hwpwm); 201 writel(value, pc->regs); 202 203 pwm_mediatek_clk_disable(chip, pwm); 204 } 205 206 static int pwm_mediatek_apply(struct pwm_chip *chip, struct pwm_device *pwm, 207 const struct pwm_state *state) 208 { 209 int err; 210 211 if (state->polarity != PWM_POLARITY_NORMAL) 212 return -EINVAL; 213 214 if (!state->enabled) { 215 if (pwm->state.enabled) 216 pwm_mediatek_disable(chip, pwm); 217 218 return 0; 219 } 220 221 err = pwm_mediatek_config(chip, pwm, state->duty_cycle, state->period); 222 if (err) 223 return err; 224 225 if (!pwm->state.enabled) 226 err = pwm_mediatek_enable(chip, pwm); 227 228 return err; 229 } 230 231 static const struct pwm_ops pwm_mediatek_ops = { 232 .apply = pwm_mediatek_apply, 233 }; 234 235 static int pwm_mediatek_probe(struct platform_device *pdev) 236 { 237 struct pwm_chip *chip; 238 struct pwm_mediatek_chip *pc; 239 const struct pwm_mediatek_of_data *soc; 240 unsigned int i; 241 int ret; 242 243 soc = of_device_get_match_data(&pdev->dev); 244 245 chip = devm_pwmchip_alloc(&pdev->dev, soc->num_pwms, sizeof(*pc)); 246 if (IS_ERR(chip)) 247 return PTR_ERR(chip); 248 pc = to_pwm_mediatek_chip(chip); 249 250 pc->soc = soc; 251 252 pc->regs = devm_platform_ioremap_resource(pdev, 0); 253 if (IS_ERR(pc->regs)) 254 return PTR_ERR(pc->regs); 255 256 pc->clk_pwms = devm_kmalloc_array(&pdev->dev, soc->num_pwms, 257 sizeof(*pc->clk_pwms), GFP_KERNEL); 258 if (!pc->clk_pwms) 259 return -ENOMEM; 260 261 pc->clk_top = devm_clk_get(&pdev->dev, "top"); 262 if (IS_ERR(pc->clk_top)) 263 return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk_top), 264 "Failed to get top clock\n"); 265 266 pc->clk_main = devm_clk_get(&pdev->dev, "main"); 267 if (IS_ERR(pc->clk_main)) 268 return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk_main), 269 "Failed to get main clock\n"); 270 271 for (i = 0; i < soc->num_pwms; i++) { 272 char name[8]; 273 274 snprintf(name, sizeof(name), "pwm%d", i + 1); 275 276 pc->clk_pwms[i] = devm_clk_get(&pdev->dev, name); 277 if (IS_ERR(pc->clk_pwms[i])) 278 return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk_pwms[i]), 279 "Failed to get %s clock\n", name); 280 } 281 282 chip->ops = &pwm_mediatek_ops; 283 284 ret = devm_pwmchip_add(&pdev->dev, chip); 285 if (ret < 0) 286 return dev_err_probe(&pdev->dev, ret, "pwmchip_add() failed\n"); 287 288 return 0; 289 } 290 291 static const struct pwm_mediatek_of_data mt2712_pwm_data = { 292 .num_pwms = 8, 293 .pwm45_fixup = false, 294 .has_ck_26m_sel = false, 295 .reg_offset = mtk_pwm_reg_offset_v1, 296 }; 297 298 static const struct pwm_mediatek_of_data mt6795_pwm_data = { 299 .num_pwms = 7, 300 .pwm45_fixup = false, 301 .has_ck_26m_sel = false, 302 .reg_offset = mtk_pwm_reg_offset_v1, 303 }; 304 305 static const struct pwm_mediatek_of_data mt7622_pwm_data = { 306 .num_pwms = 6, 307 .pwm45_fixup = false, 308 .has_ck_26m_sel = true, 309 .reg_offset = mtk_pwm_reg_offset_v1, 310 }; 311 312 static const struct pwm_mediatek_of_data mt7623_pwm_data = { 313 .num_pwms = 5, 314 .pwm45_fixup = true, 315 .has_ck_26m_sel = false, 316 .reg_offset = mtk_pwm_reg_offset_v1, 317 }; 318 319 static const struct pwm_mediatek_of_data mt7628_pwm_data = { 320 .num_pwms = 4, 321 .pwm45_fixup = true, 322 .has_ck_26m_sel = false, 323 .reg_offset = mtk_pwm_reg_offset_v1, 324 }; 325 326 static const struct pwm_mediatek_of_data mt7629_pwm_data = { 327 .num_pwms = 1, 328 .pwm45_fixup = false, 329 .has_ck_26m_sel = false, 330 .reg_offset = mtk_pwm_reg_offset_v1, 331 }; 332 333 static const struct pwm_mediatek_of_data mt7981_pwm_data = { 334 .num_pwms = 3, 335 .pwm45_fixup = false, 336 .has_ck_26m_sel = true, 337 .reg_offset = mtk_pwm_reg_offset_v2, 338 }; 339 340 static const struct pwm_mediatek_of_data mt7986_pwm_data = { 341 .num_pwms = 2, 342 .pwm45_fixup = false, 343 .has_ck_26m_sel = true, 344 .reg_offset = mtk_pwm_reg_offset_v1, 345 }; 346 347 static const struct pwm_mediatek_of_data mt7988_pwm_data = { 348 .num_pwms = 8, 349 .pwm45_fixup = false, 350 .has_ck_26m_sel = false, 351 .reg_offset = mtk_pwm_reg_offset_v2, 352 }; 353 354 static const struct pwm_mediatek_of_data mt8183_pwm_data = { 355 .num_pwms = 4, 356 .pwm45_fixup = false, 357 .has_ck_26m_sel = true, 358 .reg_offset = mtk_pwm_reg_offset_v1, 359 }; 360 361 static const struct pwm_mediatek_of_data mt8365_pwm_data = { 362 .num_pwms = 3, 363 .pwm45_fixup = false, 364 .has_ck_26m_sel = true, 365 .reg_offset = mtk_pwm_reg_offset_v1, 366 }; 367 368 static const struct pwm_mediatek_of_data mt8516_pwm_data = { 369 .num_pwms = 5, 370 .pwm45_fixup = false, 371 .has_ck_26m_sel = true, 372 .reg_offset = mtk_pwm_reg_offset_v1, 373 }; 374 375 static const struct of_device_id pwm_mediatek_of_match[] = { 376 { .compatible = "mediatek,mt2712-pwm", .data = &mt2712_pwm_data }, 377 { .compatible = "mediatek,mt6795-pwm", .data = &mt6795_pwm_data }, 378 { .compatible = "mediatek,mt7622-pwm", .data = &mt7622_pwm_data }, 379 { .compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data }, 380 { .compatible = "mediatek,mt7628-pwm", .data = &mt7628_pwm_data }, 381 { .compatible = "mediatek,mt7629-pwm", .data = &mt7629_pwm_data }, 382 { .compatible = "mediatek,mt7981-pwm", .data = &mt7981_pwm_data }, 383 { .compatible = "mediatek,mt7986-pwm", .data = &mt7986_pwm_data }, 384 { .compatible = "mediatek,mt7988-pwm", .data = &mt7988_pwm_data }, 385 { .compatible = "mediatek,mt8183-pwm", .data = &mt8183_pwm_data }, 386 { .compatible = "mediatek,mt8365-pwm", .data = &mt8365_pwm_data }, 387 { .compatible = "mediatek,mt8516-pwm", .data = &mt8516_pwm_data }, 388 { }, 389 }; 390 MODULE_DEVICE_TABLE(of, pwm_mediatek_of_match); 391 392 static struct platform_driver pwm_mediatek_driver = { 393 .driver = { 394 .name = "pwm-mediatek", 395 .of_match_table = pwm_mediatek_of_match, 396 }, 397 .probe = pwm_mediatek_probe, 398 }; 399 module_platform_driver(pwm_mediatek_driver); 400 401 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>"); 402 MODULE_DESCRIPTION("MediaTek general purpose Pulse Width Modulator driver"); 403 MODULE_LICENSE("GPL v2"); 404