1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  *  Freescale FlexTimer Module (FTM) PWM Driver
4  *
5  *  Copyright 2012-2013 Freescale Semiconductor, Inc.
6  */
7 
8 #include <linux/clk.h>
9 #include <linux/err.h>
10 #include <linux/io.h>
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/mutex.h>
14 #include <linux/of.h>
15 #include <linux/platform_device.h>
16 #include <linux/pm.h>
17 #include <linux/pwm.h>
18 #include <linux/regmap.h>
19 #include <linux/slab.h>
20 #include <linux/fsl/ftm.h>
21 
22 #define FTM_SC_CLK(c)	(((c) + 1) << FTM_SC_CLK_MASK_SHIFT)
23 
24 enum fsl_pwm_clk {
25 	FSL_PWM_CLK_SYS,
26 	FSL_PWM_CLK_FIX,
27 	FSL_PWM_CLK_EXT,
28 	FSL_PWM_CLK_CNTEN,
29 	FSL_PWM_CLK_MAX
30 };
31 
32 struct fsl_ftm_soc {
33 	bool has_enable_bits;
34 };
35 
36 struct fsl_pwm_periodcfg {
37 	enum fsl_pwm_clk clk_select;
38 	unsigned int clk_ps;
39 	unsigned int mod_period;
40 };
41 
42 struct fsl_pwm_chip {
43 	struct mutex lock;
44 	struct regmap *regmap;
45 
46 	/* This value is valid iff a pwm is running */
47 	struct fsl_pwm_periodcfg period;
48 
49 	struct clk *ipg_clk;
50 	struct clk *clk[FSL_PWM_CLK_MAX];
51 
52 	const struct fsl_ftm_soc *soc;
53 };
54 
55 static inline struct fsl_pwm_chip *to_fsl_chip(struct pwm_chip *chip)
56 {
57 	return pwmchip_get_drvdata(chip);
58 }
59 
60 static void ftm_clear_write_protection(struct fsl_pwm_chip *fpc)
61 {
62 	u32 val;
63 
64 	regmap_read(fpc->regmap, FTM_FMS, &val);
65 	if (val & FTM_FMS_WPEN)
66 		regmap_set_bits(fpc->regmap, FTM_MODE, FTM_MODE_WPDIS);
67 }
68 
69 static void ftm_set_write_protection(struct fsl_pwm_chip *fpc)
70 {
71 	regmap_set_bits(fpc->regmap, FTM_FMS, FTM_FMS_WPEN);
72 }
73 
74 static bool fsl_pwm_periodcfg_are_equal(const struct fsl_pwm_periodcfg *a,
75 					const struct fsl_pwm_periodcfg *b)
76 {
77 	if (a->clk_select != b->clk_select)
78 		return false;
79 	if (a->clk_ps != b->clk_ps)
80 		return false;
81 	if (a->mod_period != b->mod_period)
82 		return false;
83 	return true;
84 }
85 
86 static int fsl_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
87 {
88 	int ret;
89 	struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
90 
91 	ret = clk_prepare_enable(fpc->ipg_clk);
92 	if (!ret && fpc->soc->has_enable_bits) {
93 		mutex_lock(&fpc->lock);
94 		regmap_set_bits(fpc->regmap, FTM_SC, BIT(pwm->hwpwm + 16));
95 		mutex_unlock(&fpc->lock);
96 	}
97 
98 	return ret;
99 }
100 
101 static void fsl_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
102 {
103 	struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
104 
105 	if (fpc->soc->has_enable_bits) {
106 		mutex_lock(&fpc->lock);
107 		regmap_clear_bits(fpc->regmap, FTM_SC, BIT(pwm->hwpwm + 16));
108 		mutex_unlock(&fpc->lock);
109 	}
110 
111 	clk_disable_unprepare(fpc->ipg_clk);
112 }
113 
114 static unsigned int fsl_pwm_ticks_to_ns(struct fsl_pwm_chip *fpc,
115 					  unsigned int ticks)
116 {
117 	unsigned long rate;
118 	unsigned long long exval;
119 
120 	rate = clk_get_rate(fpc->clk[fpc->period.clk_select]);
121 	if (rate >> fpc->period.clk_ps == 0)
122 		return 0;
123 
124 	exval = ticks;
125 	exval *= 1000000000UL;
126 	do_div(exval, rate >> fpc->period.clk_ps);
127 	return exval;
128 }
129 
130 static bool fsl_pwm_calculate_period_clk(struct fsl_pwm_chip *fpc,
131 					 unsigned int period_ns,
132 					 enum fsl_pwm_clk index,
133 					 struct fsl_pwm_periodcfg *periodcfg
134 					 )
135 {
136 	unsigned long long c;
137 	unsigned int ps;
138 
139 	c = clk_get_rate(fpc->clk[index]);
140 	c = c * period_ns;
141 	do_div(c, 1000000000UL);
142 
143 	if (c == 0)
144 		return false;
145 
146 	for (ps = 0; ps < 8 ; ++ps, c >>= 1) {
147 		if (c <= 0x10000) {
148 			periodcfg->clk_select = index;
149 			periodcfg->clk_ps = ps;
150 			periodcfg->mod_period = c - 1;
151 			return true;
152 		}
153 	}
154 	return false;
155 }
156 
157 static bool fsl_pwm_calculate_period(struct fsl_pwm_chip *fpc,
158 				     unsigned int period_ns,
159 				     struct fsl_pwm_periodcfg *periodcfg)
160 {
161 	enum fsl_pwm_clk m0, m1;
162 	unsigned long fix_rate, ext_rate;
163 	bool ret;
164 
165 	ret = fsl_pwm_calculate_period_clk(fpc, period_ns, FSL_PWM_CLK_SYS,
166 					   periodcfg);
167 	if (ret)
168 		return true;
169 
170 	fix_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_FIX]);
171 	ext_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_EXT]);
172 
173 	if (fix_rate > ext_rate) {
174 		m0 = FSL_PWM_CLK_FIX;
175 		m1 = FSL_PWM_CLK_EXT;
176 	} else {
177 		m0 = FSL_PWM_CLK_EXT;
178 		m1 = FSL_PWM_CLK_FIX;
179 	}
180 
181 	ret = fsl_pwm_calculate_period_clk(fpc, period_ns, m0, periodcfg);
182 	if (ret)
183 		return true;
184 
185 	return fsl_pwm_calculate_period_clk(fpc, period_ns, m1, periodcfg);
186 }
187 
188 static unsigned int fsl_pwm_calculate_duty(struct fsl_pwm_chip *fpc,
189 					   unsigned int duty_ns)
190 {
191 	unsigned long long duty;
192 
193 	unsigned int period = fpc->period.mod_period + 1;
194 	unsigned int period_ns = fsl_pwm_ticks_to_ns(fpc, period);
195 
196 	if (!period_ns)
197 		return 0;
198 
199 	duty = (unsigned long long)duty_ns * period;
200 	do_div(duty, period_ns);
201 
202 	return (unsigned int)duty;
203 }
204 
205 static bool fsl_pwm_is_any_pwm_enabled(struct fsl_pwm_chip *fpc,
206 				       struct pwm_device *pwm)
207 {
208 	u32 val;
209 
210 	regmap_read(fpc->regmap, FTM_OUTMASK, &val);
211 	if (~val & 0xFF)
212 		return true;
213 	else
214 		return false;
215 }
216 
217 static bool fsl_pwm_is_other_pwm_enabled(struct fsl_pwm_chip *fpc,
218 					 struct pwm_device *pwm)
219 {
220 	u32 val;
221 
222 	regmap_read(fpc->regmap, FTM_OUTMASK, &val);
223 	if (~(val | BIT(pwm->hwpwm)) & 0xFF)
224 		return true;
225 	else
226 		return false;
227 }
228 
229 static int fsl_pwm_apply_config(struct pwm_chip *chip,
230 				struct pwm_device *pwm,
231 				const struct pwm_state *newstate)
232 {
233 	struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
234 	unsigned int duty;
235 	u32 reg_polarity;
236 
237 	struct fsl_pwm_periodcfg periodcfg;
238 	bool do_write_period = false;
239 
240 	if (!fsl_pwm_calculate_period(fpc, newstate->period, &periodcfg)) {
241 		dev_err(pwmchip_parent(chip), "failed to calculate new period\n");
242 		return -EINVAL;
243 	}
244 
245 	if (!fsl_pwm_is_any_pwm_enabled(fpc, pwm))
246 		do_write_period = true;
247 	/*
248 	 * The Freescale FTM controller supports only a single period for
249 	 * all PWM channels, therefore verify if the newly computed period
250 	 * is different than the current period being used. In such case
251 	 * we allow to change the period only if no other pwm is running.
252 	 */
253 	else if (!fsl_pwm_periodcfg_are_equal(&fpc->period, &periodcfg)) {
254 		if (fsl_pwm_is_other_pwm_enabled(fpc, pwm)) {
255 			dev_err(pwmchip_parent(chip),
256 				"Cannot change period for PWM %u, disable other PWMs first\n",
257 				pwm->hwpwm);
258 			return -EBUSY;
259 		}
260 		if (fpc->period.clk_select != periodcfg.clk_select) {
261 			int ret;
262 			enum fsl_pwm_clk oldclk = fpc->period.clk_select;
263 			enum fsl_pwm_clk newclk = periodcfg.clk_select;
264 
265 			ret = clk_prepare_enable(fpc->clk[newclk]);
266 			if (ret)
267 				return ret;
268 			clk_disable_unprepare(fpc->clk[oldclk]);
269 		}
270 		do_write_period = true;
271 	}
272 
273 	ftm_clear_write_protection(fpc);
274 
275 	if (do_write_period) {
276 		regmap_update_bits(fpc->regmap, FTM_SC, FTM_SC_CLK_MASK,
277 				   FTM_SC_CLK(periodcfg.clk_select));
278 		regmap_update_bits(fpc->regmap, FTM_SC, FTM_SC_PS_MASK,
279 				   periodcfg.clk_ps);
280 		regmap_write(fpc->regmap, FTM_MOD, periodcfg.mod_period);
281 
282 		fpc->period = periodcfg;
283 	}
284 
285 	duty = fsl_pwm_calculate_duty(fpc, newstate->duty_cycle);
286 
287 	regmap_write(fpc->regmap, FTM_CSC(pwm->hwpwm),
288 		     FTM_CSC_MSB | FTM_CSC_ELSB);
289 	regmap_write(fpc->regmap, FTM_CV(pwm->hwpwm), duty);
290 
291 	reg_polarity = 0;
292 	if (newstate->polarity == PWM_POLARITY_INVERSED)
293 		reg_polarity = BIT(pwm->hwpwm);
294 
295 	regmap_update_bits(fpc->regmap, FTM_POL, BIT(pwm->hwpwm), reg_polarity);
296 
297 	ftm_set_write_protection(fpc);
298 
299 	return 0;
300 }
301 
302 static int fsl_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
303 			 const struct pwm_state *newstate)
304 {
305 	struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
306 	struct pwm_state *oldstate = &pwm->state;
307 	int ret = 0;
308 
309 	/*
310 	 * oldstate to newstate : action
311 	 *
312 	 * disabled to disabled : ignore
313 	 * enabled to disabled : disable
314 	 * enabled to enabled : update settings
315 	 * disabled to enabled : update settings + enable
316 	 */
317 
318 	mutex_lock(&fpc->lock);
319 
320 	if (!newstate->enabled) {
321 		if (oldstate->enabled) {
322 			regmap_set_bits(fpc->regmap, FTM_OUTMASK,
323 					BIT(pwm->hwpwm));
324 			clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_CNTEN]);
325 			clk_disable_unprepare(fpc->clk[fpc->period.clk_select]);
326 		}
327 
328 		goto end_mutex;
329 	}
330 
331 	ret = fsl_pwm_apply_config(chip, pwm, newstate);
332 	if (ret)
333 		goto end_mutex;
334 
335 	/* check if need to enable */
336 	if (!oldstate->enabled) {
337 		ret = clk_prepare_enable(fpc->clk[fpc->period.clk_select]);
338 		if (ret)
339 			goto end_mutex;
340 
341 		ret = clk_prepare_enable(fpc->clk[FSL_PWM_CLK_CNTEN]);
342 		if (ret) {
343 			clk_disable_unprepare(fpc->clk[fpc->period.clk_select]);
344 			goto end_mutex;
345 		}
346 
347 		regmap_clear_bits(fpc->regmap, FTM_OUTMASK, BIT(pwm->hwpwm));
348 	}
349 
350 end_mutex:
351 	mutex_unlock(&fpc->lock);
352 	return ret;
353 }
354 
355 static const struct pwm_ops fsl_pwm_ops = {
356 	.request = fsl_pwm_request,
357 	.free = fsl_pwm_free,
358 	.apply = fsl_pwm_apply,
359 };
360 
361 static int fsl_pwm_init(struct fsl_pwm_chip *fpc)
362 {
363 	int ret;
364 
365 	ret = clk_prepare_enable(fpc->ipg_clk);
366 	if (ret)
367 		return ret;
368 
369 	regmap_write(fpc->regmap, FTM_CNTIN, 0x00);
370 	regmap_write(fpc->regmap, FTM_OUTINIT, 0x00);
371 	regmap_write(fpc->regmap, FTM_OUTMASK, 0xFF);
372 
373 	clk_disable_unprepare(fpc->ipg_clk);
374 
375 	return 0;
376 }
377 
378 static bool fsl_pwm_volatile_reg(struct device *dev, unsigned int reg)
379 {
380 	switch (reg) {
381 	case FTM_FMS:
382 	case FTM_MODE:
383 	case FTM_CNT:
384 		return true;
385 	}
386 	return false;
387 }
388 
389 static const struct regmap_config fsl_pwm_regmap_config = {
390 	.reg_bits = 32,
391 	.reg_stride = 4,
392 	.val_bits = 32,
393 
394 	.max_register = FTM_PWMLOAD,
395 	.volatile_reg = fsl_pwm_volatile_reg,
396 	.cache_type = REGCACHE_FLAT,
397 };
398 
399 static int fsl_pwm_probe(struct platform_device *pdev)
400 {
401 	struct pwm_chip *chip;
402 	struct fsl_pwm_chip *fpc;
403 	void __iomem *base;
404 	int ret;
405 
406 	chip = devm_pwmchip_alloc(&pdev->dev, 8, sizeof(*fpc));
407 	if (IS_ERR(chip))
408 		return PTR_ERR(chip);
409 	fpc = to_fsl_chip(chip);
410 
411 	mutex_init(&fpc->lock);
412 
413 	fpc->soc = of_device_get_match_data(&pdev->dev);
414 
415 	base = devm_platform_ioremap_resource(pdev, 0);
416 	if (IS_ERR(base))
417 		return PTR_ERR(base);
418 
419 	fpc->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "ftm_sys", base,
420 						&fsl_pwm_regmap_config);
421 	if (IS_ERR(fpc->regmap)) {
422 		dev_err(&pdev->dev, "regmap init failed\n");
423 		return PTR_ERR(fpc->regmap);
424 	}
425 
426 	fpc->clk[FSL_PWM_CLK_SYS] = devm_clk_get(&pdev->dev, "ftm_sys");
427 	if (IS_ERR(fpc->clk[FSL_PWM_CLK_SYS])) {
428 		dev_err(&pdev->dev, "failed to get \"ftm_sys\" clock\n");
429 		return PTR_ERR(fpc->clk[FSL_PWM_CLK_SYS]);
430 	}
431 
432 	fpc->clk[FSL_PWM_CLK_FIX] = devm_clk_get(&pdev->dev, "ftm_fix");
433 	if (IS_ERR(fpc->clk[FSL_PWM_CLK_FIX]))
434 		return PTR_ERR(fpc->clk[FSL_PWM_CLK_FIX]);
435 
436 	fpc->clk[FSL_PWM_CLK_EXT] = devm_clk_get(&pdev->dev, "ftm_ext");
437 	if (IS_ERR(fpc->clk[FSL_PWM_CLK_EXT]))
438 		return PTR_ERR(fpc->clk[FSL_PWM_CLK_EXT]);
439 
440 	fpc->clk[FSL_PWM_CLK_CNTEN] =
441 				devm_clk_get(&pdev->dev, "ftm_cnt_clk_en");
442 	if (IS_ERR(fpc->clk[FSL_PWM_CLK_CNTEN]))
443 		return PTR_ERR(fpc->clk[FSL_PWM_CLK_CNTEN]);
444 
445 	/*
446 	 * ipg_clk is the interface clock for the IP. If not provided, use the
447 	 * ftm_sys clock as the default.
448 	 */
449 	fpc->ipg_clk = devm_clk_get(&pdev->dev, "ipg");
450 	if (IS_ERR(fpc->ipg_clk))
451 		fpc->ipg_clk = fpc->clk[FSL_PWM_CLK_SYS];
452 
453 	chip->ops = &fsl_pwm_ops;
454 
455 	ret = devm_pwmchip_add(&pdev->dev, chip);
456 	if (ret < 0) {
457 		dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
458 		return ret;
459 	}
460 
461 	platform_set_drvdata(pdev, chip);
462 
463 	return fsl_pwm_init(fpc);
464 }
465 
466 #ifdef CONFIG_PM_SLEEP
467 static int fsl_pwm_suspend(struct device *dev)
468 {
469 	struct pwm_chip *chip = dev_get_drvdata(dev);
470 	struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
471 	int i;
472 
473 	regcache_cache_only(fpc->regmap, true);
474 	regcache_mark_dirty(fpc->regmap);
475 
476 	for (i = 0; i < chip->npwm; i++) {
477 		struct pwm_device *pwm = &chip->pwms[i];
478 
479 		if (!test_bit(PWMF_REQUESTED, &pwm->flags))
480 			continue;
481 
482 		clk_disable_unprepare(fpc->ipg_clk);
483 
484 		if (!pwm_is_enabled(pwm))
485 			continue;
486 
487 		clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_CNTEN]);
488 		clk_disable_unprepare(fpc->clk[fpc->period.clk_select]);
489 	}
490 
491 	return 0;
492 }
493 
494 static int fsl_pwm_resume(struct device *dev)
495 {
496 	struct pwm_chip *chip = dev_get_drvdata(dev);
497 	struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
498 	int i;
499 
500 	for (i = 0; i < chip->npwm; i++) {
501 		struct pwm_device *pwm = &chip->pwms[i];
502 
503 		if (!test_bit(PWMF_REQUESTED, &pwm->flags))
504 			continue;
505 
506 		clk_prepare_enable(fpc->ipg_clk);
507 
508 		if (!pwm_is_enabled(pwm))
509 			continue;
510 
511 		clk_prepare_enable(fpc->clk[fpc->period.clk_select]);
512 		clk_prepare_enable(fpc->clk[FSL_PWM_CLK_CNTEN]);
513 	}
514 
515 	/* restore all registers from cache */
516 	regcache_cache_only(fpc->regmap, false);
517 	regcache_sync(fpc->regmap);
518 
519 	return 0;
520 }
521 #endif
522 
523 static const struct dev_pm_ops fsl_pwm_pm_ops = {
524 	SET_SYSTEM_SLEEP_PM_OPS(fsl_pwm_suspend, fsl_pwm_resume)
525 };
526 
527 static const struct fsl_ftm_soc vf610_ftm_pwm = {
528 	.has_enable_bits = false,
529 };
530 
531 static const struct fsl_ftm_soc imx8qm_ftm_pwm = {
532 	.has_enable_bits = true,
533 };
534 
535 static const struct of_device_id fsl_pwm_dt_ids[] = {
536 	{ .compatible = "fsl,vf610-ftm-pwm", .data = &vf610_ftm_pwm },
537 	{ .compatible = "fsl,imx8qm-ftm-pwm", .data = &imx8qm_ftm_pwm },
538 	{ /* sentinel */ }
539 };
540 MODULE_DEVICE_TABLE(of, fsl_pwm_dt_ids);
541 
542 static struct platform_driver fsl_pwm_driver = {
543 	.driver = {
544 		.name = "fsl-ftm-pwm",
545 		.of_match_table = fsl_pwm_dt_ids,
546 		.pm = &fsl_pwm_pm_ops,
547 	},
548 	.probe = fsl_pwm_probe,
549 };
550 module_platform_driver(fsl_pwm_driver);
551 
552 MODULE_DESCRIPTION("Freescale FlexTimer Module PWM Driver");
553 MODULE_AUTHOR("Xiubo Li <Li.Xiubo@freescale.com>");
554 MODULE_ALIAS("platform:fsl-ftm-pwm");
555 MODULE_LICENSE("GPL");
556