1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Common code for Intel Running Average Power Limit (RAPL) support. 4 * Copyright (c) 2019, Intel Corporation. 5 */ 6 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 7 8 #include <linux/bitmap.h> 9 #include <linux/cleanup.h> 10 #include <linux/cpu.h> 11 #include <linux/delay.h> 12 #include <linux/device.h> 13 #include <linux/intel_rapl.h> 14 #include <linux/kernel.h> 15 #include <linux/list.h> 16 #include <linux/log2.h> 17 #include <linux/module.h> 18 #include <linux/nospec.h> 19 #include <linux/perf_event.h> 20 #include <linux/platform_device.h> 21 #include <linux/powercap.h> 22 #include <linux/processor.h> 23 #include <linux/slab.h> 24 #include <linux/suspend.h> 25 #include <linux/sysfs.h> 26 #include <linux/types.h> 27 28 #include <asm/cpu_device_id.h> 29 #include <asm/intel-family.h> 30 #include <asm/iosf_mbi.h> 31 #include <asm/msr.h> 32 33 /* bitmasks for RAPL MSRs, used by primitive access functions */ 34 #define ENERGY_STATUS_MASK 0xffffffff 35 36 #define POWER_LIMIT1_MASK 0x7FFF 37 #define POWER_LIMIT1_ENABLE BIT(15) 38 #define POWER_LIMIT1_CLAMP BIT(16) 39 40 #define POWER_LIMIT2_MASK (0x7FFFULL<<32) 41 #define POWER_LIMIT2_ENABLE BIT_ULL(47) 42 #define POWER_LIMIT2_CLAMP BIT_ULL(48) 43 #define POWER_HIGH_LOCK BIT_ULL(63) 44 #define POWER_LOW_LOCK BIT(31) 45 46 #define POWER_LIMIT4_MASK 0x1FFF 47 48 #define TIME_WINDOW1_MASK (0x7FULL<<17) 49 #define TIME_WINDOW2_MASK (0x7FULL<<49) 50 51 #define POWER_UNIT_OFFSET 0 52 #define POWER_UNIT_MASK 0x0F 53 54 #define ENERGY_UNIT_OFFSET 0x08 55 #define ENERGY_UNIT_MASK 0x1F00 56 57 #define TIME_UNIT_OFFSET 0x10 58 #define TIME_UNIT_MASK 0xF0000 59 60 #define POWER_INFO_MAX_MASK (0x7fffULL<<32) 61 #define POWER_INFO_MIN_MASK (0x7fffULL<<16) 62 #define POWER_INFO_MAX_TIME_WIN_MASK (0x3fULL<<48) 63 #define POWER_INFO_THERMAL_SPEC_MASK 0x7fff 64 65 #define PERF_STATUS_THROTTLE_TIME_MASK 0xffffffff 66 #define PP_POLICY_MASK 0x1F 67 68 /* 69 * SPR has different layout for Psys Domain PowerLimit registers. 70 * There are 17 bits of PL1 and PL2 instead of 15 bits. 71 * The Enable bits and TimeWindow bits are also shifted as a result. 72 */ 73 #define PSYS_POWER_LIMIT1_MASK 0x1FFFF 74 #define PSYS_POWER_LIMIT1_ENABLE BIT(17) 75 76 #define PSYS_POWER_LIMIT2_MASK (0x1FFFFULL<<32) 77 #define PSYS_POWER_LIMIT2_ENABLE BIT_ULL(49) 78 79 #define PSYS_TIME_WINDOW1_MASK (0x7FULL<<19) 80 #define PSYS_TIME_WINDOW2_MASK (0x7FULL<<51) 81 82 /* bitmasks for RAPL TPMI, used by primitive access functions */ 83 #define TPMI_POWER_LIMIT_MASK 0x3FFFF 84 #define TPMI_POWER_LIMIT_ENABLE BIT_ULL(62) 85 #define TPMI_TIME_WINDOW_MASK (0x7FULL<<18) 86 #define TPMI_INFO_SPEC_MASK 0x3FFFF 87 #define TPMI_INFO_MIN_MASK (0x3FFFFULL << 18) 88 #define TPMI_INFO_MAX_MASK (0x3FFFFULL << 36) 89 #define TPMI_INFO_MAX_TIME_WIN_MASK (0x7FULL << 54) 90 91 /* Non HW constants */ 92 #define RAPL_PRIMITIVE_DERIVED BIT(1) /* not from raw data */ 93 #define RAPL_PRIMITIVE_DUMMY BIT(2) 94 95 #define TIME_WINDOW_MAX_MSEC 40000 96 #define TIME_WINDOW_MIN_MSEC 250 97 #define ENERGY_UNIT_SCALE 1000 /* scale from driver unit to powercap unit */ 98 enum unit_type { 99 ARBITRARY_UNIT, /* no translation */ 100 POWER_UNIT, 101 ENERGY_UNIT, 102 TIME_UNIT, 103 }; 104 105 /* per domain data, some are optional */ 106 #define NR_RAW_PRIMITIVES (NR_RAPL_PRIMITIVES - 2) 107 108 #define DOMAIN_STATE_INACTIVE BIT(0) 109 #define DOMAIN_STATE_POWER_LIMIT_SET BIT(1) 110 111 static const char *pl_names[NR_POWER_LIMITS] = { 112 [POWER_LIMIT1] = "long_term", 113 [POWER_LIMIT2] = "short_term", 114 [POWER_LIMIT4] = "peak_power", 115 }; 116 117 enum pl_prims { 118 PL_ENABLE, 119 PL_CLAMP, 120 PL_LIMIT, 121 PL_TIME_WINDOW, 122 PL_MAX_POWER, 123 PL_LOCK, 124 }; 125 126 static bool is_pl_valid(struct rapl_domain *rd, int pl) 127 { 128 if (pl < POWER_LIMIT1 || pl > POWER_LIMIT4) 129 return false; 130 return rd->rpl[pl].name ? true : false; 131 } 132 133 static int get_pl_lock_prim(struct rapl_domain *rd, int pl) 134 { 135 if (rd->rp->priv->type == RAPL_IF_TPMI) { 136 if (pl == POWER_LIMIT1) 137 return PL1_LOCK; 138 if (pl == POWER_LIMIT2) 139 return PL2_LOCK; 140 if (pl == POWER_LIMIT4) 141 return PL4_LOCK; 142 } 143 144 /* MSR/MMIO Interface doesn't have Lock bit for PL4 */ 145 if (pl == POWER_LIMIT4) 146 return -EINVAL; 147 148 /* 149 * Power Limit register that supports two power limits has a different 150 * bit position for the Lock bit. 151 */ 152 if (rd->rp->priv->limits[rd->id] & BIT(POWER_LIMIT2)) 153 return FW_HIGH_LOCK; 154 return FW_LOCK; 155 } 156 157 static int get_pl_prim(struct rapl_domain *rd, int pl, enum pl_prims prim) 158 { 159 switch (pl) { 160 case POWER_LIMIT1: 161 if (prim == PL_ENABLE) 162 return PL1_ENABLE; 163 if (prim == PL_CLAMP && rd->rp->priv->type != RAPL_IF_TPMI) 164 return PL1_CLAMP; 165 if (prim == PL_LIMIT) 166 return POWER_LIMIT1; 167 if (prim == PL_TIME_WINDOW) 168 return TIME_WINDOW1; 169 if (prim == PL_MAX_POWER) 170 return THERMAL_SPEC_POWER; 171 if (prim == PL_LOCK) 172 return get_pl_lock_prim(rd, pl); 173 return -EINVAL; 174 case POWER_LIMIT2: 175 if (prim == PL_ENABLE) 176 return PL2_ENABLE; 177 if (prim == PL_CLAMP && rd->rp->priv->type != RAPL_IF_TPMI) 178 return PL2_CLAMP; 179 if (prim == PL_LIMIT) 180 return POWER_LIMIT2; 181 if (prim == PL_TIME_WINDOW) 182 return TIME_WINDOW2; 183 if (prim == PL_MAX_POWER) 184 return MAX_POWER; 185 if (prim == PL_LOCK) 186 return get_pl_lock_prim(rd, pl); 187 return -EINVAL; 188 case POWER_LIMIT4: 189 if (prim == PL_LIMIT) 190 return POWER_LIMIT4; 191 if (prim == PL_ENABLE) 192 return PL4_ENABLE; 193 /* PL4 would be around two times PL2, use same prim as PL2. */ 194 if (prim == PL_MAX_POWER) 195 return MAX_POWER; 196 if (prim == PL_LOCK) 197 return get_pl_lock_prim(rd, pl); 198 return -EINVAL; 199 default: 200 return -EINVAL; 201 } 202 } 203 204 #define power_zone_to_rapl_domain(_zone) \ 205 container_of(_zone, struct rapl_domain, power_zone) 206 207 struct rapl_defaults { 208 u8 floor_freq_reg_addr; 209 int (*check_unit)(struct rapl_domain *rd); 210 void (*set_floor_freq)(struct rapl_domain *rd, bool mode); 211 u64 (*compute_time_window)(struct rapl_domain *rd, u64 val, 212 bool to_raw); 213 unsigned int dram_domain_energy_unit; 214 unsigned int psys_domain_energy_unit; 215 bool spr_psys_bits; 216 }; 217 static struct rapl_defaults *defaults_msr; 218 static const struct rapl_defaults defaults_tpmi; 219 220 static struct rapl_defaults *get_defaults(struct rapl_package *rp) 221 { 222 return rp->priv->defaults; 223 } 224 225 /* Sideband MBI registers */ 226 #define IOSF_CPU_POWER_BUDGET_CTL_BYT (0x2) 227 #define IOSF_CPU_POWER_BUDGET_CTL_TNG (0xdf) 228 229 #define PACKAGE_PLN_INT_SAVED BIT(0) 230 #define MAX_PRIM_NAME (32) 231 232 /* per domain data. used to describe individual knobs such that access function 233 * can be consolidated into one instead of many inline functions. 234 */ 235 struct rapl_primitive_info { 236 const char *name; 237 u64 mask; 238 int shift; 239 enum rapl_domain_reg_id id; 240 enum unit_type unit; 241 u32 flag; 242 }; 243 244 #define PRIMITIVE_INFO_INIT(p, m, s, i, u, f) { \ 245 .name = #p, \ 246 .mask = m, \ 247 .shift = s, \ 248 .id = i, \ 249 .unit = u, \ 250 .flag = f \ 251 } 252 253 static void rapl_init_domains(struct rapl_package *rp); 254 static int rapl_read_data_raw(struct rapl_domain *rd, 255 enum rapl_primitives prim, 256 bool xlate, u64 *data); 257 static int rapl_write_data_raw(struct rapl_domain *rd, 258 enum rapl_primitives prim, 259 unsigned long long value); 260 static int rapl_read_pl_data(struct rapl_domain *rd, int pl, 261 enum pl_prims pl_prim, 262 bool xlate, u64 *data); 263 static int rapl_write_pl_data(struct rapl_domain *rd, int pl, 264 enum pl_prims pl_prim, 265 unsigned long long value); 266 static u64 rapl_unit_xlate(struct rapl_domain *rd, 267 enum unit_type type, u64 value, int to_raw); 268 static void package_power_limit_irq_save(struct rapl_package *rp); 269 270 static LIST_HEAD(rapl_packages); /* guarded by CPU hotplug lock */ 271 272 static const char *const rapl_domain_names[] = { 273 "package", 274 "core", 275 "uncore", 276 "dram", 277 "psys", 278 }; 279 280 static int get_energy_counter(struct powercap_zone *power_zone, 281 u64 *energy_raw) 282 { 283 struct rapl_domain *rd; 284 u64 energy_now; 285 286 /* prevent CPU hotplug, make sure the RAPL domain does not go 287 * away while reading the counter. 288 */ 289 cpus_read_lock(); 290 rd = power_zone_to_rapl_domain(power_zone); 291 292 if (!rapl_read_data_raw(rd, ENERGY_COUNTER, true, &energy_now)) { 293 *energy_raw = energy_now; 294 cpus_read_unlock(); 295 296 return 0; 297 } 298 cpus_read_unlock(); 299 300 return -EIO; 301 } 302 303 static int get_max_energy_counter(struct powercap_zone *pcd_dev, u64 *energy) 304 { 305 struct rapl_domain *rd = power_zone_to_rapl_domain(pcd_dev); 306 307 *energy = rapl_unit_xlate(rd, ENERGY_UNIT, ENERGY_STATUS_MASK, 0); 308 return 0; 309 } 310 311 static int release_zone(struct powercap_zone *power_zone) 312 { 313 struct rapl_domain *rd = power_zone_to_rapl_domain(power_zone); 314 struct rapl_package *rp = rd->rp; 315 316 /* package zone is the last zone of a package, we can free 317 * memory here since all children has been unregistered. 318 */ 319 if (rd->id == RAPL_DOMAIN_PACKAGE) { 320 kfree(rd); 321 rp->domains = NULL; 322 } 323 324 return 0; 325 326 } 327 328 static int find_nr_power_limit(struct rapl_domain *rd) 329 { 330 int i, nr_pl = 0; 331 332 for (i = 0; i < NR_POWER_LIMITS; i++) { 333 if (is_pl_valid(rd, i)) 334 nr_pl++; 335 } 336 337 return nr_pl; 338 } 339 340 static int set_domain_enable(struct powercap_zone *power_zone, bool mode) 341 { 342 struct rapl_domain *rd = power_zone_to_rapl_domain(power_zone); 343 struct rapl_defaults *defaults = get_defaults(rd->rp); 344 int ret; 345 346 cpus_read_lock(); 347 ret = rapl_write_pl_data(rd, POWER_LIMIT1, PL_ENABLE, mode); 348 if (!ret && defaults->set_floor_freq) 349 defaults->set_floor_freq(rd, mode); 350 cpus_read_unlock(); 351 352 return ret; 353 } 354 355 static int get_domain_enable(struct powercap_zone *power_zone, bool *mode) 356 { 357 struct rapl_domain *rd = power_zone_to_rapl_domain(power_zone); 358 u64 val; 359 int ret; 360 361 if (rd->rpl[POWER_LIMIT1].locked) { 362 *mode = false; 363 return 0; 364 } 365 cpus_read_lock(); 366 ret = rapl_read_pl_data(rd, POWER_LIMIT1, PL_ENABLE, true, &val); 367 if (!ret) 368 *mode = val; 369 cpus_read_unlock(); 370 371 return ret; 372 } 373 374 /* per RAPL domain ops, in the order of rapl_domain_type */ 375 static const struct powercap_zone_ops zone_ops[] = { 376 /* RAPL_DOMAIN_PACKAGE */ 377 { 378 .get_energy_uj = get_energy_counter, 379 .get_max_energy_range_uj = get_max_energy_counter, 380 .release = release_zone, 381 .set_enable = set_domain_enable, 382 .get_enable = get_domain_enable, 383 }, 384 /* RAPL_DOMAIN_PP0 */ 385 { 386 .get_energy_uj = get_energy_counter, 387 .get_max_energy_range_uj = get_max_energy_counter, 388 .release = release_zone, 389 .set_enable = set_domain_enable, 390 .get_enable = get_domain_enable, 391 }, 392 /* RAPL_DOMAIN_PP1 */ 393 { 394 .get_energy_uj = get_energy_counter, 395 .get_max_energy_range_uj = get_max_energy_counter, 396 .release = release_zone, 397 .set_enable = set_domain_enable, 398 .get_enable = get_domain_enable, 399 }, 400 /* RAPL_DOMAIN_DRAM */ 401 { 402 .get_energy_uj = get_energy_counter, 403 .get_max_energy_range_uj = get_max_energy_counter, 404 .release = release_zone, 405 .set_enable = set_domain_enable, 406 .get_enable = get_domain_enable, 407 }, 408 /* RAPL_DOMAIN_PLATFORM */ 409 { 410 .get_energy_uj = get_energy_counter, 411 .get_max_energy_range_uj = get_max_energy_counter, 412 .release = release_zone, 413 .set_enable = set_domain_enable, 414 .get_enable = get_domain_enable, 415 }, 416 }; 417 418 /* 419 * Constraint index used by powercap can be different than power limit (PL) 420 * index in that some PLs maybe missing due to non-existent MSRs. So we 421 * need to convert here by finding the valid PLs only (name populated). 422 */ 423 static int contraint_to_pl(struct rapl_domain *rd, int cid) 424 { 425 int i, j; 426 427 for (i = POWER_LIMIT1, j = 0; i < NR_POWER_LIMITS; i++) { 428 if (is_pl_valid(rd, i) && j++ == cid) { 429 pr_debug("%s: index %d\n", __func__, i); 430 return i; 431 } 432 } 433 pr_err("Cannot find matching power limit for constraint %d\n", cid); 434 435 return -EINVAL; 436 } 437 438 static int set_power_limit(struct powercap_zone *power_zone, int cid, 439 u64 power_limit) 440 { 441 struct rapl_domain *rd; 442 struct rapl_package *rp; 443 int ret = 0; 444 int id; 445 446 cpus_read_lock(); 447 rd = power_zone_to_rapl_domain(power_zone); 448 id = contraint_to_pl(rd, cid); 449 rp = rd->rp; 450 451 ret = rapl_write_pl_data(rd, id, PL_LIMIT, power_limit); 452 if (!ret) 453 package_power_limit_irq_save(rp); 454 cpus_read_unlock(); 455 return ret; 456 } 457 458 static int get_current_power_limit(struct powercap_zone *power_zone, int cid, 459 u64 *data) 460 { 461 struct rapl_domain *rd; 462 u64 val; 463 int ret = 0; 464 int id; 465 466 cpus_read_lock(); 467 rd = power_zone_to_rapl_domain(power_zone); 468 id = contraint_to_pl(rd, cid); 469 470 ret = rapl_read_pl_data(rd, id, PL_LIMIT, true, &val); 471 if (!ret) 472 *data = val; 473 474 cpus_read_unlock(); 475 476 return ret; 477 } 478 479 static int set_time_window(struct powercap_zone *power_zone, int cid, 480 u64 window) 481 { 482 struct rapl_domain *rd; 483 int ret = 0; 484 int id; 485 486 cpus_read_lock(); 487 rd = power_zone_to_rapl_domain(power_zone); 488 id = contraint_to_pl(rd, cid); 489 490 ret = rapl_write_pl_data(rd, id, PL_TIME_WINDOW, window); 491 492 cpus_read_unlock(); 493 return ret; 494 } 495 496 static int get_time_window(struct powercap_zone *power_zone, int cid, 497 u64 *data) 498 { 499 struct rapl_domain *rd; 500 u64 val; 501 int ret = 0; 502 int id; 503 504 cpus_read_lock(); 505 rd = power_zone_to_rapl_domain(power_zone); 506 id = contraint_to_pl(rd, cid); 507 508 ret = rapl_read_pl_data(rd, id, PL_TIME_WINDOW, true, &val); 509 if (!ret) 510 *data = val; 511 512 cpus_read_unlock(); 513 514 return ret; 515 } 516 517 static const char *get_constraint_name(struct powercap_zone *power_zone, 518 int cid) 519 { 520 struct rapl_domain *rd; 521 int id; 522 523 rd = power_zone_to_rapl_domain(power_zone); 524 id = contraint_to_pl(rd, cid); 525 if (id >= 0) 526 return rd->rpl[id].name; 527 528 return NULL; 529 } 530 531 static int get_max_power(struct powercap_zone *power_zone, int cid, u64 *data) 532 { 533 struct rapl_domain *rd; 534 u64 val; 535 int ret = 0; 536 int id; 537 538 cpus_read_lock(); 539 rd = power_zone_to_rapl_domain(power_zone); 540 id = contraint_to_pl(rd, cid); 541 542 ret = rapl_read_pl_data(rd, id, PL_MAX_POWER, true, &val); 543 if (!ret) 544 *data = val; 545 546 /* As a generalization rule, PL4 would be around two times PL2. */ 547 if (id == POWER_LIMIT4) 548 *data = *data * 2; 549 550 cpus_read_unlock(); 551 552 return ret; 553 } 554 555 static const struct powercap_zone_constraint_ops constraint_ops = { 556 .set_power_limit_uw = set_power_limit, 557 .get_power_limit_uw = get_current_power_limit, 558 .set_time_window_us = set_time_window, 559 .get_time_window_us = get_time_window, 560 .get_max_power_uw = get_max_power, 561 .get_name = get_constraint_name, 562 }; 563 564 /* Return the id used for read_raw/write_raw callback */ 565 static int get_rid(struct rapl_package *rp) 566 { 567 return rp->lead_cpu >= 0 ? rp->lead_cpu : rp->id; 568 } 569 570 /* called after domain detection and package level data are set */ 571 static void rapl_init_domains(struct rapl_package *rp) 572 { 573 enum rapl_domain_type i; 574 enum rapl_domain_reg_id j; 575 struct rapl_domain *rd = rp->domains; 576 577 for (i = 0; i < RAPL_DOMAIN_MAX; i++) { 578 unsigned int mask = rp->domain_map & (1 << i); 579 int t; 580 581 if (!mask) 582 continue; 583 584 rd->rp = rp; 585 586 if (i == RAPL_DOMAIN_PLATFORM && rp->id > 0) { 587 snprintf(rd->name, RAPL_DOMAIN_NAME_LENGTH, "psys-%d", 588 rp->lead_cpu >= 0 ? topology_physical_package_id(rp->lead_cpu) : 589 rp->id); 590 } else { 591 snprintf(rd->name, RAPL_DOMAIN_NAME_LENGTH, "%s", 592 rapl_domain_names[i]); 593 } 594 595 rd->id = i; 596 597 /* PL1 is supported by default */ 598 rp->priv->limits[i] |= BIT(POWER_LIMIT1); 599 600 for (t = POWER_LIMIT1; t < NR_POWER_LIMITS; t++) { 601 if (rp->priv->limits[i] & BIT(t)) 602 rd->rpl[t].name = pl_names[t]; 603 } 604 605 for (j = 0; j < RAPL_DOMAIN_REG_MAX; j++) 606 rd->regs[j] = rp->priv->regs[i][j]; 607 608 rd++; 609 } 610 } 611 612 static u64 rapl_unit_xlate(struct rapl_domain *rd, enum unit_type type, 613 u64 value, int to_raw) 614 { 615 u64 units = 1; 616 struct rapl_defaults *defaults = get_defaults(rd->rp); 617 u64 scale = 1; 618 619 switch (type) { 620 case POWER_UNIT: 621 units = rd->power_unit; 622 break; 623 case ENERGY_UNIT: 624 scale = ENERGY_UNIT_SCALE; 625 units = rd->energy_unit; 626 break; 627 case TIME_UNIT: 628 return defaults->compute_time_window(rd, value, to_raw); 629 case ARBITRARY_UNIT: 630 default: 631 return value; 632 } 633 634 if (to_raw) 635 return div64_u64(value, units) * scale; 636 637 value *= units; 638 639 return div64_u64(value, scale); 640 } 641 642 /* RAPL primitives for MSR and MMIO I/F */ 643 static struct rapl_primitive_info rpi_msr[NR_RAPL_PRIMITIVES] = { 644 /* name, mask, shift, msr index, unit divisor */ 645 [POWER_LIMIT1] = PRIMITIVE_INFO_INIT(POWER_LIMIT1, POWER_LIMIT1_MASK, 0, 646 RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0), 647 [POWER_LIMIT2] = PRIMITIVE_INFO_INIT(POWER_LIMIT2, POWER_LIMIT2_MASK, 32, 648 RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0), 649 [POWER_LIMIT4] = PRIMITIVE_INFO_INIT(POWER_LIMIT4, POWER_LIMIT4_MASK, 0, 650 RAPL_DOMAIN_REG_PL4, POWER_UNIT, 0), 651 [ENERGY_COUNTER] = PRIMITIVE_INFO_INIT(ENERGY_COUNTER, ENERGY_STATUS_MASK, 0, 652 RAPL_DOMAIN_REG_STATUS, ENERGY_UNIT, 0), 653 [FW_LOCK] = PRIMITIVE_INFO_INIT(FW_LOCK, POWER_LOW_LOCK, 31, 654 RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), 655 [FW_HIGH_LOCK] = PRIMITIVE_INFO_INIT(FW_LOCK, POWER_HIGH_LOCK, 63, 656 RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), 657 [PL1_ENABLE] = PRIMITIVE_INFO_INIT(PL1_ENABLE, POWER_LIMIT1_ENABLE, 15, 658 RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), 659 [PL1_CLAMP] = PRIMITIVE_INFO_INIT(PL1_CLAMP, POWER_LIMIT1_CLAMP, 16, 660 RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), 661 [PL2_ENABLE] = PRIMITIVE_INFO_INIT(PL2_ENABLE, POWER_LIMIT2_ENABLE, 47, 662 RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), 663 [PL2_CLAMP] = PRIMITIVE_INFO_INIT(PL2_CLAMP, POWER_LIMIT2_CLAMP, 48, 664 RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), 665 [TIME_WINDOW1] = PRIMITIVE_INFO_INIT(TIME_WINDOW1, TIME_WINDOW1_MASK, 17, 666 RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0), 667 [TIME_WINDOW2] = PRIMITIVE_INFO_INIT(TIME_WINDOW2, TIME_WINDOW2_MASK, 49, 668 RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0), 669 [THERMAL_SPEC_POWER] = PRIMITIVE_INFO_INIT(THERMAL_SPEC_POWER, POWER_INFO_THERMAL_SPEC_MASK, 670 0, RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0), 671 [MAX_POWER] = PRIMITIVE_INFO_INIT(MAX_POWER, POWER_INFO_MAX_MASK, 32, 672 RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0), 673 [MIN_POWER] = PRIMITIVE_INFO_INIT(MIN_POWER, POWER_INFO_MIN_MASK, 16, 674 RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0), 675 [MAX_TIME_WINDOW] = PRIMITIVE_INFO_INIT(MAX_TIME_WINDOW, POWER_INFO_MAX_TIME_WIN_MASK, 48, 676 RAPL_DOMAIN_REG_INFO, TIME_UNIT, 0), 677 [THROTTLED_TIME] = PRIMITIVE_INFO_INIT(THROTTLED_TIME, PERF_STATUS_THROTTLE_TIME_MASK, 0, 678 RAPL_DOMAIN_REG_PERF, TIME_UNIT, 0), 679 [PRIORITY_LEVEL] = PRIMITIVE_INFO_INIT(PRIORITY_LEVEL, PP_POLICY_MASK, 0, 680 RAPL_DOMAIN_REG_POLICY, ARBITRARY_UNIT, 0), 681 [PSYS_POWER_LIMIT1] = PRIMITIVE_INFO_INIT(PSYS_POWER_LIMIT1, PSYS_POWER_LIMIT1_MASK, 0, 682 RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0), 683 [PSYS_POWER_LIMIT2] = PRIMITIVE_INFO_INIT(PSYS_POWER_LIMIT2, PSYS_POWER_LIMIT2_MASK, 32, 684 RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0), 685 [PSYS_PL1_ENABLE] = PRIMITIVE_INFO_INIT(PSYS_PL1_ENABLE, PSYS_POWER_LIMIT1_ENABLE, 17, 686 RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), 687 [PSYS_PL2_ENABLE] = PRIMITIVE_INFO_INIT(PSYS_PL2_ENABLE, PSYS_POWER_LIMIT2_ENABLE, 49, 688 RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), 689 [PSYS_TIME_WINDOW1] = PRIMITIVE_INFO_INIT(PSYS_TIME_WINDOW1, PSYS_TIME_WINDOW1_MASK, 19, 690 RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0), 691 [PSYS_TIME_WINDOW2] = PRIMITIVE_INFO_INIT(PSYS_TIME_WINDOW2, PSYS_TIME_WINDOW2_MASK, 51, 692 RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0), 693 /* non-hardware */ 694 [AVERAGE_POWER] = PRIMITIVE_INFO_INIT(AVERAGE_POWER, 0, 0, 0, POWER_UNIT, 695 RAPL_PRIMITIVE_DERIVED), 696 }; 697 698 /* RAPL primitives for TPMI I/F */ 699 static struct rapl_primitive_info rpi_tpmi[NR_RAPL_PRIMITIVES] = { 700 /* name, mask, shift, msr index, unit divisor */ 701 [POWER_LIMIT1] = PRIMITIVE_INFO_INIT(POWER_LIMIT1, TPMI_POWER_LIMIT_MASK, 0, 702 RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0), 703 [POWER_LIMIT2] = PRIMITIVE_INFO_INIT(POWER_LIMIT2, TPMI_POWER_LIMIT_MASK, 0, 704 RAPL_DOMAIN_REG_PL2, POWER_UNIT, 0), 705 [POWER_LIMIT4] = PRIMITIVE_INFO_INIT(POWER_LIMIT4, TPMI_POWER_LIMIT_MASK, 0, 706 RAPL_DOMAIN_REG_PL4, POWER_UNIT, 0), 707 [ENERGY_COUNTER] = PRIMITIVE_INFO_INIT(ENERGY_COUNTER, ENERGY_STATUS_MASK, 0, 708 RAPL_DOMAIN_REG_STATUS, ENERGY_UNIT, 0), 709 [PL1_LOCK] = PRIMITIVE_INFO_INIT(PL1_LOCK, POWER_HIGH_LOCK, 63, 710 RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), 711 [PL2_LOCK] = PRIMITIVE_INFO_INIT(PL2_LOCK, POWER_HIGH_LOCK, 63, 712 RAPL_DOMAIN_REG_PL2, ARBITRARY_UNIT, 0), 713 [PL4_LOCK] = PRIMITIVE_INFO_INIT(PL4_LOCK, POWER_HIGH_LOCK, 63, 714 RAPL_DOMAIN_REG_PL4, ARBITRARY_UNIT, 0), 715 [PL1_ENABLE] = PRIMITIVE_INFO_INIT(PL1_ENABLE, TPMI_POWER_LIMIT_ENABLE, 62, 716 RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), 717 [PL2_ENABLE] = PRIMITIVE_INFO_INIT(PL2_ENABLE, TPMI_POWER_LIMIT_ENABLE, 62, 718 RAPL_DOMAIN_REG_PL2, ARBITRARY_UNIT, 0), 719 [PL4_ENABLE] = PRIMITIVE_INFO_INIT(PL4_ENABLE, TPMI_POWER_LIMIT_ENABLE, 62, 720 RAPL_DOMAIN_REG_PL4, ARBITRARY_UNIT, 0), 721 [TIME_WINDOW1] = PRIMITIVE_INFO_INIT(TIME_WINDOW1, TPMI_TIME_WINDOW_MASK, 18, 722 RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0), 723 [TIME_WINDOW2] = PRIMITIVE_INFO_INIT(TIME_WINDOW2, TPMI_TIME_WINDOW_MASK, 18, 724 RAPL_DOMAIN_REG_PL2, TIME_UNIT, 0), 725 [THERMAL_SPEC_POWER] = PRIMITIVE_INFO_INIT(THERMAL_SPEC_POWER, TPMI_INFO_SPEC_MASK, 0, 726 RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0), 727 [MAX_POWER] = PRIMITIVE_INFO_INIT(MAX_POWER, TPMI_INFO_MAX_MASK, 36, 728 RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0), 729 [MIN_POWER] = PRIMITIVE_INFO_INIT(MIN_POWER, TPMI_INFO_MIN_MASK, 18, 730 RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0), 731 [MAX_TIME_WINDOW] = PRIMITIVE_INFO_INIT(MAX_TIME_WINDOW, TPMI_INFO_MAX_TIME_WIN_MASK, 54, 732 RAPL_DOMAIN_REG_INFO, TIME_UNIT, 0), 733 [THROTTLED_TIME] = PRIMITIVE_INFO_INIT(THROTTLED_TIME, PERF_STATUS_THROTTLE_TIME_MASK, 0, 734 RAPL_DOMAIN_REG_PERF, TIME_UNIT, 0), 735 /* non-hardware */ 736 [AVERAGE_POWER] = PRIMITIVE_INFO_INIT(AVERAGE_POWER, 0, 0, 0, 737 POWER_UNIT, RAPL_PRIMITIVE_DERIVED), 738 }; 739 740 static struct rapl_primitive_info *get_rpi(struct rapl_package *rp, int prim) 741 { 742 struct rapl_primitive_info *rpi = rp->priv->rpi; 743 744 if (prim < 0 || prim >= NR_RAPL_PRIMITIVES || !rpi) 745 return NULL; 746 747 return &rpi[prim]; 748 } 749 750 static int rapl_config(struct rapl_package *rp) 751 { 752 switch (rp->priv->type) { 753 /* MMIO I/F shares the same register layout as MSR registers */ 754 case RAPL_IF_MMIO: 755 case RAPL_IF_MSR: 756 rp->priv->defaults = (void *)defaults_msr; 757 rp->priv->rpi = (void *)rpi_msr; 758 break; 759 case RAPL_IF_TPMI: 760 rp->priv->defaults = (void *)&defaults_tpmi; 761 rp->priv->rpi = (void *)rpi_tpmi; 762 break; 763 default: 764 return -EINVAL; 765 } 766 767 /* defaults_msr can be NULL on unsupported platforms */ 768 if (!rp->priv->defaults || !rp->priv->rpi) 769 return -ENODEV; 770 771 return 0; 772 } 773 774 static enum rapl_primitives 775 prim_fixups(struct rapl_domain *rd, enum rapl_primitives prim) 776 { 777 struct rapl_defaults *defaults = get_defaults(rd->rp); 778 779 if (!defaults->spr_psys_bits) 780 return prim; 781 782 if (rd->id != RAPL_DOMAIN_PLATFORM) 783 return prim; 784 785 switch (prim) { 786 case POWER_LIMIT1: 787 return PSYS_POWER_LIMIT1; 788 case POWER_LIMIT2: 789 return PSYS_POWER_LIMIT2; 790 case PL1_ENABLE: 791 return PSYS_PL1_ENABLE; 792 case PL2_ENABLE: 793 return PSYS_PL2_ENABLE; 794 case TIME_WINDOW1: 795 return PSYS_TIME_WINDOW1; 796 case TIME_WINDOW2: 797 return PSYS_TIME_WINDOW2; 798 default: 799 return prim; 800 } 801 } 802 803 /* Read primitive data based on its related struct rapl_primitive_info. 804 * if xlate flag is set, return translated data based on data units, i.e. 805 * time, energy, and power. 806 * RAPL MSRs are non-architectual and are laid out not consistently across 807 * domains. Here we use primitive info to allow writing consolidated access 808 * functions. 809 * For a given primitive, it is processed by MSR mask and shift. Unit conversion 810 * is pre-assigned based on RAPL unit MSRs read at init time. 811 * 63-------------------------- 31--------------------------- 0 812 * | xxxxx (mask) | 813 * | |<- shift ----------------| 814 * 63-------------------------- 31--------------------------- 0 815 */ 816 static int rapl_read_data_raw(struct rapl_domain *rd, 817 enum rapl_primitives prim, bool xlate, u64 *data) 818 { 819 u64 value; 820 enum rapl_primitives prim_fixed = prim_fixups(rd, prim); 821 struct rapl_primitive_info *rpi = get_rpi(rd->rp, prim_fixed); 822 struct reg_action ra; 823 824 if (!rpi || !rpi->name || rpi->flag & RAPL_PRIMITIVE_DUMMY) 825 return -EINVAL; 826 827 ra.reg = rd->regs[rpi->id]; 828 if (!ra.reg.val) 829 return -EINVAL; 830 831 /* non-hardware data are collected by the polling thread */ 832 if (rpi->flag & RAPL_PRIMITIVE_DERIVED) { 833 *data = rd->rdd.primitives[prim]; 834 return 0; 835 } 836 837 ra.mask = rpi->mask; 838 839 if (rd->rp->priv->read_raw(get_rid(rd->rp), &ra)) { 840 pr_debug("failed to read reg 0x%llx for %s:%s\n", ra.reg.val, rd->rp->name, rd->name); 841 return -EIO; 842 } 843 844 value = ra.value >> rpi->shift; 845 846 if (xlate) 847 *data = rapl_unit_xlate(rd, rpi->unit, value, 0); 848 else 849 *data = value; 850 851 return 0; 852 } 853 854 /* Similar use of primitive info in the read counterpart */ 855 static int rapl_write_data_raw(struct rapl_domain *rd, 856 enum rapl_primitives prim, 857 unsigned long long value) 858 { 859 enum rapl_primitives prim_fixed = prim_fixups(rd, prim); 860 struct rapl_primitive_info *rpi = get_rpi(rd->rp, prim_fixed); 861 u64 bits; 862 struct reg_action ra; 863 int ret; 864 865 if (!rpi || !rpi->name || rpi->flag & RAPL_PRIMITIVE_DUMMY) 866 return -EINVAL; 867 868 bits = rapl_unit_xlate(rd, rpi->unit, value, 1); 869 bits <<= rpi->shift; 870 bits &= rpi->mask; 871 872 memset(&ra, 0, sizeof(ra)); 873 874 ra.reg = rd->regs[rpi->id]; 875 ra.mask = rpi->mask; 876 ra.value = bits; 877 878 ret = rd->rp->priv->write_raw(get_rid(rd->rp), &ra); 879 880 return ret; 881 } 882 883 static int rapl_read_pl_data(struct rapl_domain *rd, int pl, 884 enum pl_prims pl_prim, bool xlate, u64 *data) 885 { 886 enum rapl_primitives prim = get_pl_prim(rd, pl, pl_prim); 887 888 if (!is_pl_valid(rd, pl)) 889 return -EINVAL; 890 891 return rapl_read_data_raw(rd, prim, xlate, data); 892 } 893 894 static int rapl_write_pl_data(struct rapl_domain *rd, int pl, 895 enum pl_prims pl_prim, 896 unsigned long long value) 897 { 898 enum rapl_primitives prim = get_pl_prim(rd, pl, pl_prim); 899 900 if (!is_pl_valid(rd, pl)) 901 return -EINVAL; 902 903 if (rd->rpl[pl].locked) { 904 pr_debug("%s:%s:%s locked by BIOS\n", rd->rp->name, rd->name, pl_names[pl]); 905 return -EACCES; 906 } 907 908 return rapl_write_data_raw(rd, prim, value); 909 } 910 /* 911 * Raw RAPL data stored in MSRs are in certain scales. We need to 912 * convert them into standard units based on the units reported in 913 * the RAPL unit MSRs. This is specific to CPUs as the method to 914 * calculate units differ on different CPUs. 915 * We convert the units to below format based on CPUs. 916 * i.e. 917 * energy unit: picoJoules : Represented in picoJoules by default 918 * power unit : microWatts : Represented in milliWatts by default 919 * time unit : microseconds: Represented in seconds by default 920 */ 921 static int rapl_check_unit_core(struct rapl_domain *rd) 922 { 923 struct reg_action ra; 924 u32 value; 925 926 ra.reg = rd->regs[RAPL_DOMAIN_REG_UNIT]; 927 ra.mask = ~0; 928 if (rd->rp->priv->read_raw(get_rid(rd->rp), &ra)) { 929 pr_err("Failed to read power unit REG 0x%llx on %s:%s, exit.\n", 930 ra.reg.val, rd->rp->name, rd->name); 931 return -ENODEV; 932 } 933 934 value = (ra.value & ENERGY_UNIT_MASK) >> ENERGY_UNIT_OFFSET; 935 rd->energy_unit = ENERGY_UNIT_SCALE * 1000000 / (1 << value); 936 937 value = (ra.value & POWER_UNIT_MASK) >> POWER_UNIT_OFFSET; 938 rd->power_unit = 1000000 / (1 << value); 939 940 value = (ra.value & TIME_UNIT_MASK) >> TIME_UNIT_OFFSET; 941 rd->time_unit = 1000000 / (1 << value); 942 943 pr_debug("Core CPU %s:%s energy=%dpJ, time=%dus, power=%duW\n", 944 rd->rp->name, rd->name, rd->energy_unit, rd->time_unit, rd->power_unit); 945 946 return 0; 947 } 948 949 static int rapl_check_unit_atom(struct rapl_domain *rd) 950 { 951 struct reg_action ra; 952 u32 value; 953 954 ra.reg = rd->regs[RAPL_DOMAIN_REG_UNIT]; 955 ra.mask = ~0; 956 if (rd->rp->priv->read_raw(get_rid(rd->rp), &ra)) { 957 pr_err("Failed to read power unit REG 0x%llx on %s:%s, exit.\n", 958 ra.reg.val, rd->rp->name, rd->name); 959 return -ENODEV; 960 } 961 962 value = (ra.value & ENERGY_UNIT_MASK) >> ENERGY_UNIT_OFFSET; 963 rd->energy_unit = ENERGY_UNIT_SCALE * 1 << value; 964 965 value = (ra.value & POWER_UNIT_MASK) >> POWER_UNIT_OFFSET; 966 rd->power_unit = (1 << value) * 1000; 967 968 value = (ra.value & TIME_UNIT_MASK) >> TIME_UNIT_OFFSET; 969 rd->time_unit = 1000000 / (1 << value); 970 971 pr_debug("Atom %s:%s energy=%dpJ, time=%dus, power=%duW\n", 972 rd->rp->name, rd->name, rd->energy_unit, rd->time_unit, rd->power_unit); 973 974 return 0; 975 } 976 977 static void power_limit_irq_save_cpu(void *info) 978 { 979 u32 l, h = 0; 980 struct rapl_package *rp = (struct rapl_package *)info; 981 982 /* save the state of PLN irq mask bit before disabling it */ 983 rdmsr_safe(MSR_IA32_PACKAGE_THERM_INTERRUPT, &l, &h); 984 if (!(rp->power_limit_irq & PACKAGE_PLN_INT_SAVED)) { 985 rp->power_limit_irq = l & PACKAGE_THERM_INT_PLN_ENABLE; 986 rp->power_limit_irq |= PACKAGE_PLN_INT_SAVED; 987 } 988 l &= ~PACKAGE_THERM_INT_PLN_ENABLE; 989 wrmsr_safe(MSR_IA32_PACKAGE_THERM_INTERRUPT, l, h); 990 } 991 992 /* REVISIT: 993 * When package power limit is set artificially low by RAPL, LVT 994 * thermal interrupt for package power limit should be ignored 995 * since we are not really exceeding the real limit. The intention 996 * is to avoid excessive interrupts while we are trying to save power. 997 * A useful feature might be routing the package_power_limit interrupt 998 * to userspace via eventfd. once we have a usecase, this is simple 999 * to do by adding an atomic notifier. 1000 */ 1001 1002 static void package_power_limit_irq_save(struct rapl_package *rp) 1003 { 1004 if (rp->lead_cpu < 0) 1005 return; 1006 1007 if (!boot_cpu_has(X86_FEATURE_PTS) || !boot_cpu_has(X86_FEATURE_PLN)) 1008 return; 1009 1010 smp_call_function_single(rp->lead_cpu, power_limit_irq_save_cpu, rp, 1); 1011 } 1012 1013 /* 1014 * Restore per package power limit interrupt enable state. Called from cpu 1015 * hotplug code on package removal. 1016 */ 1017 static void package_power_limit_irq_restore(struct rapl_package *rp) 1018 { 1019 u32 l, h; 1020 1021 if (rp->lead_cpu < 0) 1022 return; 1023 1024 if (!boot_cpu_has(X86_FEATURE_PTS) || !boot_cpu_has(X86_FEATURE_PLN)) 1025 return; 1026 1027 /* irq enable state not saved, nothing to restore */ 1028 if (!(rp->power_limit_irq & PACKAGE_PLN_INT_SAVED)) 1029 return; 1030 1031 rdmsr_safe(MSR_IA32_PACKAGE_THERM_INTERRUPT, &l, &h); 1032 1033 if (rp->power_limit_irq & PACKAGE_THERM_INT_PLN_ENABLE) 1034 l |= PACKAGE_THERM_INT_PLN_ENABLE; 1035 else 1036 l &= ~PACKAGE_THERM_INT_PLN_ENABLE; 1037 1038 wrmsr_safe(MSR_IA32_PACKAGE_THERM_INTERRUPT, l, h); 1039 } 1040 1041 static void set_floor_freq_default(struct rapl_domain *rd, bool mode) 1042 { 1043 int i; 1044 1045 /* always enable clamp such that p-state can go below OS requested 1046 * range. power capping priority over guranteed frequency. 1047 */ 1048 rapl_write_pl_data(rd, POWER_LIMIT1, PL_CLAMP, mode); 1049 1050 for (i = POWER_LIMIT2; i < NR_POWER_LIMITS; i++) { 1051 rapl_write_pl_data(rd, i, PL_ENABLE, mode); 1052 rapl_write_pl_data(rd, i, PL_CLAMP, mode); 1053 } 1054 } 1055 1056 static void set_floor_freq_atom(struct rapl_domain *rd, bool enable) 1057 { 1058 static u32 power_ctrl_orig_val; 1059 struct rapl_defaults *defaults = get_defaults(rd->rp); 1060 u32 mdata; 1061 1062 if (!defaults->floor_freq_reg_addr) { 1063 pr_err("Invalid floor frequency config register\n"); 1064 return; 1065 } 1066 1067 if (!power_ctrl_orig_val) 1068 iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_CR_READ, 1069 defaults->floor_freq_reg_addr, 1070 &power_ctrl_orig_val); 1071 mdata = power_ctrl_orig_val; 1072 if (enable) { 1073 mdata &= ~(0x7f << 8); 1074 mdata |= 1 << 8; 1075 } 1076 iosf_mbi_write(BT_MBI_UNIT_PMC, MBI_CR_WRITE, 1077 defaults->floor_freq_reg_addr, mdata); 1078 } 1079 1080 static u64 rapl_compute_time_window_core(struct rapl_domain *rd, u64 value, 1081 bool to_raw) 1082 { 1083 u64 f, y; /* fraction and exp. used for time unit */ 1084 1085 /* 1086 * Special processing based on 2^Y*(1+F/4), refer 1087 * to Intel Software Developer's manual Vol.3B: CH 14.9.3. 1088 */ 1089 if (!to_raw) { 1090 f = (value & 0x60) >> 5; 1091 y = value & 0x1f; 1092 value = (1 << y) * (4 + f) * rd->time_unit / 4; 1093 } else { 1094 if (value < rd->time_unit) 1095 return 0; 1096 1097 do_div(value, rd->time_unit); 1098 y = ilog2(value); 1099 1100 /* 1101 * The target hardware field is 7 bits wide, so return all ones 1102 * if the exponent is too large. 1103 */ 1104 if (y > 0x1f) 1105 return 0x7f; 1106 1107 f = div64_u64(4 * (value - (1ULL << y)), 1ULL << y); 1108 value = (y & 0x1f) | ((f & 0x3) << 5); 1109 } 1110 return value; 1111 } 1112 1113 static u64 rapl_compute_time_window_atom(struct rapl_domain *rd, u64 value, 1114 bool to_raw) 1115 { 1116 /* 1117 * Atom time unit encoding is straight forward val * time_unit, 1118 * where time_unit is default to 1 sec. Never 0. 1119 */ 1120 if (!to_raw) 1121 return (value) ? value * rd->time_unit : rd->time_unit; 1122 1123 value = div64_u64(value, rd->time_unit); 1124 1125 return value; 1126 } 1127 1128 /* TPMI Unit register has different layout */ 1129 #define TPMI_POWER_UNIT_OFFSET POWER_UNIT_OFFSET 1130 #define TPMI_POWER_UNIT_MASK POWER_UNIT_MASK 1131 #define TPMI_ENERGY_UNIT_OFFSET 0x06 1132 #define TPMI_ENERGY_UNIT_MASK 0x7C0 1133 #define TPMI_TIME_UNIT_OFFSET 0x0C 1134 #define TPMI_TIME_UNIT_MASK 0xF000 1135 1136 static int rapl_check_unit_tpmi(struct rapl_domain *rd) 1137 { 1138 struct reg_action ra; 1139 u32 value; 1140 1141 ra.reg = rd->regs[RAPL_DOMAIN_REG_UNIT]; 1142 ra.mask = ~0; 1143 if (rd->rp->priv->read_raw(get_rid(rd->rp), &ra)) { 1144 pr_err("Failed to read power unit REG 0x%llx on %s:%s, exit.\n", 1145 ra.reg.val, rd->rp->name, rd->name); 1146 return -ENODEV; 1147 } 1148 1149 value = (ra.value & TPMI_ENERGY_UNIT_MASK) >> TPMI_ENERGY_UNIT_OFFSET; 1150 rd->energy_unit = ENERGY_UNIT_SCALE * 1000000 / (1 << value); 1151 1152 value = (ra.value & TPMI_POWER_UNIT_MASK) >> TPMI_POWER_UNIT_OFFSET; 1153 rd->power_unit = 1000000 / (1 << value); 1154 1155 value = (ra.value & TPMI_TIME_UNIT_MASK) >> TPMI_TIME_UNIT_OFFSET; 1156 rd->time_unit = 1000000 / (1 << value); 1157 1158 pr_debug("Core CPU %s:%s energy=%dpJ, time=%dus, power=%duW\n", 1159 rd->rp->name, rd->name, rd->energy_unit, rd->time_unit, rd->power_unit); 1160 1161 return 0; 1162 } 1163 1164 static const struct rapl_defaults defaults_tpmi = { 1165 .check_unit = rapl_check_unit_tpmi, 1166 /* Reuse existing logic, ignore the PL_CLAMP failures and enable all Power Limits */ 1167 .set_floor_freq = set_floor_freq_default, 1168 .compute_time_window = rapl_compute_time_window_core, 1169 }; 1170 1171 static const struct rapl_defaults rapl_defaults_core = { 1172 .floor_freq_reg_addr = 0, 1173 .check_unit = rapl_check_unit_core, 1174 .set_floor_freq = set_floor_freq_default, 1175 .compute_time_window = rapl_compute_time_window_core, 1176 }; 1177 1178 static const struct rapl_defaults rapl_defaults_hsw_server = { 1179 .check_unit = rapl_check_unit_core, 1180 .set_floor_freq = set_floor_freq_default, 1181 .compute_time_window = rapl_compute_time_window_core, 1182 .dram_domain_energy_unit = 15300, 1183 }; 1184 1185 static const struct rapl_defaults rapl_defaults_spr_server = { 1186 .check_unit = rapl_check_unit_core, 1187 .set_floor_freq = set_floor_freq_default, 1188 .compute_time_window = rapl_compute_time_window_core, 1189 .psys_domain_energy_unit = 1000000000, 1190 .spr_psys_bits = true, 1191 }; 1192 1193 static const struct rapl_defaults rapl_defaults_byt = { 1194 .floor_freq_reg_addr = IOSF_CPU_POWER_BUDGET_CTL_BYT, 1195 .check_unit = rapl_check_unit_atom, 1196 .set_floor_freq = set_floor_freq_atom, 1197 .compute_time_window = rapl_compute_time_window_atom, 1198 }; 1199 1200 static const struct rapl_defaults rapl_defaults_tng = { 1201 .floor_freq_reg_addr = IOSF_CPU_POWER_BUDGET_CTL_TNG, 1202 .check_unit = rapl_check_unit_atom, 1203 .set_floor_freq = set_floor_freq_atom, 1204 .compute_time_window = rapl_compute_time_window_atom, 1205 }; 1206 1207 static const struct rapl_defaults rapl_defaults_ann = { 1208 .floor_freq_reg_addr = 0, 1209 .check_unit = rapl_check_unit_atom, 1210 .set_floor_freq = NULL, 1211 .compute_time_window = rapl_compute_time_window_atom, 1212 }; 1213 1214 static const struct rapl_defaults rapl_defaults_cht = { 1215 .floor_freq_reg_addr = 0, 1216 .check_unit = rapl_check_unit_atom, 1217 .set_floor_freq = NULL, 1218 .compute_time_window = rapl_compute_time_window_atom, 1219 }; 1220 1221 static const struct rapl_defaults rapl_defaults_amd = { 1222 .check_unit = rapl_check_unit_core, 1223 }; 1224 1225 static const struct x86_cpu_id rapl_ids[] __initconst = { 1226 X86_MATCH_VFM(INTEL_SANDYBRIDGE, &rapl_defaults_core), 1227 X86_MATCH_VFM(INTEL_SANDYBRIDGE_X, &rapl_defaults_core), 1228 1229 X86_MATCH_VFM(INTEL_IVYBRIDGE, &rapl_defaults_core), 1230 X86_MATCH_VFM(INTEL_IVYBRIDGE_X, &rapl_defaults_core), 1231 1232 X86_MATCH_VFM(INTEL_HASWELL, &rapl_defaults_core), 1233 X86_MATCH_VFM(INTEL_HASWELL_L, &rapl_defaults_core), 1234 X86_MATCH_VFM(INTEL_HASWELL_G, &rapl_defaults_core), 1235 X86_MATCH_VFM(INTEL_HASWELL_X, &rapl_defaults_hsw_server), 1236 1237 X86_MATCH_VFM(INTEL_BROADWELL, &rapl_defaults_core), 1238 X86_MATCH_VFM(INTEL_BROADWELL_G, &rapl_defaults_core), 1239 X86_MATCH_VFM(INTEL_BROADWELL_D, &rapl_defaults_core), 1240 X86_MATCH_VFM(INTEL_BROADWELL_X, &rapl_defaults_hsw_server), 1241 1242 X86_MATCH_VFM(INTEL_SKYLAKE, &rapl_defaults_core), 1243 X86_MATCH_VFM(INTEL_SKYLAKE_L, &rapl_defaults_core), 1244 X86_MATCH_VFM(INTEL_SKYLAKE_X, &rapl_defaults_hsw_server), 1245 X86_MATCH_VFM(INTEL_KABYLAKE_L, &rapl_defaults_core), 1246 X86_MATCH_VFM(INTEL_KABYLAKE, &rapl_defaults_core), 1247 X86_MATCH_VFM(INTEL_CANNONLAKE_L, &rapl_defaults_core), 1248 X86_MATCH_VFM(INTEL_ICELAKE_L, &rapl_defaults_core), 1249 X86_MATCH_VFM(INTEL_ICELAKE, &rapl_defaults_core), 1250 X86_MATCH_VFM(INTEL_ICELAKE_NNPI, &rapl_defaults_core), 1251 X86_MATCH_VFM(INTEL_ICELAKE_X, &rapl_defaults_hsw_server), 1252 X86_MATCH_VFM(INTEL_ICELAKE_D, &rapl_defaults_hsw_server), 1253 X86_MATCH_VFM(INTEL_COMETLAKE_L, &rapl_defaults_core), 1254 X86_MATCH_VFM(INTEL_COMETLAKE, &rapl_defaults_core), 1255 X86_MATCH_VFM(INTEL_TIGERLAKE_L, &rapl_defaults_core), 1256 X86_MATCH_VFM(INTEL_TIGERLAKE, &rapl_defaults_core), 1257 X86_MATCH_VFM(INTEL_ROCKETLAKE, &rapl_defaults_core), 1258 X86_MATCH_VFM(INTEL_ALDERLAKE, &rapl_defaults_core), 1259 X86_MATCH_VFM(INTEL_ALDERLAKE_L, &rapl_defaults_core), 1260 X86_MATCH_VFM(INTEL_ATOM_GRACEMONT, &rapl_defaults_core), 1261 X86_MATCH_VFM(INTEL_RAPTORLAKE, &rapl_defaults_core), 1262 X86_MATCH_VFM(INTEL_RAPTORLAKE_P, &rapl_defaults_core), 1263 X86_MATCH_VFM(INTEL_RAPTORLAKE_S, &rapl_defaults_core), 1264 X86_MATCH_VFM(INTEL_METEORLAKE, &rapl_defaults_core), 1265 X86_MATCH_VFM(INTEL_METEORLAKE_L, &rapl_defaults_core), 1266 X86_MATCH_VFM(INTEL_SAPPHIRERAPIDS_X, &rapl_defaults_spr_server), 1267 X86_MATCH_VFM(INTEL_EMERALDRAPIDS_X, &rapl_defaults_spr_server), 1268 X86_MATCH_VFM(INTEL_LUNARLAKE_M, &rapl_defaults_core), 1269 X86_MATCH_VFM(INTEL_PANTHERLAKE_L, &rapl_defaults_core), 1270 X86_MATCH_VFM(INTEL_ARROWLAKE_H, &rapl_defaults_core), 1271 X86_MATCH_VFM(INTEL_ARROWLAKE, &rapl_defaults_core), 1272 X86_MATCH_VFM(INTEL_ARROWLAKE_U, &rapl_defaults_core), 1273 X86_MATCH_VFM(INTEL_LAKEFIELD, &rapl_defaults_core), 1274 1275 X86_MATCH_VFM(INTEL_ATOM_SILVERMONT, &rapl_defaults_byt), 1276 X86_MATCH_VFM(INTEL_ATOM_AIRMONT, &rapl_defaults_cht), 1277 X86_MATCH_VFM(INTEL_ATOM_SILVERMONT_MID, &rapl_defaults_tng), 1278 X86_MATCH_VFM(INTEL_ATOM_SILVERMONT_MID2,&rapl_defaults_ann), 1279 X86_MATCH_VFM(INTEL_ATOM_GOLDMONT, &rapl_defaults_core), 1280 X86_MATCH_VFM(INTEL_ATOM_GOLDMONT_PLUS, &rapl_defaults_core), 1281 X86_MATCH_VFM(INTEL_ATOM_GOLDMONT_D, &rapl_defaults_core), 1282 X86_MATCH_VFM(INTEL_ATOM_TREMONT, &rapl_defaults_core), 1283 X86_MATCH_VFM(INTEL_ATOM_TREMONT_D, &rapl_defaults_core), 1284 X86_MATCH_VFM(INTEL_ATOM_TREMONT_L, &rapl_defaults_core), 1285 1286 X86_MATCH_VFM(INTEL_XEON_PHI_KNL, &rapl_defaults_hsw_server), 1287 X86_MATCH_VFM(INTEL_XEON_PHI_KNM, &rapl_defaults_hsw_server), 1288 1289 X86_MATCH_VENDOR_FAM(AMD, 0x17, &rapl_defaults_amd), 1290 X86_MATCH_VENDOR_FAM(AMD, 0x19, &rapl_defaults_amd), 1291 X86_MATCH_VENDOR_FAM(AMD, 0x1A, &rapl_defaults_amd), 1292 X86_MATCH_VENDOR_FAM(HYGON, 0x18, &rapl_defaults_amd), 1293 {} 1294 }; 1295 MODULE_DEVICE_TABLE(x86cpu, rapl_ids); 1296 1297 /* Read once for all raw primitive data for domains */ 1298 static void rapl_update_domain_data(struct rapl_package *rp) 1299 { 1300 int dmn, prim; 1301 u64 val; 1302 1303 for (dmn = 0; dmn < rp->nr_domains; dmn++) { 1304 pr_debug("update %s domain %s data\n", rp->name, 1305 rp->domains[dmn].name); 1306 /* exclude non-raw primitives */ 1307 for (prim = 0; prim < NR_RAW_PRIMITIVES; prim++) { 1308 struct rapl_primitive_info *rpi = get_rpi(rp, prim); 1309 1310 if (!rapl_read_data_raw(&rp->domains[dmn], prim, 1311 rpi->unit, &val)) 1312 rp->domains[dmn].rdd.primitives[prim] = val; 1313 } 1314 } 1315 1316 } 1317 1318 static int rapl_package_register_powercap(struct rapl_package *rp) 1319 { 1320 struct rapl_domain *rd; 1321 struct powercap_zone *power_zone = NULL; 1322 int nr_pl, ret; 1323 1324 /* Update the domain data of the new package */ 1325 rapl_update_domain_data(rp); 1326 1327 /* first we register package domain as the parent zone */ 1328 for (rd = rp->domains; rd < rp->domains + rp->nr_domains; rd++) { 1329 if (rd->id == RAPL_DOMAIN_PACKAGE) { 1330 nr_pl = find_nr_power_limit(rd); 1331 pr_debug("register package domain %s\n", rp->name); 1332 power_zone = powercap_register_zone(&rd->power_zone, 1333 rp->priv->control_type, rp->name, 1334 NULL, &zone_ops[rd->id], nr_pl, 1335 &constraint_ops); 1336 if (IS_ERR(power_zone)) { 1337 pr_debug("failed to register power zone %s\n", 1338 rp->name); 1339 return PTR_ERR(power_zone); 1340 } 1341 /* track parent zone in per package/socket data */ 1342 rp->power_zone = power_zone; 1343 /* done, only one package domain per socket */ 1344 break; 1345 } 1346 } 1347 if (!power_zone) { 1348 pr_err("no package domain found, unknown topology!\n"); 1349 return -ENODEV; 1350 } 1351 /* now register domains as children of the socket/package */ 1352 for (rd = rp->domains; rd < rp->domains + rp->nr_domains; rd++) { 1353 struct powercap_zone *parent = rp->power_zone; 1354 1355 if (rd->id == RAPL_DOMAIN_PACKAGE) 1356 continue; 1357 if (rd->id == RAPL_DOMAIN_PLATFORM) 1358 parent = NULL; 1359 /* number of power limits per domain varies */ 1360 nr_pl = find_nr_power_limit(rd); 1361 power_zone = powercap_register_zone(&rd->power_zone, 1362 rp->priv->control_type, 1363 rd->name, parent, 1364 &zone_ops[rd->id], nr_pl, 1365 &constraint_ops); 1366 1367 if (IS_ERR(power_zone)) { 1368 pr_debug("failed to register power_zone, %s:%s\n", 1369 rp->name, rd->name); 1370 ret = PTR_ERR(power_zone); 1371 goto err_cleanup; 1372 } 1373 } 1374 return 0; 1375 1376 err_cleanup: 1377 /* 1378 * Clean up previously initialized domains within the package if we 1379 * failed after the first domain setup. 1380 */ 1381 while (--rd >= rp->domains) { 1382 pr_debug("unregister %s domain %s\n", rp->name, rd->name); 1383 powercap_unregister_zone(rp->priv->control_type, 1384 &rd->power_zone); 1385 } 1386 1387 return ret; 1388 } 1389 1390 static int rapl_check_domain(int domain, struct rapl_package *rp) 1391 { 1392 struct reg_action ra; 1393 1394 switch (domain) { 1395 case RAPL_DOMAIN_PACKAGE: 1396 case RAPL_DOMAIN_PP0: 1397 case RAPL_DOMAIN_PP1: 1398 case RAPL_DOMAIN_DRAM: 1399 case RAPL_DOMAIN_PLATFORM: 1400 ra.reg = rp->priv->regs[domain][RAPL_DOMAIN_REG_STATUS]; 1401 break; 1402 default: 1403 pr_err("invalid domain id %d\n", domain); 1404 return -EINVAL; 1405 } 1406 /* make sure domain counters are available and contains non-zero 1407 * values, otherwise skip it. 1408 */ 1409 1410 ra.mask = ENERGY_STATUS_MASK; 1411 if (rp->priv->read_raw(get_rid(rp), &ra) || !ra.value) 1412 return -ENODEV; 1413 1414 return 0; 1415 } 1416 1417 /* 1418 * Get per domain energy/power/time unit. 1419 * RAPL Interfaces without per domain unit register will use the package 1420 * scope unit register to set per domain units. 1421 */ 1422 static int rapl_get_domain_unit(struct rapl_domain *rd) 1423 { 1424 struct rapl_defaults *defaults = get_defaults(rd->rp); 1425 int ret; 1426 1427 if (!rd->regs[RAPL_DOMAIN_REG_UNIT].val) { 1428 if (!rd->rp->priv->reg_unit.val) { 1429 pr_err("No valid Unit register found\n"); 1430 return -ENODEV; 1431 } 1432 rd->regs[RAPL_DOMAIN_REG_UNIT] = rd->rp->priv->reg_unit; 1433 } 1434 1435 if (!defaults->check_unit) { 1436 pr_err("missing .check_unit() callback\n"); 1437 return -ENODEV; 1438 } 1439 1440 ret = defaults->check_unit(rd); 1441 if (ret) 1442 return ret; 1443 1444 if (rd->id == RAPL_DOMAIN_DRAM && defaults->dram_domain_energy_unit) 1445 rd->energy_unit = defaults->dram_domain_energy_unit; 1446 if (rd->id == RAPL_DOMAIN_PLATFORM && defaults->psys_domain_energy_unit) 1447 rd->energy_unit = defaults->psys_domain_energy_unit; 1448 return 0; 1449 } 1450 1451 /* 1452 * Check if power limits are available. Two cases when they are not available: 1453 * 1. Locked by BIOS, in this case we still provide read-only access so that 1454 * users can see what limit is set by the BIOS. 1455 * 2. Some CPUs make some domains monitoring only which means PLx MSRs may not 1456 * exist at all. In this case, we do not show the constraints in powercap. 1457 * 1458 * Called after domains are detected and initialized. 1459 */ 1460 static void rapl_detect_powerlimit(struct rapl_domain *rd) 1461 { 1462 u64 val64; 1463 int i; 1464 1465 for (i = POWER_LIMIT1; i < NR_POWER_LIMITS; i++) { 1466 if (!rapl_read_pl_data(rd, i, PL_LOCK, false, &val64)) { 1467 if (val64) { 1468 rd->rpl[i].locked = true; 1469 pr_info("%s:%s:%s locked by BIOS\n", 1470 rd->rp->name, rd->name, pl_names[i]); 1471 } 1472 } 1473 1474 if (rapl_read_pl_data(rd, i, PL_LIMIT, false, &val64)) 1475 rd->rpl[i].name = NULL; 1476 } 1477 } 1478 1479 /* Detect active and valid domains for the given CPU, caller must 1480 * ensure the CPU belongs to the targeted package and CPU hotlug is disabled. 1481 */ 1482 static int rapl_detect_domains(struct rapl_package *rp) 1483 { 1484 struct rapl_domain *rd; 1485 int i; 1486 1487 for (i = 0; i < RAPL_DOMAIN_MAX; i++) { 1488 /* use physical package id to read counters */ 1489 if (!rapl_check_domain(i, rp)) { 1490 rp->domain_map |= 1 << i; 1491 pr_info("Found RAPL domain %s\n", rapl_domain_names[i]); 1492 } 1493 } 1494 rp->nr_domains = bitmap_weight(&rp->domain_map, RAPL_DOMAIN_MAX); 1495 if (!rp->nr_domains) { 1496 pr_debug("no valid rapl domains found in %s\n", rp->name); 1497 return -ENODEV; 1498 } 1499 pr_debug("found %d domains on %s\n", rp->nr_domains, rp->name); 1500 1501 rp->domains = kcalloc(rp->nr_domains, sizeof(struct rapl_domain), 1502 GFP_KERNEL); 1503 if (!rp->domains) 1504 return -ENOMEM; 1505 1506 rapl_init_domains(rp); 1507 1508 for (rd = rp->domains; rd < rp->domains + rp->nr_domains; rd++) { 1509 rapl_get_domain_unit(rd); 1510 rapl_detect_powerlimit(rd); 1511 } 1512 1513 return 0; 1514 } 1515 1516 #ifdef CONFIG_PERF_EVENTS 1517 1518 /* 1519 * Support for RAPL PMU 1520 * 1521 * Register a PMU if any of the registered RAPL Packages have the requirement 1522 * of exposing its energy counters via Perf PMU. 1523 * 1524 * PMU Name: 1525 * power 1526 * 1527 * Events: 1528 * Name Event id RAPL Domain 1529 * energy_cores 0x01 RAPL_DOMAIN_PP0 1530 * energy_pkg 0x02 RAPL_DOMAIN_PACKAGE 1531 * energy_ram 0x03 RAPL_DOMAIN_DRAM 1532 * energy_gpu 0x04 RAPL_DOMAIN_PP1 1533 * energy_psys 0x05 RAPL_DOMAIN_PLATFORM 1534 * 1535 * Unit: 1536 * Joules 1537 * 1538 * Scale: 1539 * 2.3283064365386962890625e-10 1540 * The same RAPL domain in different RAPL Packages may have different 1541 * energy units. Use 2.3283064365386962890625e-10 (2^-32) Joules as 1542 * the fixed unit for all energy counters, and covert each hardware 1543 * counter increase to N times of PMU event counter increases. 1544 * 1545 * This is fully compatible with the current MSR RAPL PMU. This means that 1546 * userspace programs like turbostat can use the same code to handle RAPL Perf 1547 * PMU, no matter what RAPL Interface driver (MSR/TPMI, etc) is running 1548 * underlying on the platform. 1549 * 1550 * Note that RAPL Packages can be probed/removed dynamically, and the events 1551 * supported by each TPMI RAPL device can be different. Thus the RAPL PMU 1552 * support is done on demand, which means 1553 * 1. PMU is registered only if it is needed by a RAPL Package. PMU events for 1554 * unsupported counters are not exposed. 1555 * 2. PMU is unregistered and registered when a new RAPL Package is probed and 1556 * supports new counters that are not supported by current PMU. 1557 * 3. PMU is unregistered when all registered RAPL Packages don't need PMU. 1558 */ 1559 1560 struct rapl_pmu { 1561 struct pmu pmu; /* Perf PMU structure */ 1562 u64 timer_ms; /* Maximum expiration time to avoid counter overflow */ 1563 unsigned long domain_map; /* Events supported by current registered PMU */ 1564 bool registered; /* Whether the PMU has been registered or not */ 1565 }; 1566 1567 static struct rapl_pmu rapl_pmu; 1568 1569 /* PMU helpers */ 1570 1571 static int get_pmu_cpu(struct rapl_package *rp) 1572 { 1573 int cpu; 1574 1575 if (!rp->has_pmu) 1576 return nr_cpu_ids; 1577 1578 /* Only TPMI RAPL is supported for now */ 1579 if (rp->priv->type != RAPL_IF_TPMI) 1580 return nr_cpu_ids; 1581 1582 /* TPMI RAPL uses any CPU in the package for PMU */ 1583 for_each_online_cpu(cpu) 1584 if (topology_physical_package_id(cpu) == rp->id) 1585 return cpu; 1586 1587 return nr_cpu_ids; 1588 } 1589 1590 static bool is_rp_pmu_cpu(struct rapl_package *rp, int cpu) 1591 { 1592 if (!rp->has_pmu) 1593 return false; 1594 1595 /* Only TPMI RAPL is supported for now */ 1596 if (rp->priv->type != RAPL_IF_TPMI) 1597 return false; 1598 1599 /* TPMI RAPL uses any CPU in the package for PMU */ 1600 return topology_physical_package_id(cpu) == rp->id; 1601 } 1602 1603 static struct rapl_package_pmu_data *event_to_pmu_data(struct perf_event *event) 1604 { 1605 struct rapl_package *rp = event->pmu_private; 1606 1607 return &rp->pmu_data; 1608 } 1609 1610 /* PMU event callbacks */ 1611 1612 static u64 event_read_counter(struct perf_event *event) 1613 { 1614 struct rapl_package *rp = event->pmu_private; 1615 u64 val; 1616 int ret; 1617 1618 /* Return 0 for unsupported events */ 1619 if (event->hw.idx < 0) 1620 return 0; 1621 1622 ret = rapl_read_data_raw(&rp->domains[event->hw.idx], ENERGY_COUNTER, false, &val); 1623 1624 /* Return 0 for failed read */ 1625 if (ret) 1626 return 0; 1627 1628 return val; 1629 } 1630 1631 static void __rapl_pmu_event_start(struct perf_event *event) 1632 { 1633 struct rapl_package_pmu_data *data = event_to_pmu_data(event); 1634 1635 if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED))) 1636 return; 1637 1638 event->hw.state = 0; 1639 1640 list_add_tail(&event->active_entry, &data->active_list); 1641 1642 local64_set(&event->hw.prev_count, event_read_counter(event)); 1643 if (++data->n_active == 1) 1644 hrtimer_start(&data->hrtimer, data->timer_interval, 1645 HRTIMER_MODE_REL_PINNED); 1646 } 1647 1648 static void rapl_pmu_event_start(struct perf_event *event, int mode) 1649 { 1650 struct rapl_package_pmu_data *data = event_to_pmu_data(event); 1651 unsigned long flags; 1652 1653 raw_spin_lock_irqsave(&data->lock, flags); 1654 __rapl_pmu_event_start(event); 1655 raw_spin_unlock_irqrestore(&data->lock, flags); 1656 } 1657 1658 static u64 rapl_event_update(struct perf_event *event) 1659 { 1660 struct hw_perf_event *hwc = &event->hw; 1661 struct rapl_package_pmu_data *data = event_to_pmu_data(event); 1662 u64 prev_raw_count, new_raw_count; 1663 s64 delta, sdelta; 1664 1665 /* 1666 * Follow the generic code to drain hwc->prev_count. 1667 * The loop is not expected to run for multiple times. 1668 */ 1669 prev_raw_count = local64_read(&hwc->prev_count); 1670 do { 1671 new_raw_count = event_read_counter(event); 1672 } while (!local64_try_cmpxchg(&hwc->prev_count, 1673 &prev_raw_count, new_raw_count)); 1674 1675 1676 /* 1677 * Now we have the new raw value and have updated the prev 1678 * timestamp already. We can now calculate the elapsed delta 1679 * (event-)time and add that to the generic event. 1680 */ 1681 delta = new_raw_count - prev_raw_count; 1682 1683 /* 1684 * Scale delta to smallest unit (2^-32) 1685 * users must then scale back: count * 1/(1e9*2^32) to get Joules 1686 * or use ldexp(count, -32). 1687 * Watts = Joules/Time delta 1688 */ 1689 sdelta = delta * data->scale[event->hw.flags]; 1690 1691 local64_add(sdelta, &event->count); 1692 1693 return new_raw_count; 1694 } 1695 1696 static void rapl_pmu_event_stop(struct perf_event *event, int mode) 1697 { 1698 struct rapl_package_pmu_data *data = event_to_pmu_data(event); 1699 struct hw_perf_event *hwc = &event->hw; 1700 unsigned long flags; 1701 1702 raw_spin_lock_irqsave(&data->lock, flags); 1703 1704 /* Mark event as deactivated and stopped */ 1705 if (!(hwc->state & PERF_HES_STOPPED)) { 1706 WARN_ON_ONCE(data->n_active <= 0); 1707 if (--data->n_active == 0) 1708 hrtimer_cancel(&data->hrtimer); 1709 1710 list_del(&event->active_entry); 1711 1712 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED); 1713 hwc->state |= PERF_HES_STOPPED; 1714 } 1715 1716 /* Check if update of sw counter is necessary */ 1717 if ((mode & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) { 1718 /* 1719 * Drain the remaining delta count out of a event 1720 * that we are disabling: 1721 */ 1722 rapl_event_update(event); 1723 hwc->state |= PERF_HES_UPTODATE; 1724 } 1725 1726 raw_spin_unlock_irqrestore(&data->lock, flags); 1727 } 1728 1729 static int rapl_pmu_event_add(struct perf_event *event, int mode) 1730 { 1731 struct rapl_package_pmu_data *data = event_to_pmu_data(event); 1732 struct hw_perf_event *hwc = &event->hw; 1733 unsigned long flags; 1734 1735 raw_spin_lock_irqsave(&data->lock, flags); 1736 1737 hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED; 1738 1739 if (mode & PERF_EF_START) 1740 __rapl_pmu_event_start(event); 1741 1742 raw_spin_unlock_irqrestore(&data->lock, flags); 1743 1744 return 0; 1745 } 1746 1747 static void rapl_pmu_event_del(struct perf_event *event, int flags) 1748 { 1749 rapl_pmu_event_stop(event, PERF_EF_UPDATE); 1750 } 1751 1752 /* RAPL PMU event ids, same as shown in sysfs */ 1753 enum perf_rapl_events { 1754 PERF_RAPL_PP0 = 1, /* all cores */ 1755 PERF_RAPL_PKG, /* entire package */ 1756 PERF_RAPL_RAM, /* DRAM */ 1757 PERF_RAPL_PP1, /* gpu */ 1758 PERF_RAPL_PSYS, /* psys */ 1759 PERF_RAPL_MAX 1760 }; 1761 #define RAPL_EVENT_MASK GENMASK(7, 0) 1762 1763 static const int event_to_domain[PERF_RAPL_MAX] = { 1764 [PERF_RAPL_PP0] = RAPL_DOMAIN_PP0, 1765 [PERF_RAPL_PKG] = RAPL_DOMAIN_PACKAGE, 1766 [PERF_RAPL_RAM] = RAPL_DOMAIN_DRAM, 1767 [PERF_RAPL_PP1] = RAPL_DOMAIN_PP1, 1768 [PERF_RAPL_PSYS] = RAPL_DOMAIN_PLATFORM, 1769 }; 1770 1771 static int rapl_pmu_event_init(struct perf_event *event) 1772 { 1773 struct rapl_package *pos, *rp = NULL; 1774 u64 cfg = event->attr.config & RAPL_EVENT_MASK; 1775 int domain, idx; 1776 1777 /* Only look at RAPL events */ 1778 if (event->attr.type != event->pmu->type) 1779 return -ENOENT; 1780 1781 /* Check for supported events only */ 1782 if (!cfg || cfg >= PERF_RAPL_MAX) 1783 return -EINVAL; 1784 1785 if (event->cpu < 0) 1786 return -EINVAL; 1787 1788 /* Find out which Package the event belongs to */ 1789 list_for_each_entry(pos, &rapl_packages, plist) { 1790 if (is_rp_pmu_cpu(pos, event->cpu)) { 1791 rp = pos; 1792 break; 1793 } 1794 } 1795 if (!rp) 1796 return -ENODEV; 1797 1798 /* Find out which RAPL Domain the event belongs to */ 1799 domain = event_to_domain[cfg]; 1800 1801 event->event_caps |= PERF_EV_CAP_READ_ACTIVE_PKG; 1802 event->pmu_private = rp; /* Which package */ 1803 event->hw.flags = domain; /* Which domain */ 1804 1805 event->hw.idx = -1; 1806 /* Find out the index in rp->domains[] to get domain pointer */ 1807 for (idx = 0; idx < rp->nr_domains; idx++) { 1808 if (rp->domains[idx].id == domain) { 1809 event->hw.idx = idx; 1810 break; 1811 } 1812 } 1813 1814 return 0; 1815 } 1816 1817 static void rapl_pmu_event_read(struct perf_event *event) 1818 { 1819 rapl_event_update(event); 1820 } 1821 1822 static enum hrtimer_restart rapl_hrtimer_handle(struct hrtimer *hrtimer) 1823 { 1824 struct rapl_package_pmu_data *data = 1825 container_of(hrtimer, struct rapl_package_pmu_data, hrtimer); 1826 struct perf_event *event; 1827 unsigned long flags; 1828 1829 if (!data->n_active) 1830 return HRTIMER_NORESTART; 1831 1832 raw_spin_lock_irqsave(&data->lock, flags); 1833 1834 list_for_each_entry(event, &data->active_list, active_entry) 1835 rapl_event_update(event); 1836 1837 raw_spin_unlock_irqrestore(&data->lock, flags); 1838 1839 hrtimer_forward_now(hrtimer, data->timer_interval); 1840 1841 return HRTIMER_RESTART; 1842 } 1843 1844 /* PMU sysfs attributes */ 1845 1846 /* 1847 * There are no default events, but we need to create "events" group (with 1848 * empty attrs) before updating it with detected events. 1849 */ 1850 static struct attribute *attrs_empty[] = { 1851 NULL, 1852 }; 1853 1854 static struct attribute_group pmu_events_group = { 1855 .name = "events", 1856 .attrs = attrs_empty, 1857 }; 1858 1859 static ssize_t cpumask_show(struct device *dev, 1860 struct device_attribute *attr, char *buf) 1861 { 1862 struct rapl_package *rp; 1863 cpumask_var_t cpu_mask; 1864 int cpu; 1865 int ret; 1866 1867 if (!alloc_cpumask_var(&cpu_mask, GFP_KERNEL)) 1868 return -ENOMEM; 1869 1870 cpus_read_lock(); 1871 1872 cpumask_clear(cpu_mask); 1873 1874 /* Choose a cpu for each RAPL Package */ 1875 list_for_each_entry(rp, &rapl_packages, plist) { 1876 cpu = get_pmu_cpu(rp); 1877 if (cpu < nr_cpu_ids) 1878 cpumask_set_cpu(cpu, cpu_mask); 1879 } 1880 cpus_read_unlock(); 1881 1882 ret = cpumap_print_to_pagebuf(true, buf, cpu_mask); 1883 1884 free_cpumask_var(cpu_mask); 1885 1886 return ret; 1887 } 1888 1889 static DEVICE_ATTR_RO(cpumask); 1890 1891 static struct attribute *pmu_cpumask_attrs[] = { 1892 &dev_attr_cpumask.attr, 1893 NULL 1894 }; 1895 1896 static struct attribute_group pmu_cpumask_group = { 1897 .attrs = pmu_cpumask_attrs, 1898 }; 1899 1900 PMU_FORMAT_ATTR(event, "config:0-7"); 1901 static struct attribute *pmu_format_attr[] = { 1902 &format_attr_event.attr, 1903 NULL 1904 }; 1905 1906 static struct attribute_group pmu_format_group = { 1907 .name = "format", 1908 .attrs = pmu_format_attr, 1909 }; 1910 1911 static const struct attribute_group *pmu_attr_groups[] = { 1912 &pmu_events_group, 1913 &pmu_cpumask_group, 1914 &pmu_format_group, 1915 NULL 1916 }; 1917 1918 #define RAPL_EVENT_ATTR_STR(_name, v, str) \ 1919 static struct perf_pmu_events_attr event_attr_##v = { \ 1920 .attr = __ATTR(_name, 0444, perf_event_sysfs_show, NULL), \ 1921 .event_str = str, \ 1922 } 1923 1924 RAPL_EVENT_ATTR_STR(energy-cores, rapl_cores, "event=0x01"); 1925 RAPL_EVENT_ATTR_STR(energy-pkg, rapl_pkg, "event=0x02"); 1926 RAPL_EVENT_ATTR_STR(energy-ram, rapl_ram, "event=0x03"); 1927 RAPL_EVENT_ATTR_STR(energy-gpu, rapl_gpu, "event=0x04"); 1928 RAPL_EVENT_ATTR_STR(energy-psys, rapl_psys, "event=0x05"); 1929 1930 RAPL_EVENT_ATTR_STR(energy-cores.unit, rapl_unit_cores, "Joules"); 1931 RAPL_EVENT_ATTR_STR(energy-pkg.unit, rapl_unit_pkg, "Joules"); 1932 RAPL_EVENT_ATTR_STR(energy-ram.unit, rapl_unit_ram, "Joules"); 1933 RAPL_EVENT_ATTR_STR(energy-gpu.unit, rapl_unit_gpu, "Joules"); 1934 RAPL_EVENT_ATTR_STR(energy-psys.unit, rapl_unit_psys, "Joules"); 1935 1936 RAPL_EVENT_ATTR_STR(energy-cores.scale, rapl_scale_cores, "2.3283064365386962890625e-10"); 1937 RAPL_EVENT_ATTR_STR(energy-pkg.scale, rapl_scale_pkg, "2.3283064365386962890625e-10"); 1938 RAPL_EVENT_ATTR_STR(energy-ram.scale, rapl_scale_ram, "2.3283064365386962890625e-10"); 1939 RAPL_EVENT_ATTR_STR(energy-gpu.scale, rapl_scale_gpu, "2.3283064365386962890625e-10"); 1940 RAPL_EVENT_ATTR_STR(energy-psys.scale, rapl_scale_psys, "2.3283064365386962890625e-10"); 1941 1942 #define RAPL_EVENT_GROUP(_name, domain) \ 1943 static struct attribute *pmu_attr_##_name[] = { \ 1944 &event_attr_rapl_##_name.attr.attr, \ 1945 &event_attr_rapl_unit_##_name.attr.attr, \ 1946 &event_attr_rapl_scale_##_name.attr.attr, \ 1947 NULL \ 1948 }; \ 1949 static umode_t is_visible_##_name(struct kobject *kobj, struct attribute *attr, int event) \ 1950 { \ 1951 return rapl_pmu.domain_map & BIT(domain) ? attr->mode : 0; \ 1952 } \ 1953 static struct attribute_group pmu_group_##_name = { \ 1954 .name = "events", \ 1955 .attrs = pmu_attr_##_name, \ 1956 .is_visible = is_visible_##_name, \ 1957 } 1958 1959 RAPL_EVENT_GROUP(cores, RAPL_DOMAIN_PP0); 1960 RAPL_EVENT_GROUP(pkg, RAPL_DOMAIN_PACKAGE); 1961 RAPL_EVENT_GROUP(ram, RAPL_DOMAIN_DRAM); 1962 RAPL_EVENT_GROUP(gpu, RAPL_DOMAIN_PP1); 1963 RAPL_EVENT_GROUP(psys, RAPL_DOMAIN_PLATFORM); 1964 1965 static const struct attribute_group *pmu_attr_update[] = { 1966 &pmu_group_cores, 1967 &pmu_group_pkg, 1968 &pmu_group_ram, 1969 &pmu_group_gpu, 1970 &pmu_group_psys, 1971 NULL 1972 }; 1973 1974 static int rapl_pmu_update(struct rapl_package *rp) 1975 { 1976 int ret = 0; 1977 1978 /* Return if PMU already covers all events supported by current RAPL Package */ 1979 if (rapl_pmu.registered && !(rp->domain_map & (~rapl_pmu.domain_map))) 1980 goto end; 1981 1982 /* Unregister previous registered PMU */ 1983 if (rapl_pmu.registered) 1984 perf_pmu_unregister(&rapl_pmu.pmu); 1985 1986 rapl_pmu.registered = false; 1987 rapl_pmu.domain_map |= rp->domain_map; 1988 1989 memset(&rapl_pmu.pmu, 0, sizeof(struct pmu)); 1990 rapl_pmu.pmu.attr_groups = pmu_attr_groups; 1991 rapl_pmu.pmu.attr_update = pmu_attr_update; 1992 rapl_pmu.pmu.task_ctx_nr = perf_invalid_context; 1993 rapl_pmu.pmu.event_init = rapl_pmu_event_init; 1994 rapl_pmu.pmu.add = rapl_pmu_event_add; 1995 rapl_pmu.pmu.del = rapl_pmu_event_del; 1996 rapl_pmu.pmu.start = rapl_pmu_event_start; 1997 rapl_pmu.pmu.stop = rapl_pmu_event_stop; 1998 rapl_pmu.pmu.read = rapl_pmu_event_read; 1999 rapl_pmu.pmu.module = THIS_MODULE; 2000 rapl_pmu.pmu.capabilities = PERF_PMU_CAP_NO_EXCLUDE | PERF_PMU_CAP_NO_INTERRUPT; 2001 ret = perf_pmu_register(&rapl_pmu.pmu, "power", -1); 2002 if (ret) { 2003 pr_info("Failed to register PMU\n"); 2004 return ret; 2005 } 2006 2007 rapl_pmu.registered = true; 2008 end: 2009 rp->has_pmu = true; 2010 return ret; 2011 } 2012 2013 int rapl_package_add_pmu(struct rapl_package *rp) 2014 { 2015 struct rapl_package_pmu_data *data = &rp->pmu_data; 2016 int idx; 2017 2018 if (rp->has_pmu) 2019 return -EEXIST; 2020 2021 guard(cpus_read_lock)(); 2022 2023 for (idx = 0; idx < rp->nr_domains; idx++) { 2024 struct rapl_domain *rd = &rp->domains[idx]; 2025 int domain = rd->id; 2026 u64 val; 2027 2028 if (!test_bit(domain, &rp->domain_map)) 2029 continue; 2030 2031 /* 2032 * The RAPL PMU granularity is 2^-32 Joules 2033 * data->scale[]: times of 2^-32 Joules for each ENERGY COUNTER increase 2034 */ 2035 val = rd->energy_unit * (1ULL << 32); 2036 do_div(val, ENERGY_UNIT_SCALE * 1000000); 2037 data->scale[domain] = val; 2038 2039 if (!rapl_pmu.timer_ms) { 2040 struct rapl_primitive_info *rpi = get_rpi(rp, ENERGY_COUNTER); 2041 2042 /* 2043 * Calculate the timer rate: 2044 * Use reference of 200W for scaling the timeout to avoid counter 2045 * overflows. 2046 * 2047 * max_count = rpi->mask >> rpi->shift + 1 2048 * max_energy_pj = max_count * rd->energy_unit 2049 * max_time_sec = (max_energy_pj / 1000000000) / 200w 2050 * 2051 * rapl_pmu.timer_ms = max_time_sec * 1000 / 2 2052 */ 2053 val = (rpi->mask >> rpi->shift) + 1; 2054 val *= rd->energy_unit; 2055 do_div(val, 1000000 * 200 * 2); 2056 rapl_pmu.timer_ms = val; 2057 2058 pr_debug("%llu ms overflow timer\n", rapl_pmu.timer_ms); 2059 } 2060 2061 pr_debug("Domain %s: hw unit %lld * 2^-32 Joules\n", rd->name, data->scale[domain]); 2062 } 2063 2064 /* Initialize per package PMU data */ 2065 raw_spin_lock_init(&data->lock); 2066 INIT_LIST_HEAD(&data->active_list); 2067 data->timer_interval = ms_to_ktime(rapl_pmu.timer_ms); 2068 hrtimer_setup(&data->hrtimer, rapl_hrtimer_handle, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 2069 2070 return rapl_pmu_update(rp); 2071 } 2072 EXPORT_SYMBOL_GPL(rapl_package_add_pmu); 2073 2074 void rapl_package_remove_pmu(struct rapl_package *rp) 2075 { 2076 struct rapl_package *pos; 2077 2078 if (!rp->has_pmu) 2079 return; 2080 2081 guard(cpus_read_lock)(); 2082 2083 list_for_each_entry(pos, &rapl_packages, plist) { 2084 /* PMU is still needed */ 2085 if (pos->has_pmu && pos != rp) 2086 return; 2087 } 2088 2089 perf_pmu_unregister(&rapl_pmu.pmu); 2090 memset(&rapl_pmu, 0, sizeof(struct rapl_pmu)); 2091 } 2092 EXPORT_SYMBOL_GPL(rapl_package_remove_pmu); 2093 #endif 2094 2095 /* called from CPU hotplug notifier, hotplug lock held */ 2096 void rapl_remove_package_cpuslocked(struct rapl_package *rp) 2097 { 2098 struct rapl_domain *rd, *rd_package = NULL; 2099 2100 package_power_limit_irq_restore(rp); 2101 2102 for (rd = rp->domains; rd < rp->domains + rp->nr_domains; rd++) { 2103 int i; 2104 2105 for (i = POWER_LIMIT1; i < NR_POWER_LIMITS; i++) { 2106 rapl_write_pl_data(rd, i, PL_ENABLE, 0); 2107 rapl_write_pl_data(rd, i, PL_CLAMP, 0); 2108 } 2109 2110 if (rd->id == RAPL_DOMAIN_PACKAGE) { 2111 rd_package = rd; 2112 continue; 2113 } 2114 pr_debug("remove package, undo power limit on %s: %s\n", 2115 rp->name, rd->name); 2116 powercap_unregister_zone(rp->priv->control_type, 2117 &rd->power_zone); 2118 } 2119 /* do parent zone last */ 2120 powercap_unregister_zone(rp->priv->control_type, 2121 &rd_package->power_zone); 2122 list_del(&rp->plist); 2123 kfree(rp); 2124 } 2125 EXPORT_SYMBOL_GPL(rapl_remove_package_cpuslocked); 2126 2127 void rapl_remove_package(struct rapl_package *rp) 2128 { 2129 guard(cpus_read_lock)(); 2130 rapl_remove_package_cpuslocked(rp); 2131 } 2132 EXPORT_SYMBOL_GPL(rapl_remove_package); 2133 2134 /* 2135 * RAPL Package energy counter scope: 2136 * 1. AMD/HYGON platforms use per-PKG package energy counter 2137 * 2. For Intel platforms 2138 * 2.1 CLX-AP platform has per-DIE package energy counter 2139 * 2.2 Other platforms that uses MSR RAPL are single die systems so the 2140 * package energy counter can be considered as per-PKG/per-DIE, 2141 * here it is considered as per-DIE. 2142 * 2.3 New platforms that use TPMI RAPL doesn't care about the 2143 * scope because they are not MSR/CPU based. 2144 */ 2145 #define rapl_msrs_are_pkg_scope() \ 2146 (boot_cpu_data.x86_vendor == X86_VENDOR_AMD || \ 2147 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) 2148 2149 /* caller to ensure CPU hotplug lock is held */ 2150 struct rapl_package *rapl_find_package_domain_cpuslocked(int id, struct rapl_if_priv *priv, 2151 bool id_is_cpu) 2152 { 2153 struct rapl_package *rp; 2154 int uid; 2155 2156 if (id_is_cpu) { 2157 uid = rapl_msrs_are_pkg_scope() ? 2158 topology_physical_package_id(id) : topology_logical_die_id(id); 2159 if (uid < 0) { 2160 pr_err("topology_logical_(package/die)_id() returned a negative value"); 2161 return NULL; 2162 } 2163 } 2164 else 2165 uid = id; 2166 2167 list_for_each_entry(rp, &rapl_packages, plist) { 2168 if (rp->id == uid 2169 && rp->priv->control_type == priv->control_type) 2170 return rp; 2171 } 2172 2173 return NULL; 2174 } 2175 EXPORT_SYMBOL_GPL(rapl_find_package_domain_cpuslocked); 2176 2177 struct rapl_package *rapl_find_package_domain(int id, struct rapl_if_priv *priv, bool id_is_cpu) 2178 { 2179 guard(cpus_read_lock)(); 2180 return rapl_find_package_domain_cpuslocked(id, priv, id_is_cpu); 2181 } 2182 EXPORT_SYMBOL_GPL(rapl_find_package_domain); 2183 2184 /* called from CPU hotplug notifier, hotplug lock held */ 2185 struct rapl_package *rapl_add_package_cpuslocked(int id, struct rapl_if_priv *priv, bool id_is_cpu) 2186 { 2187 struct rapl_package *rp; 2188 int ret; 2189 2190 rp = kzalloc(sizeof(struct rapl_package), GFP_KERNEL); 2191 if (!rp) 2192 return ERR_PTR(-ENOMEM); 2193 2194 if (id_is_cpu) { 2195 rp->id = rapl_msrs_are_pkg_scope() ? 2196 topology_physical_package_id(id) : topology_logical_die_id(id); 2197 if ((int)(rp->id) < 0) { 2198 pr_err("topology_logical_(package/die)_id() returned a negative value"); 2199 return ERR_PTR(-EINVAL); 2200 } 2201 rp->lead_cpu = id; 2202 if (!rapl_msrs_are_pkg_scope() && topology_max_dies_per_package() > 1) 2203 snprintf(rp->name, PACKAGE_DOMAIN_NAME_LENGTH, "package-%d-die-%d", 2204 topology_physical_package_id(id), topology_die_id(id)); 2205 else 2206 snprintf(rp->name, PACKAGE_DOMAIN_NAME_LENGTH, "package-%d", 2207 topology_physical_package_id(id)); 2208 } else { 2209 rp->id = id; 2210 rp->lead_cpu = -1; 2211 snprintf(rp->name, PACKAGE_DOMAIN_NAME_LENGTH, "package-%d", id); 2212 } 2213 2214 rp->priv = priv; 2215 ret = rapl_config(rp); 2216 if (ret) 2217 goto err_free_package; 2218 2219 /* check if the package contains valid domains */ 2220 if (rapl_detect_domains(rp)) { 2221 ret = -ENODEV; 2222 goto err_free_package; 2223 } 2224 ret = rapl_package_register_powercap(rp); 2225 if (!ret) { 2226 INIT_LIST_HEAD(&rp->plist); 2227 list_add(&rp->plist, &rapl_packages); 2228 return rp; 2229 } 2230 2231 err_free_package: 2232 kfree(rp->domains); 2233 kfree(rp); 2234 return ERR_PTR(ret); 2235 } 2236 EXPORT_SYMBOL_GPL(rapl_add_package_cpuslocked); 2237 2238 struct rapl_package *rapl_add_package(int id, struct rapl_if_priv *priv, bool id_is_cpu) 2239 { 2240 guard(cpus_read_lock)(); 2241 return rapl_add_package_cpuslocked(id, priv, id_is_cpu); 2242 } 2243 EXPORT_SYMBOL_GPL(rapl_add_package); 2244 2245 static void power_limit_state_save(void) 2246 { 2247 struct rapl_package *rp; 2248 struct rapl_domain *rd; 2249 int ret, i; 2250 2251 cpus_read_lock(); 2252 list_for_each_entry(rp, &rapl_packages, plist) { 2253 if (!rp->power_zone) 2254 continue; 2255 rd = power_zone_to_rapl_domain(rp->power_zone); 2256 for (i = POWER_LIMIT1; i < NR_POWER_LIMITS; i++) { 2257 ret = rapl_read_pl_data(rd, i, PL_LIMIT, true, 2258 &rd->rpl[i].last_power_limit); 2259 if (ret) 2260 rd->rpl[i].last_power_limit = 0; 2261 } 2262 } 2263 cpus_read_unlock(); 2264 } 2265 2266 static void power_limit_state_restore(void) 2267 { 2268 struct rapl_package *rp; 2269 struct rapl_domain *rd; 2270 int i; 2271 2272 cpus_read_lock(); 2273 list_for_each_entry(rp, &rapl_packages, plist) { 2274 if (!rp->power_zone) 2275 continue; 2276 rd = power_zone_to_rapl_domain(rp->power_zone); 2277 for (i = POWER_LIMIT1; i < NR_POWER_LIMITS; i++) 2278 if (rd->rpl[i].last_power_limit) 2279 rapl_write_pl_data(rd, i, PL_LIMIT, 2280 rd->rpl[i].last_power_limit); 2281 } 2282 cpus_read_unlock(); 2283 } 2284 2285 static int rapl_pm_callback(struct notifier_block *nb, 2286 unsigned long mode, void *_unused) 2287 { 2288 switch (mode) { 2289 case PM_SUSPEND_PREPARE: 2290 power_limit_state_save(); 2291 break; 2292 case PM_POST_SUSPEND: 2293 power_limit_state_restore(); 2294 break; 2295 } 2296 return NOTIFY_OK; 2297 } 2298 2299 static struct notifier_block rapl_pm_notifier = { 2300 .notifier_call = rapl_pm_callback, 2301 }; 2302 2303 static struct platform_device *rapl_msr_platdev; 2304 2305 static int __init rapl_init(void) 2306 { 2307 const struct x86_cpu_id *id; 2308 int ret; 2309 2310 id = x86_match_cpu(rapl_ids); 2311 if (id) { 2312 defaults_msr = (struct rapl_defaults *)id->driver_data; 2313 2314 rapl_msr_platdev = platform_device_alloc("intel_rapl_msr", 0); 2315 if (!rapl_msr_platdev) 2316 return -ENOMEM; 2317 2318 ret = platform_device_add(rapl_msr_platdev); 2319 if (ret) { 2320 platform_device_put(rapl_msr_platdev); 2321 return ret; 2322 } 2323 } 2324 2325 ret = register_pm_notifier(&rapl_pm_notifier); 2326 if (ret && rapl_msr_platdev) { 2327 platform_device_del(rapl_msr_platdev); 2328 platform_device_put(rapl_msr_platdev); 2329 } 2330 2331 return ret; 2332 } 2333 2334 static void __exit rapl_exit(void) 2335 { 2336 platform_device_unregister(rapl_msr_platdev); 2337 unregister_pm_notifier(&rapl_pm_notifier); 2338 } 2339 2340 fs_initcall(rapl_init); 2341 module_exit(rapl_exit); 2342 2343 MODULE_DESCRIPTION("Intel Runtime Average Power Limit (RAPL) common code"); 2344 MODULE_AUTHOR("Jacob Pan <jacob.jun.pan@intel.com>"); 2345 MODULE_LICENSE("GPL v2"); 2346