1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * AMD HSMP Platform Driver 4 * Copyright (c) 2024, AMD. 5 * All Rights Reserved. 6 * 7 * This file provides platform device implementations. 8 */ 9 10 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 11 12 #include <asm/amd/hsmp.h> 13 14 #include <linux/acpi.h> 15 #include <linux/build_bug.h> 16 #include <linux/device.h> 17 #include <linux/module.h> 18 #include <linux/pci.h> 19 #include <linux/platform_device.h> 20 #include <linux/sysfs.h> 21 22 #include <asm/amd/node.h> 23 24 #include "hsmp.h" 25 26 #define DRIVER_NAME "amd_hsmp" 27 28 /* 29 * To access specific HSMP mailbox register, s/w writes the SMN address of HSMP mailbox 30 * register into the SMN_INDEX register, and reads/writes the SMN_DATA reg. 31 * Below are required SMN address for HSMP Mailbox register offsets in SMU address space 32 */ 33 #define SMN_HSMP_BASE 0x3B00000 34 #define SMN_HSMP_MSG_ID 0x0010534 35 #define SMN_HSMP_MSG_ID_F1A_M0H 0x0010934 36 #define SMN_HSMP_MSG_RESP 0x0010980 37 #define SMN_HSMP_MSG_DATA 0x00109E0 38 39 static struct hsmp_plat_device *hsmp_pdev; 40 41 static int amd_hsmp_pci_rdwr(struct hsmp_socket *sock, u32 offset, 42 u32 *value, bool write) 43 { 44 return amd_smn_hsmp_rdwr(sock->sock_ind, sock->mbinfo.base_addr + offset, value, write); 45 } 46 47 static ssize_t hsmp_metric_tbl_plat_read(struct file *filp, struct kobject *kobj, 48 const struct bin_attribute *bin_attr, char *buf, 49 loff_t off, size_t count) 50 { 51 struct hsmp_socket *sock; 52 u16 sock_ind; 53 54 sock_ind = (uintptr_t)bin_attr->private; 55 if (sock_ind >= hsmp_pdev->num_sockets) 56 return -EINVAL; 57 58 sock = &hsmp_pdev->sock[sock_ind]; 59 60 return hsmp_metric_tbl_read(sock, buf, count); 61 } 62 63 static umode_t hsmp_is_sock_attr_visible(struct kobject *kobj, 64 const struct bin_attribute *battr, int id) 65 { 66 u16 sock_ind; 67 68 sock_ind = (uintptr_t)battr->private; 69 70 if (id == 0 && sock_ind >= hsmp_pdev->num_sockets) 71 return SYSFS_GROUP_INVISIBLE; 72 73 if (hsmp_pdev->proto_ver == HSMP_PROTO_VER6) 74 return battr->attr.mode; 75 76 return 0; 77 } 78 79 /* 80 * AMD supports maximum of 8 sockets in a system. 81 * Static array of 8 + 1(for NULL) elements is created below 82 * to create sysfs groups for sockets. 83 * is_bin_visible function is used to show / hide the necessary groups. 84 * 85 * Validate the maximum number against MAX_AMD_NUM_NODES. If this changes, 86 * then the attributes and groups below must be adjusted. 87 */ 88 static_assert(MAX_AMD_NUM_NODES == 8); 89 90 #define HSMP_BIN_ATTR(index, _list) \ 91 static const struct bin_attribute attr##index = { \ 92 .attr = { .name = HSMP_METRICS_TABLE_NAME, .mode = 0444}, \ 93 .private = (void *)index, \ 94 .read_new = hsmp_metric_tbl_plat_read, \ 95 .size = sizeof(struct hsmp_metric_table), \ 96 }; \ 97 static const struct bin_attribute _list[] = { \ 98 &attr##index, \ 99 NULL \ 100 } 101 102 HSMP_BIN_ATTR(0, *sock0_attr_list); 103 HSMP_BIN_ATTR(1, *sock1_attr_list); 104 HSMP_BIN_ATTR(2, *sock2_attr_list); 105 HSMP_BIN_ATTR(3, *sock3_attr_list); 106 HSMP_BIN_ATTR(4, *sock4_attr_list); 107 HSMP_BIN_ATTR(5, *sock5_attr_list); 108 HSMP_BIN_ATTR(6, *sock6_attr_list); 109 HSMP_BIN_ATTR(7, *sock7_attr_list); 110 111 #define HSMP_BIN_ATTR_GRP(index, _list, _name) \ 112 static const struct attribute_group sock##index##_attr_grp = { \ 113 .bin_attrs_new = _list, \ 114 .is_bin_visible = hsmp_is_sock_attr_visible, \ 115 .name = #_name, \ 116 } 117 118 HSMP_BIN_ATTR_GRP(0, sock0_attr_list, socket0); 119 HSMP_BIN_ATTR_GRP(1, sock1_attr_list, socket1); 120 HSMP_BIN_ATTR_GRP(2, sock2_attr_list, socket2); 121 HSMP_BIN_ATTR_GRP(3, sock3_attr_list, socket3); 122 HSMP_BIN_ATTR_GRP(4, sock4_attr_list, socket4); 123 HSMP_BIN_ATTR_GRP(5, sock5_attr_list, socket5); 124 HSMP_BIN_ATTR_GRP(6, sock6_attr_list, socket6); 125 HSMP_BIN_ATTR_GRP(7, sock7_attr_list, socket7); 126 127 static const struct attribute_group *hsmp_groups[] = { 128 &sock0_attr_grp, 129 &sock1_attr_grp, 130 &sock2_attr_grp, 131 &sock3_attr_grp, 132 &sock4_attr_grp, 133 &sock5_attr_grp, 134 &sock6_attr_grp, 135 &sock7_attr_grp, 136 NULL 137 }; 138 139 static inline bool is_f1a_m0h(void) 140 { 141 if (boot_cpu_data.x86 == 0x1A && boot_cpu_data.x86_model <= 0x0F) 142 return true; 143 144 return false; 145 } 146 147 static int init_platform_device(struct device *dev) 148 { 149 struct hsmp_socket *sock; 150 int ret, i; 151 152 for (i = 0; i < hsmp_pdev->num_sockets; i++) { 153 sock = &hsmp_pdev->sock[i]; 154 sock->sock_ind = i; 155 sock->dev = dev; 156 sock->mbinfo.base_addr = SMN_HSMP_BASE; 157 sock->amd_hsmp_rdwr = amd_hsmp_pci_rdwr; 158 159 /* 160 * This is a transitional change from non-ACPI to ACPI, only 161 * family 0x1A, model 0x00 platform is supported for both ACPI and non-ACPI. 162 */ 163 if (is_f1a_m0h()) 164 sock->mbinfo.msg_id_off = SMN_HSMP_MSG_ID_F1A_M0H; 165 else 166 sock->mbinfo.msg_id_off = SMN_HSMP_MSG_ID; 167 168 sock->mbinfo.msg_resp_off = SMN_HSMP_MSG_RESP; 169 sock->mbinfo.msg_arg_off = SMN_HSMP_MSG_DATA; 170 sema_init(&sock->hsmp_sem, 1); 171 172 /* Test the hsmp interface on each socket */ 173 ret = hsmp_test(i, 0xDEADBEEF); 174 if (ret) { 175 dev_err(dev, "HSMP test message failed on Fam:%x model:%x\n", 176 boot_cpu_data.x86, boot_cpu_data.x86_model); 177 dev_err(dev, "Is HSMP disabled in BIOS ?\n"); 178 return ret; 179 } 180 181 ret = hsmp_cache_proto_ver(i); 182 if (ret) { 183 dev_err(dev, "Failed to read HSMP protocol version\n"); 184 return ret; 185 } 186 187 if (hsmp_pdev->proto_ver == HSMP_PROTO_VER6) { 188 ret = hsmp_get_tbl_dram_base(i); 189 if (ret) 190 dev_err(dev, "Failed to init metric table\n"); 191 } 192 193 /* Register with hwmon interface for reporting power */ 194 ret = hsmp_create_sensor(dev, i); 195 if (ret) 196 dev_err(dev, "Failed to register HSMP sensors with hwmon\n"); 197 } 198 199 return 0; 200 } 201 202 static int hsmp_pltdrv_probe(struct platform_device *pdev) 203 { 204 int ret; 205 206 hsmp_pdev->sock = devm_kcalloc(&pdev->dev, hsmp_pdev->num_sockets, 207 sizeof(*hsmp_pdev->sock), 208 GFP_KERNEL); 209 if (!hsmp_pdev->sock) 210 return -ENOMEM; 211 212 ret = init_platform_device(&pdev->dev); 213 if (ret) { 214 dev_err(&pdev->dev, "Failed to init HSMP mailbox\n"); 215 return ret; 216 } 217 218 return hsmp_misc_register(&pdev->dev); 219 } 220 221 static void hsmp_pltdrv_remove(struct platform_device *pdev) 222 { 223 hsmp_misc_deregister(); 224 } 225 226 static struct platform_driver amd_hsmp_driver = { 227 .probe = hsmp_pltdrv_probe, 228 .remove = hsmp_pltdrv_remove, 229 .driver = { 230 .name = DRIVER_NAME, 231 .dev_groups = hsmp_groups, 232 }, 233 }; 234 235 static struct platform_device *amd_hsmp_platdev; 236 237 static int hsmp_plat_dev_register(void) 238 { 239 int ret; 240 241 amd_hsmp_platdev = platform_device_alloc(DRIVER_NAME, PLATFORM_DEVID_NONE); 242 if (!amd_hsmp_platdev) 243 return -ENOMEM; 244 245 ret = platform_device_add(amd_hsmp_platdev); 246 if (ret) 247 platform_device_put(amd_hsmp_platdev); 248 249 return ret; 250 } 251 252 /* 253 * This check is only needed for backward compatibility of previous platforms. 254 * All new platforms are expected to support ACPI based probing. 255 */ 256 static bool legacy_hsmp_support(void) 257 { 258 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) 259 return false; 260 261 switch (boot_cpu_data.x86) { 262 case 0x19: 263 switch (boot_cpu_data.x86_model) { 264 case 0x00 ... 0x1F: 265 case 0x30 ... 0x3F: 266 case 0x90 ... 0x9F: 267 case 0xA0 ... 0xAF: 268 return true; 269 default: 270 return false; 271 } 272 case 0x1A: 273 switch (boot_cpu_data.x86_model) { 274 case 0x00 ... 0x0F: 275 return true; 276 default: 277 return false; 278 } 279 default: 280 return false; 281 } 282 283 return false; 284 } 285 286 static int __init hsmp_plt_init(void) 287 { 288 int ret = -ENODEV; 289 290 if (!legacy_hsmp_support()) { 291 pr_info("HSMP is not supported on Family:%x model:%x\n", 292 boot_cpu_data.x86, boot_cpu_data.x86_model); 293 return ret; 294 } 295 296 if (acpi_dev_present(ACPI_HSMP_DEVICE_HID, NULL, -1)) 297 return -ENODEV; 298 299 hsmp_pdev = get_hsmp_pdev(); 300 if (!hsmp_pdev) 301 return -ENOMEM; 302 303 /* 304 * amd_num_nodes() returns number of SMN/DF interfaces present in the system 305 * if we have N SMN/DF interfaces that ideally means N sockets 306 */ 307 hsmp_pdev->num_sockets = amd_num_nodes(); 308 if (hsmp_pdev->num_sockets == 0 || hsmp_pdev->num_sockets > MAX_AMD_NUM_NODES) 309 return ret; 310 311 ret = platform_driver_register(&amd_hsmp_driver); 312 if (ret) 313 return ret; 314 315 ret = hsmp_plat_dev_register(); 316 if (ret) 317 platform_driver_unregister(&amd_hsmp_driver); 318 319 return ret; 320 } 321 322 static void __exit hsmp_plt_exit(void) 323 { 324 platform_device_unregister(amd_hsmp_platdev); 325 platform_driver_unregister(&amd_hsmp_driver); 326 } 327 328 device_initcall(hsmp_plt_init); 329 module_exit(hsmp_plt_exit); 330 331 MODULE_IMPORT_NS("AMD_HSMP"); 332 MODULE_DESCRIPTION("AMD HSMP Platform Interface Driver"); 333 MODULE_VERSION(DRIVER_VERSION); 334 MODULE_LICENSE("GPL"); 335