1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 2 /* 3 * Mellanox platform driver 4 * 5 * Copyright (C) 2016-2018 Mellanox Technologies 6 * Copyright (C) 2016-2018 Vadim Pasternak <vadimp@mellanox.com> 7 */ 8 9 #include <linux/device.h> 10 #include <linux/dmi.h> 11 #include <linux/i2c.h> 12 #include <linux/i2c-mux.h> 13 #include <linux/io.h> 14 #include <linux/module.h> 15 #include <linux/pci.h> 16 #include <linux/platform_device.h> 17 #include <linux/platform_data/i2c-mux-reg.h> 18 #include <linux/platform_data/mlxreg.h> 19 #include <linux/reboot.h> 20 #include <linux/regmap.h> 21 22 #define MLX_PLAT_DEVICE_NAME "mlxplat" 23 24 /* LPC bus IO offsets */ 25 #define MLXPLAT_CPLD_LPC_I2C_BASE_ADRR 0x2000 26 #define MLXPLAT_CPLD_LPC_REG_BASE_ADRR 0x2500 27 #define MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET 0x00 28 #define MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET 0x01 29 #define MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET 0x02 30 #define MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET 0x03 31 #define MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET 0x04 32 #define MLXPLAT_CPLD_LPC_REG_CPLD1_PN1_OFFSET 0x05 33 #define MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET 0x06 34 #define MLXPLAT_CPLD_LPC_REG_CPLD2_PN1_OFFSET 0x07 35 #define MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET 0x08 36 #define MLXPLAT_CPLD_LPC_REG_CPLD3_PN1_OFFSET 0x09 37 #define MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET 0x0a 38 #define MLXPLAT_CPLD_LPC_REG_CPLD4_PN1_OFFSET 0x0b 39 #define MLXPLAT_CPLD_LPC_REG_RESET_GP1_OFFSET 0x17 40 #define MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET 0x19 41 #define MLXPLAT_CPLD_LPC_REG_RESET_GP3_OFFSET 0x1b 42 #define MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET 0x1c 43 #define MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET 0x1d 44 #define MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET 0x1e 45 #define MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET 0x1f 46 #define MLXPLAT_CPLD_LPC_REG_LED1_OFFSET 0x20 47 #define MLXPLAT_CPLD_LPC_REG_LED2_OFFSET 0x21 48 #define MLXPLAT_CPLD_LPC_REG_LED3_OFFSET 0x22 49 #define MLXPLAT_CPLD_LPC_REG_LED4_OFFSET 0x23 50 #define MLXPLAT_CPLD_LPC_REG_LED5_OFFSET 0x24 51 #define MLXPLAT_CPLD_LPC_REG_LED6_OFFSET 0x25 52 #define MLXPLAT_CPLD_LPC_REG_LED7_OFFSET 0x26 53 #define MLXPLAT_CPLD_LPC_REG_LED8_OFFSET 0x27 54 #define MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION 0x2a 55 #define MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET 0x2b 56 #define MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET 0x2d 57 #define MLXPLAT_CPLD_LPC_REG_GP1_RO_OFFSET 0x2c 58 #define MLXPLAT_CPLD_LPC_REG_GP0_OFFSET 0x2e 59 #define MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET 0x2f 60 #define MLXPLAT_CPLD_LPC_REG_GP1_OFFSET 0x30 61 #define MLXPLAT_CPLD_LPC_REG_WP1_OFFSET 0x31 62 #define MLXPLAT_CPLD_LPC_REG_GP2_OFFSET 0x32 63 #define MLXPLAT_CPLD_LPC_REG_WP2_OFFSET 0x33 64 #define MLXPLAT_CPLD_LPC_REG_FIELD_UPGRADE 0x34 65 #define MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET 0x35 66 #define MLXPLAT_CPLD_LPC_SAFE_BIOS_WP_OFFSET 0x36 67 #define MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET 0x37 68 #define MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET 0x3a 69 #define MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET 0x3b 70 #define MLXPLAT_CPLD_LPC_REG_FU_CAP_OFFSET 0x3c 71 #define MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET 0x40 72 #define MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET 0x41 73 #define MLXPLAT_CPLD_LPC_REG_AGGRCO_OFFSET 0x42 74 #define MLXPLAT_CPLD_LPC_REG_AGGRCO_MASK_OFFSET 0x43 75 #define MLXPLAT_CPLD_LPC_REG_AGGRCX_OFFSET 0x44 76 #define MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET 0x45 77 #define MLXPLAT_CPLD_LPC_REG_GP3_OFFSET 0x46 78 #define MLXPLAT_CPLD_LPC_REG_BRD_OFFSET 0x47 79 #define MLXPLAT_CPLD_LPC_REG_BRD_EVENT_OFFSET 0x48 80 #define MLXPLAT_CPLD_LPC_REG_BRD_MASK_OFFSET 0x49 81 #define MLXPLAT_CPLD_LPC_REG_GWP_OFFSET 0x4a 82 #define MLXPLAT_CPLD_LPC_REG_GWP_EVENT_OFFSET 0x4b 83 #define MLXPLAT_CPLD_LPC_REG_GWP_MASK_OFFSET 0x4c 84 #define MLXPLAT_CPLD_LPC_REG_GPI_MASK_OFFSET 0x4e 85 #define MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET 0x50 86 #define MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET 0x51 87 #define MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET 0x52 88 #define MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET 0x53 89 #define MLXPLAT_CPLD_LPC_REG_ASIC2_EVENT_OFFSET 0x54 90 #define MLXPLAT_CPLD_LPC_REG_ASIC2_MASK_OFFSET 0x55 91 #define MLXPLAT_CPLD_LPC_REG_AGGRLC_OFFSET 0x56 92 #define MLXPLAT_CPLD_LPC_REG_AGGRLC_MASK_OFFSET 0x57 93 #define MLXPLAT_CPLD_LPC_REG_PSU_OFFSET 0x58 94 #define MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET 0x59 95 #define MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET 0x5a 96 #define MLXPLAT_CPLD_LPC_REG_PSU_AC_OFFSET 0x5e 97 #define MLXPLAT_CPLD_LPC_REG_PWR_OFFSET 0x64 98 #define MLXPLAT_CPLD_LPC_REG_PWR_EVENT_OFFSET 0x65 99 #define MLXPLAT_CPLD_LPC_REG_PWR_MASK_OFFSET 0x66 100 #define MLXPLAT_CPLD_LPC_REG_PSU_ALERT_OFFSET 0x6a 101 #define MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET 0x70 102 #define MLXPLAT_CPLD_LPC_REG_LC_IN_EVENT_OFFSET 0x71 103 #define MLXPLAT_CPLD_LPC_REG_LC_IN_MASK_OFFSET 0x72 104 #define MLXPLAT_CPLD_LPC_REG_FAN_OFFSET 0x88 105 #define MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET 0x89 106 #define MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET 0x8a 107 #define MLXPLAT_CPLD_LPC_REG_FAN2_OFFSET 0x8b 108 #define MLXPLAT_CPLD_LPC_REG_FAN2_EVENT_OFFSET 0x8c 109 #define MLXPLAT_CPLD_LPC_REG_FAN2_MASK_OFFSET 0x8d 110 #define MLXPLAT_CPLD_LPC_REG_CPLD5_VER_OFFSET 0x8e 111 #define MLXPLAT_CPLD_LPC_REG_CPLD5_PN_OFFSET 0x8f 112 #define MLXPLAT_CPLD_LPC_REG_CPLD5_PN1_OFFSET 0x90 113 #define MLXPLAT_CPLD_LPC_REG_EROT_OFFSET 0x91 114 #define MLXPLAT_CPLD_LPC_REG_EROT_EVENT_OFFSET 0x92 115 #define MLXPLAT_CPLD_LPC_REG_EROT_MASK_OFFSET 0x93 116 #define MLXPLAT_CPLD_LPC_REG_EROTE_OFFSET 0x94 117 #define MLXPLAT_CPLD_LPC_REG_EROTE_EVENT_OFFSET 0x95 118 #define MLXPLAT_CPLD_LPC_REG_EROTE_MASK_OFFSET 0x96 119 #define MLXPLAT_CPLD_LPC_REG_PWRB_OFFSET 0x97 120 #define MLXPLAT_CPLD_LPC_REG_PWRB_EVENT_OFFSET 0x98 121 #define MLXPLAT_CPLD_LPC_REG_PWRB_MASK_OFFSET 0x99 122 #define MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET 0x9a 123 #define MLXPLAT_CPLD_LPC_REG_LC_VR_EVENT_OFFSET 0x9b 124 #define MLXPLAT_CPLD_LPC_REG_LC_VR_MASK_OFFSET 0x9c 125 #define MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET 0x9d 126 #define MLXPLAT_CPLD_LPC_REG_LC_PG_EVENT_OFFSET 0x9e 127 #define MLXPLAT_CPLD_LPC_REG_LC_PG_MASK_OFFSET 0x9f 128 #define MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET 0xa0 129 #define MLXPLAT_CPLD_LPC_REG_LC_RD_EVENT_OFFSET 0xa1 130 #define MLXPLAT_CPLD_LPC_REG_LC_RD_MASK_OFFSET 0xa2 131 #define MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET 0xa3 132 #define MLXPLAT_CPLD_LPC_REG_LC_SN_EVENT_OFFSET 0xa4 133 #define MLXPLAT_CPLD_LPC_REG_LC_SN_MASK_OFFSET 0xa5 134 #define MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET 0xa6 135 #define MLXPLAT_CPLD_LPC_REG_LC_OK_EVENT_OFFSET 0xa7 136 #define MLXPLAT_CPLD_LPC_REG_LC_OK_MASK_OFFSET 0xa8 137 #define MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET 0xa9 138 #define MLXPLAT_CPLD_LPC_REG_LC_SD_EVENT_OFFSET 0xaa 139 #define MLXPLAT_CPLD_LPC_REG_LC_SD_MASK_OFFSET 0xab 140 #define MLXPLAT_CPLD_LPC_REG_LC_PWR_ON 0xb2 141 #define MLXPLAT_CPLD_LPC_REG_TACHO19_OFFSET 0xb4 142 #define MLXPLAT_CPLD_LPC_REG_TACHO20_OFFSET 0xb5 143 #define MLXPLAT_CPLD_LPC_REG_DBG1_OFFSET 0xb6 144 #define MLXPLAT_CPLD_LPC_REG_DBG2_OFFSET 0xb7 145 #define MLXPLAT_CPLD_LPC_REG_DBG3_OFFSET 0xb8 146 #define MLXPLAT_CPLD_LPC_REG_DBG4_OFFSET 0xb9 147 #define MLXPLAT_CPLD_LPC_REG_TACHO17_OFFSET 0xba 148 #define MLXPLAT_CPLD_LPC_REG_TACHO18_OFFSET 0xbb 149 #define MLXPLAT_CPLD_LPC_REG_ASIC_CAP_OFFSET 0xc1 150 #define MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET 0xc2 151 #define MLXPLAT_CPLD_LPC_REG_SPI_CHNL_SELECT 0xc3 152 #define MLXPLAT_CPLD_LPC_REG_CPLD5_MVER_OFFSET 0xc4 153 #define MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET 0xc7 154 #define MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET 0xc8 155 #define MLXPLAT_CPLD_LPC_REG_WD1_TMR_OFFSET 0xc9 156 #define MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET 0xcb 157 #define MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET 0xcd 158 #define MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET 0xce 159 #define MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET 0xcf 160 #define MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET 0xd1 161 #define MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET 0xd2 162 #define MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET 0xd3 163 #define MLXPLAT_CPLD_LPC_REG_CPLD6_MVER_OFFSET 0xd9 164 #define MLXPLAT_CPLD_LPC_REG_I2C_CH1_OFFSET 0xdb 165 #define MLXPLAT_CPLD_LPC_REG_I2C_CH2_OFFSET 0xda 166 #define MLXPLAT_CPLD_LPC_REG_I2C_CH3_OFFSET 0xdc 167 #define MLXPLAT_CPLD_LPC_REG_I2C_CH4_OFFSET 0xdd 168 #define MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET 0xde 169 #define MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET 0xdf 170 #define MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET 0xe0 171 #define MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET 0xe1 172 #define MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET 0xe2 173 #define MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET 0xe3 174 #define MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET 0xe4 175 #define MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET 0xe5 176 #define MLXPLAT_CPLD_LPC_REG_TACHO3_OFFSET 0xe6 177 #define MLXPLAT_CPLD_LPC_REG_TACHO4_OFFSET 0xe7 178 #define MLXPLAT_CPLD_LPC_REG_TACHO5_OFFSET 0xe8 179 #define MLXPLAT_CPLD_LPC_REG_TACHO6_OFFSET 0xe9 180 #define MLXPLAT_CPLD_LPC_REG_PWM2_OFFSET 0xea 181 #define MLXPLAT_CPLD_LPC_REG_TACHO7_OFFSET 0xeb 182 #define MLXPLAT_CPLD_LPC_REG_TACHO8_OFFSET 0xec 183 #define MLXPLAT_CPLD_LPC_REG_TACHO9_OFFSET 0xed 184 #define MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET 0xee 185 #define MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET 0xef 186 #define MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET 0xf0 187 #define MLXPLAT_CPLD_LPC_REG_TACHO13_OFFSET 0xf1 188 #define MLXPLAT_CPLD_LPC_REG_TACHO14_OFFSET 0xf2 189 #define MLXPLAT_CPLD_LPC_REG_PWM3_OFFSET 0xf3 190 #define MLXPLAT_CPLD_LPC_REG_PWM4_OFFSET 0xf4 191 #define MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET 0xf5 192 #define MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET 0xf6 193 #define MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET 0xf7 194 #define MLXPLAT_CPLD_LPC_REG_TACHO_SPEED_OFFSET 0xf8 195 #define MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET 0xf9 196 #define MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET 0xfa 197 #define MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET 0xfb 198 #define MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET 0xfc 199 #define MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET 0xfd 200 #define MLXPLAT_CPLD_LPC_REG_TACHO15_OFFSET 0xfe 201 #define MLXPLAT_CPLD_LPC_REG_TACHO16_OFFSET 0xff 202 203 #define MLXPLAT_CPLD_LPC_IO_RANGE 0x100 204 205 #define MLXPLAT_CPLD_LPC_PIO_OFFSET 0x10000UL 206 #define MLXPLAT_CPLD_LPC_REG1 ((MLXPLAT_CPLD_LPC_REG_BASE_ADRR + \ 207 MLXPLAT_CPLD_LPC_REG_I2C_CH1_OFFSET) | \ 208 MLXPLAT_CPLD_LPC_PIO_OFFSET) 209 #define MLXPLAT_CPLD_LPC_REG2 ((MLXPLAT_CPLD_LPC_REG_BASE_ADRR + \ 210 MLXPLAT_CPLD_LPC_REG_I2C_CH2_OFFSET) | \ 211 MLXPLAT_CPLD_LPC_PIO_OFFSET) 212 #define MLXPLAT_CPLD_LPC_REG3 ((MLXPLAT_CPLD_LPC_REG_BASE_ADRR + \ 213 MLXPLAT_CPLD_LPC_REG_I2C_CH3_OFFSET) | \ 214 MLXPLAT_CPLD_LPC_PIO_OFFSET) 215 #define MLXPLAT_CPLD_LPC_REG4 ((MLXPLAT_CPLD_LPC_REG_BASE_ADRR + \ 216 MLXPLAT_CPLD_LPC_REG_I2C_CH4_OFFSET) | \ 217 MLXPLAT_CPLD_LPC_PIO_OFFSET) 218 219 /* Masks for aggregation, psu, pwr and fan event in CPLD related registers. */ 220 #define MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF 0x04 221 #define MLXPLAT_CPLD_AGGR_PSU_MASK_DEF 0x08 222 #define MLXPLAT_CPLD_AGGR_PWR_MASK_DEF 0x08 223 #define MLXPLAT_CPLD_AGGR_FAN_MASK_DEF 0x40 224 #define MLXPLAT_CPLD_AGGR_MASK_DEF (MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF | \ 225 MLXPLAT_CPLD_AGGR_PSU_MASK_DEF | \ 226 MLXPLAT_CPLD_AGGR_FAN_MASK_DEF) 227 #define MLXPLAT_CPLD_AGGR_ASIC_MASK_NG 0x01 228 #define MLXPLAT_CPLD_AGGR_MASK_NG_DEF 0x04 229 #define MLXPLAT_CPLD_AGGR_MASK_COMEX BIT(0) 230 #define MLXPLAT_CPLD_AGGR_MASK_LC BIT(3) 231 #define MLXPLAT_CPLD_AGGR_MASK_DPU_BRD BIT(4) 232 #define MLXPLAT_CPLD_AGGR_MASK_DPU_CORE BIT(5) 233 #define MLXPLAT_CPLD_AGGR_MASK_MODULAR (MLXPLAT_CPLD_AGGR_MASK_NG_DEF | \ 234 MLXPLAT_CPLD_AGGR_MASK_COMEX | \ 235 MLXPLAT_CPLD_AGGR_MASK_LC) 236 #define MLXPLAT_CPLD_AGGR_MASK_SMART_SW (MLXPLAT_CPLD_AGGR_MASK_COMEX | \ 237 MLXPLAT_CPLD_AGGR_MASK_NG_DEF | \ 238 MLXPLAT_CPLD_AGGR_MASK_DPU_BRD | \ 239 MLXPLAT_CPLD_AGGR_MASK_DPU_CORE) 240 #define MLXPLAT_CPLD_AGGR_MASK_LC_PRSNT BIT(0) 241 #define MLXPLAT_CPLD_AGGR_MASK_LC_RDY BIT(1) 242 #define MLXPLAT_CPLD_AGGR_MASK_LC_PG BIT(2) 243 #define MLXPLAT_CPLD_AGGR_MASK_LC_SCRD BIT(3) 244 #define MLXPLAT_CPLD_AGGR_MASK_LC_SYNC BIT(4) 245 #define MLXPLAT_CPLD_AGGR_MASK_LC_ACT BIT(5) 246 #define MLXPLAT_CPLD_AGGR_MASK_LC_SDWN BIT(6) 247 #define MLXPLAT_CPLD_AGGR_MASK_LC_LOW (MLXPLAT_CPLD_AGGR_MASK_LC_PRSNT | \ 248 MLXPLAT_CPLD_AGGR_MASK_LC_RDY | \ 249 MLXPLAT_CPLD_AGGR_MASK_LC_PG | \ 250 MLXPLAT_CPLD_AGGR_MASK_LC_SCRD | \ 251 MLXPLAT_CPLD_AGGR_MASK_LC_SYNC | \ 252 MLXPLAT_CPLD_AGGR_MASK_LC_ACT | \ 253 MLXPLAT_CPLD_AGGR_MASK_LC_SDWN) 254 #define MLXPLAT_CPLD_LOW_AGGR_MASK_LOW 0xc1 255 #define MLXPLAT_CPLD_LOW_AGGR_MASK_ASIC2 BIT(2) 256 #define MLXPLAT_CPLD_LOW_AGGR_MASK_PWR_BUT GENMASK(5, 4) 257 #define MLXPLAT_CPLD_LOW_AGGR_MASK_I2C BIT(6) 258 #define MLXPLAT_CPLD_PSU_MASK GENMASK(1, 0) 259 #define MLXPLAT_CPLD_PWR_MASK GENMASK(1, 0) 260 #define MLXPLAT_CPLD_PSU_EXT_MASK GENMASK(3, 0) 261 #define MLXPLAT_CPLD_PWR_EXT_MASK GENMASK(3, 0) 262 #define MLXPLAT_CPLD_PSU_XDR_MASK GENMASK(7, 0) 263 #define MLXPLAT_CPLD_PWR_XDR_MASK GENMASK(7, 0) 264 #define MLXPLAT_CPLD_FAN_MASK GENMASK(3, 0) 265 #define MLXPLAT_CPLD_ASIC_MASK GENMASK(1, 0) 266 #define MLXPLAT_CPLD_ASIC_XDR_MASK GENMASK(3, 0) 267 #define MLXPLAT_CPLD_FAN_NG_MASK GENMASK(6, 0) 268 #define MLXPLAT_CPLD_FAN_XDR_MASK GENMASK(7, 0) 269 #define MLXPLAT_CPLD_LED_LO_NIBBLE_MASK GENMASK(7, 4) 270 #define MLXPLAT_CPLD_LED_HI_NIBBLE_MASK GENMASK(3, 0) 271 #define MLXPLAT_CPLD_VOLTREG_UPD_MASK GENMASK(5, 4) 272 #define MLXPLAT_CPLD_GWP_MASK GENMASK(0, 0) 273 #define MLXPLAT_CPLD_EROT_MASK GENMASK(1, 0) 274 #define MLXPLAT_CPLD_FU_CAP_MASK GENMASK(1, 0) 275 #define MLXPLAT_CPLD_BIOS_STATUS_MASK GENMASK(3, 1) 276 #define MLXPLAT_CPLD_DPU_MASK GENMASK(3, 0) 277 #define MLXPLAT_CPLD_PWR_BUTTON_MASK BIT(0) 278 #define MLXPLAT_CPLD_LATCH_RST_MASK BIT(6) 279 #define MLXPLAT_CPLD_THERMAL1_PDB_MASK BIT(3) 280 #define MLXPLAT_CPLD_THERMAL2_PDB_MASK BIT(4) 281 #define MLXPLAT_CPLD_INTRUSION_MASK BIT(6) 282 #define MLXPLAT_CPLD_PWM_PG_MASK BIT(7) 283 #define MLXPLAT_CPLD_L1_CHA_HEALTH_MASK (MLXPLAT_CPLD_THERMAL1_PDB_MASK | \ 284 MLXPLAT_CPLD_THERMAL2_PDB_MASK | \ 285 MLXPLAT_CPLD_INTRUSION_MASK |\ 286 MLXPLAT_CPLD_PWM_PG_MASK) 287 #define MLXPLAT_CPLD_I2C_CAP_BIT 0x04 288 #define MLXPLAT_CPLD_I2C_CAP_MASK GENMASK(5, MLXPLAT_CPLD_I2C_CAP_BIT) 289 #define MLXPLAT_CPLD_SYS_RESET_MASK BIT(0) 290 291 /* Masks for aggregation for comex carriers */ 292 #define MLXPLAT_CPLD_AGGR_MASK_CARRIER BIT(1) 293 #define MLXPLAT_CPLD_AGGR_MASK_CARR_DEF (MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF | \ 294 MLXPLAT_CPLD_AGGR_MASK_CARRIER) 295 #define MLXPLAT_CPLD_LOW_AGGRCX_MASK 0xc1 296 297 /* Masks for aggregation for modular systems */ 298 #define MLXPLAT_CPLD_LPC_LC_MASK GENMASK(7, 0) 299 300 /* Masks for aggregation for smart switch systems */ 301 #define MLXPLAT_CPLD_LPC_SM_SW_MASK GENMASK(7, 0) 302 303 #define MLXPLAT_CPLD_HALT_MASK BIT(3) 304 #define MLXPLAT_CPLD_RESET_MASK GENMASK(7, 1) 305 306 /* Default I2C parent bus number */ 307 #define MLXPLAT_CPLD_PHYS_ADAPTER_DEF_NR 1 308 309 /* Maximum number of possible physical buses equipped on system */ 310 #define MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM 16 311 #define MLXPLAT_CPLD_MAX_PHYS_EXT_ADAPTER_NUM 24 312 313 /* Number of channels in group */ 314 #define MLXPLAT_CPLD_GRP_CHNL_NUM 8 315 316 /* Start channel numbers */ 317 #define MLXPLAT_CPLD_CH1 2 318 #define MLXPLAT_CPLD_CH2 10 319 #define MLXPLAT_CPLD_CH3 18 320 #define MLXPLAT_CPLD_CH2_ETH_MODULAR 3 321 #define MLXPLAT_CPLD_CH3_ETH_MODULAR 43 322 #define MLXPLAT_CPLD_CH4_ETH_MODULAR 51 323 #define MLXPLAT_CPLD_CH2_RACK_SWITCH 18 324 #define MLXPLAT_CPLD_CH2_NG800 34 325 326 /* Number of LPC attached MUX platform devices */ 327 #define MLXPLAT_CPLD_LPC_MUX_DEVS 4 328 329 /* Hotplug devices adapter numbers */ 330 #define MLXPLAT_CPLD_NR_NONE -1 331 #define MLXPLAT_CPLD_PSU_DEFAULT_NR 10 332 #define MLXPLAT_CPLD_PSU_MSNXXXX_NR 4 333 #define MLXPLAT_CPLD_PSU_XDR_NR 3 334 #define MLXPLAT_CPLD_FAN1_DEFAULT_NR 11 335 #define MLXPLAT_CPLD_FAN2_DEFAULT_NR 12 336 #define MLXPLAT_CPLD_FAN3_DEFAULT_NR 13 337 #define MLXPLAT_CPLD_FAN4_DEFAULT_NR 14 338 #define MLXPLAT_CPLD_NR_ASIC 3 339 #define MLXPLAT_CPLD_NR_LC_BASE 34 340 #define MLXPLAT_CPLD_NR_DPU_BASE 18 341 342 #define MLXPLAT_CPLD_NR_LC_SET(nr) (MLXPLAT_CPLD_NR_LC_BASE + (nr)) 343 #define MLXPLAT_CPLD_LC_ADDR 0x32 344 #define MLXPLAT_CPLD_DPU_ADDR 0x68 345 346 /* Masks and default values for watchdogs */ 347 #define MLXPLAT_CPLD_WD1_CLEAR_MASK GENMASK(7, 1) 348 #define MLXPLAT_CPLD_WD2_CLEAR_MASK (GENMASK(7, 0) & ~BIT(1)) 349 350 #define MLXPLAT_CPLD_WD_TYPE1_TO_MASK GENMASK(7, 4) 351 #define MLXPLAT_CPLD_WD_TYPE2_TO_MASK 0 352 #define MLXPLAT_CPLD_WD_RESET_ACT_MASK GENMASK(7, 1) 353 #define MLXPLAT_CPLD_WD_FAN_ACT_MASK (GENMASK(7, 0) & ~BIT(4)) 354 #define MLXPLAT_CPLD_WD_COUNT_ACT_MASK (GENMASK(7, 0) & ~BIT(7)) 355 #define MLXPLAT_CPLD_WD_CPBLTY_MASK (GENMASK(7, 0) & ~BIT(6)) 356 #define MLXPLAT_CPLD_WD_DFLT_TIMEOUT 30 357 #define MLXPLAT_CPLD_WD3_DFLT_TIMEOUT 600 358 #define MLXPLAT_CPLD_WD_MAX_DEVS 2 359 #define MLXPLAT_CPLD_DPU_MAX_DEVS 4 360 361 #define MLXPLAT_CPLD_LPC_SYSIRQ 17 362 363 /* Minimum power required for turning on Ethernet modular system (WATT) */ 364 #define MLXPLAT_CPLD_ETH_MODULAR_PWR_MIN 50 365 366 /* Default value for PWM control register for rack switch system */ 367 #define MLXPLAT_REGMAP_NVSWITCH_PWM_DEFAULT 0xf4 368 369 #define MLXPLAT_I2C_MAIN_BUS_NOTIFIED 0x01 370 #define MLXPLAT_I2C_MAIN_BUS_HANDLE_CREATED 0x02 371 372 /* Lattice FPGA PCI configuration */ 373 #define PCI_VENDOR_ID_LATTICE 0x1204 374 #define PCI_DEVICE_ID_LATTICE_I2C_BRIDGE 0x9c2f 375 #define PCI_DEVICE_ID_LATTICE_JTAG_BRIDGE 0x9c30 376 #define PCI_DEVICE_ID_LATTICE_LPC_BRIDGE 0x9c32 377 378 /* mlxplat_priv - platform private data 379 * @pdev_i2c - i2c controller platform device 380 * @pdev_mux - array of mux platform devices 381 * @pdev_hotplug - hotplug platform devices 382 * @pdev_led - led platform devices 383 * @pdev_io_regs - register access platform devices 384 * @pdev_fan - FAN platform devices 385 * @pdev_wd - array of watchdog platform devices 386 * pdev_dpu - array of Data Processor Unit platform devices 387 * @regmap: device register map 388 * @hotplug_resources: system hotplug resources 389 * @hotplug_resources_size: size of system hotplug resources 390 * @hi2c_main_init_status: init status of I2C main bus 391 * @irq_fpga: FPGA IRQ number 392 */ 393 struct mlxplat_priv { 394 struct platform_device *pdev_i2c; 395 struct platform_device *pdev_mux[MLXPLAT_CPLD_LPC_MUX_DEVS]; 396 struct platform_device *pdev_hotplug; 397 struct platform_device *pdev_led; 398 struct platform_device *pdev_io_regs; 399 struct platform_device *pdev_fan; 400 struct platform_device *pdev_wd[MLXPLAT_CPLD_WD_MAX_DEVS]; 401 struct platform_device *pdev_dpu[MLXPLAT_CPLD_DPU_MAX_DEVS]; 402 void *regmap; 403 struct resource *hotplug_resources; 404 unsigned int hotplug_resources_size; 405 u8 i2c_main_init_status; 406 int irq_fpga; 407 }; 408 409 static struct platform_device *mlxplat_dev; 410 static int mlxplat_i2c_main_completion_notify(void *handle, int id); 411 static void __iomem *i2c_bridge_addr, *jtag_bridge_addr; 412 413 /* Regions for LPC I2C controller and LPC base register space */ 414 static const struct resource mlxplat_lpc_resources[] = { 415 [0] = DEFINE_RES_NAMED(MLXPLAT_CPLD_LPC_I2C_BASE_ADRR, 416 MLXPLAT_CPLD_LPC_IO_RANGE, 417 "mlxplat_cpld_lpc_i2c_ctrl", IORESOURCE_IO), 418 [1] = DEFINE_RES_NAMED(MLXPLAT_CPLD_LPC_REG_BASE_ADRR, 419 MLXPLAT_CPLD_LPC_IO_RANGE, 420 "mlxplat_cpld_lpc_regs", 421 IORESOURCE_IO), 422 }; 423 424 /* Platform systems default i2c data */ 425 static struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_i2c_default_data = { 426 .completion_notify = mlxplat_i2c_main_completion_notify, 427 }; 428 429 /* Platform i2c next generation systems data */ 430 static struct mlxreg_core_data mlxplat_mlxcpld_i2c_ng_items_data[] = { 431 { 432 .reg = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 433 .mask = MLXPLAT_CPLD_I2C_CAP_MASK, 434 .bit = MLXPLAT_CPLD_I2C_CAP_BIT, 435 }, 436 }; 437 438 static struct mlxreg_core_item mlxplat_mlxcpld_i2c_ng_items[] = { 439 { 440 .data = mlxplat_mlxcpld_i2c_ng_items_data, 441 }, 442 }; 443 444 /* Platform next generation systems i2c data */ 445 static struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_i2c_ng_data = { 446 .items = mlxplat_mlxcpld_i2c_ng_items, 447 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 448 .mask = MLXPLAT_CPLD_AGGR_MASK_COMEX, 449 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRCO_OFFSET, 450 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_I2C, 451 .completion_notify = mlxplat_i2c_main_completion_notify, 452 }; 453 454 /* Platform default channels */ 455 static const int mlxplat_default_channels[][MLXPLAT_CPLD_GRP_CHNL_NUM] = { 456 { 457 MLXPLAT_CPLD_CH1, MLXPLAT_CPLD_CH1 + 1, MLXPLAT_CPLD_CH1 + 2, 458 MLXPLAT_CPLD_CH1 + 3, MLXPLAT_CPLD_CH1 + 4, MLXPLAT_CPLD_CH1 + 459 5, MLXPLAT_CPLD_CH1 + 6, MLXPLAT_CPLD_CH1 + 7 460 }, 461 { 462 MLXPLAT_CPLD_CH2, MLXPLAT_CPLD_CH2 + 1, MLXPLAT_CPLD_CH2 + 2, 463 MLXPLAT_CPLD_CH2 + 3, MLXPLAT_CPLD_CH2 + 4, MLXPLAT_CPLD_CH2 + 464 5, MLXPLAT_CPLD_CH2 + 6, MLXPLAT_CPLD_CH2 + 7 465 }, 466 }; 467 468 /* Platform channels for MSN21xx system family */ 469 static const int mlxplat_msn21xx_channels[] = { 1, 2, 3, 4, 5, 6, 7, 8 }; 470 471 /* Platform mux data */ 472 static struct i2c_mux_reg_platform_data mlxplat_default_mux_data[] = { 473 { 474 .parent = 1, 475 .base_nr = MLXPLAT_CPLD_CH1, 476 .write_only = 1, 477 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG1, 478 .reg_size = 1, 479 .idle_in_use = 1, 480 }, 481 { 482 .parent = 1, 483 .base_nr = MLXPLAT_CPLD_CH2, 484 .write_only = 1, 485 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG2, 486 .reg_size = 1, 487 .idle_in_use = 1, 488 }, 489 490 }; 491 492 /* Platform mux configuration variables */ 493 static int mlxplat_max_adap_num; 494 static int mlxplat_mux_num; 495 static struct i2c_mux_reg_platform_data *mlxplat_mux_data; 496 static struct notifier_block *mlxplat_reboot_nb; 497 498 /* Platform extended mux data */ 499 static struct i2c_mux_reg_platform_data mlxplat_extended_mux_data[] = { 500 { 501 .parent = 1, 502 .base_nr = MLXPLAT_CPLD_CH1, 503 .write_only = 1, 504 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG1, 505 .reg_size = 1, 506 .idle_in_use = 1, 507 }, 508 { 509 .parent = 1, 510 .base_nr = MLXPLAT_CPLD_CH2, 511 .write_only = 1, 512 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG3, 513 .reg_size = 1, 514 .idle_in_use = 1, 515 }, 516 { 517 .parent = 1, 518 .base_nr = MLXPLAT_CPLD_CH3, 519 .write_only = 1, 520 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG2, 521 .reg_size = 1, 522 .idle_in_use = 1, 523 }, 524 525 }; 526 527 /* Platform channels for modular system family */ 528 static const int mlxplat_modular_upper_channel[] = { 1 }; 529 static const int mlxplat_modular_channels[] = { 530 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 531 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 532 38, 39, 40 533 }; 534 535 /* Platform modular mux data */ 536 static struct i2c_mux_reg_platform_data mlxplat_modular_mux_data[] = { 537 { 538 .parent = 1, 539 .base_nr = MLXPLAT_CPLD_CH1, 540 .write_only = 1, 541 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG4, 542 .reg_size = 1, 543 .idle_in_use = 1, 544 .values = mlxplat_modular_upper_channel, 545 .n_values = ARRAY_SIZE(mlxplat_modular_upper_channel), 546 }, 547 { 548 .parent = 1, 549 .base_nr = MLXPLAT_CPLD_CH2_ETH_MODULAR, 550 .write_only = 1, 551 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG1, 552 .reg_size = 1, 553 .idle_in_use = 1, 554 .values = mlxplat_modular_channels, 555 .n_values = ARRAY_SIZE(mlxplat_modular_channels), 556 }, 557 { 558 .parent = MLXPLAT_CPLD_CH1, 559 .base_nr = MLXPLAT_CPLD_CH3_ETH_MODULAR, 560 .write_only = 1, 561 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG3, 562 .reg_size = 1, 563 .idle_in_use = 1, 564 .values = mlxplat_msn21xx_channels, 565 .n_values = ARRAY_SIZE(mlxplat_msn21xx_channels), 566 }, 567 { 568 .parent = 1, 569 .base_nr = MLXPLAT_CPLD_CH4_ETH_MODULAR, 570 .write_only = 1, 571 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG2, 572 .reg_size = 1, 573 .idle_in_use = 1, 574 .values = mlxplat_msn21xx_channels, 575 .n_values = ARRAY_SIZE(mlxplat_msn21xx_channels), 576 }, 577 }; 578 579 /* Platform channels for rack switch system family */ 580 static const int mlxplat_rack_switch_channels[] = { 581 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 582 }; 583 584 /* Platform rack switch mux data */ 585 static struct i2c_mux_reg_platform_data mlxplat_rack_switch_mux_data[] = { 586 { 587 .parent = 1, 588 .base_nr = MLXPLAT_CPLD_CH1, 589 .write_only = 1, 590 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG1, 591 .reg_size = 1, 592 .idle_in_use = 1, 593 .values = mlxplat_rack_switch_channels, 594 .n_values = ARRAY_SIZE(mlxplat_rack_switch_channels), 595 }, 596 { 597 .parent = 1, 598 .base_nr = MLXPLAT_CPLD_CH2_RACK_SWITCH, 599 .write_only = 1, 600 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG2, 601 .reg_size = 1, 602 .idle_in_use = 1, 603 .values = mlxplat_msn21xx_channels, 604 .n_values = ARRAY_SIZE(mlxplat_msn21xx_channels), 605 }, 606 607 }; 608 609 /* Platform channels for ng800 system family */ 610 static const int mlxplat_ng800_channels[] = { 611 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 612 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32 613 }; 614 615 /* Platform ng800 mux data */ 616 static struct i2c_mux_reg_platform_data mlxplat_ng800_mux_data[] = { 617 { 618 .parent = 1, 619 .base_nr = MLXPLAT_CPLD_CH1, 620 .write_only = 1, 621 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG1, 622 .reg_size = 1, 623 .idle_in_use = 1, 624 .values = mlxplat_ng800_channels, 625 .n_values = ARRAY_SIZE(mlxplat_ng800_channels), 626 }, 627 { 628 .parent = 1, 629 .base_nr = MLXPLAT_CPLD_CH2_NG800, 630 .write_only = 1, 631 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG2, 632 .reg_size = 1, 633 .idle_in_use = 1, 634 .values = mlxplat_msn21xx_channels, 635 .n_values = ARRAY_SIZE(mlxplat_msn21xx_channels), 636 }, 637 638 }; 639 640 /* Platform hotplug devices */ 641 static struct i2c_board_info mlxplat_mlxcpld_pwr[] = { 642 { 643 I2C_BOARD_INFO("dps460", 0x59), 644 }, 645 { 646 I2C_BOARD_INFO("dps460", 0x58), 647 }, 648 }; 649 650 static struct i2c_board_info mlxplat_mlxcpld_ext_pwr[] = { 651 { 652 I2C_BOARD_INFO("dps460", 0x5b), 653 }, 654 { 655 I2C_BOARD_INFO("dps460", 0x5a), 656 }, 657 }; 658 659 static struct i2c_board_info mlxplat_mlxcpld_pwr_ng800[] = { 660 { 661 I2C_BOARD_INFO("dps460", 0x59), 662 }, 663 { 664 I2C_BOARD_INFO("dps460", 0x5a), 665 }, 666 }; 667 668 static struct i2c_board_info mlxplat_mlxcpld_xdr_pwr[] = { 669 { 670 I2C_BOARD_INFO("dps460", 0x5d), 671 }, 672 { 673 I2C_BOARD_INFO("dps460", 0x5c), 674 }, 675 { 676 I2C_BOARD_INFO("dps460", 0x5e), 677 }, 678 { 679 I2C_BOARD_INFO("dps460", 0x5f), 680 }, 681 }; 682 683 static struct i2c_board_info mlxplat_mlxcpld_fan[] = { 684 { 685 I2C_BOARD_INFO("24c32", 0x50), 686 }, 687 { 688 I2C_BOARD_INFO("24c32", 0x50), 689 }, 690 { 691 I2C_BOARD_INFO("24c32", 0x50), 692 }, 693 { 694 I2C_BOARD_INFO("24c32", 0x50), 695 }, 696 }; 697 698 /* Platform hotplug comex carrier system family data */ 699 static struct mlxreg_core_data mlxplat_mlxcpld_comex_psu_items_data[] = { 700 { 701 .label = "psu1", 702 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 703 .mask = BIT(0), 704 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 705 }, 706 { 707 .label = "psu2", 708 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 709 .mask = BIT(1), 710 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 711 }, 712 }; 713 714 /* Platform hotplug default data */ 715 static struct mlxreg_core_data mlxplat_mlxcpld_default_psu_items_data[] = { 716 { 717 .label = "psu1", 718 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 719 .mask = BIT(0), 720 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 721 }, 722 { 723 .label = "psu2", 724 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 725 .mask = BIT(1), 726 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 727 }, 728 }; 729 730 static struct mlxreg_core_data mlxplat_mlxcpld_default_pwr_items_data[] = { 731 { 732 .label = "pwr1", 733 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 734 .mask = BIT(0), 735 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[0], 736 .hpdev.nr = MLXPLAT_CPLD_PSU_DEFAULT_NR, 737 }, 738 { 739 .label = "pwr2", 740 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 741 .mask = BIT(1), 742 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[1], 743 .hpdev.nr = MLXPLAT_CPLD_PSU_DEFAULT_NR, 744 }, 745 }; 746 747 static struct mlxreg_core_data mlxplat_mlxcpld_default_pwr_wc_items_data[] = { 748 { 749 .label = "pwr1", 750 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 751 .mask = BIT(0), 752 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 753 }, 754 { 755 .label = "pwr2", 756 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 757 .mask = BIT(1), 758 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 759 }, 760 }; 761 762 static struct mlxreg_core_data mlxplat_mlxcpld_default_pwr_ng800_items_data[] = { 763 { 764 .label = "pwr1", 765 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 766 .mask = BIT(0), 767 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr_ng800[0], 768 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 769 }, 770 { 771 .label = "pwr2", 772 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 773 .mask = BIT(1), 774 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr_ng800[1], 775 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 776 }, 777 }; 778 779 static struct mlxreg_core_data mlxplat_mlxcpld_default_fan_items_data[] = { 780 { 781 .label = "fan1", 782 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 783 .mask = BIT(0), 784 .hpdev.brdinfo = &mlxplat_mlxcpld_fan[0], 785 .hpdev.nr = MLXPLAT_CPLD_FAN1_DEFAULT_NR, 786 }, 787 { 788 .label = "fan2", 789 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 790 .mask = BIT(1), 791 .hpdev.brdinfo = &mlxplat_mlxcpld_fan[1], 792 .hpdev.nr = MLXPLAT_CPLD_FAN2_DEFAULT_NR, 793 }, 794 { 795 .label = "fan3", 796 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 797 .mask = BIT(2), 798 .hpdev.brdinfo = &mlxplat_mlxcpld_fan[2], 799 .hpdev.nr = MLXPLAT_CPLD_FAN3_DEFAULT_NR, 800 }, 801 { 802 .label = "fan4", 803 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 804 .mask = BIT(3), 805 .hpdev.brdinfo = &mlxplat_mlxcpld_fan[3], 806 .hpdev.nr = MLXPLAT_CPLD_FAN4_DEFAULT_NR, 807 }, 808 }; 809 810 static struct mlxreg_core_data mlxplat_mlxcpld_default_asic_items_data[] = { 811 { 812 .label = "asic1", 813 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 814 .mask = MLXPLAT_CPLD_ASIC_MASK, 815 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 816 }, 817 }; 818 819 static struct mlxreg_core_data mlxplat_mlxcpld_default_asic2_items_data[] = { 820 { 821 .label = "asic2", 822 .reg = MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET, 823 .mask = MLXPLAT_CPLD_ASIC_MASK, 824 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 825 }, 826 }; 827 828 static struct mlxreg_core_item mlxplat_mlxcpld_default_items[] = { 829 { 830 .data = mlxplat_mlxcpld_default_psu_items_data, 831 .aggr_mask = MLXPLAT_CPLD_AGGR_PSU_MASK_DEF, 832 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 833 .mask = MLXPLAT_CPLD_PSU_MASK, 834 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_psu_items_data), 835 .inversed = 1, 836 .health = false, 837 }, 838 { 839 .data = mlxplat_mlxcpld_default_pwr_items_data, 840 .aggr_mask = MLXPLAT_CPLD_AGGR_PWR_MASK_DEF, 841 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 842 .mask = MLXPLAT_CPLD_PWR_MASK, 843 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_pwr_items_data), 844 .inversed = 0, 845 .health = false, 846 }, 847 { 848 .data = mlxplat_mlxcpld_default_fan_items_data, 849 .aggr_mask = MLXPLAT_CPLD_AGGR_FAN_MASK_DEF, 850 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 851 .mask = MLXPLAT_CPLD_FAN_MASK, 852 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_fan_items_data), 853 .inversed = 1, 854 .health = false, 855 }, 856 { 857 .data = mlxplat_mlxcpld_default_asic_items_data, 858 .aggr_mask = MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF, 859 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 860 .mask = MLXPLAT_CPLD_ASIC_MASK, 861 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data), 862 .inversed = 0, 863 .health = true, 864 }, 865 }; 866 867 static struct mlxreg_core_item mlxplat_mlxcpld_comex_items[] = { 868 { 869 .data = mlxplat_mlxcpld_comex_psu_items_data, 870 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_CARRIER, 871 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 872 .mask = MLXPLAT_CPLD_PSU_MASK, 873 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_psu_items_data), 874 .inversed = 1, 875 .health = false, 876 }, 877 { 878 .data = mlxplat_mlxcpld_default_pwr_items_data, 879 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_CARRIER, 880 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 881 .mask = MLXPLAT_CPLD_PWR_MASK, 882 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_pwr_items_data), 883 .inversed = 0, 884 .health = false, 885 }, 886 { 887 .data = mlxplat_mlxcpld_default_fan_items_data, 888 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_CARRIER, 889 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 890 .mask = MLXPLAT_CPLD_FAN_MASK, 891 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_fan_items_data), 892 .inversed = 1, 893 .health = false, 894 }, 895 { 896 .data = mlxplat_mlxcpld_default_asic_items_data, 897 .aggr_mask = MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF, 898 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 899 .mask = MLXPLAT_CPLD_ASIC_MASK, 900 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data), 901 .inversed = 0, 902 .health = true, 903 }, 904 }; 905 906 static 907 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_default_data = { 908 .items = mlxplat_mlxcpld_default_items, 909 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_items), 910 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 911 .mask = MLXPLAT_CPLD_AGGR_MASK_DEF, 912 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 913 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, 914 }; 915 916 static struct mlxreg_core_item mlxplat_mlxcpld_default_wc_items[] = { 917 { 918 .data = mlxplat_mlxcpld_comex_psu_items_data, 919 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_CARRIER, 920 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 921 .mask = MLXPLAT_CPLD_PSU_MASK, 922 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_psu_items_data), 923 .inversed = 1, 924 .health = false, 925 }, 926 { 927 .data = mlxplat_mlxcpld_default_pwr_wc_items_data, 928 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_CARRIER, 929 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 930 .mask = MLXPLAT_CPLD_PWR_MASK, 931 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_pwr_items_data), 932 .inversed = 0, 933 .health = false, 934 }, 935 { 936 .data = mlxplat_mlxcpld_default_asic_items_data, 937 .aggr_mask = MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF, 938 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 939 .mask = MLXPLAT_CPLD_ASIC_MASK, 940 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data), 941 .inversed = 0, 942 .health = true, 943 }, 944 }; 945 946 static 947 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_default_wc_data = { 948 .items = mlxplat_mlxcpld_default_wc_items, 949 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_wc_items), 950 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 951 .mask = MLXPLAT_CPLD_AGGR_MASK_DEF, 952 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 953 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, 954 }; 955 956 static 957 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_comex_data = { 958 .items = mlxplat_mlxcpld_comex_items, 959 .count = ARRAY_SIZE(mlxplat_mlxcpld_comex_items), 960 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 961 .mask = MLXPLAT_CPLD_AGGR_MASK_CARR_DEF, 962 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRCX_OFFSET, 963 .mask_low = MLXPLAT_CPLD_LOW_AGGRCX_MASK, 964 }; 965 966 static struct mlxreg_core_data mlxplat_mlxcpld_msn21xx_pwr_items_data[] = { 967 { 968 .label = "pwr1", 969 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 970 .mask = BIT(0), 971 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 972 }, 973 { 974 .label = "pwr2", 975 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 976 .mask = BIT(1), 977 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 978 }, 979 }; 980 981 /* Platform hotplug MSN21xx system family data */ 982 static struct mlxreg_core_item mlxplat_mlxcpld_msn21xx_items[] = { 983 { 984 .data = mlxplat_mlxcpld_msn21xx_pwr_items_data, 985 .aggr_mask = MLXPLAT_CPLD_AGGR_PWR_MASK_DEF, 986 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 987 .mask = MLXPLAT_CPLD_PWR_MASK, 988 .count = ARRAY_SIZE(mlxplat_mlxcpld_msn21xx_pwr_items_data), 989 .inversed = 0, 990 .health = false, 991 }, 992 { 993 .data = mlxplat_mlxcpld_default_asic_items_data, 994 .aggr_mask = MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF, 995 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 996 .mask = MLXPLAT_CPLD_ASIC_MASK, 997 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data), 998 .inversed = 0, 999 .health = true, 1000 }, 1001 }; 1002 1003 static 1004 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_msn21xx_data = { 1005 .items = mlxplat_mlxcpld_msn21xx_items, 1006 .count = ARRAY_SIZE(mlxplat_mlxcpld_msn21xx_items), 1007 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 1008 .mask = MLXPLAT_CPLD_AGGR_MASK_DEF, 1009 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 1010 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, 1011 }; 1012 1013 /* Platform hotplug msn274x system family data */ 1014 static struct mlxreg_core_data mlxplat_mlxcpld_msn274x_psu_items_data[] = { 1015 { 1016 .label = "psu1", 1017 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 1018 .mask = BIT(0), 1019 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1020 }, 1021 { 1022 .label = "psu2", 1023 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 1024 .mask = BIT(1), 1025 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1026 }, 1027 }; 1028 1029 static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_pwr_items_data[] = { 1030 { 1031 .label = "pwr1", 1032 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1033 .mask = BIT(0), 1034 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[0], 1035 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 1036 }, 1037 { 1038 .label = "pwr2", 1039 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1040 .mask = BIT(1), 1041 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[1], 1042 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 1043 }, 1044 }; 1045 1046 static struct mlxreg_core_data mlxplat_mlxcpld_msn274x_fan_items_data[] = { 1047 { 1048 .label = "fan1", 1049 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1050 .mask = BIT(0), 1051 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1052 }, 1053 { 1054 .label = "fan2", 1055 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1056 .mask = BIT(1), 1057 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1058 }, 1059 { 1060 .label = "fan3", 1061 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1062 .mask = BIT(2), 1063 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1064 }, 1065 { 1066 .label = "fan4", 1067 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1068 .mask = BIT(3), 1069 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1070 }, 1071 }; 1072 1073 static struct mlxreg_core_item mlxplat_mlxcpld_msn274x_items[] = { 1074 { 1075 .data = mlxplat_mlxcpld_msn274x_psu_items_data, 1076 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1077 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 1078 .mask = MLXPLAT_CPLD_PSU_MASK, 1079 .count = ARRAY_SIZE(mlxplat_mlxcpld_msn274x_psu_items_data), 1080 .inversed = 1, 1081 .health = false, 1082 }, 1083 { 1084 .data = mlxplat_mlxcpld_default_ng_pwr_items_data, 1085 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1086 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1087 .mask = MLXPLAT_CPLD_PWR_MASK, 1088 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_pwr_items_data), 1089 .inversed = 0, 1090 .health = false, 1091 }, 1092 { 1093 .data = mlxplat_mlxcpld_msn274x_fan_items_data, 1094 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1095 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1096 .mask = MLXPLAT_CPLD_FAN_MASK, 1097 .count = ARRAY_SIZE(mlxplat_mlxcpld_msn274x_fan_items_data), 1098 .inversed = 1, 1099 .health = false, 1100 }, 1101 { 1102 .data = mlxplat_mlxcpld_default_asic_items_data, 1103 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1104 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 1105 .mask = MLXPLAT_CPLD_ASIC_MASK, 1106 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data), 1107 .inversed = 0, 1108 .health = true, 1109 }, 1110 }; 1111 1112 static 1113 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_msn274x_data = { 1114 .items = mlxplat_mlxcpld_msn274x_items, 1115 .count = ARRAY_SIZE(mlxplat_mlxcpld_msn274x_items), 1116 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 1117 .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1118 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 1119 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, 1120 }; 1121 1122 /* Platform hotplug MSN201x system family data */ 1123 static struct mlxreg_core_data mlxplat_mlxcpld_msn201x_pwr_items_data[] = { 1124 { 1125 .label = "pwr1", 1126 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1127 .mask = BIT(0), 1128 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1129 }, 1130 { 1131 .label = "pwr2", 1132 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1133 .mask = BIT(1), 1134 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1135 }, 1136 }; 1137 1138 static struct mlxreg_core_item mlxplat_mlxcpld_msn201x_items[] = { 1139 { 1140 .data = mlxplat_mlxcpld_msn201x_pwr_items_data, 1141 .aggr_mask = MLXPLAT_CPLD_AGGR_PWR_MASK_DEF, 1142 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1143 .mask = MLXPLAT_CPLD_PWR_MASK, 1144 .count = ARRAY_SIZE(mlxplat_mlxcpld_msn201x_pwr_items_data), 1145 .inversed = 0, 1146 .health = false, 1147 }, 1148 { 1149 .data = mlxplat_mlxcpld_default_asic_items_data, 1150 .aggr_mask = MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF, 1151 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 1152 .mask = MLXPLAT_CPLD_ASIC_MASK, 1153 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data), 1154 .inversed = 0, 1155 .health = true, 1156 }, 1157 }; 1158 1159 static 1160 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_msn201x_data = { 1161 .items = mlxplat_mlxcpld_msn201x_items, 1162 .count = ARRAY_SIZE(mlxplat_mlxcpld_msn201x_items), 1163 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 1164 .mask = MLXPLAT_CPLD_AGGR_MASK_DEF, 1165 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 1166 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, 1167 }; 1168 1169 /* Platform hotplug next generation system family data */ 1170 static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_psu_items_data[] = { 1171 { 1172 .label = "psu1", 1173 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 1174 .mask = BIT(0), 1175 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1176 }, 1177 { 1178 .label = "psu2", 1179 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 1180 .mask = BIT(1), 1181 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1182 }, 1183 }; 1184 1185 static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_fan_items_data[] = { 1186 { 1187 .label = "fan1", 1188 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1189 .mask = BIT(0), 1190 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 1191 .bit = BIT(0), 1192 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1193 }, 1194 { 1195 .label = "fan2", 1196 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1197 .mask = BIT(1), 1198 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 1199 .bit = BIT(1), 1200 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1201 }, 1202 { 1203 .label = "fan3", 1204 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1205 .mask = BIT(2), 1206 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 1207 .bit = BIT(2), 1208 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1209 }, 1210 { 1211 .label = "fan4", 1212 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1213 .mask = BIT(3), 1214 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 1215 .bit = BIT(3), 1216 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1217 }, 1218 { 1219 .label = "fan5", 1220 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1221 .mask = BIT(4), 1222 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 1223 .bit = BIT(4), 1224 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1225 }, 1226 { 1227 .label = "fan6", 1228 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1229 .mask = BIT(5), 1230 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 1231 .bit = BIT(5), 1232 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1233 }, 1234 { 1235 .label = "fan7", 1236 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1237 .mask = BIT(6), 1238 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 1239 .bit = BIT(6), 1240 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1241 }, 1242 }; 1243 1244 static struct mlxreg_core_item mlxplat_mlxcpld_default_ng_items[] = { 1245 { 1246 .data = mlxplat_mlxcpld_default_ng_psu_items_data, 1247 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1248 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 1249 .mask = MLXPLAT_CPLD_PSU_MASK, 1250 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_psu_items_data), 1251 .inversed = 1, 1252 .health = false, 1253 }, 1254 { 1255 .data = mlxplat_mlxcpld_default_ng_pwr_items_data, 1256 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1257 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1258 .mask = MLXPLAT_CPLD_PWR_MASK, 1259 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_pwr_items_data), 1260 .inversed = 0, 1261 .health = false, 1262 }, 1263 { 1264 .data = mlxplat_mlxcpld_default_ng_fan_items_data, 1265 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1266 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1267 .mask = MLXPLAT_CPLD_FAN_NG_MASK, 1268 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_fan_items_data), 1269 .inversed = 1, 1270 .health = false, 1271 }, 1272 { 1273 .data = mlxplat_mlxcpld_default_asic_items_data, 1274 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1275 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 1276 .mask = MLXPLAT_CPLD_ASIC_MASK, 1277 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data), 1278 .inversed = 0, 1279 .health = true, 1280 }, 1281 }; 1282 1283 static 1284 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_default_ng_data = { 1285 .items = mlxplat_mlxcpld_default_ng_items, 1286 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_items), 1287 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 1288 .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF | MLXPLAT_CPLD_AGGR_MASK_COMEX, 1289 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 1290 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, 1291 }; 1292 1293 /* Platform hotplug extended system family data */ 1294 static struct mlxreg_core_data mlxplat_mlxcpld_ext_psu_items_data[] = { 1295 { 1296 .label = "psu1", 1297 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 1298 .mask = BIT(0), 1299 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1300 }, 1301 { 1302 .label = "psu2", 1303 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 1304 .mask = BIT(1), 1305 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1306 }, 1307 { 1308 .label = "psu3", 1309 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 1310 .mask = BIT(2), 1311 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1312 }, 1313 { 1314 .label = "psu4", 1315 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 1316 .mask = BIT(3), 1317 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1318 }, 1319 }; 1320 1321 static struct mlxreg_core_data mlxplat_mlxcpld_ext_pwr_items_data[] = { 1322 { 1323 .label = "pwr1", 1324 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1325 .mask = BIT(0), 1326 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[0], 1327 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 1328 }, 1329 { 1330 .label = "pwr2", 1331 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1332 .mask = BIT(1), 1333 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[1], 1334 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 1335 }, 1336 { 1337 .label = "pwr3", 1338 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1339 .mask = BIT(2), 1340 .hpdev.brdinfo = &mlxplat_mlxcpld_ext_pwr[0], 1341 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 1342 }, 1343 { 1344 .label = "pwr4", 1345 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1346 .mask = BIT(3), 1347 .hpdev.brdinfo = &mlxplat_mlxcpld_ext_pwr[1], 1348 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 1349 }, 1350 }; 1351 1352 static struct mlxreg_core_item mlxplat_mlxcpld_ext_items[] = { 1353 { 1354 .data = mlxplat_mlxcpld_ext_psu_items_data, 1355 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1356 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 1357 .mask = MLXPLAT_CPLD_PSU_EXT_MASK, 1358 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 1359 .count = ARRAY_SIZE(mlxplat_mlxcpld_ext_psu_items_data), 1360 .inversed = 1, 1361 .health = false, 1362 }, 1363 { 1364 .data = mlxplat_mlxcpld_ext_pwr_items_data, 1365 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1366 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1367 .mask = MLXPLAT_CPLD_PWR_EXT_MASK, 1368 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 1369 .count = ARRAY_SIZE(mlxplat_mlxcpld_ext_pwr_items_data), 1370 .inversed = 0, 1371 .health = false, 1372 }, 1373 { 1374 .data = mlxplat_mlxcpld_default_ng_fan_items_data, 1375 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1376 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1377 .mask = MLXPLAT_CPLD_FAN_NG_MASK, 1378 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_fan_items_data), 1379 .inversed = 1, 1380 .health = false, 1381 }, 1382 { 1383 .data = mlxplat_mlxcpld_default_asic_items_data, 1384 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1385 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 1386 .mask = MLXPLAT_CPLD_ASIC_MASK, 1387 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data), 1388 .inversed = 0, 1389 .health = true, 1390 }, 1391 { 1392 .data = mlxplat_mlxcpld_default_asic2_items_data, 1393 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1394 .reg = MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET, 1395 .mask = MLXPLAT_CPLD_ASIC_MASK, 1396 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic2_items_data), 1397 .inversed = 0, 1398 .health = true, 1399 } 1400 }; 1401 1402 static struct mlxreg_core_item mlxplat_mlxcpld_ng800_items[] = { 1403 { 1404 .data = mlxplat_mlxcpld_default_ng_psu_items_data, 1405 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1406 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 1407 .mask = MLXPLAT_CPLD_PSU_EXT_MASK, 1408 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 1409 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_psu_items_data), 1410 .inversed = 1, 1411 .health = false, 1412 }, 1413 { 1414 .data = mlxplat_mlxcpld_default_pwr_ng800_items_data, 1415 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1416 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1417 .mask = MLXPLAT_CPLD_PWR_EXT_MASK, 1418 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 1419 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_pwr_ng800_items_data), 1420 .inversed = 0, 1421 .health = false, 1422 }, 1423 { 1424 .data = mlxplat_mlxcpld_default_ng_fan_items_data, 1425 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1426 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1427 .mask = MLXPLAT_CPLD_FAN_NG_MASK, 1428 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_fan_items_data), 1429 .inversed = 1, 1430 .health = false, 1431 }, 1432 { 1433 .data = mlxplat_mlxcpld_default_asic_items_data, 1434 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1435 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 1436 .mask = MLXPLAT_CPLD_ASIC_MASK, 1437 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data), 1438 .inversed = 0, 1439 .health = true, 1440 }, 1441 }; 1442 1443 static 1444 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_ext_data = { 1445 .items = mlxplat_mlxcpld_ext_items, 1446 .count = ARRAY_SIZE(mlxplat_mlxcpld_ext_items), 1447 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 1448 .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF | MLXPLAT_CPLD_AGGR_MASK_COMEX, 1449 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 1450 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW | MLXPLAT_CPLD_LOW_AGGR_MASK_ASIC2, 1451 }; 1452 1453 static 1454 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_ng800_data = { 1455 .items = mlxplat_mlxcpld_ng800_items, 1456 .count = ARRAY_SIZE(mlxplat_mlxcpld_ng800_items), 1457 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 1458 .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF | MLXPLAT_CPLD_AGGR_MASK_COMEX, 1459 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 1460 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW | MLXPLAT_CPLD_LOW_AGGR_MASK_ASIC2, 1461 }; 1462 1463 static struct mlxreg_core_data mlxplat_mlxcpld_modular_pwr_items_data[] = { 1464 { 1465 .label = "pwr1", 1466 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1467 .mask = BIT(0), 1468 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[0], 1469 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 1470 }, 1471 { 1472 .label = "pwr2", 1473 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1474 .mask = BIT(1), 1475 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[1], 1476 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 1477 }, 1478 { 1479 .label = "pwr3", 1480 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1481 .mask = BIT(2), 1482 .hpdev.brdinfo = &mlxplat_mlxcpld_ext_pwr[0], 1483 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 1484 }, 1485 { 1486 .label = "pwr4", 1487 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1488 .mask = BIT(3), 1489 .hpdev.brdinfo = &mlxplat_mlxcpld_ext_pwr[1], 1490 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 1491 }, 1492 }; 1493 1494 static 1495 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_lc_act = { 1496 .irq = MLXPLAT_CPLD_LPC_SYSIRQ, 1497 }; 1498 1499 static struct mlxreg_core_data mlxplat_mlxcpld_modular_asic_items_data[] = { 1500 { 1501 .label = "asic1", 1502 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 1503 .mask = MLXPLAT_CPLD_ASIC_MASK, 1504 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1505 }, 1506 }; 1507 1508 static struct i2c_board_info mlxplat_mlxcpld_lc_i2c_dev[] = { 1509 { 1510 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR), 1511 .platform_data = &mlxplat_mlxcpld_lc_act, 1512 }, 1513 { 1514 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR), 1515 .platform_data = &mlxplat_mlxcpld_lc_act, 1516 }, 1517 { 1518 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR), 1519 .platform_data = &mlxplat_mlxcpld_lc_act, 1520 }, 1521 { 1522 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR), 1523 .platform_data = &mlxplat_mlxcpld_lc_act, 1524 }, 1525 { 1526 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR), 1527 .platform_data = &mlxplat_mlxcpld_lc_act, 1528 }, 1529 { 1530 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR), 1531 .platform_data = &mlxplat_mlxcpld_lc_act, 1532 }, 1533 { 1534 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR), 1535 .platform_data = &mlxplat_mlxcpld_lc_act, 1536 }, 1537 { 1538 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR), 1539 .platform_data = &mlxplat_mlxcpld_lc_act, 1540 }, 1541 }; 1542 1543 static struct mlxreg_core_hotplug_notifier mlxplat_mlxcpld_modular_lc_notifier[] = { 1544 { 1545 .identity = "lc1", 1546 }, 1547 { 1548 .identity = "lc2", 1549 }, 1550 { 1551 .identity = "lc3", 1552 }, 1553 { 1554 .identity = "lc4", 1555 }, 1556 { 1557 .identity = "lc5", 1558 }, 1559 { 1560 .identity = "lc6", 1561 }, 1562 { 1563 .identity = "lc7", 1564 }, 1565 { 1566 .identity = "lc8", 1567 }, 1568 }; 1569 1570 static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_pr_items_data[] = { 1571 { 1572 .label = "lc1_present", 1573 .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET, 1574 .mask = BIT(0), 1575 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[0], 1576 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(0), 1577 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1578 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[0], 1579 .slot = 1, 1580 }, 1581 { 1582 .label = "lc2_present", 1583 .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET, 1584 .mask = BIT(1), 1585 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[1], 1586 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(1), 1587 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1588 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[1], 1589 .slot = 2, 1590 }, 1591 { 1592 .label = "lc3_present", 1593 .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET, 1594 .mask = BIT(2), 1595 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[2], 1596 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(2), 1597 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1598 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[2], 1599 .slot = 3, 1600 }, 1601 { 1602 .label = "lc4_present", 1603 .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET, 1604 .mask = BIT(3), 1605 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[3], 1606 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(3), 1607 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1608 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[3], 1609 .slot = 4, 1610 }, 1611 { 1612 .label = "lc5_present", 1613 .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET, 1614 .mask = BIT(4), 1615 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[4], 1616 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(4), 1617 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1618 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[4], 1619 .slot = 5, 1620 }, 1621 { 1622 .label = "lc6_present", 1623 .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET, 1624 .mask = BIT(5), 1625 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[5], 1626 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(5), 1627 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1628 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[5], 1629 .slot = 6, 1630 }, 1631 { 1632 .label = "lc7_present", 1633 .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET, 1634 .mask = BIT(6), 1635 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[6], 1636 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(6), 1637 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1638 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[6], 1639 .slot = 7, 1640 }, 1641 { 1642 .label = "lc8_present", 1643 .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET, 1644 .mask = BIT(7), 1645 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[7], 1646 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(7), 1647 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1648 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[7], 1649 .slot = 8, 1650 }, 1651 }; 1652 1653 static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_ver_items_data[] = { 1654 { 1655 .label = "lc1_verified", 1656 .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET, 1657 .mask = BIT(0), 1658 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1659 .reg_sync = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1660 .reg_pwr = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 1661 .reg_ena = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 1662 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[0], 1663 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(0), 1664 .hpdev.action = MLXREG_HOTPLUG_DEVICE_PLATFORM_ACTION, 1665 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[0], 1666 .slot = 1, 1667 }, 1668 { 1669 .label = "lc2_verified", 1670 .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET, 1671 .mask = BIT(1), 1672 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1673 .reg_sync = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1674 .reg_pwr = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 1675 .reg_ena = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 1676 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[1], 1677 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(1), 1678 .hpdev.action = MLXREG_HOTPLUG_DEVICE_PLATFORM_ACTION, 1679 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[1], 1680 .slot = 2, 1681 }, 1682 { 1683 .label = "lc3_verified", 1684 .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET, 1685 .mask = BIT(2), 1686 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1687 .reg_sync = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1688 .reg_pwr = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 1689 .reg_ena = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 1690 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[2], 1691 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(2), 1692 .hpdev.action = MLXREG_HOTPLUG_DEVICE_PLATFORM_ACTION, 1693 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[2], 1694 .slot = 3, 1695 }, 1696 { 1697 .label = "lc4_verified", 1698 .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET, 1699 .mask = BIT(3), 1700 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1701 .reg_sync = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1702 .reg_pwr = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 1703 .reg_ena = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 1704 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[3], 1705 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(3), 1706 .hpdev.action = MLXREG_HOTPLUG_DEVICE_PLATFORM_ACTION, 1707 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[3], 1708 .slot = 4, 1709 }, 1710 { 1711 .label = "lc5_verified", 1712 .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET, 1713 .mask = BIT(4), 1714 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1715 .reg_sync = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1716 .reg_pwr = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 1717 .reg_ena = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 1718 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[4], 1719 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(4), 1720 .hpdev.action = MLXREG_HOTPLUG_DEVICE_PLATFORM_ACTION, 1721 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[4], 1722 .slot = 5, 1723 }, 1724 { 1725 .label = "lc6_verified", 1726 .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET, 1727 .mask = BIT(5), 1728 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1729 .reg_sync = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1730 .reg_pwr = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 1731 .reg_ena = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 1732 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[5], 1733 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(5), 1734 .hpdev.action = MLXREG_HOTPLUG_DEVICE_PLATFORM_ACTION, 1735 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[5], 1736 .slot = 6, 1737 }, 1738 { 1739 .label = "lc7_verified", 1740 .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET, 1741 .mask = BIT(6), 1742 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1743 .reg_sync = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1744 .reg_pwr = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 1745 .reg_ena = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 1746 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[6], 1747 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(6), 1748 .hpdev.action = MLXREG_HOTPLUG_DEVICE_PLATFORM_ACTION, 1749 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[6], 1750 .slot = 7, 1751 }, 1752 { 1753 .label = "lc8_verified", 1754 .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET, 1755 .mask = BIT(7), 1756 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1757 .reg_sync = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1758 .reg_pwr = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 1759 .reg_ena = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 1760 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[7], 1761 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(7), 1762 .hpdev.action = MLXREG_HOTPLUG_DEVICE_PLATFORM_ACTION, 1763 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[7], 1764 .slot = 8, 1765 }, 1766 }; 1767 1768 static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_pg_data[] = { 1769 { 1770 .label = "lc1_powered", 1771 .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1772 .mask = BIT(0), 1773 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[0], 1774 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(0), 1775 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1776 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[0], 1777 .slot = 1, 1778 }, 1779 { 1780 .label = "lc2_powered", 1781 .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1782 .mask = BIT(1), 1783 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[1], 1784 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(1), 1785 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1786 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[1], 1787 .slot = 2, 1788 }, 1789 { 1790 .label = "lc3_powered", 1791 .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1792 .mask = BIT(2), 1793 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[2], 1794 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(2), 1795 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1796 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[2], 1797 .slot = 3, 1798 }, 1799 { 1800 .label = "lc4_powered", 1801 .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1802 .mask = BIT(3), 1803 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[3], 1804 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(3), 1805 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1806 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[3], 1807 .slot = 4, 1808 }, 1809 { 1810 .label = "lc5_powered", 1811 .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1812 .mask = BIT(4), 1813 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[4], 1814 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(4), 1815 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1816 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[4], 1817 .slot = 5, 1818 }, 1819 { 1820 .label = "lc6_powered", 1821 .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1822 .mask = BIT(5), 1823 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[5], 1824 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(5), 1825 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1826 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[5], 1827 .slot = 6, 1828 }, 1829 { 1830 .label = "lc7_powered", 1831 .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1832 .mask = BIT(6), 1833 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[6], 1834 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(6), 1835 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1836 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[6], 1837 .slot = 7, 1838 }, 1839 { 1840 .label = "lc8_powered", 1841 .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1842 .mask = BIT(7), 1843 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[7], 1844 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(7), 1845 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1846 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[7], 1847 .slot = 8, 1848 }, 1849 }; 1850 1851 static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_ready_data[] = { 1852 { 1853 .label = "lc1_ready", 1854 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, 1855 .mask = BIT(0), 1856 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[0], 1857 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(0), 1858 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1859 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[0], 1860 .slot = 1, 1861 }, 1862 { 1863 .label = "lc2_ready", 1864 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, 1865 .mask = BIT(1), 1866 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[1], 1867 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(1), 1868 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1869 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[1], 1870 .slot = 2, 1871 }, 1872 { 1873 .label = "lc3_ready", 1874 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, 1875 .mask = BIT(2), 1876 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[2], 1877 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(2), 1878 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1879 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[2], 1880 .slot = 3, 1881 }, 1882 { 1883 .label = "lc4_ready", 1884 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, 1885 .mask = BIT(3), 1886 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[3], 1887 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(3), 1888 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1889 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[3], 1890 .slot = 4, 1891 }, 1892 { 1893 .label = "lc5_ready", 1894 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, 1895 .mask = BIT(4), 1896 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[4], 1897 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(4), 1898 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1899 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[4], 1900 .slot = 5, 1901 }, 1902 { 1903 .label = "lc6_ready", 1904 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, 1905 .mask = BIT(5), 1906 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[5], 1907 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(5), 1908 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1909 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[5], 1910 .slot = 6, 1911 }, 1912 { 1913 .label = "lc7_ready", 1914 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, 1915 .mask = BIT(6), 1916 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[6], 1917 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(6), 1918 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1919 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[6], 1920 .slot = 7, 1921 }, 1922 { 1923 .label = "lc8_ready", 1924 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, 1925 .mask = BIT(7), 1926 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[7], 1927 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(7), 1928 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1929 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[7], 1930 .slot = 8, 1931 }, 1932 }; 1933 1934 static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_synced_data[] = { 1935 { 1936 .label = "lc1_synced", 1937 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1938 .mask = BIT(0), 1939 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[0], 1940 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(0), 1941 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1942 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[0], 1943 .slot = 1, 1944 }, 1945 { 1946 .label = "lc2_synced", 1947 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1948 .mask = BIT(1), 1949 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[1], 1950 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(1), 1951 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1952 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[1], 1953 .slot = 2, 1954 }, 1955 { 1956 .label = "lc3_synced", 1957 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1958 .mask = BIT(2), 1959 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[2], 1960 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(2), 1961 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1962 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[2], 1963 .slot = 3, 1964 }, 1965 { 1966 .label = "lc4_synced", 1967 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1968 .mask = BIT(3), 1969 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[3], 1970 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(3), 1971 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1972 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[3], 1973 .slot = 4, 1974 }, 1975 { 1976 .label = "lc5_synced", 1977 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1978 .mask = BIT(4), 1979 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[4], 1980 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(4), 1981 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1982 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[4], 1983 .slot = 5, 1984 }, 1985 { 1986 .label = "lc6_synced", 1987 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1988 .mask = BIT(5), 1989 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[5], 1990 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(5), 1991 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1992 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[5], 1993 .slot = 6, 1994 }, 1995 { 1996 .label = "lc7_synced", 1997 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1998 .mask = BIT(6), 1999 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[6], 2000 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(6), 2001 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 2002 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[6], 2003 .slot = 7, 2004 }, 2005 { 2006 .label = "lc8_synced", 2007 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 2008 .mask = BIT(7), 2009 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[7], 2010 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(7), 2011 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 2012 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[7], 2013 .slot = 8, 2014 }, 2015 }; 2016 2017 static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_act_data[] = { 2018 { 2019 .label = "lc1_active", 2020 .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET, 2021 .mask = BIT(0), 2022 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[0], 2023 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(0), 2024 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 2025 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[0], 2026 .slot = 1, 2027 }, 2028 { 2029 .label = "lc2_active", 2030 .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET, 2031 .mask = BIT(1), 2032 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[1], 2033 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(1), 2034 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 2035 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[1], 2036 .slot = 2, 2037 }, 2038 { 2039 .label = "lc3_active", 2040 .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET, 2041 .mask = BIT(2), 2042 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[2], 2043 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(2), 2044 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 2045 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[2], 2046 .slot = 3, 2047 }, 2048 { 2049 .label = "lc4_active", 2050 .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET, 2051 .mask = BIT(3), 2052 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[3], 2053 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(3), 2054 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 2055 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[3], 2056 .slot = 4, 2057 }, 2058 { 2059 .label = "lc5_active", 2060 .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET, 2061 .mask = BIT(4), 2062 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[4], 2063 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(4), 2064 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 2065 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[4], 2066 .slot = 5, 2067 }, 2068 { 2069 .label = "lc6_active", 2070 .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET, 2071 .mask = BIT(5), 2072 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[5], 2073 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(5), 2074 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 2075 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[5], 2076 .slot = 6, 2077 }, 2078 { 2079 .label = "lc7_active", 2080 .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET, 2081 .mask = BIT(6), 2082 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[6], 2083 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(6), 2084 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 2085 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[6], 2086 .slot = 7, 2087 }, 2088 { 2089 .label = "lc8_active", 2090 .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET, 2091 .mask = BIT(7), 2092 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[7], 2093 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(7), 2094 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 2095 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[7], 2096 .slot = 8, 2097 }, 2098 }; 2099 2100 static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_sd_data[] = { 2101 { 2102 .label = "lc1_shutdown", 2103 .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET, 2104 .mask = BIT(0), 2105 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[0], 2106 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(0), 2107 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 2108 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[0], 2109 .slot = 1, 2110 }, 2111 { 2112 .label = "lc2_shutdown", 2113 .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET, 2114 .mask = BIT(1), 2115 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[1], 2116 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(1), 2117 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 2118 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[1], 2119 .slot = 2, 2120 }, 2121 { 2122 .label = "lc3_shutdown", 2123 .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET, 2124 .mask = BIT(2), 2125 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[2], 2126 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(2), 2127 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 2128 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[2], 2129 .slot = 3, 2130 }, 2131 { 2132 .label = "lc4_shutdown", 2133 .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET, 2134 .mask = BIT(3), 2135 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[3], 2136 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(3), 2137 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 2138 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[3], 2139 .slot = 4, 2140 }, 2141 { 2142 .label = "lc5_shutdown", 2143 .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET, 2144 .mask = BIT(4), 2145 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[4], 2146 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(4), 2147 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 2148 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[4], 2149 .slot = 5, 2150 }, 2151 { 2152 .label = "lc6_shutdown", 2153 .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET, 2154 .mask = BIT(5), 2155 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[5], 2156 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(5), 2157 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 2158 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[5], 2159 .slot = 6, 2160 }, 2161 { 2162 .label = "lc7_shutdown", 2163 .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET, 2164 .mask = BIT(6), 2165 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[6], 2166 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(6), 2167 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 2168 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[6], 2169 .slot = 7, 2170 }, 2171 { 2172 .label = "lc8_shutdown", 2173 .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET, 2174 .mask = BIT(7), 2175 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[7], 2176 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(7), 2177 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 2178 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[7], 2179 .slot = 8, 2180 }, 2181 }; 2182 2183 static struct mlxreg_core_item mlxplat_mlxcpld_modular_items[] = { 2184 { 2185 .data = mlxplat_mlxcpld_ext_psu_items_data, 2186 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 2187 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 2188 .mask = MLXPLAT_CPLD_PSU_EXT_MASK, 2189 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 2190 .count = ARRAY_SIZE(mlxplat_mlxcpld_ext_psu_items_data), 2191 .inversed = 1, 2192 .health = false, 2193 }, 2194 { 2195 .data = mlxplat_mlxcpld_modular_pwr_items_data, 2196 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 2197 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 2198 .mask = MLXPLAT_CPLD_PWR_EXT_MASK, 2199 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 2200 .count = ARRAY_SIZE(mlxplat_mlxcpld_ext_pwr_items_data), 2201 .inversed = 0, 2202 .health = false, 2203 }, 2204 { 2205 .data = mlxplat_mlxcpld_default_ng_fan_items_data, 2206 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 2207 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 2208 .mask = MLXPLAT_CPLD_FAN_NG_MASK, 2209 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_fan_items_data), 2210 .inversed = 1, 2211 .health = false, 2212 }, 2213 { 2214 .data = mlxplat_mlxcpld_modular_asic_items_data, 2215 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 2216 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 2217 .mask = MLXPLAT_CPLD_ASIC_MASK, 2218 .count = ARRAY_SIZE(mlxplat_mlxcpld_modular_asic_items_data), 2219 .inversed = 0, 2220 .health = true, 2221 }, 2222 { 2223 .data = mlxplat_mlxcpld_modular_lc_pr_items_data, 2224 .kind = MLXREG_HOTPLUG_LC_PRESENT, 2225 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_LC, 2226 .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET, 2227 .mask = MLXPLAT_CPLD_LPC_LC_MASK, 2228 .count = ARRAY_SIZE(mlxplat_mlxcpld_modular_lc_pr_items_data), 2229 .inversed = 1, 2230 .health = false, 2231 }, 2232 { 2233 .data = mlxplat_mlxcpld_modular_lc_ver_items_data, 2234 .kind = MLXREG_HOTPLUG_LC_VERIFIED, 2235 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_LC, 2236 .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET, 2237 .mask = MLXPLAT_CPLD_LPC_LC_MASK, 2238 .count = ARRAY_SIZE(mlxplat_mlxcpld_modular_lc_ver_items_data), 2239 .inversed = 0, 2240 .health = false, 2241 }, 2242 { 2243 .data = mlxplat_mlxcpld_modular_lc_pg_data, 2244 .kind = MLXREG_HOTPLUG_LC_POWERED, 2245 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_LC, 2246 .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 2247 .mask = MLXPLAT_CPLD_LPC_LC_MASK, 2248 .count = ARRAY_SIZE(mlxplat_mlxcpld_modular_lc_pg_data), 2249 .inversed = 0, 2250 .health = false, 2251 }, 2252 { 2253 .data = mlxplat_mlxcpld_modular_lc_ready_data, 2254 .kind = MLXREG_HOTPLUG_LC_READY, 2255 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_LC, 2256 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, 2257 .mask = MLXPLAT_CPLD_LPC_LC_MASK, 2258 .count = ARRAY_SIZE(mlxplat_mlxcpld_modular_lc_ready_data), 2259 .inversed = 0, 2260 .health = false, 2261 }, 2262 { 2263 .data = mlxplat_mlxcpld_modular_lc_synced_data, 2264 .kind = MLXREG_HOTPLUG_LC_SYNCED, 2265 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_LC, 2266 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 2267 .mask = MLXPLAT_CPLD_LPC_LC_MASK, 2268 .count = ARRAY_SIZE(mlxplat_mlxcpld_modular_lc_synced_data), 2269 .inversed = 0, 2270 .health = false, 2271 }, 2272 { 2273 .data = mlxplat_mlxcpld_modular_lc_act_data, 2274 .kind = MLXREG_HOTPLUG_LC_ACTIVE, 2275 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_LC, 2276 .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET, 2277 .mask = MLXPLAT_CPLD_LPC_LC_MASK, 2278 .count = ARRAY_SIZE(mlxplat_mlxcpld_modular_lc_act_data), 2279 .inversed = 0, 2280 .health = false, 2281 }, 2282 { 2283 .data = mlxplat_mlxcpld_modular_lc_sd_data, 2284 .kind = MLXREG_HOTPLUG_LC_THERMAL, 2285 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_LC, 2286 .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET, 2287 .mask = MLXPLAT_CPLD_LPC_LC_MASK, 2288 .count = ARRAY_SIZE(mlxplat_mlxcpld_modular_lc_sd_data), 2289 .inversed = 0, 2290 .health = false, 2291 }, 2292 }; 2293 2294 static 2295 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_modular_data = { 2296 .items = mlxplat_mlxcpld_modular_items, 2297 .count = ARRAY_SIZE(mlxplat_mlxcpld_modular_items), 2298 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 2299 .mask = MLXPLAT_CPLD_AGGR_MASK_MODULAR, 2300 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 2301 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, 2302 }; 2303 2304 /* Platform hotplug for NVLink blade systems family data */ 2305 static struct mlxreg_core_data mlxplat_mlxcpld_global_wp_items_data[] = { 2306 { 2307 .label = "global_wp_grant", 2308 .reg = MLXPLAT_CPLD_LPC_REG_GWP_OFFSET, 2309 .mask = MLXPLAT_CPLD_GWP_MASK, 2310 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2311 }, 2312 }; 2313 2314 static struct mlxreg_core_item mlxplat_mlxcpld_chassis_blade_items[] = { 2315 { 2316 .data = mlxplat_mlxcpld_global_wp_items_data, 2317 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 2318 .reg = MLXPLAT_CPLD_LPC_REG_GWP_OFFSET, 2319 .mask = MLXPLAT_CPLD_GWP_MASK, 2320 .count = ARRAY_SIZE(mlxplat_mlxcpld_global_wp_items_data), 2321 .inversed = 0, 2322 .health = false, 2323 }, 2324 }; 2325 2326 static 2327 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_chassis_blade_data = { 2328 .items = mlxplat_mlxcpld_chassis_blade_items, 2329 .count = ARRAY_SIZE(mlxplat_mlxcpld_chassis_blade_items), 2330 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 2331 .mask = MLXPLAT_CPLD_AGGR_MASK_COMEX, 2332 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 2333 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, 2334 }; 2335 2336 /* Platform hotplug for switch systems family data */ 2337 static struct mlxreg_core_data mlxplat_mlxcpld_erot_ap_items_data[] = { 2338 { 2339 .label = "erot1_ap", 2340 .reg = MLXPLAT_CPLD_LPC_REG_EROT_OFFSET, 2341 .mask = BIT(0), 2342 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2343 }, 2344 { 2345 .label = "erot2_ap", 2346 .reg = MLXPLAT_CPLD_LPC_REG_EROT_OFFSET, 2347 .mask = BIT(1), 2348 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2349 }, 2350 }; 2351 2352 static struct mlxreg_core_data mlxplat_mlxcpld_erot_error_items_data[] = { 2353 { 2354 .label = "erot1_error", 2355 .reg = MLXPLAT_CPLD_LPC_REG_EROTE_OFFSET, 2356 .mask = BIT(0), 2357 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2358 }, 2359 { 2360 .label = "erot2_error", 2361 .reg = MLXPLAT_CPLD_LPC_REG_EROTE_OFFSET, 2362 .mask = BIT(1), 2363 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2364 }, 2365 }; 2366 2367 static struct mlxreg_core_item mlxplat_mlxcpld_rack_switch_items[] = { 2368 { 2369 .data = mlxplat_mlxcpld_ext_psu_items_data, 2370 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 2371 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 2372 .mask = MLXPLAT_CPLD_PSU_EXT_MASK, 2373 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 2374 .count = ARRAY_SIZE(mlxplat_mlxcpld_ext_psu_items_data), 2375 .inversed = 1, 2376 .health = false, 2377 }, 2378 { 2379 .data = mlxplat_mlxcpld_ext_pwr_items_data, 2380 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 2381 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 2382 .mask = MLXPLAT_CPLD_PWR_EXT_MASK, 2383 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 2384 .count = ARRAY_SIZE(mlxplat_mlxcpld_ext_pwr_items_data), 2385 .inversed = 0, 2386 .health = false, 2387 }, 2388 { 2389 .data = mlxplat_mlxcpld_default_ng_fan_items_data, 2390 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 2391 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 2392 .mask = MLXPLAT_CPLD_FAN_NG_MASK, 2393 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_fan_items_data), 2394 .inversed = 1, 2395 .health = false, 2396 }, 2397 { 2398 .data = mlxplat_mlxcpld_erot_ap_items_data, 2399 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 2400 .reg = MLXPLAT_CPLD_LPC_REG_EROT_OFFSET, 2401 .mask = MLXPLAT_CPLD_EROT_MASK, 2402 .count = ARRAY_SIZE(mlxplat_mlxcpld_erot_ap_items_data), 2403 .inversed = 1, 2404 .health = false, 2405 }, 2406 { 2407 .data = mlxplat_mlxcpld_erot_error_items_data, 2408 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 2409 .reg = MLXPLAT_CPLD_LPC_REG_EROTE_OFFSET, 2410 .mask = MLXPLAT_CPLD_EROT_MASK, 2411 .count = ARRAY_SIZE(mlxplat_mlxcpld_erot_error_items_data), 2412 .inversed = 1, 2413 .health = false, 2414 }, 2415 }; 2416 2417 static 2418 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_rack_switch_data = { 2419 .items = mlxplat_mlxcpld_rack_switch_items, 2420 .count = ARRAY_SIZE(mlxplat_mlxcpld_rack_switch_items), 2421 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 2422 .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF | MLXPLAT_CPLD_AGGR_MASK_COMEX, 2423 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 2424 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, 2425 }; 2426 2427 /* Platform hotplug XDR and smart switch system family data */ 2428 static struct mlxreg_core_data mlxplat_mlxcpld_xdr_psu_items_data[] = { 2429 { 2430 .label = "psu1", 2431 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 2432 .mask = BIT(0), 2433 .slot = 1, 2434 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 2435 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2436 }, 2437 { 2438 .label = "psu2", 2439 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 2440 .mask = BIT(1), 2441 .slot = 2, 2442 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 2443 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2444 }, 2445 { 2446 .label = "psu3", 2447 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 2448 .mask = BIT(2), 2449 .slot = 3, 2450 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 2451 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2452 }, 2453 { 2454 .label = "psu4", 2455 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 2456 .mask = BIT(3), 2457 .slot = 4, 2458 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 2459 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2460 }, 2461 { 2462 .label = "psu5", 2463 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 2464 .mask = BIT(4), 2465 .slot = 5, 2466 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 2467 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2468 }, 2469 { 2470 .label = "psu6", 2471 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 2472 .mask = BIT(5), 2473 .slot = 6, 2474 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 2475 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2476 }, 2477 { 2478 .label = "psu7", 2479 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 2480 .mask = BIT(6), 2481 .slot = 7, 2482 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 2483 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2484 }, 2485 { 2486 .label = "psu8", 2487 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 2488 .mask = BIT(7), 2489 .slot = 8, 2490 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 2491 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2492 }, 2493 }; 2494 2495 static struct mlxreg_core_data mlxplat_mlxcpld_xdr_pwr_items_data[] = { 2496 { 2497 .label = "pwr1", 2498 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 2499 .mask = BIT(0), 2500 .slot = 1, 2501 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 2502 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[0], 2503 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 2504 }, 2505 { 2506 .label = "pwr2", 2507 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 2508 .mask = BIT(1), 2509 .slot = 2, 2510 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 2511 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[1], 2512 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 2513 }, 2514 { 2515 .label = "pwr3", 2516 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 2517 .mask = BIT(2), 2518 .slot = 3, 2519 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 2520 .hpdev.brdinfo = &mlxplat_mlxcpld_ext_pwr[0], 2521 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 2522 }, 2523 { 2524 .label = "pwr4", 2525 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 2526 .mask = BIT(3), 2527 .slot = 4, 2528 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 2529 .hpdev.brdinfo = &mlxplat_mlxcpld_ext_pwr[1], 2530 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 2531 }, 2532 { 2533 .label = "pwr5", 2534 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 2535 .mask = BIT(4), 2536 .slot = 5, 2537 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 2538 .hpdev.brdinfo = &mlxplat_mlxcpld_xdr_pwr[0], 2539 .hpdev.nr = MLXPLAT_CPLD_PSU_XDR_NR, 2540 }, 2541 { 2542 .label = "pwr6", 2543 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 2544 .mask = BIT(5), 2545 .slot = 6, 2546 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 2547 .hpdev.brdinfo = &mlxplat_mlxcpld_xdr_pwr[1], 2548 .hpdev.nr = MLXPLAT_CPLD_PSU_XDR_NR, 2549 }, 2550 { 2551 .label = "pwr7", 2552 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 2553 .mask = BIT(6), 2554 .slot = 7, 2555 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 2556 .hpdev.brdinfo = &mlxplat_mlxcpld_xdr_pwr[2], 2557 .hpdev.nr = MLXPLAT_CPLD_PSU_XDR_NR, 2558 }, 2559 { 2560 .label = "pwr8", 2561 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 2562 .mask = BIT(7), 2563 .slot = 8, 2564 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 2565 .hpdev.brdinfo = &mlxplat_mlxcpld_xdr_pwr[3], 2566 .hpdev.nr = MLXPLAT_CPLD_PSU_XDR_NR, 2567 }, 2568 }; 2569 2570 static struct mlxreg_core_data mlxplat_mlxcpld_xdr_fan_items_data[] = { 2571 { 2572 .label = "fan1", 2573 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 2574 .mask = BIT(0), 2575 .slot = 1, 2576 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2577 .bit = BIT(0), 2578 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2579 }, 2580 { 2581 .label = "fan2", 2582 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 2583 .mask = BIT(1), 2584 .slot = 2, 2585 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2586 .bit = BIT(1), 2587 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2588 }, 2589 { 2590 .label = "fan3", 2591 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 2592 .mask = BIT(2), 2593 .slot = 3, 2594 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2595 .bit = BIT(2), 2596 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2597 }, 2598 { 2599 .label = "fan4", 2600 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 2601 .mask = BIT(3), 2602 .slot = 4, 2603 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2604 .bit = BIT(3), 2605 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2606 }, 2607 { 2608 .label = "fan5", 2609 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 2610 .mask = BIT(4), 2611 .slot = 5, 2612 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2613 .bit = BIT(4), 2614 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2615 }, 2616 { 2617 .label = "fan6", 2618 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 2619 .mask = BIT(5), 2620 .slot = 6, 2621 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2622 .bit = BIT(5), 2623 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2624 }, 2625 { 2626 .label = "fan7", 2627 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 2628 .mask = BIT(6), 2629 .slot = 7, 2630 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2631 .bit = BIT(6), 2632 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2633 }, 2634 { 2635 .label = "fan8", 2636 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 2637 .mask = BIT(7), 2638 .slot = 8, 2639 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2640 .bit = BIT(7), 2641 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2642 }, 2643 }; 2644 2645 static struct mlxreg_core_data mlxplat_mlxcpld_xdr_asic1_items_data[] = { 2646 { 2647 .label = "asic1", 2648 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 2649 .mask = MLXPLAT_CPLD_ASIC_MASK, 2650 .slot = 1, 2651 .capability = MLXPLAT_CPLD_LPC_REG_ASIC_CAP_OFFSET, 2652 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2653 } 2654 }; 2655 2656 /* Platform hotplug for smart switch systems families data */ 2657 static struct mlxreg_core_data mlxplat_mlxcpld_smart_switch_dpu_ready_data[] = { 2658 { 2659 .label = "dpu1_ready", 2660 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, 2661 .mask = BIT(0), 2662 .slot = 1, 2663 .capability = MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET, 2664 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2665 }, 2666 { 2667 .label = "dpu2_ready", 2668 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, 2669 .mask = BIT(1), 2670 .slot = 2, 2671 .capability = MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET, 2672 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2673 }, 2674 { 2675 .label = "dpu3_ready", 2676 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, 2677 .mask = BIT(2), 2678 .slot = 3, 2679 .capability = MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET, 2680 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2681 }, 2682 { 2683 .label = "dpu4_ready", 2684 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, 2685 .mask = BIT(3), 2686 .slot = 4, 2687 .capability = MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET, 2688 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2689 }, 2690 }; 2691 2692 static struct mlxreg_core_data mlxplat_mlxcpld_smart_switch_dpu_shtdn_ready_data[] = { 2693 { 2694 .label = "dpu1_shtdn_ready", 2695 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 2696 .mask = BIT(0), 2697 .slot = 1, 2698 .capability = MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET, 2699 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2700 }, 2701 { 2702 .label = "dpu2_shtdn_ready", 2703 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 2704 .mask = BIT(1), 2705 .slot = 2, 2706 .capability = MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET, 2707 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2708 }, 2709 { 2710 .label = "dpu3_shtdn_ready", 2711 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 2712 .mask = BIT(2), 2713 .slot = 3, 2714 .capability = MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET, 2715 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2716 }, 2717 { 2718 .label = "dpu4_shtdn_ready", 2719 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 2720 .mask = BIT(3), 2721 .slot = 4, 2722 .capability = MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET, 2723 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2724 }, 2725 }; 2726 2727 static struct mlxreg_core_item mlxplat_mlxcpld_smart_switch_items[] = { 2728 { 2729 .data = mlxplat_mlxcpld_xdr_psu_items_data, 2730 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 2731 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 2732 .mask = MLXPLAT_CPLD_PSU_XDR_MASK, 2733 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 2734 .count = ARRAY_SIZE(mlxplat_mlxcpld_xdr_psu_items_data), 2735 .inversed = 1, 2736 .health = false, 2737 }, 2738 { 2739 .data = mlxplat_mlxcpld_xdr_pwr_items_data, 2740 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 2741 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 2742 .mask = MLXPLAT_CPLD_PWR_XDR_MASK, 2743 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 2744 .count = ARRAY_SIZE(mlxplat_mlxcpld_xdr_pwr_items_data), 2745 .inversed = 0, 2746 .health = false, 2747 }, 2748 { 2749 .data = mlxplat_mlxcpld_xdr_fan_items_data, 2750 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 2751 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 2752 .mask = MLXPLAT_CPLD_FAN_XDR_MASK, 2753 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2754 .count = ARRAY_SIZE(mlxplat_mlxcpld_xdr_fan_items_data), 2755 .inversed = 1, 2756 .health = false, 2757 }, 2758 { 2759 .data = mlxplat_mlxcpld_xdr_asic1_items_data, 2760 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 2761 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 2762 .mask = MLXPLAT_CPLD_ASIC_XDR_MASK, 2763 .capability = MLXPLAT_CPLD_LPC_REG_ASIC_CAP_OFFSET, 2764 .count = ARRAY_SIZE(mlxplat_mlxcpld_xdr_asic1_items_data), 2765 .inversed = 0, 2766 .health = true, 2767 }, 2768 { 2769 .data = mlxplat_mlxcpld_smart_switch_dpu_ready_data, 2770 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_DPU_CORE, 2771 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, 2772 .mask = MLXPLAT_CPLD_DPU_MASK, 2773 .capability = MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET, 2774 .count = ARRAY_SIZE(mlxplat_mlxcpld_smart_switch_dpu_ready_data), 2775 .inversed = 1, 2776 .health = false, 2777 }, 2778 { 2779 .data = mlxplat_mlxcpld_smart_switch_dpu_shtdn_ready_data, 2780 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_DPU_CORE, 2781 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 2782 .mask = MLXPLAT_CPLD_DPU_MASK, 2783 .capability = MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET, 2784 .count = ARRAY_SIZE(mlxplat_mlxcpld_smart_switch_dpu_shtdn_ready_data), 2785 .inversed = 1, 2786 .health = false, 2787 }, 2788 }; 2789 2790 static 2791 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_smart_switch_data = { 2792 .items = mlxplat_mlxcpld_smart_switch_items, 2793 .count = ARRAY_SIZE(mlxplat_mlxcpld_smart_switch_items), 2794 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 2795 .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF | MLXPLAT_CPLD_AGGR_MASK_COMEX | 2796 MLXPLAT_CPLD_AGGR_MASK_DPU_BRD | MLXPLAT_CPLD_AGGR_MASK_DPU_CORE, 2797 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 2798 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, 2799 }; 2800 2801 /* Smart switch data processor units data */ 2802 static struct i2c_board_info mlxplat_mlxcpld_smart_switch_dpu_devs[] = { 2803 { 2804 I2C_BOARD_INFO("mlxreg-dpu", MLXPLAT_CPLD_DPU_ADDR), 2805 .irq = MLXPLAT_CPLD_LPC_SYSIRQ, 2806 }, 2807 { 2808 I2C_BOARD_INFO("mlxreg-dpu", MLXPLAT_CPLD_DPU_ADDR), 2809 .irq = MLXPLAT_CPLD_LPC_SYSIRQ, 2810 }, 2811 { 2812 I2C_BOARD_INFO("mlxreg-dpu", MLXPLAT_CPLD_DPU_ADDR), 2813 .irq = MLXPLAT_CPLD_LPC_SYSIRQ, 2814 }, 2815 { 2816 I2C_BOARD_INFO("mlxreg-dpu", MLXPLAT_CPLD_DPU_ADDR), 2817 .irq = MLXPLAT_CPLD_LPC_SYSIRQ, 2818 }, 2819 }; 2820 2821 static struct mlxreg_core_data mlxplat_mlxcpld_smart_switch_dpu_data[] = { 2822 { 2823 .label = "dpu1", 2824 .hpdev.brdinfo = &mlxplat_mlxcpld_smart_switch_dpu_devs[0], 2825 .hpdev.nr = MLXPLAT_CPLD_NR_DPU_BASE, 2826 .slot = 1, 2827 }, 2828 { 2829 .label = "dpu2", 2830 .hpdev.brdinfo = &mlxplat_mlxcpld_smart_switch_dpu_devs[1], 2831 .hpdev.nr = MLXPLAT_CPLD_NR_DPU_BASE + 1, 2832 .slot = 2, 2833 }, 2834 { 2835 .label = "dpu3", 2836 .hpdev.brdinfo = &mlxplat_mlxcpld_smart_switch_dpu_devs[2], 2837 .hpdev.nr = MLXPLAT_CPLD_NR_DPU_BASE + 2, 2838 .slot = 3, 2839 }, 2840 { 2841 .label = "dpu4", 2842 .hpdev.brdinfo = &mlxplat_mlxcpld_smart_switch_dpu_devs[3], 2843 .hpdev.nr = MLXPLAT_CPLD_NR_DPU_BASE + 3, 2844 .slot = 4, 2845 }, 2846 }; 2847 2848 /* Callback performs graceful shutdown after notification about power button event */ 2849 static int 2850 mlxplat_mlxcpld_l1_switch_pwr_events_handler(void *handle, enum mlxreg_hotplug_kind kind, 2851 u8 action) 2852 { 2853 if (action) { 2854 dev_info(&mlxplat_dev->dev, "System shutdown due to short press of power button"); 2855 kernel_power_off(); 2856 } 2857 2858 return 0; 2859 } 2860 2861 static struct mlxreg_core_hotplug_notifier mlxplat_mlxcpld_l1_switch_pwr_events_notifier = { 2862 .user_handler = mlxplat_mlxcpld_l1_switch_pwr_events_handler, 2863 }; 2864 2865 /* Platform hotplug for l1 switch systems family data */ 2866 static struct mlxreg_core_data mlxplat_mlxcpld_l1_switch_pwr_events_items_data[] = { 2867 { 2868 .label = "power_button", 2869 .reg = MLXPLAT_CPLD_LPC_REG_PWRB_OFFSET, 2870 .mask = MLXPLAT_CPLD_PWR_BUTTON_MASK, 2871 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2872 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 2873 .hpdev.notifier = &mlxplat_mlxcpld_l1_switch_pwr_events_notifier, 2874 }, 2875 }; 2876 2877 /* Callback activates latch reset flow after notification about intrusion event */ 2878 static int 2879 mlxplat_mlxcpld_l1_switch_intrusion_events_handler(void *handle, enum mlxreg_hotplug_kind kind, 2880 u8 action) 2881 { 2882 struct mlxplat_priv *priv = platform_get_drvdata(mlxplat_dev); 2883 u32 regval; 2884 int err; 2885 2886 err = regmap_read(priv->regmap, MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, ®val); 2887 if (err) 2888 goto fail_regmap_read; 2889 2890 if (action) { 2891 dev_info(&mlxplat_dev->dev, "Detected intrusion - system latch is opened"); 2892 err = regmap_write(priv->regmap, MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 2893 regval | MLXPLAT_CPLD_LATCH_RST_MASK); 2894 } else { 2895 dev_info(&mlxplat_dev->dev, "System latch is properly closed"); 2896 err = regmap_write(priv->regmap, MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 2897 regval & ~MLXPLAT_CPLD_LATCH_RST_MASK); 2898 } 2899 2900 if (err) 2901 goto fail_regmap_write; 2902 2903 return 0; 2904 2905 fail_regmap_read: 2906 fail_regmap_write: 2907 dev_err(&mlxplat_dev->dev, "Register access failed"); 2908 return err; 2909 } 2910 2911 static struct mlxreg_core_hotplug_notifier mlxplat_mlxcpld_l1_switch_intrusion_events_notifier = { 2912 .user_handler = mlxplat_mlxcpld_l1_switch_intrusion_events_handler, 2913 }; 2914 2915 static struct mlxreg_core_data mlxplat_mlxcpld_l1_switch_health_events_items_data[] = { 2916 { 2917 .label = "thermal1_pdb", 2918 .reg = MLXPLAT_CPLD_LPC_REG_BRD_OFFSET, 2919 .mask = MLXPLAT_CPLD_THERMAL1_PDB_MASK, 2920 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2921 }, 2922 { 2923 .label = "thermal2_pdb", 2924 .reg = MLXPLAT_CPLD_LPC_REG_BRD_OFFSET, 2925 .mask = MLXPLAT_CPLD_THERMAL2_PDB_MASK, 2926 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2927 }, 2928 { 2929 .label = "intrusion", 2930 .reg = MLXPLAT_CPLD_LPC_REG_BRD_OFFSET, 2931 .mask = MLXPLAT_CPLD_INTRUSION_MASK, 2932 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2933 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 2934 .hpdev.notifier = &mlxplat_mlxcpld_l1_switch_intrusion_events_notifier, 2935 }, 2936 { 2937 .label = "pwm_pg", 2938 .reg = MLXPLAT_CPLD_LPC_REG_BRD_OFFSET, 2939 .mask = MLXPLAT_CPLD_PWM_PG_MASK, 2940 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2941 }, 2942 }; 2943 2944 static struct mlxreg_core_item mlxplat_mlxcpld_l1_switch_events_items[] = { 2945 { 2946 .data = mlxplat_mlxcpld_default_ng_fan_items_data, 2947 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 2948 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 2949 .mask = MLXPLAT_CPLD_FAN_NG_MASK, 2950 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_fan_items_data), 2951 .inversed = 1, 2952 .health = false, 2953 }, 2954 { 2955 .data = mlxplat_mlxcpld_erot_ap_items_data, 2956 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 2957 .reg = MLXPLAT_CPLD_LPC_REG_EROT_OFFSET, 2958 .mask = MLXPLAT_CPLD_EROT_MASK, 2959 .count = ARRAY_SIZE(mlxplat_mlxcpld_erot_ap_items_data), 2960 .inversed = 1, 2961 .health = false, 2962 }, 2963 { 2964 .data = mlxplat_mlxcpld_erot_error_items_data, 2965 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 2966 .reg = MLXPLAT_CPLD_LPC_REG_EROTE_OFFSET, 2967 .mask = MLXPLAT_CPLD_EROT_MASK, 2968 .count = ARRAY_SIZE(mlxplat_mlxcpld_erot_error_items_data), 2969 .inversed = 1, 2970 .health = false, 2971 }, 2972 { 2973 .data = mlxplat_mlxcpld_l1_switch_pwr_events_items_data, 2974 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 2975 .reg = MLXPLAT_CPLD_LPC_REG_PWRB_OFFSET, 2976 .mask = MLXPLAT_CPLD_PWR_BUTTON_MASK, 2977 .count = ARRAY_SIZE(mlxplat_mlxcpld_l1_switch_pwr_events_items_data), 2978 .inversed = 1, 2979 .health = false, 2980 }, 2981 { 2982 .data = mlxplat_mlxcpld_l1_switch_health_events_items_data, 2983 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 2984 .reg = MLXPLAT_CPLD_LPC_REG_BRD_OFFSET, 2985 .mask = MLXPLAT_CPLD_L1_CHA_HEALTH_MASK, 2986 .count = ARRAY_SIZE(mlxplat_mlxcpld_l1_switch_health_events_items_data), 2987 .inversed = 1, 2988 .health = false, 2989 .ind = 8, 2990 }, 2991 }; 2992 2993 static 2994 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_l1_switch_data = { 2995 .items = mlxplat_mlxcpld_l1_switch_events_items, 2996 .count = ARRAY_SIZE(mlxplat_mlxcpld_l1_switch_events_items), 2997 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 2998 .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF | MLXPLAT_CPLD_AGGR_MASK_COMEX, 2999 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 3000 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW | MLXPLAT_CPLD_LOW_AGGR_MASK_PWR_BUT, 3001 }; 3002 3003 /* Platform hotplug for 800G systems family data */ 3004 static struct mlxreg_core_item mlxplat_mlxcpld_ng800_hi171_items[] = { 3005 { 3006 .data = mlxplat_mlxcpld_ext_psu_items_data, 3007 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 3008 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 3009 .mask = MLXPLAT_CPLD_PSU_EXT_MASK, 3010 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 3011 .count = ARRAY_SIZE(mlxplat_mlxcpld_ext_psu_items_data), 3012 .inversed = 1, 3013 .health = false, 3014 }, 3015 { 3016 .data = mlxplat_mlxcpld_modular_pwr_items_data, 3017 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 3018 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 3019 .mask = MLXPLAT_CPLD_PWR_EXT_MASK, 3020 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 3021 .count = ARRAY_SIZE(mlxplat_mlxcpld_ext_pwr_items_data), 3022 .inversed = 0, 3023 .health = false, 3024 }, 3025 { 3026 .data = mlxplat_mlxcpld_xdr_fan_items_data, 3027 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 3028 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 3029 .mask = MLXPLAT_CPLD_FAN_XDR_MASK, 3030 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3031 .count = ARRAY_SIZE(mlxplat_mlxcpld_xdr_fan_items_data), 3032 .inversed = 1, 3033 .health = false, 3034 }, 3035 { 3036 .data = mlxplat_mlxcpld_default_asic_items_data, 3037 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 3038 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 3039 .mask = MLXPLAT_CPLD_ASIC_MASK, 3040 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data), 3041 .inversed = 0, 3042 .health = true, 3043 }, 3044 }; 3045 3046 static 3047 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_ng800_hi171_data = { 3048 .items = mlxplat_mlxcpld_ng800_hi171_items, 3049 .count = ARRAY_SIZE(mlxplat_mlxcpld_ng800_hi171_items), 3050 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 3051 .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF | MLXPLAT_CPLD_AGGR_MASK_COMEX, 3052 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 3053 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW | MLXPLAT_CPLD_LOW_AGGR_MASK_ASIC2, 3054 }; 3055 3056 /* Platform led default data */ 3057 static struct mlxreg_core_data mlxplat_mlxcpld_default_led_data[] = { 3058 { 3059 .label = "status:green", 3060 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 3061 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3062 }, 3063 { 3064 .label = "status:red", 3065 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 3066 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK 3067 }, 3068 { 3069 .label = "psu:green", 3070 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 3071 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3072 }, 3073 { 3074 .label = "psu:red", 3075 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 3076 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3077 }, 3078 { 3079 .label = "fan1:green", 3080 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 3081 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3082 }, 3083 { 3084 .label = "fan1:red", 3085 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 3086 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3087 }, 3088 { 3089 .label = "fan2:green", 3090 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 3091 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3092 }, 3093 { 3094 .label = "fan2:red", 3095 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 3096 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3097 }, 3098 { 3099 .label = "fan3:green", 3100 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 3101 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3102 }, 3103 { 3104 .label = "fan3:red", 3105 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 3106 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3107 }, 3108 { 3109 .label = "fan4:green", 3110 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 3111 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3112 }, 3113 { 3114 .label = "fan4:red", 3115 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 3116 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3117 }, 3118 }; 3119 3120 static struct mlxreg_core_platform_data mlxplat_default_led_data = { 3121 .data = mlxplat_mlxcpld_default_led_data, 3122 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_led_data), 3123 }; 3124 3125 /* Platform led default data for water cooling */ 3126 static struct mlxreg_core_data mlxplat_mlxcpld_default_led_wc_data[] = { 3127 { 3128 .label = "status:green", 3129 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 3130 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3131 }, 3132 { 3133 .label = "status:red", 3134 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 3135 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK 3136 }, 3137 { 3138 .label = "psu:green", 3139 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 3140 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3141 }, 3142 { 3143 .label = "psu:red", 3144 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 3145 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3146 }, 3147 }; 3148 3149 static struct mlxreg_core_platform_data mlxplat_default_led_wc_data = { 3150 .data = mlxplat_mlxcpld_default_led_wc_data, 3151 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_led_wc_data), 3152 }; 3153 3154 /* Platform led default data for water cooling Ethernet switch blade */ 3155 static struct mlxreg_core_data mlxplat_mlxcpld_default_led_eth_wc_blade_data[] = { 3156 { 3157 .label = "status:green", 3158 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 3159 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3160 }, 3161 { 3162 .label = "status:red", 3163 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 3164 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK 3165 }, 3166 }; 3167 3168 static struct mlxreg_core_platform_data mlxplat_default_led_eth_wc_blade_data = { 3169 .data = mlxplat_mlxcpld_default_led_eth_wc_blade_data, 3170 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_led_eth_wc_blade_data), 3171 }; 3172 3173 /* Platform led MSN21xx system family data */ 3174 static struct mlxreg_core_data mlxplat_mlxcpld_msn21xx_led_data[] = { 3175 { 3176 .label = "status:green", 3177 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 3178 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3179 }, 3180 { 3181 .label = "status:red", 3182 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 3183 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK 3184 }, 3185 { 3186 .label = "fan:green", 3187 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 3188 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3189 }, 3190 { 3191 .label = "fan:red", 3192 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 3193 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3194 }, 3195 { 3196 .label = "psu1:green", 3197 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 3198 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3199 }, 3200 { 3201 .label = "psu1:red", 3202 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 3203 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3204 }, 3205 { 3206 .label = "psu2:green", 3207 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 3208 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3209 }, 3210 { 3211 .label = "psu2:red", 3212 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 3213 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3214 }, 3215 { 3216 .label = "uid:blue", 3217 .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET, 3218 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3219 }, 3220 }; 3221 3222 static struct mlxreg_core_platform_data mlxplat_msn21xx_led_data = { 3223 .data = mlxplat_mlxcpld_msn21xx_led_data, 3224 .counter = ARRAY_SIZE(mlxplat_mlxcpld_msn21xx_led_data), 3225 }; 3226 3227 /* Platform led for default data for 200GbE systems */ 3228 static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_led_data[] = { 3229 { 3230 .label = "status:green", 3231 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 3232 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3233 }, 3234 { 3235 .label = "status:orange", 3236 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 3237 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK 3238 }, 3239 { 3240 .label = "psu:green", 3241 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 3242 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3243 }, 3244 { 3245 .label = "psu:orange", 3246 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 3247 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3248 }, 3249 { 3250 .label = "fan1:green", 3251 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 3252 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3253 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3254 .bit = BIT(0), 3255 }, 3256 { 3257 .label = "fan1:orange", 3258 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 3259 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3260 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3261 .bit = BIT(0), 3262 }, 3263 { 3264 .label = "fan2:green", 3265 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 3266 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3267 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3268 .bit = BIT(1), 3269 }, 3270 { 3271 .label = "fan2:orange", 3272 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 3273 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3274 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3275 .bit = BIT(1), 3276 }, 3277 { 3278 .label = "fan3:green", 3279 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 3280 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3281 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3282 .bit = BIT(2), 3283 }, 3284 { 3285 .label = "fan3:orange", 3286 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 3287 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3288 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3289 .bit = BIT(2), 3290 }, 3291 { 3292 .label = "fan4:green", 3293 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 3294 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3295 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3296 .bit = BIT(3), 3297 }, 3298 { 3299 .label = "fan4:orange", 3300 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 3301 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3302 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3303 .bit = BIT(3), 3304 }, 3305 { 3306 .label = "fan5:green", 3307 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 3308 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3309 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3310 .bit = BIT(4), 3311 }, 3312 { 3313 .label = "fan5:orange", 3314 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 3315 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3316 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3317 .bit = BIT(4), 3318 }, 3319 { 3320 .label = "fan6:green", 3321 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 3322 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3323 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3324 .bit = BIT(5), 3325 }, 3326 { 3327 .label = "fan6:orange", 3328 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 3329 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3330 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3331 .bit = BIT(5), 3332 }, 3333 { 3334 .label = "fan7:green", 3335 .reg = MLXPLAT_CPLD_LPC_REG_LED6_OFFSET, 3336 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3337 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3338 .bit = BIT(6), 3339 }, 3340 { 3341 .label = "fan7:orange", 3342 .reg = MLXPLAT_CPLD_LPC_REG_LED6_OFFSET, 3343 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3344 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3345 .bit = BIT(6), 3346 }, 3347 { 3348 .label = "uid:blue", 3349 .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET, 3350 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3351 }, 3352 }; 3353 3354 static struct mlxreg_core_platform_data mlxplat_default_ng_led_data = { 3355 .data = mlxplat_mlxcpld_default_ng_led_data, 3356 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_led_data), 3357 }; 3358 3359 /* Platform led for Comex based 100GbE systems */ 3360 static struct mlxreg_core_data mlxplat_mlxcpld_comex_100G_led_data[] = { 3361 { 3362 .label = "status:green", 3363 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 3364 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3365 }, 3366 { 3367 .label = "status:red", 3368 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 3369 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK 3370 }, 3371 { 3372 .label = "psu:green", 3373 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 3374 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3375 }, 3376 { 3377 .label = "psu:red", 3378 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 3379 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3380 }, 3381 { 3382 .label = "fan1:green", 3383 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 3384 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3385 }, 3386 { 3387 .label = "fan1:red", 3388 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 3389 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3390 }, 3391 { 3392 .label = "fan2:green", 3393 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 3394 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3395 }, 3396 { 3397 .label = "fan2:red", 3398 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 3399 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3400 }, 3401 { 3402 .label = "fan3:green", 3403 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 3404 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3405 }, 3406 { 3407 .label = "fan3:red", 3408 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 3409 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3410 }, 3411 { 3412 .label = "fan4:green", 3413 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 3414 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3415 }, 3416 { 3417 .label = "fan4:red", 3418 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 3419 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3420 }, 3421 { 3422 .label = "uid:blue", 3423 .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET, 3424 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3425 }, 3426 }; 3427 3428 static struct mlxreg_core_platform_data mlxplat_comex_100G_led_data = { 3429 .data = mlxplat_mlxcpld_comex_100G_led_data, 3430 .counter = ARRAY_SIZE(mlxplat_mlxcpld_comex_100G_led_data), 3431 }; 3432 3433 /* Platform led for data for modular systems */ 3434 static struct mlxreg_core_data mlxplat_mlxcpld_modular_led_data[] = { 3435 { 3436 .label = "status:green", 3437 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 3438 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3439 }, 3440 { 3441 .label = "status:orange", 3442 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 3443 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK 3444 }, 3445 { 3446 .label = "psu:green", 3447 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 3448 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3449 }, 3450 { 3451 .label = "psu:orange", 3452 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 3453 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3454 }, 3455 { 3456 .label = "fan1:green", 3457 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 3458 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3459 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3460 .bit = BIT(0), 3461 }, 3462 { 3463 .label = "fan1:orange", 3464 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 3465 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3466 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3467 .bit = BIT(0), 3468 }, 3469 { 3470 .label = "fan2:green", 3471 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 3472 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3473 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3474 .bit = BIT(1), 3475 }, 3476 { 3477 .label = "fan2:orange", 3478 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 3479 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3480 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3481 .bit = BIT(1), 3482 }, 3483 { 3484 .label = "fan3:green", 3485 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 3486 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3487 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3488 .bit = BIT(2), 3489 }, 3490 { 3491 .label = "fan3:orange", 3492 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 3493 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3494 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3495 .bit = BIT(2), 3496 }, 3497 { 3498 .label = "fan4:green", 3499 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 3500 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3501 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3502 .bit = BIT(3), 3503 }, 3504 { 3505 .label = "fan4:orange", 3506 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 3507 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3508 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3509 .bit = BIT(3), 3510 }, 3511 { 3512 .label = "fan5:green", 3513 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 3514 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3515 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3516 .bit = BIT(4), 3517 }, 3518 { 3519 .label = "fan5:orange", 3520 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 3521 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3522 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3523 .bit = BIT(4), 3524 }, 3525 { 3526 .label = "fan6:green", 3527 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 3528 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3529 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3530 .bit = BIT(5), 3531 }, 3532 { 3533 .label = "fan6:orange", 3534 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 3535 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3536 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3537 .bit = BIT(5), 3538 }, 3539 { 3540 .label = "fan7:green", 3541 .reg = MLXPLAT_CPLD_LPC_REG_LED6_OFFSET, 3542 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3543 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3544 .bit = BIT(6), 3545 }, 3546 { 3547 .label = "fan7:orange", 3548 .reg = MLXPLAT_CPLD_LPC_REG_LED6_OFFSET, 3549 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3550 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3551 .bit = BIT(6), 3552 }, 3553 { 3554 .label = "uid:blue", 3555 .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET, 3556 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3557 }, 3558 { 3559 .label = "fan_front:green", 3560 .reg = MLXPLAT_CPLD_LPC_REG_LED6_OFFSET, 3561 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3562 }, 3563 { 3564 .label = "fan_front:orange", 3565 .reg = MLXPLAT_CPLD_LPC_REG_LED6_OFFSET, 3566 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3567 }, 3568 { 3569 .label = "mgmt:green", 3570 .reg = MLXPLAT_CPLD_LPC_REG_LED7_OFFSET, 3571 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3572 }, 3573 { 3574 .label = "mgmt:orange", 3575 .reg = MLXPLAT_CPLD_LPC_REG_LED7_OFFSET, 3576 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3577 }, 3578 }; 3579 3580 static struct mlxreg_core_platform_data mlxplat_modular_led_data = { 3581 .data = mlxplat_mlxcpld_modular_led_data, 3582 .counter = ARRAY_SIZE(mlxplat_mlxcpld_modular_led_data), 3583 }; 3584 3585 /* Platform led data for chassis system */ 3586 static struct mlxreg_core_data mlxplat_mlxcpld_l1_switch_led_data[] = { 3587 { 3588 .label = "status:green", 3589 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 3590 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3591 }, 3592 { 3593 .label = "status:orange", 3594 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 3595 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK 3596 }, 3597 { 3598 .label = "fan1:green", 3599 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 3600 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3601 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3602 .bit = BIT(0), 3603 }, 3604 { 3605 .label = "fan1:orange", 3606 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 3607 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3608 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3609 .bit = BIT(0), 3610 }, 3611 { 3612 .label = "fan2:green", 3613 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 3614 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3615 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3616 .bit = BIT(1), 3617 }, 3618 { 3619 .label = "fan2:orange", 3620 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 3621 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3622 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3623 .bit = BIT(1), 3624 }, 3625 { 3626 .label = "fan3:green", 3627 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 3628 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3629 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3630 .bit = BIT(2), 3631 }, 3632 { 3633 .label = "fan3:orange", 3634 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 3635 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3636 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3637 .bit = BIT(2), 3638 }, 3639 { 3640 .label = "fan4:green", 3641 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 3642 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3643 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3644 .bit = BIT(3), 3645 }, 3646 { 3647 .label = "fan4:orange", 3648 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 3649 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3650 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3651 .bit = BIT(3), 3652 }, 3653 { 3654 .label = "fan5:green", 3655 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 3656 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3657 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3658 .bit = BIT(4), 3659 }, 3660 { 3661 .label = "fan5:orange", 3662 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 3663 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3664 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3665 .bit = BIT(4), 3666 }, 3667 { 3668 .label = "fan6:green", 3669 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 3670 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3671 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3672 .bit = BIT(5), 3673 }, 3674 { 3675 .label = "fan6:orange", 3676 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 3677 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3678 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3679 .bit = BIT(5), 3680 }, 3681 { 3682 .label = "uid:blue", 3683 .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET, 3684 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3685 }, 3686 }; 3687 3688 static struct mlxreg_core_platform_data mlxplat_l1_switch_led_data = { 3689 .data = mlxplat_mlxcpld_l1_switch_led_data, 3690 .counter = ARRAY_SIZE(mlxplat_mlxcpld_l1_switch_led_data), 3691 }; 3692 3693 /* Platform led data for XDR and smart switch systems */ 3694 static struct mlxreg_core_data mlxplat_mlxcpld_xdr_led_data[] = { 3695 { 3696 .label = "status:green", 3697 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 3698 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3699 }, 3700 { 3701 .label = "status:orange", 3702 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 3703 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3704 }, 3705 { 3706 .label = "psu:green", 3707 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 3708 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3709 }, 3710 { 3711 .label = "psu:orange", 3712 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 3713 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3714 }, 3715 { 3716 .label = "fan1:green", 3717 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 3718 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3719 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3720 .slot = 1, 3721 }, 3722 { 3723 .label = "fan1:orange", 3724 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 3725 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3726 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3727 .slot = 1, 3728 }, 3729 { 3730 .label = "fan2:green", 3731 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 3732 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3733 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3734 .slot = 2, 3735 }, 3736 { 3737 .label = "fan2:orange", 3738 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 3739 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3740 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3741 .slot = 2, 3742 }, 3743 { 3744 .label = "fan3:green", 3745 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 3746 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3747 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3748 .slot = 3, 3749 }, 3750 { 3751 .label = "fan3:orange", 3752 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 3753 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3754 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3755 .slot = 3, 3756 }, 3757 { 3758 .label = "fan4:green", 3759 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 3760 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3761 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3762 .slot = 4, 3763 }, 3764 { 3765 .label = "fan4:orange", 3766 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 3767 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3768 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3769 .slot = 4, 3770 }, 3771 { 3772 .label = "fan5:green", 3773 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 3774 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3775 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3776 .slot = 5, 3777 }, 3778 { 3779 .label = "fan5:orange", 3780 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 3781 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3782 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3783 .slot = 5, 3784 }, 3785 { 3786 .label = "fan6:green", 3787 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 3788 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3789 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3790 .slot = 6, 3791 }, 3792 { 3793 .label = "fan6:orange", 3794 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 3795 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3796 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3797 .slot = 6, 3798 }, 3799 { 3800 .label = "fan7:green", 3801 .reg = MLXPLAT_CPLD_LPC_REG_LED6_OFFSET, 3802 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3803 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3804 .slot = 7, 3805 }, 3806 { 3807 .label = "fan7:orange", 3808 .reg = MLXPLAT_CPLD_LPC_REG_LED6_OFFSET, 3809 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3810 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3811 .slot = 7, 3812 }, 3813 { 3814 .label = "fan8:green", 3815 .reg = MLXPLAT_CPLD_LPC_REG_LED7_OFFSET, 3816 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3817 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3818 .slot = 8, 3819 }, 3820 { 3821 .label = "fan8:orange", 3822 .reg = MLXPLAT_CPLD_LPC_REG_LED7_OFFSET, 3823 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3824 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3825 .slot = 8, 3826 }, 3827 { 3828 .label = "fan9:green", 3829 .reg = MLXPLAT_CPLD_LPC_REG_LED7_OFFSET, 3830 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3831 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3832 .slot = 9, 3833 }, 3834 { 3835 .label = "fan9:orange", 3836 .reg = MLXPLAT_CPLD_LPC_REG_LED7_OFFSET, 3837 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3838 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3839 .slot = 9, 3840 }, 3841 { 3842 .label = "fan10:green", 3843 .reg = MLXPLAT_CPLD_LPC_REG_LED8_OFFSET, 3844 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3845 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3846 .slot = 10, 3847 }, 3848 { 3849 .label = "fan10:orange", 3850 .reg = MLXPLAT_CPLD_LPC_REG_LED8_OFFSET, 3851 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3852 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3853 .slot = 10, 3854 }, 3855 { 3856 .label = "uid:blue", 3857 .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET, 3858 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3859 }, 3860 }; 3861 3862 static struct mlxreg_core_platform_data mlxplat_xdr_led_data = { 3863 .data = mlxplat_mlxcpld_xdr_led_data, 3864 .counter = ARRAY_SIZE(mlxplat_mlxcpld_xdr_led_data), 3865 }; 3866 3867 /* Platform register access default */ 3868 static struct mlxreg_core_data mlxplat_mlxcpld_default_regs_io_data[] = { 3869 { 3870 .label = "cpld1_version", 3871 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET, 3872 .bit = GENMASK(7, 0), 3873 .mode = 0444, 3874 }, 3875 { 3876 .label = "cpld2_version", 3877 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET, 3878 .bit = GENMASK(7, 0), 3879 .mode = 0444, 3880 }, 3881 { 3882 .label = "cpld1_pn", 3883 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET, 3884 .bit = GENMASK(15, 0), 3885 .mode = 0444, 3886 .regnum = 2, 3887 }, 3888 { 3889 .label = "cpld2_pn", 3890 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET, 3891 .bit = GENMASK(15, 0), 3892 .mode = 0444, 3893 .regnum = 2, 3894 }, 3895 { 3896 .label = "cpld1_version_min", 3897 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET, 3898 .bit = GENMASK(7, 0), 3899 .mode = 0444, 3900 }, 3901 { 3902 .label = "cpld2_version_min", 3903 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET, 3904 .bit = GENMASK(7, 0), 3905 .mode = 0444, 3906 }, 3907 { 3908 .label = "reset_long_pb", 3909 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 3910 .mask = GENMASK(7, 0) & ~BIT(0), 3911 .mode = 0444, 3912 }, 3913 { 3914 .label = "reset_short_pb", 3915 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 3916 .mask = GENMASK(7, 0) & ~BIT(1), 3917 .mode = 0444, 3918 }, 3919 { 3920 .label = "reset_aux_pwr_or_ref", 3921 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 3922 .mask = GENMASK(7, 0) & ~BIT(2), 3923 .mode = 0444, 3924 }, 3925 { 3926 .label = "reset_main_pwr_fail", 3927 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 3928 .mask = GENMASK(7, 0) & ~BIT(3), 3929 .mode = 0444, 3930 }, 3931 { 3932 .label = "reset_sw_reset", 3933 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 3934 .mask = GENMASK(7, 0) & ~BIT(4), 3935 .mode = 0444, 3936 }, 3937 { 3938 .label = "reset_fw_reset", 3939 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 3940 .mask = GENMASK(7, 0) & ~BIT(5), 3941 .mode = 0444, 3942 }, 3943 { 3944 .label = "reset_hotswap_or_wd", 3945 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 3946 .mask = GENMASK(7, 0) & ~BIT(6), 3947 .mode = 0444, 3948 }, 3949 { 3950 .label = "reset_asic_thermal", 3951 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 3952 .mask = GENMASK(7, 0) & ~BIT(7), 3953 .mode = 0444, 3954 }, 3955 { 3956 .label = "psu1_on", 3957 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 3958 .mask = GENMASK(7, 0) & ~BIT(0), 3959 .mode = 0200, 3960 }, 3961 { 3962 .label = "psu2_on", 3963 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 3964 .mask = GENMASK(7, 0) & ~BIT(1), 3965 .mode = 0200, 3966 }, 3967 { 3968 .label = "pwr_cycle", 3969 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 3970 .mask = GENMASK(7, 0) & ~BIT(2), 3971 .mode = 0200, 3972 }, 3973 { 3974 .label = "pwr_down", 3975 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 3976 .mask = GENMASK(7, 0) & ~BIT(3), 3977 .mode = 0200, 3978 }, 3979 { 3980 .label = "select_iio", 3981 .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, 3982 .mask = GENMASK(7, 0) & ~BIT(6), 3983 .mode = 0644, 3984 }, 3985 { 3986 .label = "asic_health", 3987 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 3988 .mask = MLXPLAT_CPLD_ASIC_MASK, 3989 .bit = 1, 3990 .mode = 0444, 3991 }, 3992 }; 3993 3994 static struct mlxreg_core_platform_data mlxplat_default_regs_io_data = { 3995 .data = mlxplat_mlxcpld_default_regs_io_data, 3996 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_regs_io_data), 3997 }; 3998 3999 /* Platform register access MSN21xx, MSN201x, MSN274x systems families data */ 4000 static struct mlxreg_core_data mlxplat_mlxcpld_msn21xx_regs_io_data[] = { 4001 { 4002 .label = "cpld1_version", 4003 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET, 4004 .bit = GENMASK(7, 0), 4005 .mode = 0444, 4006 }, 4007 { 4008 .label = "cpld2_version", 4009 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET, 4010 .bit = GENMASK(7, 0), 4011 .mode = 0444, 4012 }, 4013 { 4014 .label = "cpld1_pn", 4015 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET, 4016 .bit = GENMASK(15, 0), 4017 .mode = 0444, 4018 .regnum = 2, 4019 }, 4020 { 4021 .label = "cpld2_pn", 4022 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET, 4023 .bit = GENMASK(15, 0), 4024 .mode = 0444, 4025 .regnum = 2, 4026 }, 4027 { 4028 .label = "cpld1_version_min", 4029 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET, 4030 .bit = GENMASK(7, 0), 4031 .mode = 0444, 4032 }, 4033 { 4034 .label = "cpld2_version_min", 4035 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET, 4036 .bit = GENMASK(7, 0), 4037 .mode = 0444, 4038 }, 4039 { 4040 .label = "reset_long_pb", 4041 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 4042 .mask = GENMASK(7, 0) & ~BIT(0), 4043 .mode = 0444, 4044 }, 4045 { 4046 .label = "reset_short_pb", 4047 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 4048 .mask = GENMASK(7, 0) & ~BIT(1), 4049 .mode = 0444, 4050 }, 4051 { 4052 .label = "reset_aux_pwr_or_ref", 4053 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 4054 .mask = GENMASK(7, 0) & ~BIT(2), 4055 .mode = 0444, 4056 }, 4057 { 4058 .label = "reset_sw_reset", 4059 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 4060 .mask = GENMASK(7, 0) & ~BIT(3), 4061 .mode = 0444, 4062 }, 4063 { 4064 .label = "reset_main_pwr_fail", 4065 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 4066 .mask = GENMASK(7, 0) & ~BIT(4), 4067 .mode = 0444, 4068 }, 4069 { 4070 .label = "reset_asic_thermal", 4071 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 4072 .mask = GENMASK(7, 0) & ~BIT(5), 4073 .mode = 0444, 4074 }, 4075 { 4076 .label = "reset_hotswap_or_halt", 4077 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 4078 .mask = GENMASK(7, 0) & ~BIT(6), 4079 .mode = 0444, 4080 }, 4081 { 4082 .label = "reset_sff_wd", 4083 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 4084 .mask = GENMASK(7, 0) & ~BIT(6), 4085 .mode = 0444, 4086 }, 4087 { 4088 .label = "psu1_on", 4089 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 4090 .mask = GENMASK(7, 0) & ~BIT(0), 4091 .mode = 0200, 4092 }, 4093 { 4094 .label = "psu2_on", 4095 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 4096 .mask = GENMASK(7, 0) & ~BIT(1), 4097 .mode = 0200, 4098 }, 4099 { 4100 .label = "pwr_cycle", 4101 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 4102 .mask = GENMASK(7, 0) & ~BIT(2), 4103 .mode = 0200, 4104 }, 4105 { 4106 .label = "pwr_down", 4107 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 4108 .mask = GENMASK(7, 0) & ~BIT(3), 4109 .mode = 0200, 4110 }, 4111 { 4112 .label = "select_iio", 4113 .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, 4114 .mask = GENMASK(7, 0) & ~BIT(6), 4115 .mode = 0644, 4116 }, 4117 { 4118 .label = "asic_health", 4119 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 4120 .mask = MLXPLAT_CPLD_ASIC_MASK, 4121 .bit = 1, 4122 .mode = 0444, 4123 }, 4124 }; 4125 4126 static struct mlxreg_core_platform_data mlxplat_msn21xx_regs_io_data = { 4127 .data = mlxplat_mlxcpld_msn21xx_regs_io_data, 4128 .counter = ARRAY_SIZE(mlxplat_mlxcpld_msn21xx_regs_io_data), 4129 }; 4130 4131 /* Platform register access for next generation systems families data */ 4132 static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { 4133 { 4134 .label = "cpld1_version", 4135 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET, 4136 .bit = GENMASK(7, 0), 4137 .mode = 0444, 4138 }, 4139 { 4140 .label = "cpld2_version", 4141 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET, 4142 .bit = GENMASK(7, 0), 4143 .mode = 0444, 4144 }, 4145 { 4146 .label = "cpld3_version", 4147 .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET, 4148 .bit = GENMASK(7, 0), 4149 .mode = 0444, 4150 }, 4151 { 4152 .label = "cpld4_version", 4153 .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET, 4154 .bit = GENMASK(7, 0), 4155 .mode = 0444, 4156 }, 4157 { 4158 .label = "cpld5_version", 4159 .reg = MLXPLAT_CPLD_LPC_REG_CPLD5_VER_OFFSET, 4160 .bit = GENMASK(7, 0), 4161 .mode = 0444, 4162 }, 4163 { 4164 .label = "cpld1_pn", 4165 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET, 4166 .bit = GENMASK(15, 0), 4167 .mode = 0444, 4168 .regnum = 2, 4169 }, 4170 { 4171 .label = "cpld2_pn", 4172 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET, 4173 .bit = GENMASK(15, 0), 4174 .mode = 0444, 4175 .regnum = 2, 4176 }, 4177 { 4178 .label = "cpld3_pn", 4179 .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET, 4180 .bit = GENMASK(15, 0), 4181 .mode = 0444, 4182 .regnum = 2, 4183 }, 4184 { 4185 .label = "cpld4_pn", 4186 .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET, 4187 .bit = GENMASK(15, 0), 4188 .mode = 0444, 4189 .regnum = 2, 4190 }, 4191 { 4192 .label = "cpld5_pn", 4193 .reg = MLXPLAT_CPLD_LPC_REG_CPLD5_PN_OFFSET, 4194 .bit = GENMASK(15, 0), 4195 .mode = 0444, 4196 .regnum = 2, 4197 }, 4198 { 4199 .label = "cpld1_version_min", 4200 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET, 4201 .bit = GENMASK(7, 0), 4202 .mode = 0444, 4203 }, 4204 { 4205 .label = "cpld2_version_min", 4206 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET, 4207 .bit = GENMASK(7, 0), 4208 .mode = 0444, 4209 }, 4210 { 4211 .label = "cpld3_version_min", 4212 .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET, 4213 .bit = GENMASK(7, 0), 4214 .mode = 0444, 4215 }, 4216 { 4217 .label = "cpld4_version_min", 4218 .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET, 4219 .bit = GENMASK(7, 0), 4220 .mode = 0444, 4221 }, 4222 { 4223 .label = "cpld5_version_min", 4224 .reg = MLXPLAT_CPLD_LPC_REG_CPLD5_MVER_OFFSET, 4225 .bit = GENMASK(7, 0), 4226 .mode = 0444, 4227 }, 4228 { 4229 .label = "asic_reset", 4230 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET, 4231 .mask = GENMASK(7, 0) & ~BIT(3), 4232 .mode = 0200, 4233 }, 4234 { 4235 .label = "asic2_reset", 4236 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET, 4237 .mask = GENMASK(7, 0) & ~BIT(2), 4238 .mode = 0200, 4239 }, 4240 { 4241 .label = "erot1_reset", 4242 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET, 4243 .mask = GENMASK(7, 0) & ~BIT(6), 4244 .mode = 0644, 4245 }, 4246 { 4247 .label = "erot2_reset", 4248 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET, 4249 .mask = GENMASK(7, 0) & ~BIT(7), 4250 .mode = 0644, 4251 }, 4252 { 4253 .label = "clk_brd_prog_en", 4254 .reg = MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 4255 .mask = GENMASK(7, 0) & ~BIT(1), 4256 .mode = 0644, 4257 .secured = 1, 4258 }, 4259 { 4260 .label = "erot1_recovery", 4261 .reg = MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 4262 .mask = GENMASK(7, 0) & ~BIT(6), 4263 .mode = 0644, 4264 }, 4265 { 4266 .label = "erot2_recovery", 4267 .reg = MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 4268 .mask = GENMASK(7, 0) & ~BIT(7), 4269 .mode = 0644, 4270 }, 4271 { 4272 .label = "erot1_wp", 4273 .reg = MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 4274 .mask = GENMASK(7, 0) & ~BIT(4), 4275 .mode = 0644, 4276 .secured = 1, 4277 }, 4278 { 4279 .label = "erot2_wp", 4280 .reg = MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 4281 .mask = GENMASK(7, 0) & ~BIT(5), 4282 .mode = 0644, 4283 .secured = 1, 4284 }, 4285 { 4286 .label = "reset_long_pb", 4287 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 4288 .mask = GENMASK(7, 0) & ~BIT(0), 4289 .mode = 0444, 4290 }, 4291 { 4292 .label = "reset_short_pb", 4293 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 4294 .mask = GENMASK(7, 0) & ~BIT(1), 4295 .mode = 0444, 4296 }, 4297 { 4298 .label = "reset_aux_pwr_or_ref", 4299 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 4300 .mask = GENMASK(7, 0) & ~BIT(2), 4301 .mode = 0444, 4302 }, 4303 { 4304 .label = "reset_swb_dc_dc_pwr_fail", 4305 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 4306 .mask = GENMASK(7, 0) & ~BIT(3), 4307 .mode = 0444, 4308 }, 4309 { 4310 .label = "reset_from_asic", 4311 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 4312 .mask = GENMASK(7, 0) & ~BIT(5), 4313 .mode = 0444, 4314 }, 4315 { 4316 .label = "reset_swb_wd", 4317 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 4318 .mask = GENMASK(7, 0) & ~BIT(6), 4319 .mode = 0444, 4320 }, 4321 { 4322 .label = "reset_asic_thermal", 4323 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 4324 .mask = GENMASK(7, 0) & ~BIT(7), 4325 .mode = 0444, 4326 }, 4327 { 4328 .label = "reset_sw_reset", 4329 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 4330 .mask = GENMASK(7, 0) & ~BIT(0), 4331 .mode = 0444, 4332 }, 4333 { 4334 .label = "reset_comex_pwr_fail", 4335 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 4336 .mask = GENMASK(7, 0) & ~BIT(3), 4337 .mode = 0444, 4338 }, 4339 { 4340 .label = "reset_platform", 4341 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 4342 .mask = GENMASK(7, 0) & ~BIT(4), 4343 .mode = 0444, 4344 }, 4345 { 4346 .label = "reset_soc", 4347 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 4348 .mask = GENMASK(7, 0) & ~BIT(5), 4349 .mode = 0444, 4350 }, 4351 { 4352 .label = "reset_comex_wd", 4353 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 4354 .mask = GENMASK(7, 0) & ~BIT(6), 4355 .mode = 0444, 4356 }, 4357 { 4358 .label = "reset_pwr_converter_fail", 4359 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 4360 .mask = GENMASK(7, 0) & ~BIT(0), 4361 .mode = 0444, 4362 }, 4363 { 4364 .label = "reset_system", 4365 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 4366 .mask = GENMASK(7, 0) & ~BIT(1), 4367 .mode = 0444, 4368 }, 4369 { 4370 .label = "reset_sw_pwr_off", 4371 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 4372 .mask = GENMASK(7, 0) & ~BIT(2), 4373 .mode = 0444, 4374 }, 4375 { 4376 .label = "reset_comex_thermal", 4377 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 4378 .mask = GENMASK(7, 0) & ~BIT(3), 4379 .mode = 0444, 4380 }, 4381 { 4382 .label = "reset_reload_bios", 4383 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 4384 .mask = GENMASK(7, 0) & ~BIT(5), 4385 .mode = 0444, 4386 }, 4387 { 4388 .label = "reset_ac_pwr_fail", 4389 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 4390 .mask = GENMASK(7, 0) & ~BIT(6), 4391 .mode = 0444, 4392 }, 4393 { 4394 .label = "reset_ac_ok_fail", 4395 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 4396 .mask = GENMASK(7, 0) & ~BIT(7), 4397 .mode = 0444, 4398 }, 4399 { 4400 .label = "psu1_on", 4401 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 4402 .mask = GENMASK(7, 0) & ~BIT(0), 4403 .mode = 0200, 4404 }, 4405 { 4406 .label = "psu2_on", 4407 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 4408 .mask = GENMASK(7, 0) & ~BIT(1), 4409 .mode = 0200, 4410 }, 4411 { 4412 .label = "pwr_cycle", 4413 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 4414 .mask = GENMASK(7, 0) & ~BIT(2), 4415 .mode = 0200, 4416 }, 4417 { 4418 .label = "pwr_down", 4419 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 4420 .mask = GENMASK(7, 0) & ~BIT(3), 4421 .mode = 0200, 4422 }, 4423 { 4424 .label = "deep_pwr_cycle", 4425 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 4426 .mask = GENMASK(7, 0) & ~BIT(5), 4427 .mode = 0200, 4428 }, 4429 { 4430 .label = "latch_reset", 4431 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 4432 .mask = GENMASK(7, 0) & ~BIT(6), 4433 .mode = 0200, 4434 }, 4435 { 4436 .label = "jtag_cap", 4437 .reg = MLXPLAT_CPLD_LPC_REG_FU_CAP_OFFSET, 4438 .mask = MLXPLAT_CPLD_FU_CAP_MASK, 4439 .bit = 1, 4440 .mode = 0444, 4441 }, 4442 { 4443 .label = "jtag_enable", 4444 .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, 4445 .mask = GENMASK(7, 0) & ~BIT(4), 4446 .mode = 0644, 4447 }, 4448 { 4449 .label = "dbg1", 4450 .reg = MLXPLAT_CPLD_LPC_REG_DBG1_OFFSET, 4451 .bit = GENMASK(7, 0), 4452 .mode = 0644, 4453 }, 4454 { 4455 .label = "dbg2", 4456 .reg = MLXPLAT_CPLD_LPC_REG_DBG2_OFFSET, 4457 .bit = GENMASK(7, 0), 4458 .mode = 0644, 4459 }, 4460 { 4461 .label = "dbg3", 4462 .reg = MLXPLAT_CPLD_LPC_REG_DBG3_OFFSET, 4463 .bit = GENMASK(7, 0), 4464 .mode = 0644, 4465 }, 4466 { 4467 .label = "dbg4", 4468 .reg = MLXPLAT_CPLD_LPC_REG_DBG4_OFFSET, 4469 .bit = GENMASK(7, 0), 4470 .mode = 0644, 4471 }, 4472 { 4473 .label = "asic_health", 4474 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 4475 .mask = MLXPLAT_CPLD_ASIC_MASK, 4476 .bit = 1, 4477 .mode = 0444, 4478 }, 4479 { 4480 .label = "asic2_health", 4481 .reg = MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET, 4482 .mask = MLXPLAT_CPLD_ASIC_MASK, 4483 .bit = 1, 4484 .mode = 0444, 4485 }, 4486 { 4487 .label = "fan_dir", 4488 .reg = MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION, 4489 .bit = GENMASK(7, 0), 4490 .mode = 0444, 4491 }, 4492 { 4493 .label = "bios_safe_mode", 4494 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, 4495 .mask = GENMASK(7, 0) & ~BIT(4), 4496 .mode = 0444, 4497 }, 4498 { 4499 .label = "bios_active_image", 4500 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, 4501 .mask = GENMASK(7, 0) & ~BIT(5), 4502 .mode = 0444, 4503 }, 4504 { 4505 .label = "bios_auth_fail", 4506 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, 4507 .mask = GENMASK(7, 0) & ~BIT(6), 4508 .mode = 0444, 4509 }, 4510 { 4511 .label = "bios_upgrade_fail", 4512 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, 4513 .mask = GENMASK(7, 0) & ~BIT(7), 4514 .mode = 0444, 4515 }, 4516 { 4517 .label = "voltreg_update_status", 4518 .reg = MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET, 4519 .mask = MLXPLAT_CPLD_VOLTREG_UPD_MASK, 4520 .bit = 5, 4521 .mode = 0444, 4522 }, 4523 { 4524 .label = "pwr_converter_prog_en", 4525 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, 4526 .mask = GENMASK(7, 0) & ~BIT(0), 4527 .mode = 0644, 4528 .secured = 1, 4529 }, 4530 { 4531 .label = "vpd_wp", 4532 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, 4533 .mask = GENMASK(7, 0) & ~BIT(3), 4534 .mode = 0644, 4535 }, 4536 { 4537 .label = "pcie_asic_reset_dis", 4538 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, 4539 .mask = GENMASK(7, 0) & ~BIT(4), 4540 .mode = 0644, 4541 }, 4542 { 4543 .label = "shutdown_unlock", 4544 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, 4545 .mask = GENMASK(7, 0) & ~BIT(5), 4546 .mode = 0644, 4547 }, 4548 { 4549 .label = "erot1_ap_reset", 4550 .reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET, 4551 .mask = GENMASK(7, 0) & ~BIT(0), 4552 .mode = 0444, 4553 }, 4554 { 4555 .label = "erot2_ap_reset", 4556 .reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET, 4557 .mask = GENMASK(7, 0) & ~BIT(1), 4558 .mode = 0444, 4559 }, 4560 { 4561 .label = "lid_open", 4562 .reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET, 4563 .mask = GENMASK(7, 0) & ~BIT(2), 4564 .mode = 0444, 4565 }, 4566 { 4567 .label = "clk_brd1_boot_fail", 4568 .reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET, 4569 .mask = GENMASK(7, 0) & ~BIT(4), 4570 .mode = 0444, 4571 }, 4572 { 4573 .label = "clk_brd2_boot_fail", 4574 .reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET, 4575 .mask = GENMASK(7, 0) & ~BIT(5), 4576 .mode = 0444, 4577 }, 4578 { 4579 .label = "clk_brd_fail", 4580 .reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET, 4581 .mask = GENMASK(7, 0) & ~BIT(6), 4582 .mode = 0444, 4583 }, 4584 { 4585 .label = "asic_pg_fail", 4586 .reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET, 4587 .mask = GENMASK(7, 0) & ~BIT(7), 4588 .mode = 0444, 4589 }, 4590 { 4591 .label = "spi_chnl_select", 4592 .reg = MLXPLAT_CPLD_LPC_REG_SPI_CHNL_SELECT, 4593 .mask = GENMASK(7, 0), 4594 .bit = 1, 4595 .mode = 0644, 4596 }, 4597 { 4598 .label = "config1", 4599 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET, 4600 .bit = GENMASK(7, 0), 4601 .mode = 0444, 4602 }, 4603 { 4604 .label = "config2", 4605 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET, 4606 .bit = GENMASK(7, 0), 4607 .mode = 0444, 4608 }, 4609 { 4610 .label = "config3", 4611 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET, 4612 .bit = GENMASK(7, 0), 4613 .mode = 0444, 4614 }, 4615 { 4616 .label = "ufm_version", 4617 .reg = MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET, 4618 .bit = GENMASK(7, 0), 4619 .mode = 0444, 4620 }, 4621 }; 4622 4623 static struct mlxreg_core_platform_data mlxplat_default_ng_regs_io_data = { 4624 .data = mlxplat_mlxcpld_default_ng_regs_io_data, 4625 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_regs_io_data), 4626 }; 4627 4628 /* Platform register access for modular systems families data */ 4629 static struct mlxreg_core_data mlxplat_mlxcpld_modular_regs_io_data[] = { 4630 { 4631 .label = "cpld1_version", 4632 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET, 4633 .bit = GENMASK(7, 0), 4634 .mode = 0444, 4635 }, 4636 { 4637 .label = "cpld2_version", 4638 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET, 4639 .bit = GENMASK(7, 0), 4640 .mode = 0444, 4641 }, 4642 { 4643 .label = "cpld3_version", 4644 .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET, 4645 .bit = GENMASK(7, 0), 4646 .mode = 0444, 4647 }, 4648 { 4649 .label = "cpld4_version", 4650 .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET, 4651 .bit = GENMASK(7, 0), 4652 .mode = 0444, 4653 }, 4654 { 4655 .label = "cpld1_pn", 4656 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET, 4657 .bit = GENMASK(15, 0), 4658 .mode = 0444, 4659 .regnum = 2, 4660 }, 4661 { 4662 .label = "cpld2_pn", 4663 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET, 4664 .bit = GENMASK(15, 0), 4665 .mode = 0444, 4666 .regnum = 2, 4667 }, 4668 { 4669 .label = "cpld3_pn", 4670 .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET, 4671 .bit = GENMASK(15, 0), 4672 .mode = 0444, 4673 .regnum = 2, 4674 }, 4675 { 4676 .label = "cpld4_pn", 4677 .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET, 4678 .bit = GENMASK(15, 0), 4679 .mode = 0444, 4680 .regnum = 2, 4681 }, 4682 { 4683 .label = "cpld1_version_min", 4684 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET, 4685 .bit = GENMASK(7, 0), 4686 .mode = 0444, 4687 }, 4688 { 4689 .label = "cpld2_version_min", 4690 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET, 4691 .bit = GENMASK(7, 0), 4692 .mode = 0444, 4693 }, 4694 { 4695 .label = "cpld3_version_min", 4696 .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET, 4697 .bit = GENMASK(7, 0), 4698 .mode = 0444, 4699 }, 4700 { 4701 .label = "cpld4_version_min", 4702 .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET, 4703 .bit = GENMASK(7, 0), 4704 .mode = 0444, 4705 }, 4706 { 4707 .label = "lc1_enable", 4708 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 4709 .mask = GENMASK(7, 0) & ~BIT(0), 4710 .mode = 0644, 4711 }, 4712 { 4713 .label = "lc2_enable", 4714 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 4715 .mask = GENMASK(7, 0) & ~BIT(1), 4716 .mode = 0644, 4717 }, 4718 { 4719 .label = "lc3_enable", 4720 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 4721 .mask = GENMASK(7, 0) & ~BIT(2), 4722 .mode = 0644, 4723 }, 4724 { 4725 .label = "lc4_enable", 4726 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 4727 .mask = GENMASK(7, 0) & ~BIT(3), 4728 .mode = 0644, 4729 }, 4730 { 4731 .label = "lc5_enable", 4732 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 4733 .mask = GENMASK(7, 0) & ~BIT(4), 4734 .mode = 0644, 4735 }, 4736 { 4737 .label = "lc6_enable", 4738 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 4739 .mask = GENMASK(7, 0) & ~BIT(5), 4740 .mode = 0644, 4741 }, 4742 { 4743 .label = "lc7_enable", 4744 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 4745 .mask = GENMASK(7, 0) & ~BIT(6), 4746 .mode = 0644, 4747 }, 4748 { 4749 .label = "lc8_enable", 4750 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 4751 .mask = GENMASK(7, 0) & ~BIT(7), 4752 .mode = 0644, 4753 }, 4754 { 4755 .label = "reset_long_pb", 4756 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 4757 .mask = GENMASK(7, 0) & ~BIT(0), 4758 .mode = 0444, 4759 }, 4760 { 4761 .label = "reset_short_pb", 4762 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 4763 .mask = GENMASK(7, 0) & ~BIT(1), 4764 .mode = 0444, 4765 }, 4766 { 4767 .label = "reset_aux_pwr_or_fu", 4768 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 4769 .mask = GENMASK(7, 0) & ~BIT(2), 4770 .mode = 0444, 4771 }, 4772 { 4773 .label = "reset_mgmt_dc_dc_pwr_fail", 4774 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 4775 .mask = GENMASK(7, 0) & ~BIT(3), 4776 .mode = 0444, 4777 }, 4778 { 4779 .label = "reset_sys_comex_bios", 4780 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 4781 .mask = GENMASK(7, 0) & ~BIT(5), 4782 .mode = 0444, 4783 }, 4784 { 4785 .label = "reset_sw_reset", 4786 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 4787 .mask = GENMASK(7, 0) & ~BIT(0), 4788 .mode = 0444, 4789 }, 4790 { 4791 .label = "reset_aux_pwr_or_reload", 4792 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 4793 .mask = GENMASK(7, 0) & ~BIT(2), 4794 .mode = 0444, 4795 }, 4796 { 4797 .label = "reset_comex_pwr_fail", 4798 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 4799 .mask = GENMASK(7, 0) & ~BIT(3), 4800 .mode = 0444, 4801 }, 4802 { 4803 .label = "reset_platform", 4804 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 4805 .mask = GENMASK(7, 0) & ~BIT(4), 4806 .mode = 0444, 4807 }, 4808 { 4809 .label = "reset_soc", 4810 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 4811 .mask = GENMASK(7, 0) & ~BIT(5), 4812 .mode = 0444, 4813 }, 4814 { 4815 .label = "reset_pwr_off_from_carrier", 4816 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 4817 .mask = GENMASK(7, 0) & ~BIT(7), 4818 .mode = 0444, 4819 }, 4820 { 4821 .label = "reset_swb_wd", 4822 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 4823 .mask = GENMASK(7, 0) & ~BIT(0), 4824 .mode = 0444, 4825 }, 4826 { 4827 .label = "reset_swb_aux_pwr_or_fu", 4828 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 4829 .mask = GENMASK(7, 0) & ~BIT(2), 4830 .mode = 0444, 4831 }, 4832 { 4833 .label = "reset_swb_dc_dc_pwr_fail", 4834 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 4835 .mask = GENMASK(7, 0) & ~BIT(3), 4836 .mode = 0444, 4837 }, 4838 { 4839 .label = "reset_swb_12v_fail", 4840 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 4841 .mask = GENMASK(7, 0) & ~BIT(4), 4842 .mode = 0444, 4843 }, 4844 { 4845 .label = "reset_system", 4846 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 4847 .mask = GENMASK(7, 0) & ~BIT(5), 4848 .mode = 0444, 4849 }, 4850 { 4851 .label = "reset_thermal_spc_or_pciesw", 4852 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 4853 .mask = GENMASK(7, 0) & ~BIT(7), 4854 .mode = 0444, 4855 }, 4856 { 4857 .label = "bios_safe_mode", 4858 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, 4859 .mask = GENMASK(7, 0) & ~BIT(4), 4860 .mode = 0444, 4861 }, 4862 { 4863 .label = "bios_active_image", 4864 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, 4865 .mask = GENMASK(7, 0) & ~BIT(5), 4866 .mode = 0444, 4867 }, 4868 { 4869 .label = "bios_auth_fail", 4870 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, 4871 .mask = GENMASK(7, 0) & ~BIT(6), 4872 .mode = 0444, 4873 }, 4874 { 4875 .label = "bios_upgrade_fail", 4876 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, 4877 .mask = GENMASK(7, 0) & ~BIT(7), 4878 .mode = 0444, 4879 }, 4880 { 4881 .label = "voltreg_update_status", 4882 .reg = MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET, 4883 .mask = MLXPLAT_CPLD_VOLTREG_UPD_MASK, 4884 .bit = 5, 4885 .mode = 0444, 4886 }, 4887 { 4888 .label = "vpd_wp", 4889 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, 4890 .mask = GENMASK(7, 0) & ~BIT(3), 4891 .mode = 0644, 4892 }, 4893 { 4894 .label = "pcie_asic_reset_dis", 4895 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, 4896 .mask = GENMASK(7, 0) & ~BIT(4), 4897 .mode = 0644, 4898 }, 4899 { 4900 .label = "shutdown_unlock", 4901 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, 4902 .mask = GENMASK(7, 0) & ~BIT(5), 4903 .mode = 0644, 4904 }, 4905 { 4906 .label = "lc1_rst_mask", 4907 .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, 4908 .mask = GENMASK(7, 0) & ~BIT(0), 4909 .mode = 0200, 4910 }, 4911 { 4912 .label = "lc2_rst_mask", 4913 .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, 4914 .mask = GENMASK(7, 0) & ~BIT(1), 4915 .mode = 0200, 4916 }, 4917 { 4918 .label = "lc3_rst_mask", 4919 .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, 4920 .mask = GENMASK(7, 0) & ~BIT(2), 4921 .mode = 0200, 4922 }, 4923 { 4924 .label = "lc4_rst_mask", 4925 .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, 4926 .mask = GENMASK(7, 0) & ~BIT(3), 4927 .mode = 0200, 4928 }, 4929 { 4930 .label = "lc5_rst_mask", 4931 .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, 4932 .mask = GENMASK(7, 0) & ~BIT(4), 4933 .mode = 0200, 4934 }, 4935 { 4936 .label = "lc6_rst_mask", 4937 .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, 4938 .mask = GENMASK(7, 0) & ~BIT(5), 4939 .mode = 0200, 4940 }, 4941 { 4942 .label = "lc7_rst_mask", 4943 .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, 4944 .mask = GENMASK(7, 0) & ~BIT(6), 4945 .mode = 0200, 4946 }, 4947 { 4948 .label = "lc8_rst_mask", 4949 .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, 4950 .mask = GENMASK(7, 0) & ~BIT(7), 4951 .mode = 0200, 4952 }, 4953 { 4954 .label = "psu1_on", 4955 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 4956 .mask = GENMASK(7, 0) & ~BIT(0), 4957 .mode = 0200, 4958 }, 4959 { 4960 .label = "psu2_on", 4961 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 4962 .mask = GENMASK(7, 0) & ~BIT(1), 4963 .mode = 0200, 4964 }, 4965 { 4966 .label = "pwr_cycle", 4967 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 4968 .mask = GENMASK(7, 0) & ~BIT(2), 4969 .mode = 0200, 4970 }, 4971 { 4972 .label = "pwr_down", 4973 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 4974 .mask = GENMASK(7, 0) & ~BIT(3), 4975 .mode = 0200, 4976 }, 4977 { 4978 .label = "psu3_on", 4979 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 4980 .mask = GENMASK(7, 0) & ~BIT(4), 4981 .mode = 0200, 4982 }, 4983 { 4984 .label = "psu4_on", 4985 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 4986 .mask = GENMASK(7, 0) & ~BIT(5), 4987 .mode = 0200, 4988 }, 4989 { 4990 .label = "auto_power_mode", 4991 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 4992 .mask = GENMASK(7, 0) & ~BIT(6), 4993 .mode = 0644, 4994 }, 4995 { 4996 .label = "pm_mgmt_en", 4997 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 4998 .mask = GENMASK(7, 0) & ~BIT(7), 4999 .mode = 0644, 5000 }, 5001 { 5002 .label = "jtag_enable", 5003 .reg = MLXPLAT_CPLD_LPC_REG_FIELD_UPGRADE, 5004 .mask = GENMASK(3, 0), 5005 .bit = 1, 5006 .mode = 0644, 5007 }, 5008 { 5009 .label = "safe_bios_dis", 5010 .reg = MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET, 5011 .mask = GENMASK(7, 0) & ~BIT(5), 5012 .mode = 0644, 5013 }, 5014 { 5015 .label = "safe_bios_dis_wp", 5016 .reg = MLXPLAT_CPLD_LPC_SAFE_BIOS_WP_OFFSET, 5017 .mask = GENMASK(7, 0) & ~BIT(5), 5018 .mode = 0644, 5019 }, 5020 { 5021 .label = "asic_health", 5022 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 5023 .mask = MLXPLAT_CPLD_ASIC_MASK, 5024 .bit = 1, 5025 .mode = 0444, 5026 }, 5027 { 5028 .label = "fan_dir", 5029 .reg = MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION, 5030 .bit = GENMASK(7, 0), 5031 .mode = 0444, 5032 }, 5033 { 5034 .label = "lc1_pwr", 5035 .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 5036 .mask = GENMASK(7, 0) & ~BIT(0), 5037 .mode = 0644, 5038 }, 5039 { 5040 .label = "lc2_pwr", 5041 .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 5042 .mask = GENMASK(7, 0) & ~BIT(1), 5043 .mode = 0644, 5044 }, 5045 { 5046 .label = "lc3_pwr", 5047 .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 5048 .mask = GENMASK(7, 0) & ~BIT(2), 5049 .mode = 0644, 5050 }, 5051 { 5052 .label = "lc4_pwr", 5053 .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 5054 .mask = GENMASK(7, 0) & ~BIT(3), 5055 .mode = 0644, 5056 }, 5057 { 5058 .label = "lc5_pwr", 5059 .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 5060 .mask = GENMASK(7, 0) & ~BIT(4), 5061 .mode = 0644, 5062 }, 5063 { 5064 .label = "lc6_pwr", 5065 .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 5066 .mask = GENMASK(7, 0) & ~BIT(5), 5067 .mode = 0644, 5068 }, 5069 { 5070 .label = "lc7_pwr", 5071 .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 5072 .mask = GENMASK(7, 0) & ~BIT(6), 5073 .mode = 0644, 5074 }, 5075 { 5076 .label = "lc8_pwr", 5077 .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 5078 .mask = GENMASK(7, 0) & ~BIT(7), 5079 .mode = 0644, 5080 }, 5081 { 5082 .label = "config1", 5083 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET, 5084 .bit = GENMASK(7, 0), 5085 .mode = 0444, 5086 }, 5087 { 5088 .label = "config2", 5089 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET, 5090 .bit = GENMASK(7, 0), 5091 .mode = 0444, 5092 }, 5093 { 5094 .label = "config3", 5095 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET, 5096 .bit = GENMASK(7, 0), 5097 .mode = 0444, 5098 }, 5099 { 5100 .label = "ufm_version", 5101 .reg = MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET, 5102 .bit = GENMASK(7, 0), 5103 .mode = 0444, 5104 }, 5105 }; 5106 5107 static struct mlxreg_core_platform_data mlxplat_modular_regs_io_data = { 5108 .data = mlxplat_mlxcpld_modular_regs_io_data, 5109 .counter = ARRAY_SIZE(mlxplat_mlxcpld_modular_regs_io_data), 5110 }; 5111 5112 /* Platform register access for chassis blade systems family data */ 5113 static struct mlxreg_core_data mlxplat_mlxcpld_chassis_blade_regs_io_data[] = { 5114 { 5115 .label = "cpld1_version", 5116 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET, 5117 .bit = GENMASK(7, 0), 5118 .mode = 0444, 5119 }, 5120 { 5121 .label = "cpld1_pn", 5122 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET, 5123 .bit = GENMASK(15, 0), 5124 .mode = 0444, 5125 .regnum = 2, 5126 }, 5127 { 5128 .label = "cpld1_version_min", 5129 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET, 5130 .bit = GENMASK(7, 0), 5131 .mode = 0444, 5132 }, 5133 { 5134 .label = "reset_aux_pwr_or_ref", 5135 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 5136 .mask = GENMASK(7, 0) & ~BIT(2), 5137 .mode = 0444, 5138 }, 5139 { 5140 .label = "reset_from_comex", 5141 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 5142 .mask = GENMASK(7, 0) & ~BIT(4), 5143 .mode = 0444, 5144 }, 5145 { 5146 .label = "reset_comex_pwr_fail", 5147 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 5148 .mask = GENMASK(7, 0) & ~BIT(3), 5149 .mode = 0444, 5150 }, 5151 { 5152 .label = "reset_platform", 5153 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 5154 .mask = GENMASK(7, 0) & ~BIT(4), 5155 .mode = 0444, 5156 }, 5157 { 5158 .label = "reset_soc", 5159 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 5160 .mask = GENMASK(7, 0) & ~BIT(5), 5161 .mode = 0444, 5162 }, 5163 { 5164 .label = "reset_comex_wd", 5165 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 5166 .mask = GENMASK(7, 0) & ~BIT(6), 5167 .mode = 0444, 5168 }, 5169 { 5170 .label = "reset_voltmon_upgrade_fail", 5171 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 5172 .mask = GENMASK(7, 0) & ~BIT(0), 5173 .mode = 0444, 5174 }, 5175 { 5176 .label = "reset_system", 5177 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 5178 .mask = GENMASK(7, 0) & ~BIT(1), 5179 .mode = 0444, 5180 }, 5181 { 5182 .label = "reset_sw_pwr_off", 5183 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 5184 .mask = GENMASK(7, 0) & ~BIT(2), 5185 .mode = 0444, 5186 }, 5187 { 5188 .label = "reset_comex_thermal", 5189 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 5190 .mask = GENMASK(7, 0) & ~BIT(3), 5191 .mode = 0444, 5192 }, 5193 { 5194 .label = "reset_reload_bios", 5195 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 5196 .mask = GENMASK(7, 0) & ~BIT(5), 5197 .mode = 0444, 5198 }, 5199 { 5200 .label = "reset_ac_pwr_fail", 5201 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 5202 .mask = GENMASK(7, 0) & ~BIT(6), 5203 .mode = 0444, 5204 }, 5205 { 5206 .label = "reset_long_pwr_pb", 5207 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 5208 .mask = GENMASK(7, 0) & ~BIT(7), 5209 .mode = 0444, 5210 }, 5211 { 5212 .label = "pwr_cycle", 5213 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 5214 .mask = GENMASK(7, 0) & ~BIT(2), 5215 .mode = 0200, 5216 }, 5217 { 5218 .label = "pwr_down", 5219 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 5220 .mask = GENMASK(7, 0) & ~BIT(3), 5221 .mode = 0200, 5222 }, 5223 { 5224 .label = "global_wp_request", 5225 .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, 5226 .mask = GENMASK(7, 0) & ~BIT(0), 5227 .mode = 0644, 5228 }, 5229 { 5230 .label = "jtag_enable", 5231 .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, 5232 .mask = GENMASK(7, 0) & ~BIT(4), 5233 .mode = 0644, 5234 }, 5235 { 5236 .label = "comm_chnl_ready", 5237 .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, 5238 .mask = GENMASK(7, 0) & ~BIT(6), 5239 .mode = 0200, 5240 }, 5241 { 5242 .label = "bios_safe_mode", 5243 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, 5244 .mask = GENMASK(7, 0) & ~BIT(4), 5245 .mode = 0444, 5246 }, 5247 { 5248 .label = "bios_active_image", 5249 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, 5250 .mask = GENMASK(7, 0) & ~BIT(5), 5251 .mode = 0444, 5252 }, 5253 { 5254 .label = "bios_auth_fail", 5255 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, 5256 .mask = GENMASK(7, 0) & ~BIT(6), 5257 .mode = 0444, 5258 }, 5259 { 5260 .label = "bios_upgrade_fail", 5261 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, 5262 .mask = GENMASK(7, 0) & ~BIT(7), 5263 .mode = 0444, 5264 }, 5265 { 5266 .label = "voltreg_update_status", 5267 .reg = MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET, 5268 .mask = MLXPLAT_CPLD_VOLTREG_UPD_MASK, 5269 .bit = 5, 5270 .mode = 0444, 5271 }, 5272 { 5273 .label = "vpd_wp", 5274 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, 5275 .mask = GENMASK(7, 0) & ~BIT(3), 5276 .mode = 0644, 5277 }, 5278 { 5279 .label = "pcie_asic_reset_dis", 5280 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, 5281 .mask = GENMASK(7, 0) & ~BIT(4), 5282 .mode = 0644, 5283 }, 5284 { 5285 .label = "global_wp_response", 5286 .reg = MLXPLAT_CPLD_LPC_REG_GWP_OFFSET, 5287 .mask = GENMASK(7, 0) & ~BIT(0), 5288 .mode = 0444, 5289 }, 5290 { 5291 .label = "config1", 5292 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET, 5293 .bit = GENMASK(7, 0), 5294 .mode = 0444, 5295 }, 5296 { 5297 .label = "config2", 5298 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET, 5299 .bit = GENMASK(7, 0), 5300 .mode = 0444, 5301 }, 5302 { 5303 .label = "config3", 5304 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET, 5305 .bit = GENMASK(7, 0), 5306 .mode = 0444, 5307 }, 5308 { 5309 .label = "ufm_version", 5310 .reg = MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET, 5311 .bit = GENMASK(7, 0), 5312 .mode = 0444, 5313 }, 5314 }; 5315 5316 static struct mlxreg_core_platform_data mlxplat_chassis_blade_regs_io_data = { 5317 .data = mlxplat_mlxcpld_chassis_blade_regs_io_data, 5318 .counter = ARRAY_SIZE(mlxplat_mlxcpld_chassis_blade_regs_io_data), 5319 }; 5320 5321 /* Platform register access for smart switch systems families data */ 5322 static struct mlxreg_core_data mlxplat_mlxcpld_smart_switch_regs_io_data[] = { 5323 { 5324 .label = "cpld1_version", 5325 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET, 5326 .bit = GENMASK(7, 0), 5327 .mode = 0444, 5328 }, 5329 { 5330 .label = "cpld2_version", 5331 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET, 5332 .bit = GENMASK(7, 0), 5333 .mode = 0444, 5334 }, 5335 { 5336 .label = "cpld3_version", 5337 .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET, 5338 .bit = GENMASK(7, 0), 5339 .mode = 0444, 5340 }, 5341 { 5342 .label = "cpld1_pn", 5343 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET, 5344 .bit = GENMASK(15, 0), 5345 .mode = 0444, 5346 .regnum = 2, 5347 }, 5348 { 5349 .label = "cpld2_pn", 5350 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET, 5351 .bit = GENMASK(15, 0), 5352 .mode = 0444, 5353 .regnum = 2, 5354 }, 5355 { 5356 .label = "cpld3_pn", 5357 .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET, 5358 .bit = GENMASK(15, 0), 5359 .mode = 0444, 5360 .regnum = 2, 5361 }, 5362 { 5363 .label = "cpld1_version_min", 5364 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET, 5365 .bit = GENMASK(7, 0), 5366 .mode = 0444, 5367 }, 5368 { 5369 .label = "cpld2_version_min", 5370 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET, 5371 .bit = GENMASK(7, 0), 5372 .mode = 0444, 5373 }, 5374 { 5375 .label = "cpld3_version_min", 5376 .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET, 5377 .bit = GENMASK(7, 0), 5378 .mode = 0444, 5379 }, 5380 { 5381 .label = "kexec_activated", 5382 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP1_OFFSET, 5383 .mask = GENMASK(7, 0) & ~BIT(1), 5384 .mode = 0644, 5385 }, 5386 { 5387 .label = "asic_reset", 5388 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET, 5389 .mask = GENMASK(7, 0) & ~BIT(3), 5390 .mode = 0644, 5391 }, 5392 { 5393 .label = "eth_switch_reset", 5394 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET, 5395 .mask = GENMASK(7, 0) & ~BIT(4), 5396 .mode = 0644, 5397 }, 5398 { 5399 .label = "dpu1_rst", 5400 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP3_OFFSET, 5401 .mask = GENMASK(7, 0) & ~BIT(0), 5402 .mode = 0200, 5403 }, 5404 { 5405 .label = "dpu2_rst", 5406 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP3_OFFSET, 5407 .mask = GENMASK(7, 0) & ~BIT(1), 5408 .mode = 0200, 5409 }, 5410 { 5411 .label = "dpu3_rst", 5412 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP3_OFFSET, 5413 .mask = GENMASK(7, 0) & ~BIT(2), 5414 .mode = 0200, 5415 }, 5416 { 5417 .label = "dpu4_rst", 5418 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP3_OFFSET, 5419 .mask = GENMASK(7, 0) & ~BIT(3), 5420 .mode = 0200, 5421 }, 5422 { 5423 .label = "dpu1_pwr", 5424 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 5425 .mask = GENMASK(7, 0) & ~BIT(0), 5426 .mode = 0200, 5427 }, 5428 { 5429 .label = "dpu2_pwr", 5430 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 5431 .mask = GENMASK(7, 0) & ~BIT(1), 5432 .mode = 0200, 5433 }, 5434 { 5435 .label = "dpu3_pwr", 5436 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 5437 .mask = GENMASK(7, 0) & ~BIT(2), 5438 .mode = 0200, 5439 }, 5440 { 5441 .label = "dpu4_pwr", 5442 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 5443 .mask = GENMASK(7, 0) & ~BIT(3), 5444 .mode = 0200, 5445 }, 5446 { 5447 .label = "reset_long_pb", 5448 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 5449 .mask = GENMASK(7, 0) & ~BIT(0), 5450 .mode = 0444, 5451 }, 5452 { 5453 .label = "reset_short_pb", 5454 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 5455 .mask = GENMASK(7, 0) & ~BIT(1), 5456 .mode = 0444, 5457 }, 5458 { 5459 .label = "reset_aux_pwr_or_ref", 5460 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 5461 .mask = GENMASK(7, 0) & ~BIT(2), 5462 .mode = 0444, 5463 }, 5464 { 5465 .label = "reset_swb_dc_dc_pwr_fail", 5466 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 5467 .mask = GENMASK(7, 0) & ~BIT(3), 5468 .mode = 0444, 5469 }, 5470 { 5471 .label = "reset_swb_wd", 5472 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 5473 .mask = GENMASK(7, 0) & ~BIT(6), 5474 .mode = 0444, 5475 }, 5476 { 5477 .label = "reset_asic_thermal", 5478 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 5479 .mask = GENMASK(7, 0) & ~BIT(7), 5480 .mode = 0444, 5481 }, 5482 { 5483 .label = "reset_sw_reset", 5484 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 5485 .mask = GENMASK(7, 0) & ~BIT(0), 5486 .mode = 0444, 5487 }, 5488 { 5489 .label = "reset_aux_pwr_or_reload", 5490 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 5491 .mask = GENMASK(7, 0) & ~BIT(2), 5492 .mode = 0444, 5493 }, 5494 { 5495 .label = "reset_comex_pwr_fail", 5496 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 5497 .mask = GENMASK(7, 0) & ~BIT(3), 5498 .mode = 0444, 5499 }, 5500 { 5501 .label = "reset_platform", 5502 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 5503 .mask = GENMASK(7, 0) & ~BIT(4), 5504 .mode = 0444, 5505 }, 5506 { 5507 .label = "reset_soc", 5508 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 5509 .mask = GENMASK(7, 0) & ~BIT(5), 5510 .mode = 0444, 5511 }, 5512 { 5513 .label = "reset_pwr", 5514 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 5515 .mask = GENMASK(7, 0) & ~BIT(7), 5516 .mode = 0444, 5517 }, 5518 { 5519 .label = "reset_pwr_converter_fail", 5520 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 5521 .mask = GENMASK(7, 0) & ~BIT(0), 5522 .mode = 0444, 5523 }, 5524 { 5525 .label = "reset_system", 5526 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 5527 .mask = GENMASK(7, 0) & ~BIT(1), 5528 .mode = 0444, 5529 }, 5530 { 5531 .label = "reset_sw_pwr_off", 5532 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 5533 .mask = GENMASK(7, 0) & ~BIT(2), 5534 .mode = 0444, 5535 }, 5536 { 5537 .label = "reset_comex_thermal", 5538 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 5539 .mask = GENMASK(7, 0) & ~BIT(3), 5540 .mode = 0444, 5541 }, 5542 { 5543 .label = "reset_ac_pwr_fail", 5544 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 5545 .mask = GENMASK(7, 0) & ~BIT(6), 5546 .mode = 0444, 5547 }, 5548 { 5549 .label = "voltreg_update_status", 5550 .reg = MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET, 5551 .mask = MLXPLAT_CPLD_VOLTREG_UPD_MASK, 5552 .bit = 5, 5553 .mode = 0444, 5554 }, 5555 { 5556 .label = "port80", 5557 .reg = MLXPLAT_CPLD_LPC_REG_GP1_RO_OFFSET, 5558 .bit = GENMASK(7, 0), 5559 .mode = 0444, 5560 }, 5561 { 5562 .label = "bios_status", 5563 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, 5564 .mask = MLXPLAT_CPLD_BIOS_STATUS_MASK, 5565 .bit = 2, 5566 .mode = 0444, 5567 }, 5568 { 5569 .label = "bios_start_retry", 5570 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, 5571 .mask = GENMASK(7, 0) & ~BIT(4), 5572 .mode = 0444, 5573 }, 5574 { 5575 .label = "bios_active_image", 5576 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, 5577 .mask = GENMASK(7, 0) & ~BIT(5), 5578 .mode = 0444, 5579 }, 5580 { 5581 .label = "vpd_wp", 5582 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, 5583 .mask = GENMASK(7, 0) & ~BIT(3), 5584 .mode = 0644, 5585 }, 5586 { 5587 .label = "pcie_asic_reset_dis", 5588 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, 5589 .mask = GENMASK(7, 0) & ~BIT(4), 5590 .mode = 0644, 5591 }, 5592 { 5593 .label = "shutdown_unlock", 5594 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, 5595 .mask = GENMASK(7, 0) & ~BIT(5), 5596 .mode = 0644, 5597 }, 5598 { 5599 .label = "fan_dir", 5600 .reg = MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION, 5601 .bit = GENMASK(7, 0), 5602 .mode = 0444, 5603 }, 5604 { 5605 .label = "dpu1_rst_en", 5606 .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, 5607 .mask = GENMASK(7, 0) & ~BIT(0), 5608 .mode = 0200, 5609 }, 5610 { 5611 .label = "dpu2_rst_en", 5612 .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, 5613 .mask = GENMASK(7, 0) & ~BIT(1), 5614 .mode = 0200, 5615 }, 5616 { 5617 .label = "dpu3_rst_en", 5618 .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, 5619 .mask = GENMASK(7, 0) & ~BIT(2), 5620 .mode = 0200, 5621 }, 5622 { 5623 .label = "dpu4_rst_en", 5624 .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, 5625 .mask = GENMASK(7, 0) & ~BIT(3), 5626 .mode = 0200, 5627 }, 5628 { 5629 .label = "psu1_on", 5630 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 5631 .mask = GENMASK(7, 0) & ~BIT(0), 5632 .mode = 0200, 5633 }, 5634 { 5635 .label = "psu2_on", 5636 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 5637 .mask = GENMASK(7, 0) & ~BIT(1), 5638 .mode = 0200, 5639 }, 5640 { 5641 .label = "pwr_cycle", 5642 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 5643 .mask = GENMASK(7, 0) & ~BIT(2), 5644 .mode = 0200, 5645 }, 5646 { 5647 .label = "pwr_down", 5648 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 5649 .mask = GENMASK(7, 0) & ~BIT(3), 5650 .mode = 0200, 5651 }, 5652 { 5653 .label = "jtag_cap", 5654 .reg = MLXPLAT_CPLD_LPC_REG_FU_CAP_OFFSET, 5655 .mask = MLXPLAT_CPLD_FU_CAP_MASK, 5656 .bit = 1, 5657 .mode = 0444, 5658 }, 5659 { 5660 .label = "jtag_enable", 5661 .reg = MLXPLAT_CPLD_LPC_REG_FIELD_UPGRADE, 5662 .mask = GENMASK(1, 0), 5663 .bit = 1, 5664 .mode = 0644, 5665 }, 5666 { 5667 .label = "non_active_bios_select", 5668 .reg = MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET, 5669 .mask = GENMASK(7, 0) & ~BIT(4), 5670 .mode = 0644, 5671 }, 5672 { 5673 .label = "bios_upgrade_fail", 5674 .reg = MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET, 5675 .mask = GENMASK(7, 0) & ~BIT(5), 5676 .mode = 0444, 5677 }, 5678 { 5679 .label = "bios_image_invert", 5680 .reg = MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET, 5681 .mask = GENMASK(7, 0) & ~BIT(6), 5682 .mode = 0644, 5683 }, 5684 { 5685 .label = "me_reboot", 5686 .reg = MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET, 5687 .mask = GENMASK(7, 0) & ~BIT(7), 5688 .mode = 0644, 5689 }, 5690 { 5691 .label = "dpu1_pwr_force", 5692 .reg = MLXPLAT_CPLD_LPC_REG_GP3_OFFSET, 5693 .mask = GENMASK(7, 0) & ~BIT(0), 5694 .mode = 0200, 5695 }, 5696 { 5697 .label = "dpu2_pwr_force", 5698 .reg = MLXPLAT_CPLD_LPC_REG_GP3_OFFSET, 5699 .mask = GENMASK(7, 0) & ~BIT(1), 5700 .mode = 0200, 5701 }, 5702 { 5703 .label = "dpu3_pwr_force", 5704 .reg = MLXPLAT_CPLD_LPC_REG_GP3_OFFSET, 5705 .mask = GENMASK(7, 0) & ~BIT(2), 5706 .mode = 0200, 5707 }, 5708 { 5709 .label = "dpu4_pwr_force", 5710 .reg = MLXPLAT_CPLD_LPC_REG_GP3_OFFSET, 5711 .mask = GENMASK(7, 0) & ~BIT(3), 5712 .mode = 0200, 5713 }, 5714 { 5715 .label = "ufm_done", 5716 .reg = MLXPLAT_CPLD_LPC_REG_GPI_MASK_OFFSET, 5717 .bit = GENMASK(7, 0), 5718 .mode = 0444, 5719 }, 5720 { 5721 .label = "asic_health", 5722 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 5723 .mask = MLXPLAT_CPLD_ASIC_MASK, 5724 .bit = 1, 5725 .mode = 0444, 5726 }, 5727 { 5728 .label = "psu1_ac_ok", 5729 .reg = MLXPLAT_CPLD_LPC_REG_PSU_AC_OFFSET, 5730 .mask = GENMASK(7, 0) & ~BIT(0), 5731 .mode = 0644, 5732 }, 5733 { 5734 .label = "psu2_ac_ok", 5735 .reg = MLXPLAT_CPLD_LPC_REG_PSU_AC_OFFSET, 5736 .mask = GENMASK(7, 0) & ~BIT(1), 5737 .mode = 0644, 5738 }, 5739 { 5740 .label = "psu1_no_alert", 5741 .reg = MLXPLAT_CPLD_LPC_REG_PSU_ALERT_OFFSET, 5742 .mask = GENMASK(7, 0) & ~BIT(0), 5743 .mode = 0644, 5744 }, 5745 { 5746 .label = "psu2_no_alert", 5747 .reg = MLXPLAT_CPLD_LPC_REG_PSU_ALERT_OFFSET, 5748 .mask = GENMASK(7, 0) & ~BIT(1), 5749 .mode = 0644, 5750 }, 5751 { 5752 .label = "asic_pg_fail", 5753 .reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET, 5754 .mask = GENMASK(7, 0) & ~BIT(7), 5755 .mode = 0444, 5756 }, 5757 { 5758 .label = "spi_chnl_select", 5759 .reg = MLXPLAT_CPLD_LPC_REG_SPI_CHNL_SELECT, 5760 .mask = GENMASK(7, 0), 5761 .bit = 1, 5762 .mode = 0644, 5763 }, 5764 { 5765 .label = "config1", 5766 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET, 5767 .bit = GENMASK(7, 0), 5768 .mode = 0444, 5769 }, 5770 { 5771 .label = "config2", 5772 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET, 5773 .bit = GENMASK(7, 0), 5774 .mode = 0444, 5775 }, 5776 { 5777 .label = "config3", 5778 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET, 5779 .bit = GENMASK(7, 0), 5780 .mode = 0444, 5781 }, 5782 { 5783 .label = "ufm_version", 5784 .reg = MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET, 5785 .bit = GENMASK(7, 0), 5786 .mode = 0444, 5787 }, 5788 }; 5789 5790 static struct mlxreg_core_platform_data mlxplat_smart_switch_regs_io_data = { 5791 .data = mlxplat_mlxcpld_smart_switch_regs_io_data, 5792 .counter = ARRAY_SIZE(mlxplat_mlxcpld_smart_switch_regs_io_data), 5793 }; 5794 5795 /* Platform FAN default */ 5796 static struct mlxreg_core_data mlxplat_mlxcpld_default_fan_data[] = { 5797 { 5798 .label = "pwm1", 5799 .reg = MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET, 5800 }, 5801 { 5802 .label = "pwm2", 5803 .reg = MLXPLAT_CPLD_LPC_REG_PWM2_OFFSET, 5804 }, 5805 { 5806 .label = "pwm3", 5807 .reg = MLXPLAT_CPLD_LPC_REG_PWM3_OFFSET, 5808 }, 5809 { 5810 .label = "pwm4", 5811 .reg = MLXPLAT_CPLD_LPC_REG_PWM4_OFFSET, 5812 }, 5813 { 5814 .label = "tacho1", 5815 .reg = MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET, 5816 .mask = GENMASK(7, 0), 5817 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 5818 .bit = BIT(0), 5819 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 5820 5821 }, 5822 { 5823 .label = "tacho2", 5824 .reg = MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET, 5825 .mask = GENMASK(7, 0), 5826 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 5827 .bit = BIT(1), 5828 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 5829 }, 5830 { 5831 .label = "tacho3", 5832 .reg = MLXPLAT_CPLD_LPC_REG_TACHO3_OFFSET, 5833 .mask = GENMASK(7, 0), 5834 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 5835 .bit = BIT(2), 5836 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 5837 }, 5838 { 5839 .label = "tacho4", 5840 .reg = MLXPLAT_CPLD_LPC_REG_TACHO4_OFFSET, 5841 .mask = GENMASK(7, 0), 5842 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 5843 .bit = BIT(3), 5844 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 5845 }, 5846 { 5847 .label = "tacho5", 5848 .reg = MLXPLAT_CPLD_LPC_REG_TACHO5_OFFSET, 5849 .mask = GENMASK(7, 0), 5850 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 5851 .bit = BIT(4), 5852 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 5853 }, 5854 { 5855 .label = "tacho6", 5856 .reg = MLXPLAT_CPLD_LPC_REG_TACHO6_OFFSET, 5857 .mask = GENMASK(7, 0), 5858 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 5859 .bit = BIT(5), 5860 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 5861 }, 5862 { 5863 .label = "tacho7", 5864 .reg = MLXPLAT_CPLD_LPC_REG_TACHO7_OFFSET, 5865 .mask = GENMASK(7, 0), 5866 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 5867 .bit = BIT(6), 5868 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 5869 }, 5870 { 5871 .label = "tacho8", 5872 .reg = MLXPLAT_CPLD_LPC_REG_TACHO8_OFFSET, 5873 .mask = GENMASK(7, 0), 5874 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 5875 .bit = BIT(7), 5876 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 5877 }, 5878 { 5879 .label = "tacho9", 5880 .reg = MLXPLAT_CPLD_LPC_REG_TACHO9_OFFSET, 5881 .mask = GENMASK(7, 0), 5882 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET, 5883 .bit = BIT(0), 5884 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 5885 }, 5886 { 5887 .label = "tacho10", 5888 .reg = MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET, 5889 .mask = GENMASK(7, 0), 5890 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET, 5891 .bit = BIT(1), 5892 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 5893 }, 5894 { 5895 .label = "tacho11", 5896 .reg = MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET, 5897 .mask = GENMASK(7, 0), 5898 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET, 5899 .bit = BIT(2), 5900 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 5901 }, 5902 { 5903 .label = "tacho12", 5904 .reg = MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET, 5905 .mask = GENMASK(7, 0), 5906 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET, 5907 .bit = BIT(3), 5908 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 5909 }, 5910 { 5911 .label = "tacho13", 5912 .reg = MLXPLAT_CPLD_LPC_REG_TACHO13_OFFSET, 5913 .mask = GENMASK(7, 0), 5914 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET, 5915 .bit = BIT(4), 5916 }, 5917 { 5918 .label = "tacho14", 5919 .reg = MLXPLAT_CPLD_LPC_REG_TACHO14_OFFSET, 5920 .mask = GENMASK(7, 0), 5921 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET, 5922 .bit = BIT(5), 5923 }, 5924 { 5925 .label = "conf", 5926 .capability = MLXPLAT_CPLD_LPC_REG_TACHO_SPEED_OFFSET, 5927 }, 5928 }; 5929 5930 static struct mlxreg_core_platform_data mlxplat_default_fan_data = { 5931 .data = mlxplat_mlxcpld_default_fan_data, 5932 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_fan_data), 5933 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 5934 }; 5935 5936 /* XDR and smart switch platform fan data */ 5937 static struct mlxreg_core_data mlxplat_mlxcpld_xdr_fan_data[] = { 5938 { 5939 .label = "pwm1", 5940 .reg = MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET, 5941 }, 5942 { 5943 .label = "tacho1", 5944 .reg = MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET, 5945 .mask = GENMASK(7, 0), 5946 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 5947 .slot = 1, 5948 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 5949 }, 5950 { 5951 .label = "tacho2", 5952 .reg = MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET, 5953 .mask = GENMASK(7, 0), 5954 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 5955 .slot = 2, 5956 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 5957 }, 5958 { 5959 .label = "tacho3", 5960 .reg = MLXPLAT_CPLD_LPC_REG_TACHO3_OFFSET, 5961 .mask = GENMASK(7, 0), 5962 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 5963 .slot = 3, 5964 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 5965 }, 5966 { 5967 .label = "tacho4", 5968 .reg = MLXPLAT_CPLD_LPC_REG_TACHO4_OFFSET, 5969 .mask = GENMASK(7, 0), 5970 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 5971 .slot = 4, 5972 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 5973 }, 5974 { 5975 .label = "tacho5", 5976 .reg = MLXPLAT_CPLD_LPC_REG_TACHO5_OFFSET, 5977 .mask = GENMASK(7, 0), 5978 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 5979 .slot = 5, 5980 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 5981 }, 5982 { 5983 .label = "tacho6", 5984 .reg = MLXPLAT_CPLD_LPC_REG_TACHO6_OFFSET, 5985 .mask = GENMASK(7, 0), 5986 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 5987 .slot = 6, 5988 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 5989 }, 5990 { 5991 .label = "tacho7", 5992 .reg = MLXPLAT_CPLD_LPC_REG_TACHO7_OFFSET, 5993 .mask = GENMASK(7, 0), 5994 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 5995 .slot = 7, 5996 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 5997 }, 5998 { 5999 .label = "tacho8", 6000 .reg = MLXPLAT_CPLD_LPC_REG_TACHO8_OFFSET, 6001 .mask = GENMASK(7, 0), 6002 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 6003 .slot = 8, 6004 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 6005 }, 6006 { 6007 .label = "tacho9", 6008 .reg = MLXPLAT_CPLD_LPC_REG_TACHO9_OFFSET, 6009 .mask = GENMASK(7, 0), 6010 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 6011 .slot = 9, 6012 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 6013 }, 6014 { 6015 .label = "tacho10", 6016 .reg = MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET, 6017 .mask = GENMASK(7, 0), 6018 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 6019 .slot = 10, 6020 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 6021 }, 6022 { 6023 .label = "tacho11", 6024 .reg = MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET, 6025 .mask = GENMASK(7, 0), 6026 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 6027 .slot = 11, 6028 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 6029 }, 6030 { 6031 .label = "tacho12", 6032 .reg = MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET, 6033 .mask = GENMASK(7, 0), 6034 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 6035 .slot = 12, 6036 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 6037 }, 6038 { 6039 .label = "tacho13", 6040 .reg = MLXPLAT_CPLD_LPC_REG_TACHO13_OFFSET, 6041 .mask = GENMASK(7, 0), 6042 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 6043 .slot = 13, 6044 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 6045 }, 6046 { 6047 .label = "tacho14", 6048 .reg = MLXPLAT_CPLD_LPC_REG_TACHO14_OFFSET, 6049 .mask = GENMASK(7, 0), 6050 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 6051 .slot = 14, 6052 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 6053 }, 6054 { 6055 .label = "tacho15", 6056 .reg = MLXPLAT_CPLD_LPC_REG_TACHO15_OFFSET, 6057 .mask = GENMASK(7, 0), 6058 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 6059 .slot = 15, 6060 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 6061 }, 6062 { 6063 .label = "tacho16", 6064 .reg = MLXPLAT_CPLD_LPC_REG_TACHO16_OFFSET, 6065 .mask = GENMASK(7, 0), 6066 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 6067 .slot = 16, 6068 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 6069 }, 6070 { 6071 .label = "tacho17", 6072 .reg = MLXPLAT_CPLD_LPC_REG_TACHO17_OFFSET, 6073 .mask = GENMASK(7, 0), 6074 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 6075 .slot = 17, 6076 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN2_OFFSET, 6077 }, 6078 { 6079 .label = "tacho18", 6080 .reg = MLXPLAT_CPLD_LPC_REG_TACHO18_OFFSET, 6081 .mask = GENMASK(7, 0), 6082 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 6083 .slot = 18, 6084 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN2_OFFSET, 6085 }, 6086 { 6087 .label = "tacho19", 6088 .reg = MLXPLAT_CPLD_LPC_REG_TACHO19_OFFSET, 6089 .mask = GENMASK(7, 0), 6090 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 6091 .slot = 19, 6092 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN2_OFFSET, 6093 }, 6094 { 6095 .label = "tacho20", 6096 .reg = MLXPLAT_CPLD_LPC_REG_TACHO20_OFFSET, 6097 .mask = GENMASK(7, 0), 6098 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 6099 .slot = 20, 6100 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN2_OFFSET, 6101 }, 6102 { 6103 .label = "conf", 6104 .capability = MLXPLAT_CPLD_LPC_REG_TACHO_SPEED_OFFSET, 6105 }, 6106 }; 6107 6108 static struct mlxreg_core_platform_data mlxplat_xdr_fan_data = { 6109 .data = mlxplat_mlxcpld_xdr_fan_data, 6110 .counter = ARRAY_SIZE(mlxplat_mlxcpld_xdr_fan_data), 6111 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 6112 .version = 1, 6113 }; 6114 6115 /* Watchdog type1: hardware implementation version1 6116 * (MSN2700, MSN2410, MSN2740, MSN2100 and MSN2140 systems). 6117 */ 6118 static struct mlxreg_core_data mlxplat_mlxcpld_wd_main_regs_type1[] = { 6119 { 6120 .label = "action", 6121 .reg = MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET, 6122 .mask = MLXPLAT_CPLD_WD_RESET_ACT_MASK, 6123 .bit = 0, 6124 }, 6125 { 6126 .label = "timeout", 6127 .reg = MLXPLAT_CPLD_LPC_REG_WD1_TMR_OFFSET, 6128 .mask = MLXPLAT_CPLD_WD_TYPE1_TO_MASK, 6129 .health_cntr = MLXPLAT_CPLD_WD_DFLT_TIMEOUT, 6130 }, 6131 { 6132 .label = "ping", 6133 .reg = MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET, 6134 .mask = MLXPLAT_CPLD_WD1_CLEAR_MASK, 6135 .bit = 0, 6136 }, 6137 { 6138 .label = "reset", 6139 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 6140 .mask = GENMASK(7, 0) & ~BIT(6), 6141 .bit = 6, 6142 }, 6143 }; 6144 6145 static struct mlxreg_core_data mlxplat_mlxcpld_wd_aux_regs_type1[] = { 6146 { 6147 .label = "action", 6148 .reg = MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET, 6149 .mask = MLXPLAT_CPLD_WD_FAN_ACT_MASK, 6150 .bit = 4, 6151 }, 6152 { 6153 .label = "timeout", 6154 .reg = MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET, 6155 .mask = MLXPLAT_CPLD_WD_TYPE1_TO_MASK, 6156 .health_cntr = MLXPLAT_CPLD_WD_DFLT_TIMEOUT, 6157 }, 6158 { 6159 .label = "ping", 6160 .reg = MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET, 6161 .mask = MLXPLAT_CPLD_WD1_CLEAR_MASK, 6162 .bit = 1, 6163 }, 6164 }; 6165 6166 static struct mlxreg_core_platform_data mlxplat_mlxcpld_wd_set_type1[] = { 6167 { 6168 .data = mlxplat_mlxcpld_wd_main_regs_type1, 6169 .counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_main_regs_type1), 6170 .version = MLX_WDT_TYPE1, 6171 .identity = "mlx-wdt-main", 6172 }, 6173 { 6174 .data = mlxplat_mlxcpld_wd_aux_regs_type1, 6175 .counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_aux_regs_type1), 6176 .version = MLX_WDT_TYPE1, 6177 .identity = "mlx-wdt-aux", 6178 }, 6179 }; 6180 6181 /* Watchdog type2: hardware implementation version 2 6182 * (all systems except (MSN2700, MSN2410, MSN2740, MSN2100 and MSN2140). 6183 */ 6184 static struct mlxreg_core_data mlxplat_mlxcpld_wd_main_regs_type2[] = { 6185 { 6186 .label = "action", 6187 .reg = MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET, 6188 .mask = MLXPLAT_CPLD_WD_RESET_ACT_MASK, 6189 .bit = 0, 6190 }, 6191 { 6192 .label = "timeout", 6193 .reg = MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET, 6194 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK, 6195 .health_cntr = MLXPLAT_CPLD_WD_DFLT_TIMEOUT, 6196 }, 6197 { 6198 .label = "timeleft", 6199 .reg = MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET, 6200 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK, 6201 }, 6202 { 6203 .label = "ping", 6204 .reg = MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET, 6205 .mask = MLXPLAT_CPLD_WD_RESET_ACT_MASK, 6206 .bit = 0, 6207 }, 6208 { 6209 .label = "reset", 6210 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 6211 .mask = GENMASK(7, 0) & ~BIT(6), 6212 .bit = 6, 6213 }, 6214 }; 6215 6216 static struct mlxreg_core_data mlxplat_mlxcpld_wd_aux_regs_type2[] = { 6217 { 6218 .label = "action", 6219 .reg = MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET, 6220 .mask = MLXPLAT_CPLD_WD_FAN_ACT_MASK, 6221 .bit = 4, 6222 }, 6223 { 6224 .label = "timeout", 6225 .reg = MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET, 6226 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK, 6227 .health_cntr = MLXPLAT_CPLD_WD_DFLT_TIMEOUT, 6228 }, 6229 { 6230 .label = "timeleft", 6231 .reg = MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET, 6232 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK, 6233 }, 6234 { 6235 .label = "ping", 6236 .reg = MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET, 6237 .mask = MLXPLAT_CPLD_WD_FAN_ACT_MASK, 6238 .bit = 4, 6239 }, 6240 }; 6241 6242 static struct mlxreg_core_platform_data mlxplat_mlxcpld_wd_set_type2[] = { 6243 { 6244 .data = mlxplat_mlxcpld_wd_main_regs_type2, 6245 .counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_main_regs_type2), 6246 .version = MLX_WDT_TYPE2, 6247 .identity = "mlx-wdt-main", 6248 }, 6249 { 6250 .data = mlxplat_mlxcpld_wd_aux_regs_type2, 6251 .counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_aux_regs_type2), 6252 .version = MLX_WDT_TYPE2, 6253 .identity = "mlx-wdt-aux", 6254 }, 6255 }; 6256 6257 /* Watchdog type3: hardware implementation version 3 6258 * Can be on all systems. It's differentiated by WD capability bit. 6259 * Old systems (MSN2700, MSN2410, MSN2740, MSN2100 and MSN2140) 6260 * still have only one main watchdog. 6261 */ 6262 static struct mlxreg_core_data mlxplat_mlxcpld_wd_main_regs_type3[] = { 6263 { 6264 .label = "action", 6265 .reg = MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET, 6266 .mask = MLXPLAT_CPLD_WD_RESET_ACT_MASK, 6267 .bit = 0, 6268 }, 6269 { 6270 .label = "timeout", 6271 .reg = MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET, 6272 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK, 6273 .health_cntr = MLXPLAT_CPLD_WD3_DFLT_TIMEOUT, 6274 }, 6275 { 6276 .label = "timeleft", 6277 .reg = MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET, 6278 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK, 6279 }, 6280 { 6281 .label = "ping", 6282 .reg = MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET, 6283 .mask = MLXPLAT_CPLD_WD_RESET_ACT_MASK, 6284 .bit = 0, 6285 }, 6286 { 6287 .label = "reset", 6288 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 6289 .mask = GENMASK(7, 0) & ~BIT(6), 6290 .bit = 6, 6291 }, 6292 }; 6293 6294 static struct mlxreg_core_data mlxplat_mlxcpld_wd_aux_regs_type3[] = { 6295 { 6296 .label = "action", 6297 .reg = MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET, 6298 .mask = MLXPLAT_CPLD_WD_FAN_ACT_MASK, 6299 .bit = 4, 6300 }, 6301 { 6302 .label = "timeout", 6303 .reg = MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET, 6304 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK, 6305 .health_cntr = MLXPLAT_CPLD_WD3_DFLT_TIMEOUT, 6306 }, 6307 { 6308 .label = "timeleft", 6309 .reg = MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET, 6310 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK, 6311 }, 6312 { 6313 .label = "ping", 6314 .reg = MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET, 6315 .mask = MLXPLAT_CPLD_WD_FAN_ACT_MASK, 6316 .bit = 4, 6317 }, 6318 }; 6319 6320 static struct mlxreg_core_platform_data mlxplat_mlxcpld_wd_set_type3[] = { 6321 { 6322 .data = mlxplat_mlxcpld_wd_main_regs_type3, 6323 .counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_main_regs_type3), 6324 .version = MLX_WDT_TYPE3, 6325 .identity = "mlx-wdt-main", 6326 }, 6327 { 6328 .data = mlxplat_mlxcpld_wd_aux_regs_type3, 6329 .counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_aux_regs_type3), 6330 .version = MLX_WDT_TYPE3, 6331 .identity = "mlx-wdt-aux", 6332 }, 6333 }; 6334 6335 static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg) 6336 { 6337 switch (reg) { 6338 case MLXPLAT_CPLD_LPC_REG_RESET_GP1_OFFSET: 6339 case MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET: 6340 case MLXPLAT_CPLD_LPC_REG_RESET_GP3_OFFSET: 6341 case MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET: 6342 case MLXPLAT_CPLD_LPC_REG_LED1_OFFSET: 6343 case MLXPLAT_CPLD_LPC_REG_LED2_OFFSET: 6344 case MLXPLAT_CPLD_LPC_REG_LED3_OFFSET: 6345 case MLXPLAT_CPLD_LPC_REG_LED4_OFFSET: 6346 case MLXPLAT_CPLD_LPC_REG_LED5_OFFSET: 6347 case MLXPLAT_CPLD_LPC_REG_LED6_OFFSET: 6348 case MLXPLAT_CPLD_LPC_REG_LED7_OFFSET: 6349 case MLXPLAT_CPLD_LPC_REG_LED8_OFFSET: 6350 case MLXPLAT_CPLD_LPC_REG_GP0_OFFSET: 6351 case MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET: 6352 case MLXPLAT_CPLD_LPC_REG_GP1_OFFSET: 6353 case MLXPLAT_CPLD_LPC_REG_WP1_OFFSET: 6354 case MLXPLAT_CPLD_LPC_REG_GP2_OFFSET: 6355 case MLXPLAT_CPLD_LPC_REG_WP2_OFFSET: 6356 case MLXPLAT_CPLD_LPC_REG_GP3_OFFSET: 6357 case MLXPLAT_CPLD_LPC_REG_FIELD_UPGRADE: 6358 case MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET: 6359 case MLXPLAT_CPLD_LPC_SAFE_BIOS_WP_OFFSET: 6360 case MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET: 6361 case MLXPLAT_CPLD_LPC_REG_FU_CAP_OFFSET: 6362 case MLXPLAT_CPLD_LPC_REG_DBG1_OFFSET: 6363 case MLXPLAT_CPLD_LPC_REG_DBG2_OFFSET: 6364 case MLXPLAT_CPLD_LPC_REG_DBG3_OFFSET: 6365 case MLXPLAT_CPLD_LPC_REG_DBG4_OFFSET: 6366 case MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET: 6367 case MLXPLAT_CPLD_LPC_REG_AGGRCO_MASK_OFFSET: 6368 case MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET: 6369 case MLXPLAT_CPLD_LPC_REG_GWP_EVENT_OFFSET: 6370 case MLXPLAT_CPLD_LPC_REG_GWP_MASK_OFFSET: 6371 case MLXPLAT_CPLD_LPC_REG_BRD_OFFSET: 6372 case MLXPLAT_CPLD_LPC_REG_BRD_EVENT_OFFSET: 6373 case MLXPLAT_CPLD_LPC_REG_BRD_MASK_OFFSET: 6374 case MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET: 6375 case MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET: 6376 case MLXPLAT_CPLD_LPC_REG_ASIC2_EVENT_OFFSET: 6377 case MLXPLAT_CPLD_LPC_REG_ASIC2_MASK_OFFSET: 6378 case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET: 6379 case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET: 6380 case MLXPLAT_CPLD_LPC_REG_PSU_AC_OFFSET: 6381 case MLXPLAT_CPLD_LPC_REG_PWR_EVENT_OFFSET: 6382 case MLXPLAT_CPLD_LPC_REG_PWR_MASK_OFFSET: 6383 case MLXPLAT_CPLD_LPC_REG_PSU_ALERT_OFFSET: 6384 case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET: 6385 case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET: 6386 case MLXPLAT_CPLD_LPC_REG_FAN2_EVENT_OFFSET: 6387 case MLXPLAT_CPLD_LPC_REG_FAN2_MASK_OFFSET: 6388 case MLXPLAT_CPLD_LPC_REG_EROT_EVENT_OFFSET: 6389 case MLXPLAT_CPLD_LPC_REG_EROT_MASK_OFFSET: 6390 case MLXPLAT_CPLD_LPC_REG_EROTE_EVENT_OFFSET: 6391 case MLXPLAT_CPLD_LPC_REG_EROTE_MASK_OFFSET: 6392 case MLXPLAT_CPLD_LPC_REG_PWRB_EVENT_OFFSET: 6393 case MLXPLAT_CPLD_LPC_REG_PWRB_MASK_OFFSET: 6394 case MLXPLAT_CPLD_LPC_REG_AGGRLC_MASK_OFFSET: 6395 case MLXPLAT_CPLD_LPC_REG_LC_IN_EVENT_OFFSET: 6396 case MLXPLAT_CPLD_LPC_REG_LC_IN_MASK_OFFSET: 6397 case MLXPLAT_CPLD_LPC_REG_LC_VR_EVENT_OFFSET: 6398 case MLXPLAT_CPLD_LPC_REG_LC_VR_MASK_OFFSET: 6399 case MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET: 6400 case MLXPLAT_CPLD_LPC_REG_LC_PG_EVENT_OFFSET: 6401 case MLXPLAT_CPLD_LPC_REG_LC_PG_MASK_OFFSET: 6402 case MLXPLAT_CPLD_LPC_REG_LC_RD_EVENT_OFFSET: 6403 case MLXPLAT_CPLD_LPC_REG_LC_RD_MASK_OFFSET: 6404 case MLXPLAT_CPLD_LPC_REG_LC_OK_EVENT_OFFSET: 6405 case MLXPLAT_CPLD_LPC_REG_LC_OK_MASK_OFFSET: 6406 case MLXPLAT_CPLD_LPC_REG_LC_SN_EVENT_OFFSET: 6407 case MLXPLAT_CPLD_LPC_REG_LC_SN_MASK_OFFSET: 6408 case MLXPLAT_CPLD_LPC_REG_LC_SD_EVENT_OFFSET: 6409 case MLXPLAT_CPLD_LPC_REG_LC_SD_MASK_OFFSET: 6410 case MLXPLAT_CPLD_LPC_REG_LC_PWR_ON: 6411 case MLXPLAT_CPLD_LPC_REG_SPI_CHNL_SELECT: 6412 case MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET: 6413 case MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET: 6414 case MLXPLAT_CPLD_LPC_REG_WD1_TMR_OFFSET: 6415 case MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET: 6416 case MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET: 6417 case MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET: 6418 case MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET: 6419 case MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET: 6420 case MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET: 6421 case MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET: 6422 case MLXPLAT_CPLD_LPC_REG_I2C_CH1_OFFSET: 6423 case MLXPLAT_CPLD_LPC_REG_I2C_CH2_OFFSET: 6424 case MLXPLAT_CPLD_LPC_REG_I2C_CH3_OFFSET: 6425 case MLXPLAT_CPLD_LPC_REG_I2C_CH4_OFFSET: 6426 case MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET: 6427 case MLXPLAT_CPLD_LPC_REG_PWM2_OFFSET: 6428 case MLXPLAT_CPLD_LPC_REG_PWM3_OFFSET: 6429 case MLXPLAT_CPLD_LPC_REG_PWM4_OFFSET: 6430 case MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET: 6431 return true; 6432 } 6433 return false; 6434 } 6435 6436 static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) 6437 { 6438 switch (reg) { 6439 case MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET: 6440 case MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET: 6441 case MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET: 6442 case MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET: 6443 case MLXPLAT_CPLD_LPC_REG_CPLD5_VER_OFFSET: 6444 case MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET: 6445 case MLXPLAT_CPLD_LPC_REG_CPLD1_PN1_OFFSET: 6446 case MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET: 6447 case MLXPLAT_CPLD_LPC_REG_CPLD2_PN1_OFFSET: 6448 case MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET: 6449 case MLXPLAT_CPLD_LPC_REG_CPLD3_PN1_OFFSET: 6450 case MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET: 6451 case MLXPLAT_CPLD_LPC_REG_CPLD4_PN1_OFFSET: 6452 case MLXPLAT_CPLD_LPC_REG_CPLD5_PN_OFFSET: 6453 case MLXPLAT_CPLD_LPC_REG_CPLD5_PN1_OFFSET: 6454 case MLXPLAT_CPLD_LPC_REG_RESET_GP1_OFFSET: 6455 case MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET: 6456 case MLXPLAT_CPLD_LPC_REG_RESET_GP3_OFFSET: 6457 case MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET: 6458 case MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET: 6459 case MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET: 6460 case MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET: 6461 case MLXPLAT_CPLD_LPC_REG_LED1_OFFSET: 6462 case MLXPLAT_CPLD_LPC_REG_LED2_OFFSET: 6463 case MLXPLAT_CPLD_LPC_REG_LED3_OFFSET: 6464 case MLXPLAT_CPLD_LPC_REG_LED4_OFFSET: 6465 case MLXPLAT_CPLD_LPC_REG_LED5_OFFSET: 6466 case MLXPLAT_CPLD_LPC_REG_LED6_OFFSET: 6467 case MLXPLAT_CPLD_LPC_REG_LED7_OFFSET: 6468 case MLXPLAT_CPLD_LPC_REG_LED8_OFFSET: 6469 case MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION: 6470 case MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET: 6471 case MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET: 6472 case MLXPLAT_CPLD_LPC_REG_GP1_RO_OFFSET: 6473 case MLXPLAT_CPLD_LPC_REG_GP0_OFFSET: 6474 case MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET: 6475 case MLXPLAT_CPLD_LPC_REG_GP1_OFFSET: 6476 case MLXPLAT_CPLD_LPC_REG_WP1_OFFSET: 6477 case MLXPLAT_CPLD_LPC_REG_GP2_OFFSET: 6478 case MLXPLAT_CPLD_LPC_REG_WP2_OFFSET: 6479 case MLXPLAT_CPLD_LPC_REG_GP3_OFFSET: 6480 case MLXPLAT_CPLD_LPC_REG_FIELD_UPGRADE: 6481 case MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET: 6482 case MLXPLAT_CPLD_LPC_SAFE_BIOS_WP_OFFSET: 6483 case MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET: 6484 case MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET: 6485 case MLXPLAT_CPLD_LPC_REG_FU_CAP_OFFSET: 6486 case MLXPLAT_CPLD_LPC_REG_DBG1_OFFSET: 6487 case MLXPLAT_CPLD_LPC_REG_DBG2_OFFSET: 6488 case MLXPLAT_CPLD_LPC_REG_DBG3_OFFSET: 6489 case MLXPLAT_CPLD_LPC_REG_DBG4_OFFSET: 6490 case MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET: 6491 case MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET: 6492 case MLXPLAT_CPLD_LPC_REG_AGGRCO_OFFSET: 6493 case MLXPLAT_CPLD_LPC_REG_AGGRCO_MASK_OFFSET: 6494 case MLXPLAT_CPLD_LPC_REG_AGGRCX_OFFSET: 6495 case MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET: 6496 case MLXPLAT_CPLD_LPC_REG_GWP_OFFSET: 6497 case MLXPLAT_CPLD_LPC_REG_GWP_EVENT_OFFSET: 6498 case MLXPLAT_CPLD_LPC_REG_GWP_MASK_OFFSET: 6499 case MLXPLAT_CPLD_LPC_REG_GPI_MASK_OFFSET: 6500 case MLXPLAT_CPLD_LPC_REG_BRD_OFFSET: 6501 case MLXPLAT_CPLD_LPC_REG_BRD_EVENT_OFFSET: 6502 case MLXPLAT_CPLD_LPC_REG_BRD_MASK_OFFSET: 6503 case MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET: 6504 case MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET: 6505 case MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET: 6506 case MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET: 6507 case MLXPLAT_CPLD_LPC_REG_ASIC2_EVENT_OFFSET: 6508 case MLXPLAT_CPLD_LPC_REG_ASIC2_MASK_OFFSET: 6509 case MLXPLAT_CPLD_LPC_REG_PSU_OFFSET: 6510 case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET: 6511 case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET: 6512 case MLXPLAT_CPLD_LPC_REG_PSU_AC_OFFSET: 6513 case MLXPLAT_CPLD_LPC_REG_PWR_OFFSET: 6514 case MLXPLAT_CPLD_LPC_REG_PWR_EVENT_OFFSET: 6515 case MLXPLAT_CPLD_LPC_REG_PWR_MASK_OFFSET: 6516 case MLXPLAT_CPLD_LPC_REG_PSU_ALERT_OFFSET: 6517 case MLXPLAT_CPLD_LPC_REG_FAN_OFFSET: 6518 case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET: 6519 case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET: 6520 case MLXPLAT_CPLD_LPC_REG_FAN2_OFFSET: 6521 case MLXPLAT_CPLD_LPC_REG_FAN2_EVENT_OFFSET: 6522 case MLXPLAT_CPLD_LPC_REG_FAN2_MASK_OFFSET: 6523 case MLXPLAT_CPLD_LPC_REG_EROT_OFFSET: 6524 case MLXPLAT_CPLD_LPC_REG_EROT_EVENT_OFFSET: 6525 case MLXPLAT_CPLD_LPC_REG_EROT_MASK_OFFSET: 6526 case MLXPLAT_CPLD_LPC_REG_EROTE_OFFSET: 6527 case MLXPLAT_CPLD_LPC_REG_EROTE_EVENT_OFFSET: 6528 case MLXPLAT_CPLD_LPC_REG_EROTE_MASK_OFFSET: 6529 case MLXPLAT_CPLD_LPC_REG_PWRB_OFFSET: 6530 case MLXPLAT_CPLD_LPC_REG_PWRB_EVENT_OFFSET: 6531 case MLXPLAT_CPLD_LPC_REG_PWRB_MASK_OFFSET: 6532 case MLXPLAT_CPLD_LPC_REG_AGGRLC_OFFSET: 6533 case MLXPLAT_CPLD_LPC_REG_AGGRLC_MASK_OFFSET: 6534 case MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET: 6535 case MLXPLAT_CPLD_LPC_REG_LC_IN_EVENT_OFFSET: 6536 case MLXPLAT_CPLD_LPC_REG_LC_IN_MASK_OFFSET: 6537 case MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET: 6538 case MLXPLAT_CPLD_LPC_REG_LC_VR_EVENT_OFFSET: 6539 case MLXPLAT_CPLD_LPC_REG_LC_VR_MASK_OFFSET: 6540 case MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET: 6541 case MLXPLAT_CPLD_LPC_REG_LC_PG_EVENT_OFFSET: 6542 case MLXPLAT_CPLD_LPC_REG_LC_PG_MASK_OFFSET: 6543 case MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET: 6544 case MLXPLAT_CPLD_LPC_REG_LC_RD_EVENT_OFFSET: 6545 case MLXPLAT_CPLD_LPC_REG_LC_RD_MASK_OFFSET: 6546 case MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET: 6547 case MLXPLAT_CPLD_LPC_REG_LC_OK_EVENT_OFFSET: 6548 case MLXPLAT_CPLD_LPC_REG_LC_OK_MASK_OFFSET: 6549 case MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET: 6550 case MLXPLAT_CPLD_LPC_REG_LC_SN_EVENT_OFFSET: 6551 case MLXPLAT_CPLD_LPC_REG_LC_SN_MASK_OFFSET: 6552 case MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET: 6553 case MLXPLAT_CPLD_LPC_REG_LC_SD_EVENT_OFFSET: 6554 case MLXPLAT_CPLD_LPC_REG_LC_SD_MASK_OFFSET: 6555 case MLXPLAT_CPLD_LPC_REG_LC_PWR_ON: 6556 case MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET: 6557 case MLXPLAT_CPLD_LPC_REG_SPI_CHNL_SELECT: 6558 case MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET: 6559 case MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET: 6560 case MLXPLAT_CPLD_LPC_REG_WD1_TMR_OFFSET: 6561 case MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET: 6562 case MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET: 6563 case MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET: 6564 case MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET: 6565 case MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET: 6566 case MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET: 6567 case MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET: 6568 case MLXPLAT_CPLD_LPC_REG_CPLD6_MVER_OFFSET: 6569 case MLXPLAT_CPLD_LPC_REG_I2C_CH1_OFFSET: 6570 case MLXPLAT_CPLD_LPC_REG_I2C_CH2_OFFSET: 6571 case MLXPLAT_CPLD_LPC_REG_I2C_CH3_OFFSET: 6572 case MLXPLAT_CPLD_LPC_REG_I2C_CH4_OFFSET: 6573 case MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET: 6574 case MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET: 6575 case MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET: 6576 case MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET: 6577 case MLXPLAT_CPLD_LPC_REG_CPLD5_MVER_OFFSET: 6578 case MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET: 6579 case MLXPLAT_CPLD_LPC_REG_PWM2_OFFSET: 6580 case MLXPLAT_CPLD_LPC_REG_PWM3_OFFSET: 6581 case MLXPLAT_CPLD_LPC_REG_PWM4_OFFSET: 6582 case MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET: 6583 case MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET: 6584 case MLXPLAT_CPLD_LPC_REG_TACHO3_OFFSET: 6585 case MLXPLAT_CPLD_LPC_REG_TACHO4_OFFSET: 6586 case MLXPLAT_CPLD_LPC_REG_TACHO5_OFFSET: 6587 case MLXPLAT_CPLD_LPC_REG_TACHO6_OFFSET: 6588 case MLXPLAT_CPLD_LPC_REG_TACHO7_OFFSET: 6589 case MLXPLAT_CPLD_LPC_REG_TACHO8_OFFSET: 6590 case MLXPLAT_CPLD_LPC_REG_TACHO9_OFFSET: 6591 case MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET: 6592 case MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET: 6593 case MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET: 6594 case MLXPLAT_CPLD_LPC_REG_TACHO13_OFFSET: 6595 case MLXPLAT_CPLD_LPC_REG_TACHO14_OFFSET: 6596 case MLXPLAT_CPLD_LPC_REG_TACHO15_OFFSET: 6597 case MLXPLAT_CPLD_LPC_REG_TACHO16_OFFSET: 6598 case MLXPLAT_CPLD_LPC_REG_TACHO17_OFFSET: 6599 case MLXPLAT_CPLD_LPC_REG_TACHO18_OFFSET: 6600 case MLXPLAT_CPLD_LPC_REG_TACHO19_OFFSET: 6601 case MLXPLAT_CPLD_LPC_REG_TACHO20_OFFSET: 6602 case MLXPLAT_CPLD_LPC_REG_ASIC_CAP_OFFSET: 6603 case MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET: 6604 case MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET: 6605 case MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET: 6606 case MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET: 6607 case MLXPLAT_CPLD_LPC_REG_TACHO_SPEED_OFFSET: 6608 case MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET: 6609 case MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET: 6610 case MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET: 6611 case MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET: 6612 case MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET: 6613 case MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET: 6614 return true; 6615 } 6616 return false; 6617 } 6618 6619 static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) 6620 { 6621 switch (reg) { 6622 case MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET: 6623 case MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET: 6624 case MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET: 6625 case MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET: 6626 case MLXPLAT_CPLD_LPC_REG_CPLD5_VER_OFFSET: 6627 case MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET: 6628 case MLXPLAT_CPLD_LPC_REG_CPLD1_PN1_OFFSET: 6629 case MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET: 6630 case MLXPLAT_CPLD_LPC_REG_CPLD2_PN1_OFFSET: 6631 case MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET: 6632 case MLXPLAT_CPLD_LPC_REG_CPLD3_PN1_OFFSET: 6633 case MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET: 6634 case MLXPLAT_CPLD_LPC_REG_CPLD4_PN1_OFFSET: 6635 case MLXPLAT_CPLD_LPC_REG_CPLD5_PN_OFFSET: 6636 case MLXPLAT_CPLD_LPC_REG_CPLD5_PN1_OFFSET: 6637 case MLXPLAT_CPLD_LPC_REG_RESET_GP1_OFFSET: 6638 case MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET: 6639 case MLXPLAT_CPLD_LPC_REG_RESET_GP3_OFFSET: 6640 case MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET: 6641 case MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET: 6642 case MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET: 6643 case MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET: 6644 case MLXPLAT_CPLD_LPC_REG_LED1_OFFSET: 6645 case MLXPLAT_CPLD_LPC_REG_LED2_OFFSET: 6646 case MLXPLAT_CPLD_LPC_REG_LED3_OFFSET: 6647 case MLXPLAT_CPLD_LPC_REG_LED4_OFFSET: 6648 case MLXPLAT_CPLD_LPC_REG_LED5_OFFSET: 6649 case MLXPLAT_CPLD_LPC_REG_LED6_OFFSET: 6650 case MLXPLAT_CPLD_LPC_REG_LED7_OFFSET: 6651 case MLXPLAT_CPLD_LPC_REG_LED8_OFFSET: 6652 case MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION: 6653 case MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET: 6654 case MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET: 6655 case MLXPLAT_CPLD_LPC_REG_GP1_RO_OFFSET: 6656 case MLXPLAT_CPLD_LPC_REG_GP0_OFFSET: 6657 case MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET: 6658 case MLXPLAT_CPLD_LPC_REG_GP1_OFFSET: 6659 case MLXPLAT_CPLD_LPC_REG_GP2_OFFSET: 6660 case MLXPLAT_CPLD_LPC_REG_GP3_OFFSET: 6661 case MLXPLAT_CPLD_LPC_REG_FIELD_UPGRADE: 6662 case MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET: 6663 case MLXPLAT_CPLD_LPC_SAFE_BIOS_WP_OFFSET: 6664 case MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET: 6665 case MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET: 6666 case MLXPLAT_CPLD_LPC_REG_FU_CAP_OFFSET: 6667 case MLXPLAT_CPLD_LPC_REG_DBG1_OFFSET: 6668 case MLXPLAT_CPLD_LPC_REG_DBG2_OFFSET: 6669 case MLXPLAT_CPLD_LPC_REG_DBG3_OFFSET: 6670 case MLXPLAT_CPLD_LPC_REG_DBG4_OFFSET: 6671 case MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET: 6672 case MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET: 6673 case MLXPLAT_CPLD_LPC_REG_AGGRCO_OFFSET: 6674 case MLXPLAT_CPLD_LPC_REG_AGGRCO_MASK_OFFSET: 6675 case MLXPLAT_CPLD_LPC_REG_AGGRCX_OFFSET: 6676 case MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET: 6677 case MLXPLAT_CPLD_LPC_REG_GWP_OFFSET: 6678 case MLXPLAT_CPLD_LPC_REG_GWP_EVENT_OFFSET: 6679 case MLXPLAT_CPLD_LPC_REG_GWP_MASK_OFFSET: 6680 case MLXPLAT_CPLD_LPC_REG_GPI_MASK_OFFSET: 6681 case MLXPLAT_CPLD_LPC_REG_BRD_OFFSET: 6682 case MLXPLAT_CPLD_LPC_REG_BRD_EVENT_OFFSET: 6683 case MLXPLAT_CPLD_LPC_REG_BRD_MASK_OFFSET: 6684 case MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET: 6685 case MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET: 6686 case MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET: 6687 case MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET: 6688 case MLXPLAT_CPLD_LPC_REG_ASIC2_EVENT_OFFSET: 6689 case MLXPLAT_CPLD_LPC_REG_ASIC2_MASK_OFFSET: 6690 case MLXPLAT_CPLD_LPC_REG_PSU_OFFSET: 6691 case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET: 6692 case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET: 6693 case MLXPLAT_CPLD_LPC_REG_PSU_AC_OFFSET: 6694 case MLXPLAT_CPLD_LPC_REG_PWR_OFFSET: 6695 case MLXPLAT_CPLD_LPC_REG_PWR_EVENT_OFFSET: 6696 case MLXPLAT_CPLD_LPC_REG_PWR_MASK_OFFSET: 6697 case MLXPLAT_CPLD_LPC_REG_PSU_ALERT_OFFSET: 6698 case MLXPLAT_CPLD_LPC_REG_FAN_OFFSET: 6699 case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET: 6700 case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET: 6701 case MLXPLAT_CPLD_LPC_REG_EROT_OFFSET: 6702 case MLXPLAT_CPLD_LPC_REG_EROT_EVENT_OFFSET: 6703 case MLXPLAT_CPLD_LPC_REG_EROT_MASK_OFFSET: 6704 case MLXPLAT_CPLD_LPC_REG_EROTE_OFFSET: 6705 case MLXPLAT_CPLD_LPC_REG_EROTE_EVENT_OFFSET: 6706 case MLXPLAT_CPLD_LPC_REG_EROTE_MASK_OFFSET: 6707 case MLXPLAT_CPLD_LPC_REG_PWRB_OFFSET: 6708 case MLXPLAT_CPLD_LPC_REG_PWRB_EVENT_OFFSET: 6709 case MLXPLAT_CPLD_LPC_REG_PWRB_MASK_OFFSET: 6710 case MLXPLAT_CPLD_LPC_REG_AGGRLC_OFFSET: 6711 case MLXPLAT_CPLD_LPC_REG_AGGRLC_MASK_OFFSET: 6712 case MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET: 6713 case MLXPLAT_CPLD_LPC_REG_LC_IN_EVENT_OFFSET: 6714 case MLXPLAT_CPLD_LPC_REG_LC_IN_MASK_OFFSET: 6715 case MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET: 6716 case MLXPLAT_CPLD_LPC_REG_LC_VR_EVENT_OFFSET: 6717 case MLXPLAT_CPLD_LPC_REG_LC_VR_MASK_OFFSET: 6718 case MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET: 6719 case MLXPLAT_CPLD_LPC_REG_LC_PG_EVENT_OFFSET: 6720 case MLXPLAT_CPLD_LPC_REG_LC_PG_MASK_OFFSET: 6721 case MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET: 6722 case MLXPLAT_CPLD_LPC_REG_LC_RD_EVENT_OFFSET: 6723 case MLXPLAT_CPLD_LPC_REG_LC_RD_MASK_OFFSET: 6724 case MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET: 6725 case MLXPLAT_CPLD_LPC_REG_LC_OK_EVENT_OFFSET: 6726 case MLXPLAT_CPLD_LPC_REG_LC_OK_MASK_OFFSET: 6727 case MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET: 6728 case MLXPLAT_CPLD_LPC_REG_LC_SN_EVENT_OFFSET: 6729 case MLXPLAT_CPLD_LPC_REG_LC_SN_MASK_OFFSET: 6730 case MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET: 6731 case MLXPLAT_CPLD_LPC_REG_LC_SD_EVENT_OFFSET: 6732 case MLXPLAT_CPLD_LPC_REG_LC_SD_MASK_OFFSET: 6733 case MLXPLAT_CPLD_LPC_REG_LC_PWR_ON: 6734 case MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET: 6735 case MLXPLAT_CPLD_LPC_REG_SPI_CHNL_SELECT: 6736 case MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET: 6737 case MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET: 6738 case MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET: 6739 case MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET: 6740 case MLXPLAT_CPLD_LPC_REG_CPLD6_MVER_OFFSET: 6741 case MLXPLAT_CPLD_LPC_REG_I2C_CH1_OFFSET: 6742 case MLXPLAT_CPLD_LPC_REG_I2C_CH2_OFFSET: 6743 case MLXPLAT_CPLD_LPC_REG_I2C_CH3_OFFSET: 6744 case MLXPLAT_CPLD_LPC_REG_I2C_CH4_OFFSET: 6745 case MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET: 6746 case MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET: 6747 case MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET: 6748 case MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET: 6749 case MLXPLAT_CPLD_LPC_REG_CPLD5_MVER_OFFSET: 6750 case MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET: 6751 case MLXPLAT_CPLD_LPC_REG_PWM2_OFFSET: 6752 case MLXPLAT_CPLD_LPC_REG_PWM3_OFFSET: 6753 case MLXPLAT_CPLD_LPC_REG_PWM4_OFFSET: 6754 case MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET: 6755 case MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET: 6756 case MLXPLAT_CPLD_LPC_REG_TACHO3_OFFSET: 6757 case MLXPLAT_CPLD_LPC_REG_TACHO4_OFFSET: 6758 case MLXPLAT_CPLD_LPC_REG_TACHO5_OFFSET: 6759 case MLXPLAT_CPLD_LPC_REG_TACHO6_OFFSET: 6760 case MLXPLAT_CPLD_LPC_REG_TACHO7_OFFSET: 6761 case MLXPLAT_CPLD_LPC_REG_TACHO8_OFFSET: 6762 case MLXPLAT_CPLD_LPC_REG_TACHO9_OFFSET: 6763 case MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET: 6764 case MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET: 6765 case MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET: 6766 case MLXPLAT_CPLD_LPC_REG_TACHO13_OFFSET: 6767 case MLXPLAT_CPLD_LPC_REG_TACHO14_OFFSET: 6768 case MLXPLAT_CPLD_LPC_REG_TACHO15_OFFSET: 6769 case MLXPLAT_CPLD_LPC_REG_TACHO16_OFFSET: 6770 case MLXPLAT_CPLD_LPC_REG_TACHO17_OFFSET: 6771 case MLXPLAT_CPLD_LPC_REG_TACHO18_OFFSET: 6772 case MLXPLAT_CPLD_LPC_REG_TACHO19_OFFSET: 6773 case MLXPLAT_CPLD_LPC_REG_TACHO20_OFFSET: 6774 case MLXPLAT_CPLD_LPC_REG_ASIC_CAP_OFFSET: 6775 case MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET: 6776 case MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET: 6777 case MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET: 6778 case MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET: 6779 case MLXPLAT_CPLD_LPC_REG_TACHO_SPEED_OFFSET: 6780 case MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET: 6781 case MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET: 6782 case MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET: 6783 case MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET: 6784 case MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET: 6785 case MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET: 6786 return true; 6787 } 6788 return false; 6789 } 6790 6791 static const struct reg_default mlxplat_mlxcpld_regmap_default[] = { 6792 { MLXPLAT_CPLD_LPC_REG_WP1_OFFSET, 0x00 }, 6793 { MLXPLAT_CPLD_LPC_REG_WP2_OFFSET, 0x00 }, 6794 { MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 0x00 }, 6795 { MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET, 0x00 }, 6796 }; 6797 6798 static const struct reg_default mlxplat_mlxcpld_regmap_ng[] = { 6799 { MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 0x00 }, 6800 { MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET, 0x00 }, 6801 }; 6802 6803 static const struct reg_default mlxplat_mlxcpld_regmap_comex_default[] = { 6804 { MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET, 6805 MLXPLAT_CPLD_LOW_AGGRCX_MASK }, 6806 { MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 0x00 }, 6807 }; 6808 6809 static const struct reg_default mlxplat_mlxcpld_regmap_ng400[] = { 6810 { MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 0x00 }, 6811 { MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET, 0x00 }, 6812 { MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET, 0x00 }, 6813 { MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET, 0x00 }, 6814 }; 6815 6816 static const struct reg_default mlxplat_mlxcpld_regmap_rack_switch[] = { 6817 { MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, MLXPLAT_REGMAP_NVSWITCH_PWM_DEFAULT }, 6818 { MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET, 0x00 }, 6819 { MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET, 0x00 }, 6820 { MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET, 0x00 }, 6821 }; 6822 6823 static const struct reg_default mlxplat_mlxcpld_regmap_eth_modular[] = { 6824 { MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, 0x61 }, 6825 { MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 0x00 }, 6826 { MLXPLAT_CPLD_LPC_REG_PWM2_OFFSET, 0x00 }, 6827 { MLXPLAT_CPLD_LPC_REG_PWM3_OFFSET, 0x00 }, 6828 { MLXPLAT_CPLD_LPC_REG_PWM4_OFFSET, 0x00 }, 6829 { MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET, 0x00 }, 6830 { MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET, 0x00 }, 6831 { MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET, 0x00 }, 6832 { MLXPLAT_CPLD_LPC_REG_AGGRLC_MASK_OFFSET, 6833 MLXPLAT_CPLD_AGGR_MASK_LC_LOW }, 6834 }; 6835 6836 static const struct reg_default mlxplat_mlxcpld_regmap_smart_switch[] = { 6837 { MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 0x00 }, 6838 { MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET, 0x00 }, 6839 { MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET, 0x00 }, 6840 { MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET, 0x00 }, 6841 { MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET, MLXPLAT_CPLD_LPC_SM_SW_MASK }, 6842 }; 6843 6844 struct mlxplat_mlxcpld_regmap_context { 6845 void __iomem *base; 6846 }; 6847 6848 static struct mlxplat_mlxcpld_regmap_context mlxplat_mlxcpld_regmap_ctx; 6849 6850 static int 6851 mlxplat_mlxcpld_reg_read(void *context, unsigned int reg, unsigned int *val) 6852 { 6853 struct mlxplat_mlxcpld_regmap_context *ctx = context; 6854 6855 *val = ioread8(ctx->base + reg); 6856 return 0; 6857 } 6858 6859 static int 6860 mlxplat_mlxcpld_reg_write(void *context, unsigned int reg, unsigned int val) 6861 { 6862 struct mlxplat_mlxcpld_regmap_context *ctx = context; 6863 6864 iowrite8(val, ctx->base + reg); 6865 return 0; 6866 } 6867 6868 static const struct regmap_config mlxplat_mlxcpld_regmap_config = { 6869 .reg_bits = 8, 6870 .val_bits = 8, 6871 .max_register = 255, 6872 .cache_type = REGCACHE_FLAT, 6873 .writeable_reg = mlxplat_mlxcpld_writeable_reg, 6874 .readable_reg = mlxplat_mlxcpld_readable_reg, 6875 .volatile_reg = mlxplat_mlxcpld_volatile_reg, 6876 .reg_defaults = mlxplat_mlxcpld_regmap_default, 6877 .num_reg_defaults = ARRAY_SIZE(mlxplat_mlxcpld_regmap_default), 6878 .reg_read = mlxplat_mlxcpld_reg_read, 6879 .reg_write = mlxplat_mlxcpld_reg_write, 6880 }; 6881 6882 static const struct regmap_config mlxplat_mlxcpld_regmap_config_ng = { 6883 .reg_bits = 8, 6884 .val_bits = 8, 6885 .max_register = 255, 6886 .cache_type = REGCACHE_FLAT, 6887 .writeable_reg = mlxplat_mlxcpld_writeable_reg, 6888 .readable_reg = mlxplat_mlxcpld_readable_reg, 6889 .volatile_reg = mlxplat_mlxcpld_volatile_reg, 6890 .reg_defaults = mlxplat_mlxcpld_regmap_ng, 6891 .num_reg_defaults = ARRAY_SIZE(mlxplat_mlxcpld_regmap_ng), 6892 .reg_read = mlxplat_mlxcpld_reg_read, 6893 .reg_write = mlxplat_mlxcpld_reg_write, 6894 }; 6895 6896 static const struct regmap_config mlxplat_mlxcpld_regmap_config_comex = { 6897 .reg_bits = 8, 6898 .val_bits = 8, 6899 .max_register = 255, 6900 .cache_type = REGCACHE_FLAT, 6901 .writeable_reg = mlxplat_mlxcpld_writeable_reg, 6902 .readable_reg = mlxplat_mlxcpld_readable_reg, 6903 .volatile_reg = mlxplat_mlxcpld_volatile_reg, 6904 .reg_defaults = mlxplat_mlxcpld_regmap_comex_default, 6905 .num_reg_defaults = ARRAY_SIZE(mlxplat_mlxcpld_regmap_comex_default), 6906 .reg_read = mlxplat_mlxcpld_reg_read, 6907 .reg_write = mlxplat_mlxcpld_reg_write, 6908 }; 6909 6910 static const struct regmap_config mlxplat_mlxcpld_regmap_config_ng400 = { 6911 .reg_bits = 8, 6912 .val_bits = 8, 6913 .max_register = 255, 6914 .cache_type = REGCACHE_FLAT, 6915 .writeable_reg = mlxplat_mlxcpld_writeable_reg, 6916 .readable_reg = mlxplat_mlxcpld_readable_reg, 6917 .volatile_reg = mlxplat_mlxcpld_volatile_reg, 6918 .reg_defaults = mlxplat_mlxcpld_regmap_ng400, 6919 .num_reg_defaults = ARRAY_SIZE(mlxplat_mlxcpld_regmap_ng400), 6920 .reg_read = mlxplat_mlxcpld_reg_read, 6921 .reg_write = mlxplat_mlxcpld_reg_write, 6922 }; 6923 6924 static const struct regmap_config mlxplat_mlxcpld_regmap_config_rack_switch = { 6925 .reg_bits = 8, 6926 .val_bits = 8, 6927 .max_register = 255, 6928 .cache_type = REGCACHE_FLAT, 6929 .writeable_reg = mlxplat_mlxcpld_writeable_reg, 6930 .readable_reg = mlxplat_mlxcpld_readable_reg, 6931 .volatile_reg = mlxplat_mlxcpld_volatile_reg, 6932 .reg_defaults = mlxplat_mlxcpld_regmap_rack_switch, 6933 .num_reg_defaults = ARRAY_SIZE(mlxplat_mlxcpld_regmap_rack_switch), 6934 .reg_read = mlxplat_mlxcpld_reg_read, 6935 .reg_write = mlxplat_mlxcpld_reg_write, 6936 }; 6937 6938 static const struct regmap_config mlxplat_mlxcpld_regmap_config_eth_modular = { 6939 .reg_bits = 8, 6940 .val_bits = 8, 6941 .max_register = 255, 6942 .cache_type = REGCACHE_FLAT, 6943 .writeable_reg = mlxplat_mlxcpld_writeable_reg, 6944 .readable_reg = mlxplat_mlxcpld_readable_reg, 6945 .volatile_reg = mlxplat_mlxcpld_volatile_reg, 6946 .reg_defaults = mlxplat_mlxcpld_regmap_eth_modular, 6947 .num_reg_defaults = ARRAY_SIZE(mlxplat_mlxcpld_regmap_eth_modular), 6948 .reg_read = mlxplat_mlxcpld_reg_read, 6949 .reg_write = mlxplat_mlxcpld_reg_write, 6950 }; 6951 6952 static const struct regmap_config mlxplat_mlxcpld_regmap_config_smart_switch = { 6953 .reg_bits = 8, 6954 .val_bits = 8, 6955 .max_register = 255, 6956 .cache_type = REGCACHE_FLAT, 6957 .writeable_reg = mlxplat_mlxcpld_writeable_reg, 6958 .readable_reg = mlxplat_mlxcpld_readable_reg, 6959 .volatile_reg = mlxplat_mlxcpld_volatile_reg, 6960 .reg_defaults = mlxplat_mlxcpld_regmap_smart_switch, 6961 .num_reg_defaults = ARRAY_SIZE(mlxplat_mlxcpld_regmap_smart_switch), 6962 .reg_read = mlxplat_mlxcpld_reg_read, 6963 .reg_write = mlxplat_mlxcpld_reg_write, 6964 }; 6965 6966 static struct resource mlxplat_mlxcpld_resources[] = { 6967 [0] = DEFINE_RES_IRQ_NAMED(MLXPLAT_CPLD_LPC_SYSIRQ, "mlxreg-hotplug"), 6968 }; 6969 6970 static struct mlxreg_core_hotplug_platform_data *mlxplat_i2c; 6971 static struct mlxreg_core_hotplug_platform_data *mlxplat_hotplug; 6972 static struct mlxreg_core_platform_data *mlxplat_led; 6973 static struct mlxreg_core_platform_data *mlxplat_regs_io; 6974 static struct mlxreg_core_platform_data *mlxplat_fan; 6975 static struct mlxreg_core_platform_data 6976 *mlxplat_wd_data[MLXPLAT_CPLD_WD_MAX_DEVS]; 6977 static struct mlxreg_core_data *mlxplat_dpu_data[MLXPLAT_CPLD_DPU_MAX_DEVS]; 6978 static const struct regmap_config *mlxplat_regmap_config; 6979 static struct pci_dev *lpc_bridge; 6980 static struct pci_dev *i2c_bridge; 6981 static struct pci_dev *jtag_bridge; 6982 6983 /* Platform default reset function */ 6984 static int mlxplat_reboot_notifier(struct notifier_block *nb, unsigned long action, void *unused) 6985 { 6986 struct mlxplat_priv *priv = platform_get_drvdata(mlxplat_dev); 6987 u32 regval; 6988 int ret; 6989 6990 ret = regmap_read(priv->regmap, MLXPLAT_CPLD_LPC_REG_RESET_GP1_OFFSET, ®val); 6991 6992 if (action == SYS_RESTART && !ret && regval & MLXPLAT_CPLD_SYS_RESET_MASK) 6993 regmap_write(priv->regmap, MLXPLAT_CPLD_LPC_REG_RESET_GP1_OFFSET, 6994 MLXPLAT_CPLD_RESET_MASK); 6995 6996 return NOTIFY_DONE; 6997 } 6998 6999 static struct notifier_block mlxplat_reboot_default_nb = { 7000 .notifier_call = mlxplat_reboot_notifier, 7001 }; 7002 7003 /* Platform default poweroff function */ 7004 static void mlxplat_poweroff(void) 7005 { 7006 struct mlxplat_priv *priv = platform_get_drvdata(mlxplat_dev); 7007 7008 if (mlxplat_reboot_nb) 7009 unregister_reboot_notifier(mlxplat_reboot_nb); 7010 regmap_write(priv->regmap, MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, MLXPLAT_CPLD_HALT_MASK); 7011 kernel_halt(); 7012 } 7013 7014 static int __init mlxplat_register_platform_device(void) 7015 { 7016 mlxplat_dev = platform_device_register_simple(MLX_PLAT_DEVICE_NAME, -1, 7017 mlxplat_lpc_resources, 7018 ARRAY_SIZE(mlxplat_lpc_resources)); 7019 if (IS_ERR(mlxplat_dev)) 7020 return PTR_ERR(mlxplat_dev); 7021 else 7022 return 1; 7023 } 7024 7025 static int __init mlxplat_dmi_default_matched(const struct dmi_system_id *dmi) 7026 { 7027 int i; 7028 7029 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 7030 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data); 7031 mlxplat_mux_data = mlxplat_default_mux_data; 7032 for (i = 0; i < mlxplat_mux_num; i++) { 7033 mlxplat_mux_data[i].values = mlxplat_default_channels[i]; 7034 mlxplat_mux_data[i].n_values = 7035 ARRAY_SIZE(mlxplat_default_channels[i]); 7036 } 7037 mlxplat_hotplug = &mlxplat_mlxcpld_default_data; 7038 mlxplat_hotplug->deferred_nr = 7039 mlxplat_default_channels[i - 1][MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 7040 mlxplat_led = &mlxplat_default_led_data; 7041 mlxplat_regs_io = &mlxplat_default_regs_io_data; 7042 mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0]; 7043 mlxplat_i2c = &mlxplat_mlxcpld_i2c_default_data; 7044 7045 return mlxplat_register_platform_device(); 7046 } 7047 7048 static int __init mlxplat_dmi_default_wc_matched(const struct dmi_system_id *dmi) 7049 { 7050 int i; 7051 7052 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 7053 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data); 7054 mlxplat_mux_data = mlxplat_default_mux_data; 7055 for (i = 0; i < mlxplat_mux_num; i++) { 7056 mlxplat_mux_data[i].values = mlxplat_default_channels[i]; 7057 mlxplat_mux_data[i].n_values = 7058 ARRAY_SIZE(mlxplat_default_channels[i]); 7059 } 7060 mlxplat_hotplug = &mlxplat_mlxcpld_default_wc_data; 7061 mlxplat_hotplug->deferred_nr = 7062 mlxplat_default_channels[i - 1][MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 7063 mlxplat_led = &mlxplat_default_led_wc_data; 7064 mlxplat_regs_io = &mlxplat_default_regs_io_data; 7065 mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0]; 7066 mlxplat_i2c = &mlxplat_mlxcpld_i2c_default_data; 7067 7068 return mlxplat_register_platform_device(); 7069 } 7070 7071 static int __init mlxplat_dmi_default_eth_wc_blade_matched(const struct dmi_system_id *dmi) 7072 { 7073 int i; 7074 7075 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 7076 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data); 7077 mlxplat_mux_data = mlxplat_default_mux_data; 7078 for (i = 0; i < mlxplat_mux_num; i++) { 7079 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels; 7080 mlxplat_mux_data[i].n_values = 7081 ARRAY_SIZE(mlxplat_msn21xx_channels); 7082 } 7083 mlxplat_hotplug = &mlxplat_mlxcpld_default_wc_data; 7084 mlxplat_hotplug->deferred_nr = 7085 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 7086 mlxplat_led = &mlxplat_default_led_eth_wc_blade_data; 7087 mlxplat_regs_io = &mlxplat_default_ng_regs_io_data; 7088 for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++) 7089 mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i]; 7090 mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data; 7091 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_ng; 7092 7093 return mlxplat_register_platform_device(); 7094 } 7095 7096 static int __init mlxplat_dmi_msn21xx_matched(const struct dmi_system_id *dmi) 7097 { 7098 int i; 7099 7100 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 7101 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data); 7102 mlxplat_mux_data = mlxplat_default_mux_data; 7103 for (i = 0; i < mlxplat_mux_num; i++) { 7104 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels; 7105 mlxplat_mux_data[i].n_values = 7106 ARRAY_SIZE(mlxplat_msn21xx_channels); 7107 } 7108 mlxplat_hotplug = &mlxplat_mlxcpld_msn21xx_data; 7109 mlxplat_hotplug->deferred_nr = 7110 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 7111 mlxplat_led = &mlxplat_msn21xx_led_data; 7112 mlxplat_regs_io = &mlxplat_msn21xx_regs_io_data; 7113 mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0]; 7114 mlxplat_i2c = &mlxplat_mlxcpld_i2c_default_data; 7115 7116 return mlxplat_register_platform_device(); 7117 } 7118 7119 static int __init mlxplat_dmi_msn274x_matched(const struct dmi_system_id *dmi) 7120 { 7121 int i; 7122 7123 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 7124 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data); 7125 mlxplat_mux_data = mlxplat_default_mux_data; 7126 for (i = 0; i < mlxplat_mux_num; i++) { 7127 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels; 7128 mlxplat_mux_data[i].n_values = 7129 ARRAY_SIZE(mlxplat_msn21xx_channels); 7130 } 7131 mlxplat_hotplug = &mlxplat_mlxcpld_msn274x_data; 7132 mlxplat_hotplug->deferred_nr = 7133 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 7134 mlxplat_led = &mlxplat_default_led_data; 7135 mlxplat_regs_io = &mlxplat_msn21xx_regs_io_data; 7136 mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0]; 7137 mlxplat_i2c = &mlxplat_mlxcpld_i2c_default_data; 7138 7139 return mlxplat_register_platform_device(); 7140 } 7141 7142 static int __init mlxplat_dmi_msn201x_matched(const struct dmi_system_id *dmi) 7143 { 7144 int i; 7145 7146 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 7147 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data); 7148 mlxplat_mux_data = mlxplat_default_mux_data; 7149 for (i = 0; i < mlxplat_mux_num; i++) { 7150 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels; 7151 mlxplat_mux_data[i].n_values = 7152 ARRAY_SIZE(mlxplat_msn21xx_channels); 7153 } 7154 mlxplat_hotplug = &mlxplat_mlxcpld_msn201x_data; 7155 mlxplat_hotplug->deferred_nr = 7156 mlxplat_default_channels[i - 1][MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 7157 mlxplat_led = &mlxplat_msn21xx_led_data; 7158 mlxplat_regs_io = &mlxplat_msn21xx_regs_io_data; 7159 mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0]; 7160 mlxplat_i2c = &mlxplat_mlxcpld_i2c_default_data; 7161 7162 return mlxplat_register_platform_device(); 7163 } 7164 7165 static int __init mlxplat_dmi_qmb7xx_matched(const struct dmi_system_id *dmi) 7166 { 7167 int i; 7168 7169 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 7170 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data); 7171 mlxplat_mux_data = mlxplat_default_mux_data; 7172 for (i = 0; i < mlxplat_mux_num; i++) { 7173 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels; 7174 mlxplat_mux_data[i].n_values = 7175 ARRAY_SIZE(mlxplat_msn21xx_channels); 7176 } 7177 mlxplat_hotplug = &mlxplat_mlxcpld_default_ng_data; 7178 mlxplat_hotplug->deferred_nr = 7179 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 7180 mlxplat_led = &mlxplat_default_ng_led_data; 7181 mlxplat_regs_io = &mlxplat_default_ng_regs_io_data; 7182 mlxplat_fan = &mlxplat_default_fan_data; 7183 for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++) 7184 mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i]; 7185 mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data; 7186 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_ng; 7187 7188 return mlxplat_register_platform_device(); 7189 } 7190 7191 static int __init mlxplat_dmi_comex_matched(const struct dmi_system_id *dmi) 7192 { 7193 int i; 7194 7195 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_EXT_ADAPTER_NUM; 7196 mlxplat_mux_num = ARRAY_SIZE(mlxplat_extended_mux_data); 7197 mlxplat_mux_data = mlxplat_extended_mux_data; 7198 for (i = 0; i < mlxplat_mux_num; i++) { 7199 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels; 7200 mlxplat_mux_data[i].n_values = 7201 ARRAY_SIZE(mlxplat_msn21xx_channels); 7202 } 7203 mlxplat_hotplug = &mlxplat_mlxcpld_comex_data; 7204 mlxplat_hotplug->deferred_nr = MLXPLAT_CPLD_MAX_PHYS_EXT_ADAPTER_NUM; 7205 mlxplat_led = &mlxplat_comex_100G_led_data; 7206 mlxplat_regs_io = &mlxplat_default_ng_regs_io_data; 7207 mlxplat_fan = &mlxplat_default_fan_data; 7208 for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++) 7209 mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i]; 7210 mlxplat_i2c = &mlxplat_mlxcpld_i2c_default_data; 7211 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_comex; 7212 7213 return mlxplat_register_platform_device(); 7214 } 7215 7216 static int __init mlxplat_dmi_ng400_matched(const struct dmi_system_id *dmi) 7217 { 7218 int i; 7219 7220 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 7221 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data); 7222 mlxplat_mux_data = mlxplat_default_mux_data; 7223 for (i = 0; i < mlxplat_mux_num; i++) { 7224 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels; 7225 mlxplat_mux_data[i].n_values = 7226 ARRAY_SIZE(mlxplat_msn21xx_channels); 7227 } 7228 mlxplat_hotplug = &mlxplat_mlxcpld_ext_data; 7229 mlxplat_hotplug->deferred_nr = 7230 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 7231 mlxplat_led = &mlxplat_default_ng_led_data; 7232 mlxplat_regs_io = &mlxplat_default_ng_regs_io_data; 7233 mlxplat_fan = &mlxplat_default_fan_data; 7234 for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++) 7235 mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i]; 7236 mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data; 7237 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_ng400; 7238 7239 return mlxplat_register_platform_device(); 7240 } 7241 7242 static int __init mlxplat_dmi_modular_matched(const struct dmi_system_id *dmi) 7243 { 7244 int i; 7245 7246 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 7247 mlxplat_mux_num = ARRAY_SIZE(mlxplat_modular_mux_data); 7248 mlxplat_mux_data = mlxplat_modular_mux_data; 7249 mlxplat_hotplug = &mlxplat_mlxcpld_modular_data; 7250 mlxplat_hotplug->deferred_nr = MLXPLAT_CPLD_CH4_ETH_MODULAR; 7251 mlxplat_led = &mlxplat_modular_led_data; 7252 mlxplat_regs_io = &mlxplat_modular_regs_io_data; 7253 mlxplat_fan = &mlxplat_default_fan_data; 7254 for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++) 7255 mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i]; 7256 mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data; 7257 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_eth_modular; 7258 7259 return mlxplat_register_platform_device(); 7260 } 7261 7262 static int __init mlxplat_dmi_chassis_blade_matched(const struct dmi_system_id *dmi) 7263 { 7264 int i; 7265 7266 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 7267 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data); 7268 mlxplat_mux_data = mlxplat_default_mux_data; 7269 mlxplat_hotplug = &mlxplat_mlxcpld_chassis_blade_data; 7270 mlxplat_hotplug->deferred_nr = 7271 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 7272 for (i = 0; i < mlxplat_mux_num; i++) { 7273 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels; 7274 mlxplat_mux_data[i].n_values = 7275 ARRAY_SIZE(mlxplat_msn21xx_channels); 7276 } 7277 mlxplat_regs_io = &mlxplat_chassis_blade_regs_io_data; 7278 mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data; 7279 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_ng400; 7280 7281 return mlxplat_register_platform_device(); 7282 } 7283 7284 static int __init mlxplat_dmi_rack_switch_matched(const struct dmi_system_id *dmi) 7285 { 7286 int i; 7287 7288 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 7289 mlxplat_mux_num = ARRAY_SIZE(mlxplat_rack_switch_mux_data); 7290 mlxplat_mux_data = mlxplat_rack_switch_mux_data; 7291 mlxplat_hotplug = &mlxplat_mlxcpld_rack_switch_data; 7292 mlxplat_hotplug->deferred_nr = 7293 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 7294 mlxplat_led = &mlxplat_default_ng_led_data; 7295 mlxplat_regs_io = &mlxplat_default_ng_regs_io_data; 7296 mlxplat_fan = &mlxplat_default_fan_data; 7297 for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++) 7298 mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i]; 7299 mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data; 7300 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_rack_switch; 7301 7302 return mlxplat_register_platform_device(); 7303 } 7304 7305 static int __init mlxplat_dmi_ng800_matched(const struct dmi_system_id *dmi) 7306 { 7307 int i; 7308 7309 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 7310 mlxplat_mux_num = ARRAY_SIZE(mlxplat_ng800_mux_data); 7311 mlxplat_mux_data = mlxplat_ng800_mux_data; 7312 mlxplat_hotplug = &mlxplat_mlxcpld_ng800_data; 7313 mlxplat_hotplug->deferred_nr = 7314 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 7315 mlxplat_led = &mlxplat_default_ng_led_data; 7316 mlxplat_regs_io = &mlxplat_default_ng_regs_io_data; 7317 mlxplat_fan = &mlxplat_default_fan_data; 7318 for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++) 7319 mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i]; 7320 mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data; 7321 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_ng400; 7322 7323 return mlxplat_register_platform_device(); 7324 } 7325 7326 static int __init mlxplat_dmi_l1_switch_matched(const struct dmi_system_id *dmi) 7327 { 7328 int i; 7329 7330 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 7331 mlxplat_mux_num = ARRAY_SIZE(mlxplat_rack_switch_mux_data); 7332 mlxplat_mux_data = mlxplat_rack_switch_mux_data; 7333 mlxplat_hotplug = &mlxplat_mlxcpld_l1_switch_data; 7334 mlxplat_hotplug->deferred_nr = 7335 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 7336 mlxplat_led = &mlxplat_l1_switch_led_data; 7337 mlxplat_regs_io = &mlxplat_default_ng_regs_io_data; 7338 mlxplat_fan = &mlxplat_default_fan_data; 7339 for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++) 7340 mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i]; 7341 mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data; 7342 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_rack_switch; 7343 pm_power_off = mlxplat_poweroff; 7344 mlxplat_reboot_nb = &mlxplat_reboot_default_nb; 7345 7346 return mlxplat_register_platform_device(); 7347 } 7348 7349 static int __init mlxplat_dmi_smart_switch_matched(const struct dmi_system_id *dmi) 7350 { 7351 int i; 7352 7353 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 7354 mlxplat_mux_num = ARRAY_SIZE(mlxplat_ng800_mux_data); 7355 mlxplat_mux_data = mlxplat_ng800_mux_data; 7356 mlxplat_hotplug = &mlxplat_mlxcpld_smart_switch_data; 7357 mlxplat_hotplug->deferred_nr = 7358 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 7359 mlxplat_led = &mlxplat_xdr_led_data; 7360 mlxplat_regs_io = &mlxplat_smart_switch_regs_io_data; 7361 mlxplat_fan = &mlxplat_xdr_fan_data; 7362 7363 for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++) 7364 mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i]; 7365 for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_smart_switch_dpu_data); i++) 7366 mlxplat_dpu_data[i] = &mlxplat_mlxcpld_smart_switch_dpu_data[i]; 7367 7368 mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data; 7369 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_smart_switch; 7370 7371 return mlxplat_register_platform_device(); 7372 } 7373 7374 static int __init mlxplat_dmi_ng400_hi171_matched(const struct dmi_system_id *dmi) 7375 { 7376 unsigned int i; 7377 7378 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 7379 mlxplat_mux_num = ARRAY_SIZE(mlxplat_ng800_mux_data); 7380 mlxplat_mux_data = mlxplat_ng800_mux_data; 7381 mlxplat_hotplug = &mlxplat_mlxcpld_ng800_hi171_data; 7382 mlxplat_hotplug->deferred_nr = 7383 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 7384 mlxplat_led = &mlxplat_default_ng_led_data; 7385 mlxplat_regs_io = &mlxplat_default_ng_regs_io_data; 7386 mlxplat_fan = &mlxplat_xdr_fan_data; 7387 7388 for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type3); i++) 7389 mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type3[i]; 7390 7391 mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data; 7392 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_ng400; 7393 7394 return mlxplat_register_platform_device(); 7395 } 7396 7397 static const struct dmi_system_id mlxplat_dmi_table[] __initconst = { 7398 { 7399 .callback = mlxplat_dmi_default_wc_matched, 7400 .matches = { 7401 DMI_MATCH(DMI_BOARD_NAME, "VMOD0001"), 7402 DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "HI138"), 7403 }, 7404 }, 7405 { 7406 .callback = mlxplat_dmi_default_matched, 7407 .matches = { 7408 DMI_MATCH(DMI_BOARD_NAME, "VMOD0001"), 7409 }, 7410 }, 7411 { 7412 .callback = mlxplat_dmi_msn21xx_matched, 7413 .matches = { 7414 DMI_MATCH(DMI_BOARD_NAME, "VMOD0002"), 7415 }, 7416 }, 7417 { 7418 .callback = mlxplat_dmi_msn274x_matched, 7419 .matches = { 7420 DMI_MATCH(DMI_BOARD_NAME, "VMOD0003"), 7421 }, 7422 }, 7423 { 7424 .callback = mlxplat_dmi_msn201x_matched, 7425 .matches = { 7426 DMI_MATCH(DMI_BOARD_NAME, "VMOD0004"), 7427 }, 7428 }, 7429 { 7430 .callback = mlxplat_dmi_default_eth_wc_blade_matched, 7431 .matches = { 7432 DMI_MATCH(DMI_BOARD_NAME, "VMOD0005"), 7433 DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "HI139"), 7434 }, 7435 }, 7436 { 7437 .callback = mlxplat_dmi_qmb7xx_matched, 7438 .matches = { 7439 DMI_MATCH(DMI_BOARD_NAME, "VMOD0005"), 7440 }, 7441 }, 7442 { 7443 .callback = mlxplat_dmi_qmb7xx_matched, 7444 .matches = { 7445 DMI_MATCH(DMI_BOARD_NAME, "VMOD0007"), 7446 }, 7447 }, 7448 { 7449 .callback = mlxplat_dmi_comex_matched, 7450 .matches = { 7451 DMI_MATCH(DMI_BOARD_NAME, "VMOD0009"), 7452 }, 7453 }, 7454 { 7455 .callback = mlxplat_dmi_rack_switch_matched, 7456 .matches = { 7457 DMI_MATCH(DMI_BOARD_NAME, "VMOD0010"), 7458 DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "HI142"), 7459 }, 7460 }, 7461 { 7462 .callback = mlxplat_dmi_ng400_matched, 7463 .matches = { 7464 DMI_MATCH(DMI_BOARD_NAME, "VMOD0010"), 7465 }, 7466 }, 7467 { 7468 .callback = mlxplat_dmi_modular_matched, 7469 .matches = { 7470 DMI_MATCH(DMI_BOARD_NAME, "VMOD0011"), 7471 }, 7472 }, 7473 { 7474 .callback = mlxplat_dmi_ng800_matched, 7475 .matches = { 7476 DMI_MATCH(DMI_BOARD_NAME, "VMOD0013"), 7477 }, 7478 }, 7479 { 7480 .callback = mlxplat_dmi_chassis_blade_matched, 7481 .matches = { 7482 DMI_MATCH(DMI_BOARD_NAME, "VMOD0015"), 7483 }, 7484 }, 7485 { 7486 .callback = mlxplat_dmi_l1_switch_matched, 7487 .matches = { 7488 DMI_MATCH(DMI_BOARD_NAME, "VMOD0017"), 7489 }, 7490 }, 7491 { 7492 .callback = mlxplat_dmi_smart_switch_matched, 7493 .matches = { 7494 DMI_MATCH(DMI_BOARD_NAME, "VMOD0019"), 7495 }, 7496 }, 7497 { 7498 .callback = mlxplat_dmi_ng400_hi171_matched, 7499 .matches = { 7500 DMI_MATCH(DMI_BOARD_NAME, "VMOD0022"), 7501 DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "HI171"), 7502 }, 7503 }, 7504 { 7505 .callback = mlxplat_dmi_ng400_hi171_matched, 7506 .matches = { 7507 DMI_MATCH(DMI_BOARD_NAME, "VMOD0022"), 7508 DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "HI172"), 7509 }, 7510 }, 7511 { 7512 .callback = mlxplat_dmi_msn274x_matched, 7513 .matches = { 7514 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 7515 DMI_MATCH(DMI_PRODUCT_NAME, "MSN274"), 7516 }, 7517 }, 7518 { 7519 .callback = mlxplat_dmi_default_matched, 7520 .matches = { 7521 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 7522 DMI_MATCH(DMI_PRODUCT_NAME, "MSN24"), 7523 }, 7524 }, 7525 { 7526 .callback = mlxplat_dmi_default_matched, 7527 .matches = { 7528 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 7529 DMI_MATCH(DMI_PRODUCT_NAME, "MSN27"), 7530 }, 7531 }, 7532 { 7533 .callback = mlxplat_dmi_default_matched, 7534 .matches = { 7535 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 7536 DMI_MATCH(DMI_PRODUCT_NAME, "MSB"), 7537 }, 7538 }, 7539 { 7540 .callback = mlxplat_dmi_default_matched, 7541 .matches = { 7542 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 7543 DMI_MATCH(DMI_PRODUCT_NAME, "MSX"), 7544 }, 7545 }, 7546 { 7547 .callback = mlxplat_dmi_msn21xx_matched, 7548 .matches = { 7549 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 7550 DMI_MATCH(DMI_PRODUCT_NAME, "MSN21"), 7551 }, 7552 }, 7553 { 7554 .callback = mlxplat_dmi_msn201x_matched, 7555 .matches = { 7556 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 7557 DMI_MATCH(DMI_PRODUCT_NAME, "MSN201"), 7558 }, 7559 }, 7560 { 7561 .callback = mlxplat_dmi_qmb7xx_matched, 7562 .matches = { 7563 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 7564 DMI_MATCH(DMI_PRODUCT_NAME, "MQM87"), 7565 }, 7566 }, 7567 { 7568 .callback = mlxplat_dmi_qmb7xx_matched, 7569 .matches = { 7570 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 7571 DMI_MATCH(DMI_PRODUCT_NAME, "MSN37"), 7572 }, 7573 }, 7574 { 7575 .callback = mlxplat_dmi_qmb7xx_matched, 7576 .matches = { 7577 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 7578 DMI_MATCH(DMI_PRODUCT_NAME, "MSN34"), 7579 }, 7580 }, 7581 { 7582 .callback = mlxplat_dmi_qmb7xx_matched, 7583 .matches = { 7584 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 7585 DMI_MATCH(DMI_PRODUCT_NAME, "MSN38"), 7586 }, 7587 }, 7588 { } 7589 }; 7590 7591 MODULE_DEVICE_TABLE(dmi, mlxplat_dmi_table); 7592 7593 static int mlxplat_mlxcpld_verify_bus_topology(int *nr) 7594 { 7595 struct i2c_adapter *search_adap; 7596 int i, shift = 0; 7597 7598 /* Scan adapters from expected id to verify it is free. */ 7599 *nr = MLXPLAT_CPLD_PHYS_ADAPTER_DEF_NR; 7600 for (i = MLXPLAT_CPLD_PHYS_ADAPTER_DEF_NR; i < 7601 mlxplat_max_adap_num; i++) { 7602 search_adap = i2c_get_adapter(i); 7603 if (search_adap) { 7604 i2c_put_adapter(search_adap); 7605 continue; 7606 } 7607 7608 /* Return if expected parent adapter is free. */ 7609 if (i == MLXPLAT_CPLD_PHYS_ADAPTER_DEF_NR) 7610 return 0; 7611 break; 7612 } 7613 7614 /* Return with error if free id for adapter is not found. */ 7615 if (i == mlxplat_max_adap_num) 7616 return -ENODEV; 7617 7618 /* Shift adapter ids, since expected parent adapter is not free. */ 7619 *nr = i; 7620 for (i = 0; i < mlxplat_mux_num; i++) { 7621 shift = *nr - mlxplat_mux_data[i].parent; 7622 mlxplat_mux_data[i].parent = *nr; 7623 mlxplat_mux_data[i].base_nr += shift; 7624 } 7625 7626 if (shift > 0) 7627 mlxplat_hotplug->shift_nr = shift; 7628 7629 return 0; 7630 } 7631 7632 static int mlxplat_mlxcpld_check_wd_capability(void *regmap) 7633 { 7634 u32 regval; 7635 int i, rc; 7636 7637 rc = regmap_read(regmap, MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 7638 ®val); 7639 if (rc) 7640 return rc; 7641 7642 if (!(regval & ~MLXPLAT_CPLD_WD_CPBLTY_MASK)) { 7643 for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type3); i++) { 7644 if (mlxplat_wd_data[i]) 7645 mlxplat_wd_data[i] = 7646 &mlxplat_mlxcpld_wd_set_type3[i]; 7647 } 7648 } 7649 7650 return 0; 7651 } 7652 7653 static int mlxplat_lpc_cpld_device_init(struct resource **hotplug_resources, 7654 unsigned int *hotplug_resources_size) 7655 { 7656 int err; 7657 7658 mlxplat_mlxcpld_regmap_ctx.base = devm_ioport_map(&mlxplat_dev->dev, 7659 mlxplat_lpc_resources[1].start, 1); 7660 if (!mlxplat_mlxcpld_regmap_ctx.base) { 7661 err = -ENOMEM; 7662 goto fail_devm_ioport_map; 7663 } 7664 7665 *hotplug_resources = mlxplat_mlxcpld_resources; 7666 *hotplug_resources_size = ARRAY_SIZE(mlxplat_mlxcpld_resources); 7667 7668 return 0; 7669 7670 fail_devm_ioport_map: 7671 return err; 7672 } 7673 7674 static void mlxplat_lpc_cpld_device_exit(void) 7675 { 7676 } 7677 7678 static int 7679 mlxplat_pci_fpga_device_init(unsigned int device, const char *res_name, struct pci_dev **pci_bridge, 7680 void __iomem **pci_bridge_addr) 7681 { 7682 void __iomem *pci_mem_addr; 7683 struct pci_dev *pci_dev; 7684 int err; 7685 7686 pci_dev = pci_get_device(PCI_VENDOR_ID_LATTICE, device, NULL); 7687 if (!pci_dev) 7688 return -ENODEV; 7689 7690 err = pci_enable_device(pci_dev); 7691 if (err) { 7692 dev_err(&pci_dev->dev, "pci_enable_device failed with error %d\n", err); 7693 goto fail_pci_enable_device; 7694 } 7695 7696 err = pci_request_region(pci_dev, 0, res_name); 7697 if (err) { 7698 dev_err(&pci_dev->dev, "pci_request_regions failed with error %d\n", err); 7699 goto fail_pci_request_regions; 7700 } 7701 7702 err = dma_set_mask_and_coherent(&pci_dev->dev, DMA_BIT_MASK(64)); 7703 if (err) { 7704 err = dma_set_mask(&pci_dev->dev, DMA_BIT_MASK(32)); 7705 if (err) { 7706 dev_err(&pci_dev->dev, "dma_set_mask failed with error %d\n", err); 7707 goto fail_pci_set_dma_mask; 7708 } 7709 } 7710 7711 pci_set_master(pci_dev); 7712 7713 pci_mem_addr = devm_ioremap(&pci_dev->dev, pci_resource_start(pci_dev, 0), 7714 pci_resource_len(pci_dev, 0)); 7715 if (!pci_mem_addr) { 7716 dev_err(&mlxplat_dev->dev, "ioremap failed\n"); 7717 err = -EIO; 7718 goto fail_ioremap; 7719 } 7720 7721 *pci_bridge = pci_dev; 7722 *pci_bridge_addr = pci_mem_addr; 7723 7724 return 0; 7725 7726 fail_ioremap: 7727 fail_pci_set_dma_mask: 7728 pci_release_regions(pci_dev); 7729 fail_pci_request_regions: 7730 pci_disable_device(pci_dev); 7731 fail_pci_enable_device: 7732 pci_dev_put(pci_dev); 7733 return err; 7734 } 7735 7736 static void 7737 mlxplat_pci_fpga_device_exit(struct pci_dev *pci_bridge, 7738 void __iomem *pci_bridge_addr) 7739 { 7740 iounmap(pci_bridge_addr); 7741 pci_release_regions(pci_bridge); 7742 pci_disable_device(pci_bridge); 7743 pci_dev_put(pci_bridge); 7744 } 7745 7746 static int 7747 mlxplat_pci_fpga_devices_init(struct resource **hotplug_resources, 7748 unsigned int *hotplug_resources_size) 7749 { 7750 int err; 7751 7752 err = mlxplat_pci_fpga_device_init(PCI_DEVICE_ID_LATTICE_LPC_BRIDGE, 7753 "mlxplat_lpc_bridge", &lpc_bridge, 7754 &mlxplat_mlxcpld_regmap_ctx.base); 7755 if (err) 7756 goto mlxplat_pci_fpga_device_init_lpc_fail; 7757 7758 err = mlxplat_pci_fpga_device_init(PCI_DEVICE_ID_LATTICE_I2C_BRIDGE, 7759 "mlxplat_i2c_bridge", &i2c_bridge, 7760 &i2c_bridge_addr); 7761 if (err) 7762 goto mlxplat_pci_fpga_device_init_i2c_fail; 7763 7764 err = mlxplat_pci_fpga_device_init(PCI_DEVICE_ID_LATTICE_JTAG_BRIDGE, 7765 "mlxplat_jtag_bridge", &jtag_bridge, 7766 &jtag_bridge_addr); 7767 if (err) 7768 goto mlxplat_pci_fpga_device_init_jtag_fail; 7769 7770 return 0; 7771 7772 mlxplat_pci_fpga_device_init_jtag_fail: 7773 mlxplat_pci_fpga_device_exit(i2c_bridge, i2c_bridge_addr); 7774 mlxplat_pci_fpga_device_init_i2c_fail: 7775 mlxplat_pci_fpga_device_exit(lpc_bridge, mlxplat_mlxcpld_regmap_ctx.base); 7776 mlxplat_pci_fpga_device_init_lpc_fail: 7777 return err; 7778 } 7779 7780 static void mlxplat_pci_fpga_devices_exit(void) 7781 { 7782 mlxplat_pci_fpga_device_exit(jtag_bridge, jtag_bridge_addr); 7783 mlxplat_pci_fpga_device_exit(i2c_bridge, i2c_bridge_addr); 7784 mlxplat_pci_fpga_device_exit(lpc_bridge, mlxplat_mlxcpld_regmap_ctx.base); 7785 } 7786 7787 static int 7788 mlxplat_logicdev_init(struct resource **hotplug_resources, unsigned int *hotplug_resources_size) 7789 { 7790 int err; 7791 7792 err = mlxplat_pci_fpga_devices_init(hotplug_resources, hotplug_resources_size); 7793 if (err == -ENODEV) 7794 return mlxplat_lpc_cpld_device_init(hotplug_resources, hotplug_resources_size); 7795 7796 return err; 7797 } 7798 7799 static void mlxplat_logicdev_exit(void) 7800 { 7801 if (lpc_bridge) 7802 mlxplat_pci_fpga_devices_exit(); 7803 else 7804 mlxplat_lpc_cpld_device_exit(); 7805 } 7806 7807 static int mlxplat_platdevs_init(struct mlxplat_priv *priv) 7808 { 7809 int i = 0, err; 7810 7811 /* Add hotplug driver */ 7812 if (mlxplat_hotplug) { 7813 mlxplat_hotplug->regmap = priv->regmap; 7814 if (priv->irq_fpga) 7815 mlxplat_hotplug->irq = priv->irq_fpga; 7816 priv->pdev_hotplug = 7817 platform_device_register_resndata(&mlxplat_dev->dev, 7818 "mlxreg-hotplug", PLATFORM_DEVID_NONE, 7819 priv->hotplug_resources, 7820 priv->hotplug_resources_size, 7821 mlxplat_hotplug, sizeof(*mlxplat_hotplug)); 7822 if (IS_ERR(priv->pdev_hotplug)) { 7823 err = PTR_ERR(priv->pdev_hotplug); 7824 goto fail_platform_hotplug_register; 7825 } 7826 } 7827 7828 /* Add LED driver. */ 7829 if (mlxplat_led) { 7830 mlxplat_led->regmap = priv->regmap; 7831 priv->pdev_led = 7832 platform_device_register_resndata(&mlxplat_dev->dev, "leds-mlxreg", 7833 PLATFORM_DEVID_NONE, NULL, 0, mlxplat_led, 7834 sizeof(*mlxplat_led)); 7835 if (IS_ERR(priv->pdev_led)) { 7836 err = PTR_ERR(priv->pdev_led); 7837 goto fail_platform_leds_register; 7838 } 7839 } 7840 7841 /* Add registers io access driver. */ 7842 if (mlxplat_regs_io) { 7843 mlxplat_regs_io->regmap = priv->regmap; 7844 priv->pdev_io_regs = platform_device_register_resndata(&mlxplat_dev->dev, 7845 "mlxreg-io", 7846 PLATFORM_DEVID_NONE, NULL, 7847 0, mlxplat_regs_io, 7848 sizeof(*mlxplat_regs_io)); 7849 if (IS_ERR(priv->pdev_io_regs)) { 7850 err = PTR_ERR(priv->pdev_io_regs); 7851 goto fail_platform_io_register; 7852 } 7853 } 7854 7855 /* Add FAN driver. */ 7856 if (mlxplat_fan) { 7857 mlxplat_fan->regmap = priv->regmap; 7858 priv->pdev_fan = platform_device_register_resndata(&mlxplat_dev->dev, "mlxreg-fan", 7859 PLATFORM_DEVID_NONE, NULL, 0, 7860 mlxplat_fan, 7861 sizeof(*mlxplat_fan)); 7862 if (IS_ERR(priv->pdev_fan)) { 7863 err = PTR_ERR(priv->pdev_fan); 7864 goto fail_platform_fan_register; 7865 } 7866 } 7867 7868 /* Add WD drivers. */ 7869 err = mlxplat_mlxcpld_check_wd_capability(priv->regmap); 7870 if (err) 7871 goto fail_platform_wd_register; 7872 for (i = 0; i < MLXPLAT_CPLD_WD_MAX_DEVS; i++) { 7873 if (mlxplat_wd_data[i]) { 7874 mlxplat_wd_data[i]->regmap = priv->regmap; 7875 priv->pdev_wd[i] = 7876 platform_device_register_resndata(&mlxplat_dev->dev, "mlx-wdt", i, 7877 NULL, 0, mlxplat_wd_data[i], 7878 sizeof(*mlxplat_wd_data[i])); 7879 if (IS_ERR(priv->pdev_wd[i])) { 7880 err = PTR_ERR(priv->pdev_wd[i]); 7881 goto fail_platform_wd_register; 7882 } 7883 } 7884 } 7885 7886 /* Add DPU drivers. */ 7887 for (i = 0; i < MLXPLAT_CPLD_DPU_MAX_DEVS; i++) { 7888 if (!mlxplat_dpu_data[i]) 7889 continue; 7890 priv->pdev_dpu[i] = 7891 platform_device_register_resndata(&mlxplat_dev->dev, "mlxreg-dpu", 7892 i, NULL, 0, mlxplat_dpu_data[i], 7893 sizeof(*mlxplat_dpu_data[i])); 7894 if (IS_ERR(priv->pdev_dpu[i])) { 7895 err = PTR_ERR(priv->pdev_dpu[i]); 7896 goto fail_platform_dpu_register; 7897 } 7898 } 7899 7900 return 0; 7901 7902 fail_platform_dpu_register: 7903 while (i--) 7904 platform_device_unregister(priv->pdev_dpu[i]); 7905 fail_platform_wd_register: 7906 while (i--) 7907 platform_device_unregister(priv->pdev_wd[i]); 7908 fail_platform_fan_register: 7909 if (mlxplat_regs_io) 7910 platform_device_unregister(priv->pdev_io_regs); 7911 fail_platform_io_register: 7912 if (mlxplat_led) 7913 platform_device_unregister(priv->pdev_led); 7914 fail_platform_leds_register: 7915 if (mlxplat_hotplug) 7916 platform_device_unregister(priv->pdev_hotplug); 7917 fail_platform_hotplug_register: 7918 return err; 7919 } 7920 7921 static void mlxplat_platdevs_exit(struct mlxplat_priv *priv) 7922 { 7923 int i; 7924 7925 for (i = MLXPLAT_CPLD_DPU_MAX_DEVS - 1; i >= 0; i--) 7926 platform_device_unregister(priv->pdev_dpu[i]); 7927 for (i = MLXPLAT_CPLD_WD_MAX_DEVS - 1; i >= 0; i--) 7928 platform_device_unregister(priv->pdev_wd[i]); 7929 if (priv->pdev_fan) 7930 platform_device_unregister(priv->pdev_fan); 7931 if (priv->pdev_io_regs) 7932 platform_device_unregister(priv->pdev_io_regs); 7933 if (priv->pdev_led) 7934 platform_device_unregister(priv->pdev_led); 7935 if (priv->pdev_hotplug) 7936 platform_device_unregister(priv->pdev_hotplug); 7937 } 7938 7939 static int 7940 mlxplat_i2c_mux_complition_notify(void *handle, struct i2c_adapter *parent, 7941 struct i2c_adapter *adapters[]) 7942 { 7943 struct mlxplat_priv *priv = handle; 7944 7945 return mlxplat_platdevs_init(priv); 7946 } 7947 7948 static int mlxplat_i2c_mux_topology_init(struct mlxplat_priv *priv) 7949 { 7950 int i, err; 7951 7952 if (!priv->pdev_i2c) { 7953 priv->i2c_main_init_status = MLXPLAT_I2C_MAIN_BUS_NOTIFIED; 7954 return 0; 7955 } 7956 7957 priv->i2c_main_init_status = MLXPLAT_I2C_MAIN_BUS_HANDLE_CREATED; 7958 for (i = 0; i < mlxplat_mux_num; i++) { 7959 priv->pdev_mux[i] = platform_device_register_resndata(&priv->pdev_i2c->dev, 7960 "i2c-mux-reg", i, NULL, 0, 7961 &mlxplat_mux_data[i], 7962 sizeof(mlxplat_mux_data[i])); 7963 if (IS_ERR(priv->pdev_mux[i])) { 7964 err = PTR_ERR(priv->pdev_mux[i]); 7965 goto fail_platform_mux_register; 7966 } 7967 } 7968 7969 return mlxplat_i2c_mux_complition_notify(priv, NULL, NULL); 7970 7971 fail_platform_mux_register: 7972 while (i--) 7973 platform_device_unregister(priv->pdev_mux[i]); 7974 return err; 7975 } 7976 7977 static void mlxplat_i2c_mux_topology_exit(struct mlxplat_priv *priv) 7978 { 7979 int i; 7980 7981 for (i = mlxplat_mux_num - 1; i >= 0; i--) { 7982 if (priv->pdev_mux[i]) 7983 platform_device_unregister(priv->pdev_mux[i]); 7984 } 7985 } 7986 7987 static int mlxplat_i2c_main_completion_notify(void *handle, int id) 7988 { 7989 struct mlxplat_priv *priv = handle; 7990 7991 return mlxplat_i2c_mux_topology_init(priv); 7992 } 7993 7994 static int mlxplat_i2c_main_init(struct mlxplat_priv *priv) 7995 { 7996 int nr, err; 7997 7998 if (!mlxplat_i2c) 7999 return 0; 8000 8001 err = mlxplat_mlxcpld_verify_bus_topology(&nr); 8002 if (nr < 0) 8003 goto fail_mlxplat_mlxcpld_verify_bus_topology; 8004 8005 nr = (nr == mlxplat_max_adap_num) ? -1 : nr; 8006 mlxplat_i2c->regmap = priv->regmap; 8007 mlxplat_i2c->handle = priv; 8008 8009 /* Set mapped base address of I2C-LPC bridge over PCIe */ 8010 if (lpc_bridge) 8011 mlxplat_i2c->addr = i2c_bridge_addr; 8012 priv->pdev_i2c = platform_device_register_resndata(&mlxplat_dev->dev, "i2c_mlxcpld", 8013 nr, priv->hotplug_resources, 8014 priv->hotplug_resources_size, 8015 mlxplat_i2c, sizeof(*mlxplat_i2c)); 8016 if (IS_ERR(priv->pdev_i2c)) { 8017 err = PTR_ERR(priv->pdev_i2c); 8018 goto fail_platform_i2c_register; 8019 } 8020 8021 if (priv->i2c_main_init_status == MLXPLAT_I2C_MAIN_BUS_NOTIFIED) { 8022 err = mlxplat_i2c_mux_topology_init(priv); 8023 if (err) 8024 goto fail_mlxplat_i2c_mux_topology_init; 8025 } 8026 8027 return 0; 8028 8029 fail_mlxplat_i2c_mux_topology_init: 8030 platform_device_unregister(priv->pdev_i2c); 8031 fail_platform_i2c_register: 8032 fail_mlxplat_mlxcpld_verify_bus_topology: 8033 return err; 8034 } 8035 8036 static void mlxplat_i2c_main_exit(struct mlxplat_priv *priv) 8037 { 8038 mlxplat_platdevs_exit(priv); 8039 mlxplat_i2c_mux_topology_exit(priv); 8040 if (priv->pdev_i2c) 8041 platform_device_unregister(priv->pdev_i2c); 8042 } 8043 8044 static int mlxplat_probe(struct platform_device *pdev) 8045 { 8046 unsigned int hotplug_resources_size = 0; 8047 struct resource *hotplug_resources = NULL; 8048 struct acpi_device *acpi_dev; 8049 struct mlxplat_priv *priv; 8050 int irq_fpga = 0, i, err; 8051 8052 acpi_dev = ACPI_COMPANION(&pdev->dev); 8053 if (acpi_dev) { 8054 irq_fpga = acpi_dev_gpio_irq_get(acpi_dev, 0); 8055 if (irq_fpga < 0) 8056 return -ENODEV; 8057 mlxplat_dev = pdev; 8058 } 8059 8060 err = mlxplat_logicdev_init(&hotplug_resources, &hotplug_resources_size); 8061 if (err) 8062 return err; 8063 8064 priv = devm_kzalloc(&mlxplat_dev->dev, sizeof(struct mlxplat_priv), 8065 GFP_KERNEL); 8066 if (!priv) { 8067 err = -ENOMEM; 8068 goto fail_alloc; 8069 } 8070 platform_set_drvdata(mlxplat_dev, priv); 8071 priv->hotplug_resources = hotplug_resources; 8072 priv->hotplug_resources_size = hotplug_resources_size; 8073 priv->irq_fpga = irq_fpga; 8074 8075 if (!mlxplat_regmap_config) 8076 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config; 8077 8078 priv->regmap = devm_regmap_init(&mlxplat_dev->dev, NULL, 8079 &mlxplat_mlxcpld_regmap_ctx, 8080 mlxplat_regmap_config); 8081 if (IS_ERR(priv->regmap)) { 8082 err = PTR_ERR(priv->regmap); 8083 goto fail_alloc; 8084 } 8085 8086 /* Set default registers. */ 8087 for (i = 0; i < mlxplat_regmap_config->num_reg_defaults; i++) { 8088 err = regmap_write(priv->regmap, 8089 mlxplat_regmap_config->reg_defaults[i].reg, 8090 mlxplat_regmap_config->reg_defaults[i].def); 8091 if (err) 8092 goto fail_regmap_write; 8093 } 8094 8095 err = mlxplat_i2c_main_init(priv); 8096 if (err) 8097 goto fail_mlxplat_i2c_main_init; 8098 8099 /* Sync registers with hardware. */ 8100 regcache_mark_dirty(priv->regmap); 8101 err = regcache_sync(priv->regmap); 8102 if (err) 8103 goto fail_regcache_sync; 8104 8105 if (mlxplat_reboot_nb) { 8106 err = register_reboot_notifier(mlxplat_reboot_nb); 8107 if (err) 8108 goto fail_register_reboot_notifier; 8109 } 8110 8111 return 0; 8112 8113 fail_register_reboot_notifier: 8114 fail_regcache_sync: 8115 mlxplat_i2c_main_exit(priv); 8116 fail_mlxplat_i2c_main_init: 8117 fail_regmap_write: 8118 fail_alloc: 8119 mlxplat_logicdev_exit(); 8120 8121 return err; 8122 } 8123 8124 static void mlxplat_remove(struct platform_device *pdev) 8125 { 8126 struct mlxplat_priv *priv = platform_get_drvdata(mlxplat_dev); 8127 8128 if (pm_power_off) 8129 pm_power_off = NULL; 8130 if (mlxplat_reboot_nb) 8131 unregister_reboot_notifier(mlxplat_reboot_nb); 8132 mlxplat_i2c_main_exit(priv); 8133 mlxplat_logicdev_exit(); 8134 } 8135 8136 static const struct acpi_device_id mlxplat_acpi_table[] = { 8137 { "MLNXBF49", 0 }, 8138 {} 8139 }; 8140 MODULE_DEVICE_TABLE(acpi, mlxplat_acpi_table); 8141 8142 static struct platform_driver mlxplat_driver = { 8143 .driver = { 8144 .name = "mlxplat", 8145 .acpi_match_table = mlxplat_acpi_table, 8146 .probe_type = PROBE_FORCE_SYNCHRONOUS, 8147 }, 8148 .probe = mlxplat_probe, 8149 .remove = mlxplat_remove, 8150 }; 8151 8152 static int __init mlxplat_init(void) 8153 { 8154 int err; 8155 8156 if (!dmi_check_system(mlxplat_dmi_table)) 8157 return -ENODEV; 8158 8159 err = platform_driver_register(&mlxplat_driver); 8160 if (err) 8161 return err; 8162 return 0; 8163 } 8164 module_init(mlxplat_init); 8165 8166 static void __exit mlxplat_exit(void) 8167 { 8168 if (mlxplat_dev) 8169 platform_device_unregister(mlxplat_dev); 8170 8171 platform_driver_unregister(&mlxplat_driver); 8172 } 8173 module_exit(mlxplat_exit); 8174 8175 MODULE_AUTHOR("Vadim Pasternak <vadimp@mellanox.com>"); 8176 MODULE_DESCRIPTION("Mellanox platform driver"); 8177 MODULE_LICENSE("Dual BSD/GPL"); 8178