1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Driver for the NVIDIA Tegra pinmux 4 * 5 * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved. 6 * 7 * Derived from code: 8 * Copyright (C) 2010 Google, Inc. 9 * Copyright (C) 2010 NVIDIA Corporation 10 * Copyright (C) 2009-2011 ST-Ericsson AB 11 */ 12 13 #include <linux/err.h> 14 #include <linux/init.h> 15 #include <linux/io.h> 16 #include <linux/of.h> 17 #include <linux/platform_device.h> 18 #include <linux/seq_file.h> 19 #include <linux/slab.h> 20 21 #include <linux/pinctrl/machine.h> 22 #include <linux/pinctrl/pinconf.h> 23 #include <linux/pinctrl/pinctrl.h> 24 #include <linux/pinctrl/pinmux.h> 25 26 #include "../core.h" 27 #include "../pinctrl-utils.h" 28 #include "pinctrl-tegra.h" 29 30 static inline u32 pmx_readl(struct tegra_pmx *pmx, u32 bank, u32 reg) 31 { 32 return readl(pmx->regs[bank] + reg); 33 } 34 35 static inline void pmx_writel(struct tegra_pmx *pmx, u32 val, u32 bank, u32 reg) 36 { 37 writel_relaxed(val, pmx->regs[bank] + reg); 38 /* make sure pinmux register write completed */ 39 pmx_readl(pmx, bank, reg); 40 } 41 42 static int tegra_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) 43 { 44 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 45 46 return pmx->soc->ngroups; 47 } 48 49 static const char *tegra_pinctrl_get_group_name(struct pinctrl_dev *pctldev, 50 unsigned group) 51 { 52 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 53 54 return pmx->soc->groups[group].name; 55 } 56 57 static int tegra_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, 58 unsigned group, 59 const unsigned **pins, 60 unsigned *num_pins) 61 { 62 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 63 64 *pins = pmx->soc->groups[group].pins; 65 *num_pins = pmx->soc->groups[group].npins; 66 67 return 0; 68 } 69 70 #ifdef CONFIG_DEBUG_FS 71 static void tegra_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev, 72 struct seq_file *s, 73 unsigned offset) 74 { 75 seq_printf(s, " %s", dev_name(pctldev->dev)); 76 } 77 #endif 78 79 static const struct cfg_param { 80 const char *property; 81 enum tegra_pinconf_param param; 82 } cfg_params[] = { 83 {"nvidia,pull", TEGRA_PINCONF_PARAM_PULL}, 84 {"nvidia,tristate", TEGRA_PINCONF_PARAM_TRISTATE}, 85 {"nvidia,enable-input", TEGRA_PINCONF_PARAM_ENABLE_INPUT}, 86 {"nvidia,open-drain", TEGRA_PINCONF_PARAM_OPEN_DRAIN}, 87 {"nvidia,lock", TEGRA_PINCONF_PARAM_LOCK}, 88 {"nvidia,io-reset", TEGRA_PINCONF_PARAM_IORESET}, 89 {"nvidia,rcv-sel", TEGRA_PINCONF_PARAM_RCV_SEL}, 90 {"nvidia,io-hv", TEGRA_PINCONF_PARAM_RCV_SEL}, 91 {"nvidia,high-speed-mode", TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE}, 92 {"nvidia,schmitt", TEGRA_PINCONF_PARAM_SCHMITT}, 93 {"nvidia,low-power-mode", TEGRA_PINCONF_PARAM_LOW_POWER_MODE}, 94 {"nvidia,pull-down-strength", TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH}, 95 {"nvidia,pull-up-strength", TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH}, 96 {"nvidia,slew-rate-falling", TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING}, 97 {"nvidia,slew-rate-rising", TEGRA_PINCONF_PARAM_SLEW_RATE_RISING}, 98 {"nvidia,drive-type", TEGRA_PINCONF_PARAM_DRIVE_TYPE}, 99 {"nvidia,gpio-mode", TEGRA_PINCONF_PARAM_GPIO_MODE}, 100 }; 101 102 static int tegra_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, 103 struct device_node *np, 104 struct pinctrl_map **map, 105 unsigned *reserved_maps, 106 unsigned *num_maps) 107 { 108 struct device *dev = pctldev->dev; 109 int ret, i; 110 const char *function; 111 u32 val; 112 unsigned long config; 113 unsigned long *configs = NULL; 114 unsigned num_configs = 0; 115 unsigned reserve; 116 struct property *prop; 117 const char *group; 118 119 ret = of_property_read_string(np, "nvidia,function", &function); 120 if (ret < 0) { 121 /* EINVAL=missing, which is fine since it's optional */ 122 if (ret != -EINVAL) 123 dev_err(dev, 124 "%pOF: could not parse property nvidia,function\n", np); 125 function = NULL; 126 } 127 128 for (i = 0; i < ARRAY_SIZE(cfg_params); i++) { 129 ret = of_property_read_u32(np, cfg_params[i].property, &val); 130 if (!ret) { 131 config = TEGRA_PINCONF_PACK(cfg_params[i].param, val); 132 ret = pinctrl_utils_add_config(pctldev, &configs, 133 &num_configs, config); 134 if (ret < 0) 135 goto exit; 136 /* EINVAL=missing, which is fine since it's optional */ 137 } else if (ret != -EINVAL) { 138 dev_err(dev, "%pOF: could not parse property %s\n", 139 np, cfg_params[i].property); 140 } 141 } 142 143 reserve = 0; 144 if (function != NULL) 145 reserve++; 146 if (num_configs) 147 reserve++; 148 ret = of_property_count_strings(np, "nvidia,pins"); 149 if (ret < 0) { 150 dev_err(dev, "%pOF: could not parse property nvidia,pins\n", np); 151 goto exit; 152 } 153 reserve *= ret; 154 155 ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps, 156 num_maps, reserve); 157 if (ret < 0) 158 goto exit; 159 160 of_property_for_each_string(np, "nvidia,pins", prop, group) { 161 if (function) { 162 ret = pinctrl_utils_add_map_mux(pctldev, map, 163 reserved_maps, num_maps, group, 164 function); 165 if (ret < 0) 166 goto exit; 167 } 168 169 if (num_configs) { 170 ret = pinctrl_utils_add_map_configs(pctldev, map, 171 reserved_maps, num_maps, group, 172 configs, num_configs, 173 PIN_MAP_TYPE_CONFIGS_GROUP); 174 if (ret < 0) 175 goto exit; 176 } 177 } 178 179 ret = 0; 180 181 exit: 182 kfree(configs); 183 return ret; 184 } 185 186 static int tegra_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, 187 struct device_node *np_config, 188 struct pinctrl_map **map, 189 unsigned *num_maps) 190 { 191 unsigned reserved_maps; 192 int ret; 193 194 reserved_maps = 0; 195 *map = NULL; 196 *num_maps = 0; 197 198 for_each_child_of_node_scoped(np_config, np) { 199 ret = tegra_pinctrl_dt_subnode_to_map(pctldev, np, map, 200 &reserved_maps, num_maps); 201 if (ret < 0) { 202 pinctrl_utils_free_map(pctldev, *map, 203 *num_maps); 204 return ret; 205 } 206 } 207 208 return 0; 209 } 210 211 static const struct pinctrl_ops tegra_pinctrl_ops = { 212 .get_groups_count = tegra_pinctrl_get_groups_count, 213 .get_group_name = tegra_pinctrl_get_group_name, 214 .get_group_pins = tegra_pinctrl_get_group_pins, 215 #ifdef CONFIG_DEBUG_FS 216 .pin_dbg_show = tegra_pinctrl_pin_dbg_show, 217 #endif 218 .dt_node_to_map = tegra_pinctrl_dt_node_to_map, 219 .dt_free_map = pinctrl_utils_free_map, 220 }; 221 222 static int tegra_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev) 223 { 224 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 225 226 return pmx->soc->nfunctions; 227 } 228 229 static const char *tegra_pinctrl_get_func_name(struct pinctrl_dev *pctldev, 230 unsigned function) 231 { 232 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 233 234 return pmx->functions[function].name; 235 } 236 237 static int tegra_pinctrl_get_func_groups(struct pinctrl_dev *pctldev, 238 unsigned function, 239 const char * const **groups, 240 unsigned * const num_groups) 241 { 242 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 243 244 *groups = pmx->functions[function].groups; 245 *num_groups = pmx->functions[function].ngroups; 246 247 return 0; 248 } 249 250 static int tegra_pinctrl_set_mux(struct pinctrl_dev *pctldev, 251 unsigned function, 252 unsigned group) 253 { 254 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 255 const struct tegra_pingroup *g; 256 int i; 257 u32 val; 258 259 g = &pmx->soc->groups[group]; 260 261 if (WARN_ON(g->mux_reg < 0)) 262 return -EINVAL; 263 264 for (i = 0; i < ARRAY_SIZE(g->funcs); i++) { 265 if (g->funcs[i] == function) 266 break; 267 } 268 if (WARN_ON(i == ARRAY_SIZE(g->funcs))) 269 return -EINVAL; 270 271 val = pmx_readl(pmx, g->mux_bank, g->mux_reg); 272 val &= ~(0x3 << g->mux_bit); 273 val |= i << g->mux_bit; 274 /* Set the SFIO/GPIO selection to SFIO when under pinmux control*/ 275 if (pmx->soc->sfsel_in_mux) 276 val |= (1 << g->sfsel_bit); 277 pmx_writel(pmx, val, g->mux_bank, g->mux_reg); 278 279 return 0; 280 } 281 282 static int tegra_pinctrl_get_group_index(struct pinctrl_dev *pctldev, 283 unsigned int offset) 284 { 285 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 286 unsigned int group, num_pins, j; 287 const unsigned int *pins; 288 int ret; 289 290 for (group = 0; group < pmx->soc->ngroups; ++group) { 291 ret = tegra_pinctrl_get_group_pins(pctldev, group, &pins, &num_pins); 292 if (ret < 0) 293 continue; 294 for (j = 0; j < num_pins; j++) { 295 if (offset == pins[j]) 296 return group; 297 } 298 } 299 300 return -EINVAL; 301 } 302 303 static const struct tegra_pingroup *tegra_pinctrl_get_group(struct pinctrl_dev *pctldev, 304 unsigned int offset, 305 int group_index) 306 { 307 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 308 309 if (group_index < 0 || group_index >= pmx->soc->ngroups) 310 return NULL; 311 312 return &pmx->soc->groups[group_index]; 313 } 314 315 static struct tegra_pingroup_config *tegra_pinctrl_get_group_config(struct pinctrl_dev *pctldev, 316 unsigned int offset, 317 int group_index) 318 { 319 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 320 321 if (group_index < 0) 322 return NULL; 323 324 return &pmx->pingroup_configs[group_index]; 325 } 326 327 static int tegra_pinctrl_gpio_request_enable(struct pinctrl_dev *pctldev, 328 struct pinctrl_gpio_range *range, 329 unsigned int offset) 330 { 331 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 332 const struct tegra_pingroup *group; 333 struct tegra_pingroup_config *config; 334 int group_index; 335 u32 value; 336 337 if (!pmx->soc->sfsel_in_mux) 338 return 0; 339 340 group_index = tegra_pinctrl_get_group_index(pctldev, offset); 341 group = tegra_pinctrl_get_group(pctldev, offset, group_index); 342 343 if (!group) 344 return -EINVAL; 345 346 if (group->mux_reg < 0 || group->sfsel_bit < 0) 347 return -EINVAL; 348 349 config = tegra_pinctrl_get_group_config(pctldev, offset, group_index); 350 if (!config) 351 return -EINVAL; 352 value = pmx_readl(pmx, group->mux_bank, group->mux_reg); 353 config->is_sfsel = (value & BIT(group->sfsel_bit)) != 0; 354 value &= ~BIT(group->sfsel_bit); 355 pmx_writel(pmx, value, group->mux_bank, group->mux_reg); 356 357 return 0; 358 } 359 360 static void tegra_pinctrl_gpio_disable_free(struct pinctrl_dev *pctldev, 361 struct pinctrl_gpio_range *range, 362 unsigned int offset) 363 { 364 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 365 const struct tegra_pingroup *group; 366 struct tegra_pingroup_config *config; 367 int group_index; 368 u32 value; 369 370 if (!pmx->soc->sfsel_in_mux) 371 return; 372 373 group_index = tegra_pinctrl_get_group_index(pctldev, offset); 374 group = tegra_pinctrl_get_group(pctldev, offset, group_index); 375 376 if (!group) 377 return; 378 379 if (group->mux_reg < 0 || group->sfsel_bit < 0) 380 return; 381 382 config = tegra_pinctrl_get_group_config(pctldev, offset, group_index); 383 if (!config) 384 return; 385 value = pmx_readl(pmx, group->mux_bank, group->mux_reg); 386 if (config->is_sfsel) 387 value |= BIT(group->sfsel_bit); 388 pmx_writel(pmx, value, group->mux_bank, group->mux_reg); 389 } 390 391 static const struct pinmux_ops tegra_pinmux_ops = { 392 .get_functions_count = tegra_pinctrl_get_funcs_count, 393 .get_function_name = tegra_pinctrl_get_func_name, 394 .get_function_groups = tegra_pinctrl_get_func_groups, 395 .set_mux = tegra_pinctrl_set_mux, 396 .gpio_request_enable = tegra_pinctrl_gpio_request_enable, 397 .gpio_disable_free = tegra_pinctrl_gpio_disable_free, 398 }; 399 400 static int tegra_pinconf_reg(struct tegra_pmx *pmx, 401 const struct tegra_pingroup *g, 402 enum tegra_pinconf_param param, 403 bool report_err, 404 s8 *bank, s32 *reg, s8 *bit, s8 *width) 405 { 406 switch (param) { 407 case TEGRA_PINCONF_PARAM_PULL: 408 *bank = g->pupd_bank; 409 *reg = g->pupd_reg; 410 *bit = g->pupd_bit; 411 *width = 2; 412 break; 413 case TEGRA_PINCONF_PARAM_TRISTATE: 414 *bank = g->tri_bank; 415 *reg = g->tri_reg; 416 *bit = g->tri_bit; 417 *width = 1; 418 break; 419 case TEGRA_PINCONF_PARAM_ENABLE_INPUT: 420 *bank = g->mux_bank; 421 *reg = g->mux_reg; 422 *bit = g->einput_bit; 423 *width = 1; 424 break; 425 case TEGRA_PINCONF_PARAM_OPEN_DRAIN: 426 *bank = g->mux_bank; 427 *reg = g->mux_reg; 428 *bit = g->odrain_bit; 429 *width = 1; 430 break; 431 case TEGRA_PINCONF_PARAM_LOCK: 432 *bank = g->mux_bank; 433 *reg = g->mux_reg; 434 *bit = g->lock_bit; 435 *width = 1; 436 break; 437 case TEGRA_PINCONF_PARAM_IORESET: 438 *bank = g->mux_bank; 439 *reg = g->mux_reg; 440 *bit = g->ioreset_bit; 441 *width = 1; 442 break; 443 case TEGRA_PINCONF_PARAM_RCV_SEL: 444 *bank = g->mux_bank; 445 *reg = g->mux_reg; 446 *bit = g->rcv_sel_bit; 447 *width = 1; 448 break; 449 case TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE: 450 if (pmx->soc->hsm_in_mux) { 451 *bank = g->mux_bank; 452 *reg = g->mux_reg; 453 } else { 454 *bank = g->drv_bank; 455 *reg = g->drv_reg; 456 } 457 *bit = g->hsm_bit; 458 *width = 1; 459 break; 460 case TEGRA_PINCONF_PARAM_SCHMITT: 461 if (pmx->soc->schmitt_in_mux) { 462 *bank = g->mux_bank; 463 *reg = g->mux_reg; 464 } else { 465 *bank = g->drv_bank; 466 *reg = g->drv_reg; 467 } 468 *bit = g->schmitt_bit; 469 *width = 1; 470 break; 471 case TEGRA_PINCONF_PARAM_LOW_POWER_MODE: 472 *bank = g->drv_bank; 473 *reg = g->drv_reg; 474 *bit = g->lpmd_bit; 475 *width = 2; 476 break; 477 case TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH: 478 *bank = g->drv_bank; 479 *reg = g->drv_reg; 480 *bit = g->drvdn_bit; 481 *width = g->drvdn_width; 482 break; 483 case TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH: 484 *bank = g->drv_bank; 485 *reg = g->drv_reg; 486 *bit = g->drvup_bit; 487 *width = g->drvup_width; 488 break; 489 case TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING: 490 *bank = g->drv_bank; 491 *reg = g->drv_reg; 492 *bit = g->slwf_bit; 493 *width = g->slwf_width; 494 break; 495 case TEGRA_PINCONF_PARAM_SLEW_RATE_RISING: 496 *bank = g->drv_bank; 497 *reg = g->drv_reg; 498 *bit = g->slwr_bit; 499 *width = g->slwr_width; 500 break; 501 case TEGRA_PINCONF_PARAM_DRIVE_TYPE: 502 if (pmx->soc->drvtype_in_mux) { 503 *bank = g->mux_bank; 504 *reg = g->mux_reg; 505 } else { 506 *bank = g->drv_bank; 507 *reg = g->drv_reg; 508 } 509 *bit = g->drvtype_bit; 510 *width = 2; 511 break; 512 case TEGRA_PINCONF_PARAM_GPIO_MODE: 513 if (pmx->soc->sfsel_in_mux) { 514 *bank = g->mux_bank; 515 *reg = g->mux_reg; 516 *bit = g->sfsel_bit; 517 *width = 1; 518 } else { 519 *reg = -EINVAL; 520 } 521 break; 522 default: 523 dev_err(pmx->dev, "Invalid config param %04x\n", param); 524 return -ENOTSUPP; 525 } 526 527 if (*reg < 0 || *bit < 0) { 528 if (report_err) { 529 const char *prop = "unknown"; 530 int i; 531 532 for (i = 0; i < ARRAY_SIZE(cfg_params); i++) { 533 if (cfg_params[i].param == param) { 534 prop = cfg_params[i].property; 535 break; 536 } 537 } 538 539 dev_err(pmx->dev, 540 "Config param %04x (%s) not supported on group %s\n", 541 param, prop, g->name); 542 } 543 return -ENOTSUPP; 544 } 545 546 return 0; 547 } 548 549 static int tegra_pinconf_get(struct pinctrl_dev *pctldev, 550 unsigned pin, unsigned long *config) 551 { 552 dev_err(pctldev->dev, "pin_config_get op not supported\n"); 553 return -ENOTSUPP; 554 } 555 556 static int tegra_pinconf_set(struct pinctrl_dev *pctldev, 557 unsigned pin, unsigned long *configs, 558 unsigned num_configs) 559 { 560 dev_err(pctldev->dev, "pin_config_set op not supported\n"); 561 return -ENOTSUPP; 562 } 563 564 static int tegra_pinconf_group_get(struct pinctrl_dev *pctldev, 565 unsigned group, unsigned long *config) 566 { 567 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 568 enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(*config); 569 u16 arg; 570 const struct tegra_pingroup *g; 571 int ret; 572 s8 bank, bit, width; 573 s32 reg; 574 u32 val, mask; 575 576 g = &pmx->soc->groups[group]; 577 578 ret = tegra_pinconf_reg(pmx, g, param, true, &bank, ®, &bit, 579 &width); 580 if (ret < 0) 581 return ret; 582 583 val = pmx_readl(pmx, bank, reg); 584 mask = (1 << width) - 1; 585 arg = (val >> bit) & mask; 586 587 *config = TEGRA_PINCONF_PACK(param, arg); 588 589 return 0; 590 } 591 592 static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev, 593 unsigned group, unsigned long *configs, 594 unsigned num_configs) 595 { 596 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 597 enum tegra_pinconf_param param; 598 u16 arg; 599 const struct tegra_pingroup *g; 600 int ret, i; 601 s8 bank, bit, width; 602 s32 reg; 603 u32 val, mask; 604 605 g = &pmx->soc->groups[group]; 606 607 for (i = 0; i < num_configs; i++) { 608 param = TEGRA_PINCONF_UNPACK_PARAM(configs[i]); 609 arg = TEGRA_PINCONF_UNPACK_ARG(configs[i]); 610 611 ret = tegra_pinconf_reg(pmx, g, param, true, &bank, ®, &bit, 612 &width); 613 if (ret < 0) 614 return ret; 615 616 val = pmx_readl(pmx, bank, reg); 617 618 /* LOCK can't be cleared */ 619 if (param == TEGRA_PINCONF_PARAM_LOCK) { 620 if ((val & BIT(bit)) && !arg) { 621 dev_err(pctldev->dev, "LOCK bit cannot be cleared\n"); 622 return -EINVAL; 623 } 624 } 625 626 /* Special-case Boolean values; allow any non-zero as true */ 627 if (width == 1) 628 arg = !!arg; 629 630 /* Range-check user-supplied value */ 631 mask = (1 << width) - 1; 632 if (arg & ~mask) { 633 dev_err(pctldev->dev, 634 "config %lx: %x too big for %d bit register\n", 635 configs[i], arg, width); 636 return -EINVAL; 637 } 638 639 /* Update register */ 640 val &= ~(mask << bit); 641 val |= arg << bit; 642 pmx_writel(pmx, val, bank, reg); 643 } /* for each config */ 644 645 return 0; 646 } 647 648 #ifdef CONFIG_DEBUG_FS 649 static void tegra_pinconf_dbg_show(struct pinctrl_dev *pctldev, 650 struct seq_file *s, unsigned offset) 651 { 652 } 653 654 static const char *strip_prefix(const char *s) 655 { 656 const char *comma = strchr(s, ','); 657 if (!comma) 658 return s; 659 660 return comma + 1; 661 } 662 663 static void tegra_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, 664 struct seq_file *s, unsigned group) 665 { 666 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 667 const struct tegra_pingroup *g; 668 int i, ret; 669 s8 bank, bit, width; 670 s32 reg; 671 u32 val; 672 673 g = &pmx->soc->groups[group]; 674 675 for (i = 0; i < ARRAY_SIZE(cfg_params); i++) { 676 ret = tegra_pinconf_reg(pmx, g, cfg_params[i].param, false, 677 &bank, ®, &bit, &width); 678 if (ret < 0) 679 continue; 680 681 val = pmx_readl(pmx, bank, reg); 682 val >>= bit; 683 val &= (1 << width) - 1; 684 685 seq_printf(s, "\n\t%s=%u", 686 strip_prefix(cfg_params[i].property), val); 687 } 688 689 if (g->mux_reg >= 0) { 690 /* read pinmux function and dump to seq_file */ 691 val = pmx_readl(pmx, g->mux_bank, g->mux_reg); 692 val = g->funcs[(val >> g->mux_bit) & 0x3]; 693 694 seq_printf(s, "\n\tfunction=%s", pmx->functions[val].name); 695 } 696 } 697 698 static void tegra_pinconf_config_dbg_show(struct pinctrl_dev *pctldev, 699 struct seq_file *s, 700 unsigned long config) 701 { 702 enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(config); 703 u16 arg = TEGRA_PINCONF_UNPACK_ARG(config); 704 const char *pname = "unknown"; 705 int i; 706 707 for (i = 0; i < ARRAY_SIZE(cfg_params); i++) { 708 if (cfg_params[i].param == param) { 709 pname = cfg_params[i].property; 710 break; 711 } 712 } 713 714 seq_printf(s, "%s=%d", strip_prefix(pname), arg); 715 } 716 #endif 717 718 static const struct pinconf_ops tegra_pinconf_ops = { 719 .pin_config_get = tegra_pinconf_get, 720 .pin_config_set = tegra_pinconf_set, 721 .pin_config_group_get = tegra_pinconf_group_get, 722 .pin_config_group_set = tegra_pinconf_group_set, 723 #ifdef CONFIG_DEBUG_FS 724 .pin_config_dbg_show = tegra_pinconf_dbg_show, 725 .pin_config_group_dbg_show = tegra_pinconf_group_dbg_show, 726 .pin_config_config_dbg_show = tegra_pinconf_config_dbg_show, 727 #endif 728 }; 729 730 static void tegra_pinctrl_clear_parked_bits(struct tegra_pmx *pmx) 731 { 732 int i = 0; 733 const struct tegra_pingroup *g; 734 u32 val; 735 736 for (i = 0; i < pmx->soc->ngroups; ++i) { 737 g = &pmx->soc->groups[i]; 738 if (g->parked_bitmask > 0) { 739 unsigned int bank, reg; 740 741 if (g->mux_reg != -1) { 742 bank = g->mux_bank; 743 reg = g->mux_reg; 744 } else { 745 bank = g->drv_bank; 746 reg = g->drv_reg; 747 } 748 749 val = pmx_readl(pmx, bank, reg); 750 val &= ~g->parked_bitmask; 751 pmx_writel(pmx, val, bank, reg); 752 } 753 } 754 } 755 756 static size_t tegra_pinctrl_get_bank_size(struct device *dev, 757 unsigned int bank_id) 758 { 759 struct platform_device *pdev = to_platform_device(dev); 760 struct resource *res; 761 762 res = platform_get_resource(pdev, IORESOURCE_MEM, bank_id); 763 764 return resource_size(res) / 4; 765 } 766 767 static int tegra_pinctrl_suspend(struct device *dev) 768 { 769 struct tegra_pmx *pmx = dev_get_drvdata(dev); 770 u32 *backup_regs = pmx->backup_regs; 771 u32 __iomem *regs; 772 size_t bank_size; 773 unsigned int i, k; 774 775 for (i = 0; i < pmx->nbanks; i++) { 776 bank_size = tegra_pinctrl_get_bank_size(dev, i); 777 regs = pmx->regs[i]; 778 for (k = 0; k < bank_size; k++) 779 *backup_regs++ = readl_relaxed(regs++); 780 } 781 782 return pinctrl_force_sleep(pmx->pctl); 783 } 784 785 static int tegra_pinctrl_resume(struct device *dev) 786 { 787 struct tegra_pmx *pmx = dev_get_drvdata(dev); 788 u32 *backup_regs = pmx->backup_regs; 789 u32 __iomem *regs; 790 size_t bank_size; 791 unsigned int i, k; 792 793 for (i = 0; i < pmx->nbanks; i++) { 794 bank_size = tegra_pinctrl_get_bank_size(dev, i); 795 regs = pmx->regs[i]; 796 for (k = 0; k < bank_size; k++) 797 writel_relaxed(*backup_regs++, regs++); 798 } 799 800 /* flush all the prior writes */ 801 readl_relaxed(pmx->regs[0]); 802 /* wait for pinctrl register read to complete */ 803 rmb(); 804 return 0; 805 } 806 807 DEFINE_NOIRQ_DEV_PM_OPS(tegra_pinctrl_pm, tegra_pinctrl_suspend, tegra_pinctrl_resume); 808 809 static bool tegra_pinctrl_gpio_node_has_range(struct tegra_pmx *pmx) 810 { 811 struct device_node *np; 812 bool has_prop = false; 813 814 np = of_find_compatible_node(NULL, NULL, pmx->soc->gpio_compatible); 815 if (!np) 816 return has_prop; 817 818 has_prop = of_find_property(np, "gpio-ranges", NULL); 819 820 of_node_put(np); 821 822 return has_prop; 823 } 824 825 int tegra_pinctrl_probe(struct platform_device *pdev, 826 const struct tegra_pinctrl_soc_data *soc_data) 827 { 828 struct tegra_pmx *pmx; 829 struct resource *res; 830 int i; 831 const char **group_pins; 832 int fn, gn, gfn; 833 unsigned long backup_regs_size = 0; 834 835 pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL); 836 if (!pmx) 837 return -ENOMEM; 838 839 pmx->dev = &pdev->dev; 840 pmx->soc = soc_data; 841 842 pmx->pingroup_configs = devm_kcalloc(&pdev->dev, 843 pmx->soc->ngroups, sizeof(*pmx->pingroup_configs), 844 GFP_KERNEL); 845 if (!pmx->pingroup_configs) 846 return -ENOMEM; 847 848 /* 849 * Each mux group will appear in 4 functions' list of groups. 850 * This over-allocates slightly, since not all groups are mux groups. 851 */ 852 pmx->group_pins = devm_kcalloc(&pdev->dev, pmx->soc->ngroups * 4, 853 sizeof(*pmx->group_pins), GFP_KERNEL); 854 if (!pmx->group_pins) 855 return -ENOMEM; 856 857 pmx->functions = devm_kcalloc(&pdev->dev, pmx->soc->nfunctions, 858 sizeof(*pmx->functions), GFP_KERNEL); 859 if (!pmx->functions) 860 return -ENOMEM; 861 862 group_pins = pmx->group_pins; 863 864 for (fn = 0; fn < pmx->soc->nfunctions; fn++) { 865 struct tegra_function *func = &pmx->functions[fn]; 866 867 func->name = pmx->soc->functions[fn]; 868 func->groups = group_pins; 869 870 for (gn = 0; gn < pmx->soc->ngroups; gn++) { 871 const struct tegra_pingroup *g = &pmx->soc->groups[gn]; 872 873 if (g->mux_reg == -1) 874 continue; 875 876 for (gfn = 0; gfn < 4; gfn++) 877 if (g->funcs[gfn] == fn) 878 break; 879 if (gfn == 4) 880 continue; 881 882 BUG_ON(group_pins - pmx->group_pins >= 883 pmx->soc->ngroups * 4); 884 *group_pins++ = g->name; 885 func->ngroups++; 886 } 887 } 888 889 pmx->gpio_range.name = "Tegra GPIOs"; 890 pmx->gpio_range.id = 0; 891 pmx->gpio_range.base = 0; 892 pmx->gpio_range.npins = pmx->soc->ngpios; 893 894 pmx->desc.pctlops = &tegra_pinctrl_ops; 895 pmx->desc.pmxops = &tegra_pinmux_ops; 896 pmx->desc.confops = &tegra_pinconf_ops; 897 pmx->desc.owner = THIS_MODULE; 898 pmx->desc.name = dev_name(&pdev->dev); 899 pmx->desc.pins = pmx->soc->pins; 900 pmx->desc.npins = pmx->soc->npins; 901 902 for (i = 0; ; i++) { 903 res = platform_get_resource(pdev, IORESOURCE_MEM, i); 904 if (!res) 905 break; 906 backup_regs_size += resource_size(res); 907 } 908 pmx->nbanks = i; 909 910 pmx->regs = devm_kcalloc(&pdev->dev, pmx->nbanks, sizeof(*pmx->regs), 911 GFP_KERNEL); 912 if (!pmx->regs) 913 return -ENOMEM; 914 915 pmx->backup_regs = devm_kzalloc(&pdev->dev, backup_regs_size, 916 GFP_KERNEL); 917 if (!pmx->backup_regs) 918 return -ENOMEM; 919 920 for (i = 0; i < pmx->nbanks; i++) { 921 pmx->regs[i] = devm_platform_ioremap_resource(pdev, i); 922 if (IS_ERR(pmx->regs[i])) 923 return PTR_ERR(pmx->regs[i]); 924 } 925 926 pmx->pctl = devm_pinctrl_register(&pdev->dev, &pmx->desc, pmx); 927 if (IS_ERR(pmx->pctl)) { 928 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); 929 return PTR_ERR(pmx->pctl); 930 } 931 932 tegra_pinctrl_clear_parked_bits(pmx); 933 934 if (pmx->soc->ngpios > 0 && !tegra_pinctrl_gpio_node_has_range(pmx)) 935 pinctrl_add_gpio_range(pmx->pctl, &pmx->gpio_range); 936 937 platform_set_drvdata(pdev, pmx); 938 939 dev_dbg(&pdev->dev, "Probed Tegra pinctrl driver\n"); 940 941 return 0; 942 } 943