1 /* 2 * Allwinner V3/V3s SoCs pinctrl driver. 3 * 4 * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz> 5 * 6 * Based on pinctrl-sun8i-h3.c, which is: 7 * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> 8 * 9 * Based on pinctrl-sun8i-a23.c, which is: 10 * Copyright (C) 2014 Chen-Yu Tsai <wens@csie.org> 11 * Copyright (C) 2014 Maxime Ripard <maxime.ripard@free-electrons.com> 12 * 13 * This file is licensed under the terms of the GNU General Public 14 * License version 2. This program is licensed "as is" without any 15 * warranty of any kind, whether express or implied. 16 */ 17 18 #include <linux/module.h> 19 #include <linux/platform_device.h> 20 #include <linux/of.h> 21 #include <linux/pinctrl/pinctrl.h> 22 23 #include "pinctrl-sunxi.h" 24 25 #define PINCTRL_SUN8I_V3 BIT(0) 26 #define PINCTRL_SUN8I_V3S BIT(1) 27 28 static const struct sunxi_desc_pin sun8i_v3s_pins[] = { 29 /* Hole */ 30 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0), 31 SUNXI_FUNCTION(0x0, "gpio_in"), 32 SUNXI_FUNCTION(0x1, "gpio_out"), 33 SUNXI_FUNCTION(0x2, "uart2"), /* TX */ 34 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PB_EINT0 */ 35 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1), 36 SUNXI_FUNCTION(0x0, "gpio_in"), 37 SUNXI_FUNCTION(0x1, "gpio_out"), 38 SUNXI_FUNCTION(0x2, "uart2"), /* RX */ 39 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PB_EINT1 */ 40 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2), 41 SUNXI_FUNCTION(0x0, "gpio_in"), 42 SUNXI_FUNCTION(0x1, "gpio_out"), 43 SUNXI_FUNCTION(0x2, "uart2"), /* RTS */ 44 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PB_EINT2 */ 45 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3), 46 SUNXI_FUNCTION(0x0, "gpio_in"), 47 SUNXI_FUNCTION(0x1, "gpio_out"), 48 SUNXI_FUNCTION(0x2, "uart2"), /* D1 */ 49 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PB_EINT3 */ 50 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4), 51 SUNXI_FUNCTION(0x0, "gpio_in"), 52 SUNXI_FUNCTION(0x1, "gpio_out"), 53 SUNXI_FUNCTION(0x2, "pwm0"), 54 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PB_EINT4 */ 55 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5), 56 SUNXI_FUNCTION(0x0, "gpio_in"), 57 SUNXI_FUNCTION(0x1, "gpio_out"), 58 SUNXI_FUNCTION(0x2, "pwm1"), 59 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PB_EINT5 */ 60 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6), 61 SUNXI_FUNCTION(0x0, "gpio_in"), 62 SUNXI_FUNCTION(0x1, "gpio_out"), 63 SUNXI_FUNCTION(0x2, "i2c0"), /* SCK */ 64 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PB_EINT6 */ 65 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7), 66 SUNXI_FUNCTION(0x0, "gpio_in"), 67 SUNXI_FUNCTION(0x1, "gpio_out"), 68 SUNXI_FUNCTION(0x2, "i2c0"), /* SDA */ 69 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PB_EINT7 */ 70 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8), 71 SUNXI_FUNCTION(0x0, "gpio_in"), 72 SUNXI_FUNCTION(0x1, "gpio_out"), 73 SUNXI_FUNCTION(0x2, "i2c1"), /* SDA */ 74 SUNXI_FUNCTION(0x3, "uart0"), /* TX */ 75 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PB_EINT8 */ 76 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9), 77 SUNXI_FUNCTION(0x0, "gpio_in"), 78 SUNXI_FUNCTION(0x1, "gpio_out"), 79 SUNXI_FUNCTION(0x2, "i2c1"), /* SCK */ 80 SUNXI_FUNCTION(0x3, "uart0"), /* RX */ 81 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PB_EINT9 */ 82 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(B, 10), 83 PINCTRL_SUN8I_V3, 84 SUNXI_FUNCTION(0x0, "gpio_in"), 85 SUNXI_FUNCTION(0x1, "gpio_out"), 86 SUNXI_FUNCTION(0x2, "jtag"), /* MS */ 87 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PB_EINT10 */ 88 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(B, 11), 89 PINCTRL_SUN8I_V3, 90 SUNXI_FUNCTION(0x0, "gpio_in"), 91 SUNXI_FUNCTION(0x1, "gpio_out"), 92 SUNXI_FUNCTION(0x2, "jtag"), /* CK */ 93 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), /* PB_EINT11 */ 94 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(B, 12), 95 PINCTRL_SUN8I_V3, 96 SUNXI_FUNCTION(0x0, "gpio_in"), 97 SUNXI_FUNCTION(0x1, "gpio_out"), 98 SUNXI_FUNCTION(0x2, "jtag"), /* DO */ 99 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)), /* PB_EINT12 */ 100 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(B, 13), 101 PINCTRL_SUN8I_V3, 102 SUNXI_FUNCTION(0x0, "gpio_in"), 103 SUNXI_FUNCTION(0x1, "gpio_out"), 104 SUNXI_FUNCTION(0x2, "jtag"), /* DI */ 105 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 13)), /* PB_EINT13 */ 106 /* Hole */ 107 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0), 108 SUNXI_FUNCTION(0x0, "gpio_in"), 109 SUNXI_FUNCTION(0x1, "gpio_out"), 110 SUNXI_FUNCTION(0x2, "mmc2"), /* CLK */ 111 SUNXI_FUNCTION(0x3, "spi0")), /* MISO */ 112 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1), 113 SUNXI_FUNCTION(0x0, "gpio_in"), 114 SUNXI_FUNCTION(0x1, "gpio_out"), 115 SUNXI_FUNCTION(0x2, "mmc2"), /* CMD */ 116 SUNXI_FUNCTION(0x3, "spi0")), /* CLK */ 117 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2), 118 SUNXI_FUNCTION(0x0, "gpio_in"), 119 SUNXI_FUNCTION(0x1, "gpio_out"), 120 SUNXI_FUNCTION(0x2, "mmc2"), /* RST */ 121 SUNXI_FUNCTION(0x3, "spi0")), /* CS */ 122 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3), 123 SUNXI_FUNCTION(0x0, "gpio_in"), 124 SUNXI_FUNCTION(0x1, "gpio_out"), 125 SUNXI_FUNCTION(0x2, "mmc2"), /* D0 */ 126 SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */ 127 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 4), 128 PINCTRL_SUN8I_V3, 129 SUNXI_FUNCTION(0x0, "gpio_in"), 130 SUNXI_FUNCTION(0x1, "gpio_out"), 131 SUNXI_FUNCTION(0x2, "mmc2")), /* D1 */ 132 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 5), 133 PINCTRL_SUN8I_V3, 134 SUNXI_FUNCTION(0x0, "gpio_in"), 135 SUNXI_FUNCTION(0x1, "gpio_out"), 136 SUNXI_FUNCTION(0x2, "mmc2")), /* D2 */ 137 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 6), 138 PINCTRL_SUN8I_V3, 139 SUNXI_FUNCTION(0x0, "gpio_in"), 140 SUNXI_FUNCTION(0x1, "gpio_out"), 141 SUNXI_FUNCTION(0x2, "mmc2")), /* D3 */ 142 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 7), 143 PINCTRL_SUN8I_V3, 144 SUNXI_FUNCTION(0x0, "gpio_in"), 145 SUNXI_FUNCTION(0x1, "gpio_out"), 146 SUNXI_FUNCTION(0x2, "mmc2")), /* D4 */ 147 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 8), 148 PINCTRL_SUN8I_V3, 149 SUNXI_FUNCTION(0x0, "gpio_in"), 150 SUNXI_FUNCTION(0x1, "gpio_out"), 151 SUNXI_FUNCTION(0x2, "mmc2")), /* D5 */ 152 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 9), 153 PINCTRL_SUN8I_V3, 154 SUNXI_FUNCTION(0x0, "gpio_in"), 155 SUNXI_FUNCTION(0x1, "gpio_out"), 156 SUNXI_FUNCTION(0x2, "mmc2")), /* D6 */ 157 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 10), 158 PINCTRL_SUN8I_V3, 159 SUNXI_FUNCTION(0x0, "gpio_in"), 160 SUNXI_FUNCTION(0x1, "gpio_out"), 161 SUNXI_FUNCTION(0x2, "mmc2")), /* D7 */ 162 /* Hole */ 163 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 0), 164 PINCTRL_SUN8I_V3, 165 SUNXI_FUNCTION(0x0, "gpio_in"), 166 SUNXI_FUNCTION(0x1, "gpio_out"), 167 SUNXI_FUNCTION(0x2, "lcd"), /* D2 */ 168 SUNXI_FUNCTION(0x4, "emac")), /* RXD3 */ 169 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 1), 170 PINCTRL_SUN8I_V3, 171 SUNXI_FUNCTION(0x0, "gpio_in"), 172 SUNXI_FUNCTION(0x1, "gpio_out"), 173 SUNXI_FUNCTION(0x2, "lcd"), /* D3 */ 174 SUNXI_FUNCTION(0x4, "emac")), /* RXD2 */ 175 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 2), 176 PINCTRL_SUN8I_V3, 177 SUNXI_FUNCTION(0x0, "gpio_in"), 178 SUNXI_FUNCTION(0x1, "gpio_out"), 179 SUNXI_FUNCTION(0x2, "lcd"), /* D4 */ 180 SUNXI_FUNCTION(0x4, "emac")), /* RXD1 */ 181 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 3), 182 PINCTRL_SUN8I_V3, 183 SUNXI_FUNCTION(0x0, "gpio_in"), 184 SUNXI_FUNCTION(0x1, "gpio_out"), 185 SUNXI_FUNCTION(0x2, "lcd"), /* D5 */ 186 SUNXI_FUNCTION(0x4, "emac")), /* RXD0 */ 187 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 4), 188 PINCTRL_SUN8I_V3, 189 SUNXI_FUNCTION(0x0, "gpio_in"), 190 SUNXI_FUNCTION(0x1, "gpio_out"), 191 SUNXI_FUNCTION(0x2, "lcd"), /* D6 */ 192 SUNXI_FUNCTION(0x4, "emac")), /* RXCK */ 193 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 5), 194 PINCTRL_SUN8I_V3, 195 SUNXI_FUNCTION(0x0, "gpio_in"), 196 SUNXI_FUNCTION(0x1, "gpio_out"), 197 SUNXI_FUNCTION(0x2, "lcd"), /* D7 */ 198 SUNXI_FUNCTION(0x4, "emac")), /* RXCTL/RXDV */ 199 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 6), 200 PINCTRL_SUN8I_V3, 201 SUNXI_FUNCTION(0x0, "gpio_in"), 202 SUNXI_FUNCTION(0x1, "gpio_out"), 203 SUNXI_FUNCTION(0x2, "lcd"), /* D10 */ 204 SUNXI_FUNCTION(0x4, "emac")), /* RXERR */ 205 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 7), 206 PINCTRL_SUN8I_V3, 207 SUNXI_FUNCTION(0x0, "gpio_in"), 208 SUNXI_FUNCTION(0x1, "gpio_out"), 209 SUNXI_FUNCTION(0x2, "lcd"), /* D11 */ 210 SUNXI_FUNCTION(0x4, "emac")), /* TXD3 */ 211 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 8), 212 PINCTRL_SUN8I_V3, 213 SUNXI_FUNCTION(0x0, "gpio_in"), 214 SUNXI_FUNCTION(0x1, "gpio_out"), 215 SUNXI_FUNCTION(0x2, "lcd"), /* D12 */ 216 SUNXI_FUNCTION(0x4, "emac")), /* TXD2 */ 217 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 9), 218 PINCTRL_SUN8I_V3, 219 SUNXI_FUNCTION(0x0, "gpio_in"), 220 SUNXI_FUNCTION(0x1, "gpio_out"), 221 SUNXI_FUNCTION(0x2, "lcd"), /* D13 */ 222 SUNXI_FUNCTION(0x4, "emac")), /* TXD1 */ 223 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 10), 224 PINCTRL_SUN8I_V3, 225 SUNXI_FUNCTION(0x0, "gpio_in"), 226 SUNXI_FUNCTION(0x1, "gpio_out"), 227 SUNXI_FUNCTION(0x2, "lcd"), /* D14 */ 228 SUNXI_FUNCTION(0x4, "emac")), /* TXD0 */ 229 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 11), 230 PINCTRL_SUN8I_V3, 231 SUNXI_FUNCTION(0x0, "gpio_in"), 232 SUNXI_FUNCTION(0x1, "gpio_out"), 233 SUNXI_FUNCTION(0x2, "lcd"), /* D15 */ 234 SUNXI_FUNCTION(0x4, "emac")), /* CRS */ 235 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 12), 236 PINCTRL_SUN8I_V3, 237 SUNXI_FUNCTION(0x0, "gpio_in"), 238 SUNXI_FUNCTION(0x1, "gpio_out"), 239 SUNXI_FUNCTION(0x2, "lcd"), /* D18 */ 240 SUNXI_FUNCTION(0x3, "lvds"), /* VP0 */ 241 SUNXI_FUNCTION(0x4, "emac")), /* TXCK */ 242 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 13), 243 PINCTRL_SUN8I_V3, 244 SUNXI_FUNCTION(0x0, "gpio_in"), 245 SUNXI_FUNCTION(0x1, "gpio_out"), 246 SUNXI_FUNCTION(0x2, "lcd"), /* D19 */ 247 SUNXI_FUNCTION(0x3, "lvds"), /* VN0 */ 248 SUNXI_FUNCTION(0x4, "emac")), /* TXCTL/TXEN */ 249 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 14), 250 PINCTRL_SUN8I_V3, 251 SUNXI_FUNCTION(0x0, "gpio_in"), 252 SUNXI_FUNCTION(0x1, "gpio_out"), 253 SUNXI_FUNCTION(0x2, "lcd"), /* D20 */ 254 SUNXI_FUNCTION(0x3, "lvds"), /* VP1 */ 255 SUNXI_FUNCTION(0x4, "emac")), /* TXERR */ 256 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 15), 257 PINCTRL_SUN8I_V3, 258 SUNXI_FUNCTION(0x0, "gpio_in"), 259 SUNXI_FUNCTION(0x1, "gpio_out"), 260 SUNXI_FUNCTION(0x2, "lcd"), /* D21 */ 261 SUNXI_FUNCTION(0x3, "lvds"), /* VN1 */ 262 SUNXI_FUNCTION(0x4, "emac")), /* CLKIN/COL */ 263 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 16), 264 PINCTRL_SUN8I_V3, 265 SUNXI_FUNCTION(0x0, "gpio_in"), 266 SUNXI_FUNCTION(0x1, "gpio_out"), 267 SUNXI_FUNCTION(0x2, "lcd"), /* D22 */ 268 SUNXI_FUNCTION(0x3, "lvds"), /* VP2 */ 269 SUNXI_FUNCTION(0x4, "emac")), /* MDC */ 270 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 17), 271 PINCTRL_SUN8I_V3, 272 SUNXI_FUNCTION(0x0, "gpio_in"), 273 SUNXI_FUNCTION(0x1, "gpio_out"), 274 SUNXI_FUNCTION(0x2, "lcd"), /* D23 */ 275 SUNXI_FUNCTION(0x3, "lvds"), /* VN2 */ 276 SUNXI_FUNCTION(0x4, "emac")), /* MDIO */ 277 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 18), 278 PINCTRL_SUN8I_V3, 279 SUNXI_FUNCTION(0x0, "gpio_in"), 280 SUNXI_FUNCTION(0x1, "gpio_out"), 281 SUNXI_FUNCTION(0x2, "lcd"), /* CLK */ 282 SUNXI_FUNCTION(0x3, "lvds")), /* VPC */ 283 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 19), 284 PINCTRL_SUN8I_V3, 285 SUNXI_FUNCTION(0x0, "gpio_in"), 286 SUNXI_FUNCTION(0x1, "gpio_out"), 287 SUNXI_FUNCTION(0x2, "lcd"), /* DE */ 288 SUNXI_FUNCTION(0x3, "lvds")), /* VNC */ 289 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 20), 290 PINCTRL_SUN8I_V3, 291 SUNXI_FUNCTION(0x0, "gpio_in"), 292 SUNXI_FUNCTION(0x1, "gpio_out"), 293 SUNXI_FUNCTION(0x2, "lcd"), /* HSYNC */ 294 SUNXI_FUNCTION(0x3, "lvds")), /* VP3 */ 295 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 21), 296 PINCTRL_SUN8I_V3, 297 SUNXI_FUNCTION(0x0, "gpio_in"), 298 SUNXI_FUNCTION(0x1, "gpio_out"), 299 SUNXI_FUNCTION(0x2, "lcd"), /* VSYNC */ 300 SUNXI_FUNCTION(0x3, "lvds")), /* VN3 */ 301 /* Hole */ 302 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0), 303 SUNXI_FUNCTION(0x0, "gpio_in"), 304 SUNXI_FUNCTION(0x1, "gpio_out"), 305 SUNXI_FUNCTION(0x2, "csi"), /* PCLK */ 306 SUNXI_FUNCTION(0x3, "lcd")), /* CLK */ 307 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1), 308 SUNXI_FUNCTION(0x0, "gpio_in"), 309 SUNXI_FUNCTION(0x1, "gpio_out"), 310 SUNXI_FUNCTION(0x2, "csi"), /* MCLK */ 311 SUNXI_FUNCTION(0x3, "lcd")), /* DE */ 312 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2), 313 SUNXI_FUNCTION(0x0, "gpio_in"), 314 SUNXI_FUNCTION(0x1, "gpio_out"), 315 SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */ 316 SUNXI_FUNCTION(0x3, "lcd")), /* HSYNC */ 317 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3), 318 SUNXI_FUNCTION(0x0, "gpio_in"), 319 SUNXI_FUNCTION(0x1, "gpio_out"), 320 SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */ 321 SUNXI_FUNCTION(0x3, "lcd")), /* VSYNC */ 322 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4), 323 SUNXI_FUNCTION(0x0, "gpio_in"), 324 SUNXI_FUNCTION(0x1, "gpio_out"), 325 SUNXI_FUNCTION(0x2, "csi"), /* D0 */ 326 SUNXI_FUNCTION(0x3, "lcd")), /* D2 */ 327 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5), 328 SUNXI_FUNCTION(0x0, "gpio_in"), 329 SUNXI_FUNCTION(0x1, "gpio_out"), 330 SUNXI_FUNCTION(0x2, "csi"), /* D1 */ 331 SUNXI_FUNCTION(0x3, "lcd")), /* D3 */ 332 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6), 333 SUNXI_FUNCTION(0x0, "gpio_in"), 334 SUNXI_FUNCTION(0x1, "gpio_out"), 335 SUNXI_FUNCTION(0x2, "csi"), /* D2 */ 336 SUNXI_FUNCTION(0x3, "lcd")), /* D4 */ 337 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7), 338 SUNXI_FUNCTION(0x0, "gpio_in"), 339 SUNXI_FUNCTION(0x1, "gpio_out"), 340 SUNXI_FUNCTION(0x2, "csi"), /* D3 */ 341 SUNXI_FUNCTION(0x3, "lcd")), /* D5 */ 342 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8), 343 SUNXI_FUNCTION(0x0, "gpio_in"), 344 SUNXI_FUNCTION(0x1, "gpio_out"), 345 SUNXI_FUNCTION(0x2, "csi"), /* D4 */ 346 SUNXI_FUNCTION(0x3, "lcd")), /* D6 */ 347 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9), 348 SUNXI_FUNCTION(0x0, "gpio_in"), 349 SUNXI_FUNCTION(0x1, "gpio_out"), 350 SUNXI_FUNCTION(0x2, "csi"), /* D5 */ 351 SUNXI_FUNCTION(0x3, "lcd")), /* D7 */ 352 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10), 353 SUNXI_FUNCTION(0x0, "gpio_in"), 354 SUNXI_FUNCTION(0x1, "gpio_out"), 355 SUNXI_FUNCTION(0x2, "csi"), /* D6 */ 356 SUNXI_FUNCTION(0x3, "lcd")), /* D10 */ 357 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11), 358 SUNXI_FUNCTION(0x0, "gpio_in"), 359 SUNXI_FUNCTION(0x1, "gpio_out"), 360 SUNXI_FUNCTION(0x2, "csi"), /* D7 */ 361 SUNXI_FUNCTION(0x3, "lcd")), /* D11 */ 362 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12), 363 SUNXI_FUNCTION(0x0, "gpio_in"), 364 SUNXI_FUNCTION(0x1, "gpio_out"), 365 SUNXI_FUNCTION(0x2, "csi"), /* D8 */ 366 SUNXI_FUNCTION(0x3, "lcd")), /* D12 */ 367 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13), 368 SUNXI_FUNCTION(0x0, "gpio_in"), 369 SUNXI_FUNCTION(0x1, "gpio_out"), 370 SUNXI_FUNCTION(0x2, "csi"), /* D9 */ 371 SUNXI_FUNCTION(0x3, "lcd")), /* D13 */ 372 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14), 373 SUNXI_FUNCTION(0x0, "gpio_in"), 374 SUNXI_FUNCTION(0x1, "gpio_out"), 375 SUNXI_FUNCTION(0x2, "csi"), /* D10 */ 376 SUNXI_FUNCTION(0x3, "lcd")), /* D14 */ 377 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15), 378 SUNXI_FUNCTION(0x0, "gpio_in"), 379 SUNXI_FUNCTION(0x1, "gpio_out"), 380 SUNXI_FUNCTION(0x2, "csi"), /* D11 */ 381 SUNXI_FUNCTION(0x3, "lcd")), /* D15 */ 382 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 16), 383 SUNXI_FUNCTION(0x0, "gpio_in"), 384 SUNXI_FUNCTION(0x1, "gpio_out"), 385 SUNXI_FUNCTION(0x2, "csi"), /* D12 */ 386 SUNXI_FUNCTION(0x3, "lcd")), /* D18 */ 387 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 17), 388 SUNXI_FUNCTION(0x0, "gpio_in"), 389 SUNXI_FUNCTION(0x1, "gpio_out"), 390 SUNXI_FUNCTION(0x2, "csi"), /* D13 */ 391 SUNXI_FUNCTION(0x3, "lcd")), /* D19 */ 392 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 18), 393 SUNXI_FUNCTION(0x0, "gpio_in"), 394 SUNXI_FUNCTION(0x1, "gpio_out"), 395 SUNXI_FUNCTION(0x2, "csi"), /* D14 */ 396 SUNXI_FUNCTION(0x3, "lcd")), /* D20 */ 397 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 19), 398 SUNXI_FUNCTION(0x0, "gpio_in"), 399 SUNXI_FUNCTION(0x1, "gpio_out"), 400 SUNXI_FUNCTION(0x2, "csi"), /* D15 */ 401 SUNXI_FUNCTION(0x3, "lcd")), /* D21 */ 402 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 20), 403 SUNXI_FUNCTION(0x0, "gpio_in"), 404 SUNXI_FUNCTION(0x1, "gpio_out"), 405 SUNXI_FUNCTION(0x2, "csi"), /* FIELD */ 406 SUNXI_FUNCTION(0x3, "csi_mipi")), /* MCLK */ 407 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 21), 408 SUNXI_FUNCTION(0x0, "gpio_in"), 409 SUNXI_FUNCTION(0x1, "gpio_out"), 410 SUNXI_FUNCTION(0x2, "csi"), /* SCK */ 411 SUNXI_FUNCTION(0x3, "i2c1"), /* SCK */ 412 SUNXI_FUNCTION(0x4, "uart1")), /* TX */ 413 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 22), 414 SUNXI_FUNCTION(0x0, "gpio_in"), 415 SUNXI_FUNCTION(0x1, "gpio_out"), 416 SUNXI_FUNCTION(0x2, "csi"), /* SDA */ 417 SUNXI_FUNCTION(0x3, "i2c1"), /* SDA */ 418 SUNXI_FUNCTION(0x4, "uart1")), /* RX */ 419 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 23), 420 SUNXI_FUNCTION(0x0, "gpio_in"), 421 SUNXI_FUNCTION(0x1, "gpio_out"), 422 SUNXI_FUNCTION(0x3, "lcd"), /* D22 */ 423 SUNXI_FUNCTION(0x4, "uart1")), /* RTS */ 424 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 24), 425 SUNXI_FUNCTION(0x0, "gpio_in"), 426 SUNXI_FUNCTION(0x1, "gpio_out"), 427 SUNXI_FUNCTION(0x3, "lcd"), /* D23 */ 428 SUNXI_FUNCTION(0x4, "uart1")), /* CTS */ 429 /* Hole */ 430 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0), 431 SUNXI_FUNCTION(0x0, "gpio_in"), 432 SUNXI_FUNCTION(0x1, "gpio_out"), 433 SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */ 434 SUNXI_FUNCTION(0x3, "jtag")), /* MS */ 435 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1), 436 SUNXI_FUNCTION(0x0, "gpio_in"), 437 SUNXI_FUNCTION(0x1, "gpio_out"), 438 SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */ 439 SUNXI_FUNCTION(0x3, "jtag")), /* DI */ 440 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2), 441 SUNXI_FUNCTION(0x0, "gpio_in"), 442 SUNXI_FUNCTION(0x1, "gpio_out"), 443 SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */ 444 SUNXI_FUNCTION(0x3, "uart0")), /* TX */ 445 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3), 446 SUNXI_FUNCTION(0x0, "gpio_in"), 447 SUNXI_FUNCTION(0x1, "gpio_out"), 448 SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */ 449 SUNXI_FUNCTION(0x3, "jtag")), /* DO */ 450 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4), 451 SUNXI_FUNCTION(0x0, "gpio_in"), 452 SUNXI_FUNCTION(0x1, "gpio_out"), 453 SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */ 454 SUNXI_FUNCTION(0x3, "uart0")), /* RX */ 455 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5), 456 SUNXI_FUNCTION(0x0, "gpio_in"), 457 SUNXI_FUNCTION(0x1, "gpio_out"), 458 SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */ 459 SUNXI_FUNCTION(0x3, "jtag")), /* CK */ 460 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6), 461 SUNXI_FUNCTION(0x0, "gpio_in"), 462 SUNXI_FUNCTION(0x1, "gpio_out")), 463 /* Hole */ 464 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0), 465 SUNXI_FUNCTION(0x0, "gpio_in"), 466 SUNXI_FUNCTION(0x1, "gpio_out"), 467 SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */ 468 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), /* PG_EINT0 */ 469 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1), 470 SUNXI_FUNCTION(0x0, "gpio_in"), 471 SUNXI_FUNCTION(0x1, "gpio_out"), 472 SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */ 473 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), /* PG_EINT1 */ 474 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2), 475 SUNXI_FUNCTION(0x0, "gpio_in"), 476 SUNXI_FUNCTION(0x1, "gpio_out"), 477 SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */ 478 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), /* PG_EINT2 */ 479 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3), 480 SUNXI_FUNCTION(0x0, "gpio_in"), 481 SUNXI_FUNCTION(0x1, "gpio_out"), 482 SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */ 483 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), /* PG_EINT3 */ 484 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4), 485 SUNXI_FUNCTION(0x0, "gpio_in"), 486 SUNXI_FUNCTION(0x1, "gpio_out"), 487 SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */ 488 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* PG_EINT4 */ 489 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5), 490 SUNXI_FUNCTION(0x0, "gpio_in"), 491 SUNXI_FUNCTION(0x1, "gpio_out"), 492 SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */ 493 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PG_EINT5 */ 494 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 6), 495 PINCTRL_SUN8I_V3, 496 SUNXI_FUNCTION(0x0, "gpio_in"), 497 SUNXI_FUNCTION(0x1, "gpio_out"), 498 SUNXI_FUNCTION(0x2, "uart1"), /* TX */ 499 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), /* PG_EINT6 */ 500 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 7), 501 PINCTRL_SUN8I_V3, 502 SUNXI_FUNCTION(0x0, "gpio_in"), 503 SUNXI_FUNCTION(0x1, "gpio_out"), 504 SUNXI_FUNCTION(0x2, "uart1"), /* RX */ 505 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)), /* PG_EINT7 */ 506 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 8), 507 PINCTRL_SUN8I_V3, 508 SUNXI_FUNCTION(0x0, "gpio_in"), 509 SUNXI_FUNCTION(0x1, "gpio_out"), 510 SUNXI_FUNCTION(0x2, "uart1"), /* RTS */ 511 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 8)), /* PG_EINT8 */ 512 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 9), 513 PINCTRL_SUN8I_V3, 514 SUNXI_FUNCTION(0x0, "gpio_in"), 515 SUNXI_FUNCTION(0x1, "gpio_out"), 516 SUNXI_FUNCTION(0x2, "uart1"), /* CTS */ 517 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 9)), /* PG_EINT9 */ 518 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 10), 519 PINCTRL_SUN8I_V3, 520 SUNXI_FUNCTION(0x0, "gpio_in"), 521 SUNXI_FUNCTION(0x1, "gpio_out"), 522 SUNXI_FUNCTION(0x2, "i2s"), /* SYNC */ 523 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 10)), /* PG_EINT10 */ 524 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 11), 525 PINCTRL_SUN8I_V3, 526 SUNXI_FUNCTION(0x0, "gpio_in"), 527 SUNXI_FUNCTION(0x1, "gpio_out"), 528 SUNXI_FUNCTION(0x2, "i2s"), /* BCLK */ 529 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 11)), /* PG_EINT11 */ 530 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 12), 531 PINCTRL_SUN8I_V3, 532 SUNXI_FUNCTION(0x0, "gpio_in"), 533 SUNXI_FUNCTION(0x1, "gpio_out"), 534 SUNXI_FUNCTION(0x2, "i2s"), /* DOUT */ 535 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 12)), /* PG_EINT12 */ 536 SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 13), 537 PINCTRL_SUN8I_V3, 538 SUNXI_FUNCTION(0x0, "gpio_in"), 539 SUNXI_FUNCTION(0x1, "gpio_out"), 540 SUNXI_FUNCTION(0x2, "i2s"), /* DIN */ 541 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 13)), /* PG_EINT13 */ 542 }; 543 544 static const unsigned int sun8i_v3s_pinctrl_irq_bank_map[] = { 1, 2 }; 545 546 static const struct sunxi_pinctrl_desc sun8i_v3s_pinctrl_data = { 547 .pins = sun8i_v3s_pins, 548 .npins = ARRAY_SIZE(sun8i_v3s_pins), 549 .irq_banks = 2, 550 .irq_bank_map = sun8i_v3s_pinctrl_irq_bank_map, 551 .irq_read_needs_mux = true 552 }; 553 554 static int sun8i_v3s_pinctrl_probe(struct platform_device *pdev) 555 { 556 unsigned long variant = (unsigned long)of_device_get_match_data(&pdev->dev); 557 558 return sunxi_pinctrl_init_with_flags(pdev, &sun8i_v3s_pinctrl_data, 559 variant); 560 } 561 562 static const struct of_device_id sun8i_v3s_pinctrl_match[] = { 563 { 564 .compatible = "allwinner,sun8i-v3-pinctrl", 565 .data = (void *)PINCTRL_SUN8I_V3 566 }, 567 { 568 .compatible = "allwinner,sun8i-v3s-pinctrl", 569 .data = (void *)PINCTRL_SUN8I_V3S 570 }, 571 { }, 572 }; 573 574 static struct platform_driver sun8i_v3s_pinctrl_driver = { 575 .probe = sun8i_v3s_pinctrl_probe, 576 .driver = { 577 .name = "sun8i-v3s-pinctrl", 578 .of_match_table = sun8i_v3s_pinctrl_match, 579 }, 580 }; 581 builtin_platform_driver(sun8i_v3s_pinctrl_driver); 582