1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) Maxime Coquelin 2015 4 * Copyright (C) STMicroelectronics 2017 5 * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com> 6 * 7 * Heavily based on Mediatek's pinctrl driver 8 */ 9 #include <linux/clk.h> 10 #include <linux/gpio/driver.h> 11 #include <linux/hwspinlock.h> 12 #include <linux/io.h> 13 #include <linux/irq.h> 14 #include <linux/mfd/syscon.h> 15 #include <linux/module.h> 16 #include <linux/of.h> 17 #include <linux/of_address.h> 18 #include <linux/of_irq.h> 19 #include <linux/platform_device.h> 20 #include <linux/property.h> 21 #include <linux/regmap.h> 22 #include <linux/reset.h> 23 #include <linux/seq_file.h> 24 #include <linux/slab.h> 25 #include <linux/string_choices.h> 26 27 #include <linux/pinctrl/consumer.h> 28 #include <linux/pinctrl/machine.h> 29 #include <linux/pinctrl/pinconf-generic.h> 30 #include <linux/pinctrl/pinconf.h> 31 #include <linux/pinctrl/pinctrl.h> 32 #include <linux/pinctrl/pinmux.h> 33 34 #include "../core.h" 35 #include "../pinconf.h" 36 #include "../pinctrl-utils.h" 37 #include "pinctrl-stm32.h" 38 39 #define STM32_GPIO_MODER 0x00 40 #define STM32_GPIO_TYPER 0x04 41 #define STM32_GPIO_SPEEDR 0x08 42 #define STM32_GPIO_PUPDR 0x0c 43 #define STM32_GPIO_IDR 0x10 44 #define STM32_GPIO_ODR 0x14 45 #define STM32_GPIO_BSRR 0x18 46 #define STM32_GPIO_LCKR 0x1c 47 #define STM32_GPIO_AFRL 0x20 48 #define STM32_GPIO_AFRH 0x24 49 #define STM32_GPIO_SECCFGR 0x30 50 51 /* custom bitfield to backup pin status */ 52 #define STM32_GPIO_BKP_MODE_SHIFT 0 53 #define STM32_GPIO_BKP_MODE_MASK GENMASK(1, 0) 54 #define STM32_GPIO_BKP_ALT_SHIFT 2 55 #define STM32_GPIO_BKP_ALT_MASK GENMASK(5, 2) 56 #define STM32_GPIO_BKP_SPEED_SHIFT 6 57 #define STM32_GPIO_BKP_SPEED_MASK GENMASK(7, 6) 58 #define STM32_GPIO_BKP_PUPD_SHIFT 8 59 #define STM32_GPIO_BKP_PUPD_MASK GENMASK(9, 8) 60 #define STM32_GPIO_BKP_TYPE 10 61 #define STM32_GPIO_BKP_VAL 11 62 63 #define STM32_GPIO_PINS_PER_BANK 16 64 #define STM32_GPIO_IRQ_LINE 16 65 66 #define SYSCFG_IRQMUX_MASK GENMASK(3, 0) 67 68 #define gpio_range_to_bank(chip) \ 69 container_of(chip, struct stm32_gpio_bank, range) 70 71 #define HWSPNLCK_TIMEOUT 1000 /* usec */ 72 73 static const char * const stm32_gpio_functions[] = { 74 "gpio", "af0", "af1", 75 "af2", "af3", "af4", 76 "af5", "af6", "af7", 77 "af8", "af9", "af10", 78 "af11", "af12", "af13", 79 "af14", "af15", "analog", 80 }; 81 82 struct stm32_pinctrl_group { 83 const char *name; 84 unsigned long config; 85 unsigned pin; 86 }; 87 88 struct stm32_gpio_bank { 89 void __iomem *base; 90 struct reset_control *rstc; 91 spinlock_t lock; 92 struct gpio_chip gpio_chip; 93 struct pinctrl_gpio_range range; 94 struct fwnode_handle *fwnode; 95 struct irq_domain *domain; 96 u32 bank_nr; 97 u32 bank_ioport_nr; 98 u32 pin_backup[STM32_GPIO_PINS_PER_BANK]; 99 u8 irq_type[STM32_GPIO_PINS_PER_BANK]; 100 bool secure_control; 101 }; 102 103 struct stm32_pinctrl { 104 struct device *dev; 105 struct pinctrl_dev *pctl_dev; 106 struct pinctrl_desc pctl_desc; 107 struct stm32_pinctrl_group *groups; 108 unsigned ngroups; 109 const char **grp_names; 110 struct stm32_gpio_bank *banks; 111 struct clk_bulk_data *clks; 112 unsigned nbanks; 113 const struct stm32_pinctrl_match_data *match_data; 114 struct irq_domain *domain; 115 struct regmap *regmap; 116 struct regmap_field *irqmux[STM32_GPIO_PINS_PER_BANK]; 117 struct hwspinlock *hwlock; 118 struct stm32_desc_pin *pins; 119 u32 npins; 120 u32 pkg; 121 u16 irqmux_map; 122 spinlock_t irqmux_lock; 123 }; 124 125 static inline int stm32_gpio_pin(int gpio) 126 { 127 return gpio % STM32_GPIO_PINS_PER_BANK; 128 } 129 130 static inline u32 stm32_gpio_get_mode(u32 function) 131 { 132 switch (function) { 133 case STM32_PIN_GPIO: 134 return 0; 135 case STM32_PIN_AF(0) ... STM32_PIN_AF(15): 136 return 2; 137 case STM32_PIN_ANALOG: 138 return 3; 139 } 140 141 return 0; 142 } 143 144 static inline u32 stm32_gpio_get_alt(u32 function) 145 { 146 switch (function) { 147 case STM32_PIN_GPIO: 148 return 0; 149 case STM32_PIN_AF(0) ... STM32_PIN_AF(15): 150 return function - 1; 151 case STM32_PIN_ANALOG: 152 return 0; 153 } 154 155 return 0; 156 } 157 158 static void stm32_gpio_backup_value(struct stm32_gpio_bank *bank, 159 u32 offset, u32 value) 160 { 161 bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_VAL); 162 bank->pin_backup[offset] |= value << STM32_GPIO_BKP_VAL; 163 } 164 165 static void stm32_gpio_backup_mode(struct stm32_gpio_bank *bank, u32 offset, 166 u32 mode, u32 alt) 167 { 168 bank->pin_backup[offset] &= ~(STM32_GPIO_BKP_MODE_MASK | 169 STM32_GPIO_BKP_ALT_MASK); 170 bank->pin_backup[offset] |= mode << STM32_GPIO_BKP_MODE_SHIFT; 171 bank->pin_backup[offset] |= alt << STM32_GPIO_BKP_ALT_SHIFT; 172 } 173 174 static void stm32_gpio_backup_driving(struct stm32_gpio_bank *bank, u32 offset, 175 u32 drive) 176 { 177 bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_TYPE); 178 bank->pin_backup[offset] |= drive << STM32_GPIO_BKP_TYPE; 179 } 180 181 static void stm32_gpio_backup_speed(struct stm32_gpio_bank *bank, u32 offset, 182 u32 speed) 183 { 184 bank->pin_backup[offset] &= ~STM32_GPIO_BKP_SPEED_MASK; 185 bank->pin_backup[offset] |= speed << STM32_GPIO_BKP_SPEED_SHIFT; 186 } 187 188 static void stm32_gpio_backup_bias(struct stm32_gpio_bank *bank, u32 offset, 189 u32 bias) 190 { 191 bank->pin_backup[offset] &= ~STM32_GPIO_BKP_PUPD_MASK; 192 bank->pin_backup[offset] |= bias << STM32_GPIO_BKP_PUPD_SHIFT; 193 } 194 195 /* GPIO functions */ 196 197 static inline void __stm32_gpio_set(struct stm32_gpio_bank *bank, 198 unsigned offset, int value) 199 { 200 stm32_gpio_backup_value(bank, offset, value); 201 202 if (!value) 203 offset += STM32_GPIO_PINS_PER_BANK; 204 205 writel_relaxed(BIT(offset), bank->base + STM32_GPIO_BSRR); 206 } 207 208 static int stm32_gpio_request(struct gpio_chip *chip, unsigned offset) 209 { 210 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); 211 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 212 struct pinctrl_gpio_range *range; 213 int pin = offset + (bank->bank_nr * STM32_GPIO_PINS_PER_BANK); 214 215 range = pinctrl_find_gpio_range_from_pin_nolock(pctl->pctl_dev, pin); 216 if (!range) { 217 dev_err(pctl->dev, "pin %d not in range.\n", pin); 218 return -EINVAL; 219 } 220 221 return pinctrl_gpio_request(chip, offset); 222 } 223 224 static int stm32_gpio_get(struct gpio_chip *chip, unsigned offset) 225 { 226 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); 227 228 return !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset)); 229 } 230 231 static int stm32_gpio_set(struct gpio_chip *chip, unsigned int offset, 232 int value) 233 { 234 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); 235 236 __stm32_gpio_set(bank, offset, value); 237 238 return 0; 239 } 240 241 static int stm32_gpio_direction_output(struct gpio_chip *chip, 242 unsigned offset, int value) 243 { 244 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); 245 246 __stm32_gpio_set(bank, offset, value); 247 248 return pinctrl_gpio_direction_output(chip, offset); 249 } 250 251 252 static int stm32_gpio_to_irq(struct gpio_chip *chip, unsigned int offset) 253 { 254 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); 255 struct irq_fwspec fwspec; 256 257 fwspec.fwnode = bank->fwnode; 258 fwspec.param_count = 2; 259 fwspec.param[0] = offset; 260 fwspec.param[1] = IRQ_TYPE_NONE; 261 262 return irq_create_fwspec_mapping(&fwspec); 263 } 264 265 static int stm32_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 266 { 267 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); 268 int pin = stm32_gpio_pin(offset); 269 int ret; 270 u32 mode, alt; 271 272 stm32_pmx_get_mode(bank, pin, &mode, &alt); 273 if ((alt == 0) && (mode == 0)) 274 ret = GPIO_LINE_DIRECTION_IN; 275 else if ((alt == 0) && (mode == 1)) 276 ret = GPIO_LINE_DIRECTION_OUT; 277 else 278 ret = -EINVAL; 279 280 return ret; 281 } 282 283 static int stm32_gpio_init_valid_mask(struct gpio_chip *chip, 284 unsigned long *valid_mask, 285 unsigned int ngpios) 286 { 287 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); 288 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 289 unsigned int i; 290 u32 sec; 291 292 /* All gpio are valid per default */ 293 bitmap_fill(valid_mask, ngpios); 294 295 if (bank->secure_control) { 296 /* Tag secured pins as invalid */ 297 sec = readl_relaxed(bank->base + STM32_GPIO_SECCFGR); 298 299 for (i = 0; i < ngpios; i++) { 300 if (sec & BIT(i)) { 301 clear_bit(i, valid_mask); 302 dev_dbg(pctl->dev, "No access to gpio %d - %d\n", bank->bank_nr, i); 303 } 304 } 305 } 306 307 return 0; 308 } 309 310 static const struct gpio_chip stm32_gpio_template = { 311 .request = stm32_gpio_request, 312 .free = pinctrl_gpio_free, 313 .get = stm32_gpio_get, 314 .set_rv = stm32_gpio_set, 315 .direction_input = pinctrl_gpio_direction_input, 316 .direction_output = stm32_gpio_direction_output, 317 .to_irq = stm32_gpio_to_irq, 318 .get_direction = stm32_gpio_get_direction, 319 .set_config = gpiochip_generic_config, 320 .init_valid_mask = stm32_gpio_init_valid_mask, 321 }; 322 323 static void stm32_gpio_irq_trigger(struct irq_data *d) 324 { 325 struct stm32_gpio_bank *bank = d->domain->host_data; 326 int level; 327 328 /* Do not access the GPIO if this is not LEVEL triggered IRQ. */ 329 if (!(bank->irq_type[d->hwirq] & IRQ_TYPE_LEVEL_MASK)) 330 return; 331 332 /* If level interrupt type then retrig */ 333 level = stm32_gpio_get(&bank->gpio_chip, d->hwirq); 334 if ((level == 0 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_LOW) || 335 (level == 1 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_HIGH)) 336 irq_chip_retrigger_hierarchy(d); 337 } 338 339 static void stm32_gpio_irq_eoi(struct irq_data *d) 340 { 341 irq_chip_eoi_parent(d); 342 stm32_gpio_irq_trigger(d); 343 }; 344 345 static int stm32_gpio_set_type(struct irq_data *d, unsigned int type) 346 { 347 struct stm32_gpio_bank *bank = d->domain->host_data; 348 u32 parent_type; 349 350 switch (type) { 351 case IRQ_TYPE_EDGE_RISING: 352 case IRQ_TYPE_EDGE_FALLING: 353 case IRQ_TYPE_EDGE_BOTH: 354 parent_type = type; 355 break; 356 case IRQ_TYPE_LEVEL_HIGH: 357 parent_type = IRQ_TYPE_EDGE_RISING; 358 break; 359 case IRQ_TYPE_LEVEL_LOW: 360 parent_type = IRQ_TYPE_EDGE_FALLING; 361 break; 362 default: 363 return -EINVAL; 364 } 365 366 bank->irq_type[d->hwirq] = type; 367 368 return irq_chip_set_type_parent(d, parent_type); 369 }; 370 371 static int stm32_gpio_irq_request_resources(struct irq_data *irq_data) 372 { 373 struct stm32_gpio_bank *bank = irq_data->domain->host_data; 374 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 375 int ret; 376 377 ret = pinctrl_gpio_direction_input(&bank->gpio_chip, irq_data->hwirq); 378 if (ret) 379 return ret; 380 381 ret = gpiochip_lock_as_irq(&bank->gpio_chip, irq_data->hwirq); 382 if (ret) { 383 dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n", 384 irq_data->hwirq); 385 return ret; 386 } 387 388 return 0; 389 } 390 391 static void stm32_gpio_irq_release_resources(struct irq_data *irq_data) 392 { 393 struct stm32_gpio_bank *bank = irq_data->domain->host_data; 394 395 gpiochip_unlock_as_irq(&bank->gpio_chip, irq_data->hwirq); 396 } 397 398 static void stm32_gpio_irq_unmask(struct irq_data *d) 399 { 400 irq_chip_unmask_parent(d); 401 stm32_gpio_irq_trigger(d); 402 } 403 404 static struct irq_chip stm32_gpio_irq_chip = { 405 .name = "stm32gpio", 406 .irq_eoi = stm32_gpio_irq_eoi, 407 .irq_ack = irq_chip_ack_parent, 408 .irq_mask = irq_chip_mask_parent, 409 .irq_unmask = stm32_gpio_irq_unmask, 410 .irq_set_type = stm32_gpio_set_type, 411 .irq_set_wake = irq_chip_set_wake_parent, 412 .irq_request_resources = stm32_gpio_irq_request_resources, 413 .irq_release_resources = stm32_gpio_irq_release_resources, 414 }; 415 416 static int stm32_gpio_domain_translate(struct irq_domain *d, 417 struct irq_fwspec *fwspec, 418 unsigned long *hwirq, 419 unsigned int *type) 420 { 421 if ((fwspec->param_count != 2) || 422 (fwspec->param[0] >= STM32_GPIO_IRQ_LINE)) 423 return -EINVAL; 424 425 *hwirq = fwspec->param[0]; 426 *type = fwspec->param[1]; 427 return 0; 428 } 429 430 static int stm32_gpio_domain_activate(struct irq_domain *d, 431 struct irq_data *irq_data, bool reserve) 432 { 433 struct stm32_gpio_bank *bank = d->host_data; 434 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 435 int ret = 0; 436 437 if (pctl->hwlock) { 438 ret = hwspin_lock_timeout_in_atomic(pctl->hwlock, 439 HWSPNLCK_TIMEOUT); 440 if (ret) { 441 dev_err(pctl->dev, "Can't get hwspinlock\n"); 442 return ret; 443 } 444 } 445 446 regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->bank_ioport_nr); 447 448 if (pctl->hwlock) 449 hwspin_unlock_in_atomic(pctl->hwlock); 450 451 return ret; 452 } 453 454 static int stm32_gpio_domain_alloc(struct irq_domain *d, 455 unsigned int virq, 456 unsigned int nr_irqs, void *data) 457 { 458 struct stm32_gpio_bank *bank = d->host_data; 459 struct irq_fwspec *fwspec = data; 460 struct irq_fwspec parent_fwspec; 461 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 462 irq_hw_number_t hwirq = fwspec->param[0]; 463 unsigned long flags; 464 int ret = 0; 465 466 /* 467 * Check first that the IRQ MUX of that line is free. 468 * gpio irq mux is shared between several banks, protect with a lock 469 */ 470 spin_lock_irqsave(&pctl->irqmux_lock, flags); 471 472 if (pctl->irqmux_map & BIT(hwirq)) { 473 dev_err(pctl->dev, "irq line %ld already requested.\n", hwirq); 474 ret = -EBUSY; 475 } else { 476 pctl->irqmux_map |= BIT(hwirq); 477 } 478 479 spin_unlock_irqrestore(&pctl->irqmux_lock, flags); 480 if (ret) 481 return ret; 482 483 parent_fwspec.fwnode = d->parent->fwnode; 484 parent_fwspec.param_count = 2; 485 parent_fwspec.param[0] = fwspec->param[0]; 486 parent_fwspec.param[1] = fwspec->param[1]; 487 488 irq_domain_set_hwirq_and_chip(d, virq, hwirq, &stm32_gpio_irq_chip, 489 bank); 490 491 return irq_domain_alloc_irqs_parent(d, virq, nr_irqs, &parent_fwspec); 492 } 493 494 static void stm32_gpio_domain_free(struct irq_domain *d, unsigned int virq, 495 unsigned int nr_irqs) 496 { 497 struct stm32_gpio_bank *bank = d->host_data; 498 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 499 struct irq_data *irq_data = irq_domain_get_irq_data(d, virq); 500 unsigned long flags, hwirq = irq_data->hwirq; 501 502 irq_domain_free_irqs_common(d, virq, nr_irqs); 503 504 spin_lock_irqsave(&pctl->irqmux_lock, flags); 505 pctl->irqmux_map &= ~BIT(hwirq); 506 spin_unlock_irqrestore(&pctl->irqmux_lock, flags); 507 } 508 509 static const struct irq_domain_ops stm32_gpio_domain_ops = { 510 .translate = stm32_gpio_domain_translate, 511 .alloc = stm32_gpio_domain_alloc, 512 .free = stm32_gpio_domain_free, 513 .activate = stm32_gpio_domain_activate, 514 }; 515 516 /* Pinctrl functions */ 517 static struct stm32_pinctrl_group * 518 stm32_pctrl_find_group_by_pin(struct stm32_pinctrl *pctl, u32 pin) 519 { 520 int i; 521 522 for (i = 0; i < pctl->ngroups; i++) { 523 struct stm32_pinctrl_group *grp = pctl->groups + i; 524 525 if (grp->pin == pin) 526 return grp; 527 } 528 529 return NULL; 530 } 531 532 static bool stm32_pctrl_is_function_valid(struct stm32_pinctrl *pctl, 533 u32 pin_num, u32 fnum) 534 { 535 int i, k; 536 537 for (i = 0; i < pctl->npins; i++) { 538 const struct stm32_desc_pin *pin = pctl->pins + i; 539 const struct stm32_desc_function *func = pin->functions; 540 541 if (pin->pin.number != pin_num) 542 continue; 543 544 for (k = 0; k < STM32_CONFIG_NUM; k++) { 545 if (func->num == fnum) 546 return true; 547 func++; 548 } 549 550 break; 551 } 552 553 dev_err(pctl->dev, "invalid function %d on pin %d .\n", fnum, pin_num); 554 555 return false; 556 } 557 558 static int stm32_pctrl_dt_node_to_map_func(struct stm32_pinctrl *pctl, 559 u32 pin, u32 fnum, struct stm32_pinctrl_group *grp, 560 struct pinctrl_map **map, unsigned *reserved_maps, 561 unsigned *num_maps) 562 { 563 if (*num_maps == *reserved_maps) 564 return -ENOSPC; 565 566 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; 567 (*map)[*num_maps].data.mux.group = grp->name; 568 569 if (!stm32_pctrl_is_function_valid(pctl, pin, fnum)) 570 return -EINVAL; 571 572 (*map)[*num_maps].data.mux.function = stm32_gpio_functions[fnum]; 573 (*num_maps)++; 574 575 return 0; 576 } 577 578 static int stm32_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, 579 struct device_node *node, 580 struct pinctrl_map **map, 581 unsigned *reserved_maps, 582 unsigned *num_maps) 583 { 584 struct stm32_pinctrl *pctl; 585 struct stm32_pinctrl_group *grp; 586 struct property *pins; 587 u32 pinfunc, pin, func; 588 unsigned long *configs; 589 unsigned int num_configs; 590 bool has_config = 0; 591 unsigned reserve = 0; 592 int num_pins, num_funcs, maps_per_pin, i, err = 0; 593 594 pctl = pinctrl_dev_get_drvdata(pctldev); 595 596 pins = of_find_property(node, "pinmux", NULL); 597 if (!pins) { 598 dev_err(pctl->dev, "missing pins property in node %pOFn .\n", 599 node); 600 return -EINVAL; 601 } 602 603 err = pinconf_generic_parse_dt_config(node, pctldev, &configs, 604 &num_configs); 605 if (err) 606 return err; 607 608 if (num_configs) 609 has_config = 1; 610 611 num_pins = pins->length / sizeof(u32); 612 num_funcs = num_pins; 613 maps_per_pin = 0; 614 if (num_funcs) 615 maps_per_pin++; 616 if (has_config && num_pins >= 1) 617 maps_per_pin++; 618 619 if (!num_pins || !maps_per_pin) { 620 err = -EINVAL; 621 goto exit; 622 } 623 624 reserve = num_pins * maps_per_pin; 625 626 err = pinctrl_utils_reserve_map(pctldev, map, 627 reserved_maps, num_maps, reserve); 628 if (err) 629 goto exit; 630 631 for (i = 0; i < num_pins; i++) { 632 err = of_property_read_u32_index(node, "pinmux", 633 i, &pinfunc); 634 if (err) 635 goto exit; 636 637 pin = STM32_GET_PIN_NO(pinfunc); 638 func = STM32_GET_PIN_FUNC(pinfunc); 639 640 if (!stm32_pctrl_is_function_valid(pctl, pin, func)) { 641 err = -EINVAL; 642 goto exit; 643 } 644 645 grp = stm32_pctrl_find_group_by_pin(pctl, pin); 646 if (!grp) { 647 dev_err(pctl->dev, "unable to match pin %d to group\n", 648 pin); 649 err = -EINVAL; 650 goto exit; 651 } 652 653 err = stm32_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map, 654 reserved_maps, num_maps); 655 if (err) 656 goto exit; 657 658 if (has_config) { 659 err = pinctrl_utils_add_map_configs(pctldev, map, 660 reserved_maps, num_maps, grp->name, 661 configs, num_configs, 662 PIN_MAP_TYPE_CONFIGS_GROUP); 663 if (err) 664 goto exit; 665 } 666 } 667 668 exit: 669 kfree(configs); 670 return err; 671 } 672 673 static int stm32_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev, 674 struct device_node *np_config, 675 struct pinctrl_map **map, unsigned *num_maps) 676 { 677 unsigned reserved_maps; 678 int ret; 679 680 *map = NULL; 681 *num_maps = 0; 682 reserved_maps = 0; 683 684 for_each_child_of_node_scoped(np_config, np) { 685 ret = stm32_pctrl_dt_subnode_to_map(pctldev, np, map, 686 &reserved_maps, num_maps); 687 if (ret < 0) { 688 pinctrl_utils_free_map(pctldev, *map, *num_maps); 689 return ret; 690 } 691 } 692 693 return 0; 694 } 695 696 static int stm32_pctrl_get_groups_count(struct pinctrl_dev *pctldev) 697 { 698 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 699 700 return pctl->ngroups; 701 } 702 703 static const char *stm32_pctrl_get_group_name(struct pinctrl_dev *pctldev, 704 unsigned group) 705 { 706 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 707 708 return pctl->groups[group].name; 709 } 710 711 static int stm32_pctrl_get_group_pins(struct pinctrl_dev *pctldev, 712 unsigned group, 713 const unsigned **pins, 714 unsigned *num_pins) 715 { 716 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 717 718 *pins = (unsigned *)&pctl->groups[group].pin; 719 *num_pins = 1; 720 721 return 0; 722 } 723 724 static const struct pinctrl_ops stm32_pctrl_ops = { 725 .dt_node_to_map = stm32_pctrl_dt_node_to_map, 726 .dt_free_map = pinctrl_utils_free_map, 727 .get_groups_count = stm32_pctrl_get_groups_count, 728 .get_group_name = stm32_pctrl_get_group_name, 729 .get_group_pins = stm32_pctrl_get_group_pins, 730 }; 731 732 733 /* Pinmux functions */ 734 735 static int stm32_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) 736 { 737 return ARRAY_SIZE(stm32_gpio_functions); 738 } 739 740 static const char *stm32_pmx_get_func_name(struct pinctrl_dev *pctldev, 741 unsigned selector) 742 { 743 return stm32_gpio_functions[selector]; 744 } 745 746 static int stm32_pmx_get_func_groups(struct pinctrl_dev *pctldev, 747 unsigned function, 748 const char * const **groups, 749 unsigned * const num_groups) 750 { 751 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 752 753 *groups = pctl->grp_names; 754 *num_groups = pctl->ngroups; 755 756 return 0; 757 } 758 759 static int stm32_pmx_set_mode(struct stm32_gpio_bank *bank, 760 int pin, u32 mode, u32 alt) 761 { 762 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 763 u32 val; 764 int alt_shift = (pin % 8) * 4; 765 int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4; 766 unsigned long flags; 767 int err = 0; 768 769 spin_lock_irqsave(&bank->lock, flags); 770 771 if (pctl->hwlock) { 772 err = hwspin_lock_timeout_in_atomic(pctl->hwlock, 773 HWSPNLCK_TIMEOUT); 774 if (err) { 775 dev_err(pctl->dev, "Can't get hwspinlock\n"); 776 goto unlock; 777 } 778 } 779 780 val = readl_relaxed(bank->base + alt_offset); 781 val &= ~GENMASK(alt_shift + 3, alt_shift); 782 val |= (alt << alt_shift); 783 writel_relaxed(val, bank->base + alt_offset); 784 785 val = readl_relaxed(bank->base + STM32_GPIO_MODER); 786 val &= ~GENMASK(pin * 2 + 1, pin * 2); 787 val |= mode << (pin * 2); 788 writel_relaxed(val, bank->base + STM32_GPIO_MODER); 789 790 if (pctl->hwlock) 791 hwspin_unlock_in_atomic(pctl->hwlock); 792 793 stm32_gpio_backup_mode(bank, pin, mode, alt); 794 795 unlock: 796 spin_unlock_irqrestore(&bank->lock, flags); 797 798 return err; 799 } 800 801 void stm32_pmx_get_mode(struct stm32_gpio_bank *bank, int pin, u32 *mode, 802 u32 *alt) 803 { 804 u32 val; 805 int alt_shift = (pin % 8) * 4; 806 int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4; 807 unsigned long flags; 808 809 spin_lock_irqsave(&bank->lock, flags); 810 811 val = readl_relaxed(bank->base + alt_offset); 812 val &= GENMASK(alt_shift + 3, alt_shift); 813 *alt = val >> alt_shift; 814 815 val = readl_relaxed(bank->base + STM32_GPIO_MODER); 816 val &= GENMASK(pin * 2 + 1, pin * 2); 817 *mode = val >> (pin * 2); 818 819 spin_unlock_irqrestore(&bank->lock, flags); 820 } 821 822 static int stm32_pmx_set_mux(struct pinctrl_dev *pctldev, 823 unsigned function, 824 unsigned group) 825 { 826 bool ret; 827 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 828 struct stm32_pinctrl_group *g = pctl->groups + group; 829 struct pinctrl_gpio_range *range; 830 struct stm32_gpio_bank *bank; 831 u32 mode, alt; 832 int pin; 833 834 ret = stm32_pctrl_is_function_valid(pctl, g->pin, function); 835 if (!ret) 836 return -EINVAL; 837 838 range = pinctrl_find_gpio_range_from_pin(pctldev, g->pin); 839 if (!range) { 840 dev_err(pctl->dev, "No gpio range defined.\n"); 841 return -EINVAL; 842 } 843 844 bank = gpiochip_get_data(range->gc); 845 pin = stm32_gpio_pin(g->pin); 846 847 mode = stm32_gpio_get_mode(function); 848 alt = stm32_gpio_get_alt(function); 849 850 return stm32_pmx_set_mode(bank, pin, mode, alt); 851 } 852 853 static int stm32_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, 854 struct pinctrl_gpio_range *range, unsigned gpio, 855 bool input) 856 { 857 struct stm32_gpio_bank *bank = gpiochip_get_data(range->gc); 858 int pin = stm32_gpio_pin(gpio); 859 860 return stm32_pmx_set_mode(bank, pin, !input, 0); 861 } 862 863 static int stm32_pmx_request(struct pinctrl_dev *pctldev, unsigned int gpio) 864 { 865 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 866 struct pinctrl_gpio_range *range; 867 868 range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, gpio); 869 if (!range) { 870 dev_err(pctl->dev, "No gpio range defined.\n"); 871 return -EINVAL; 872 } 873 874 if (!gpiochip_line_is_valid(range->gc, stm32_gpio_pin(gpio))) { 875 dev_warn(pctl->dev, "Can't access gpio %d\n", gpio); 876 return -EACCES; 877 } 878 879 return 0; 880 } 881 882 static const struct pinmux_ops stm32_pmx_ops = { 883 .get_functions_count = stm32_pmx_get_funcs_cnt, 884 .get_function_name = stm32_pmx_get_func_name, 885 .get_function_groups = stm32_pmx_get_func_groups, 886 .set_mux = stm32_pmx_set_mux, 887 .gpio_set_direction = stm32_pmx_gpio_set_direction, 888 .request = stm32_pmx_request, 889 .strict = true, 890 }; 891 892 /* Pinconf functions */ 893 894 static int stm32_pconf_set_driving(struct stm32_gpio_bank *bank, 895 unsigned offset, u32 drive) 896 { 897 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 898 unsigned long flags; 899 u32 val; 900 int err = 0; 901 902 spin_lock_irqsave(&bank->lock, flags); 903 904 if (pctl->hwlock) { 905 err = hwspin_lock_timeout_in_atomic(pctl->hwlock, 906 HWSPNLCK_TIMEOUT); 907 if (err) { 908 dev_err(pctl->dev, "Can't get hwspinlock\n"); 909 goto unlock; 910 } 911 } 912 913 val = readl_relaxed(bank->base + STM32_GPIO_TYPER); 914 val &= ~BIT(offset); 915 val |= drive << offset; 916 writel_relaxed(val, bank->base + STM32_GPIO_TYPER); 917 918 if (pctl->hwlock) 919 hwspin_unlock_in_atomic(pctl->hwlock); 920 921 stm32_gpio_backup_driving(bank, offset, drive); 922 923 unlock: 924 spin_unlock_irqrestore(&bank->lock, flags); 925 926 return err; 927 } 928 929 static u32 stm32_pconf_get_driving(struct stm32_gpio_bank *bank, 930 unsigned int offset) 931 { 932 unsigned long flags; 933 u32 val; 934 935 spin_lock_irqsave(&bank->lock, flags); 936 937 val = readl_relaxed(bank->base + STM32_GPIO_TYPER); 938 val &= BIT(offset); 939 940 spin_unlock_irqrestore(&bank->lock, flags); 941 942 return (val >> offset); 943 } 944 945 static int stm32_pconf_set_speed(struct stm32_gpio_bank *bank, 946 unsigned offset, u32 speed) 947 { 948 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 949 unsigned long flags; 950 u32 val; 951 int err = 0; 952 953 spin_lock_irqsave(&bank->lock, flags); 954 955 if (pctl->hwlock) { 956 err = hwspin_lock_timeout_in_atomic(pctl->hwlock, 957 HWSPNLCK_TIMEOUT); 958 if (err) { 959 dev_err(pctl->dev, "Can't get hwspinlock\n"); 960 goto unlock; 961 } 962 } 963 964 val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR); 965 val &= ~GENMASK(offset * 2 + 1, offset * 2); 966 val |= speed << (offset * 2); 967 writel_relaxed(val, bank->base + STM32_GPIO_SPEEDR); 968 969 if (pctl->hwlock) 970 hwspin_unlock_in_atomic(pctl->hwlock); 971 972 stm32_gpio_backup_speed(bank, offset, speed); 973 974 unlock: 975 spin_unlock_irqrestore(&bank->lock, flags); 976 977 return err; 978 } 979 980 static u32 stm32_pconf_get_speed(struct stm32_gpio_bank *bank, 981 unsigned int offset) 982 { 983 unsigned long flags; 984 u32 val; 985 986 spin_lock_irqsave(&bank->lock, flags); 987 988 val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR); 989 val &= GENMASK(offset * 2 + 1, offset * 2); 990 991 spin_unlock_irqrestore(&bank->lock, flags); 992 993 return (val >> (offset * 2)); 994 } 995 996 static int stm32_pconf_set_bias(struct stm32_gpio_bank *bank, 997 unsigned offset, u32 bias) 998 { 999 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 1000 unsigned long flags; 1001 u32 val; 1002 int err = 0; 1003 1004 spin_lock_irqsave(&bank->lock, flags); 1005 1006 if (pctl->hwlock) { 1007 err = hwspin_lock_timeout_in_atomic(pctl->hwlock, 1008 HWSPNLCK_TIMEOUT); 1009 if (err) { 1010 dev_err(pctl->dev, "Can't get hwspinlock\n"); 1011 goto unlock; 1012 } 1013 } 1014 1015 val = readl_relaxed(bank->base + STM32_GPIO_PUPDR); 1016 val &= ~GENMASK(offset * 2 + 1, offset * 2); 1017 val |= bias << (offset * 2); 1018 writel_relaxed(val, bank->base + STM32_GPIO_PUPDR); 1019 1020 if (pctl->hwlock) 1021 hwspin_unlock_in_atomic(pctl->hwlock); 1022 1023 stm32_gpio_backup_bias(bank, offset, bias); 1024 1025 unlock: 1026 spin_unlock_irqrestore(&bank->lock, flags); 1027 1028 return err; 1029 } 1030 1031 static u32 stm32_pconf_get_bias(struct stm32_gpio_bank *bank, 1032 unsigned int offset) 1033 { 1034 unsigned long flags; 1035 u32 val; 1036 1037 spin_lock_irqsave(&bank->lock, flags); 1038 1039 val = readl_relaxed(bank->base + STM32_GPIO_PUPDR); 1040 val &= GENMASK(offset * 2 + 1, offset * 2); 1041 1042 spin_unlock_irqrestore(&bank->lock, flags); 1043 1044 return (val >> (offset * 2)); 1045 } 1046 1047 static bool stm32_pconf_get(struct stm32_gpio_bank *bank, 1048 unsigned int offset, bool dir) 1049 { 1050 unsigned long flags; 1051 u32 val; 1052 1053 spin_lock_irqsave(&bank->lock, flags); 1054 1055 if (dir) 1056 val = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & 1057 BIT(offset)); 1058 else 1059 val = !!(readl_relaxed(bank->base + STM32_GPIO_ODR) & 1060 BIT(offset)); 1061 1062 spin_unlock_irqrestore(&bank->lock, flags); 1063 1064 return val; 1065 } 1066 1067 static int stm32_pconf_parse_conf(struct pinctrl_dev *pctldev, 1068 unsigned int pin, enum pin_config_param param, 1069 enum pin_config_param arg) 1070 { 1071 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 1072 struct pinctrl_gpio_range *range; 1073 struct stm32_gpio_bank *bank; 1074 int offset, ret = 0; 1075 1076 range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin); 1077 if (!range) { 1078 dev_err(pctl->dev, "No gpio range defined.\n"); 1079 return -EINVAL; 1080 } 1081 1082 bank = gpiochip_get_data(range->gc); 1083 offset = stm32_gpio_pin(pin); 1084 1085 if (!gpiochip_line_is_valid(range->gc, offset)) { 1086 dev_warn(pctl->dev, "Can't access gpio %d\n", pin); 1087 return -EACCES; 1088 } 1089 1090 switch (param) { 1091 case PIN_CONFIG_DRIVE_PUSH_PULL: 1092 ret = stm32_pconf_set_driving(bank, offset, 0); 1093 break; 1094 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 1095 ret = stm32_pconf_set_driving(bank, offset, 1); 1096 break; 1097 case PIN_CONFIG_SLEW_RATE: 1098 ret = stm32_pconf_set_speed(bank, offset, arg); 1099 break; 1100 case PIN_CONFIG_BIAS_DISABLE: 1101 ret = stm32_pconf_set_bias(bank, offset, 0); 1102 break; 1103 case PIN_CONFIG_BIAS_PULL_UP: 1104 ret = stm32_pconf_set_bias(bank, offset, 1); 1105 break; 1106 case PIN_CONFIG_BIAS_PULL_DOWN: 1107 ret = stm32_pconf_set_bias(bank, offset, 2); 1108 break; 1109 case PIN_CONFIG_OUTPUT: 1110 __stm32_gpio_set(bank, offset, arg); 1111 ret = stm32_pmx_gpio_set_direction(pctldev, range, pin, false); 1112 break; 1113 default: 1114 ret = -ENOTSUPP; 1115 } 1116 1117 return ret; 1118 } 1119 1120 static int stm32_pconf_group_get(struct pinctrl_dev *pctldev, 1121 unsigned group, 1122 unsigned long *config) 1123 { 1124 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 1125 1126 *config = pctl->groups[group].config; 1127 1128 return 0; 1129 } 1130 1131 static int stm32_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group, 1132 unsigned long *configs, unsigned num_configs) 1133 { 1134 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 1135 struct stm32_pinctrl_group *g = &pctl->groups[group]; 1136 int i, ret; 1137 1138 for (i = 0; i < num_configs; i++) { 1139 mutex_lock(&pctldev->mutex); 1140 ret = stm32_pconf_parse_conf(pctldev, g->pin, 1141 pinconf_to_config_param(configs[i]), 1142 pinconf_to_config_argument(configs[i])); 1143 mutex_unlock(&pctldev->mutex); 1144 if (ret < 0) 1145 return ret; 1146 1147 g->config = configs[i]; 1148 } 1149 1150 return 0; 1151 } 1152 1153 static int stm32_pconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 1154 unsigned long *configs, unsigned int num_configs) 1155 { 1156 int i, ret; 1157 1158 for (i = 0; i < num_configs; i++) { 1159 ret = stm32_pconf_parse_conf(pctldev, pin, 1160 pinconf_to_config_param(configs[i]), 1161 pinconf_to_config_argument(configs[i])); 1162 if (ret < 0) 1163 return ret; 1164 } 1165 1166 return 0; 1167 } 1168 1169 static struct stm32_desc_pin * 1170 stm32_pconf_get_pin_desc_by_pin_number(struct stm32_pinctrl *pctl, 1171 unsigned int pin_number) 1172 { 1173 struct stm32_desc_pin *pins = pctl->pins; 1174 int i; 1175 1176 for (i = 0; i < pctl->npins; i++) { 1177 if (pins->pin.number == pin_number) 1178 return pins; 1179 pins++; 1180 } 1181 return NULL; 1182 } 1183 1184 static void stm32_pconf_dbg_show(struct pinctrl_dev *pctldev, 1185 struct seq_file *s, 1186 unsigned int pin) 1187 { 1188 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 1189 const struct stm32_desc_pin *pin_desc; 1190 struct pinctrl_gpio_range *range; 1191 struct stm32_gpio_bank *bank; 1192 int offset; 1193 u32 mode, alt, drive, speed, bias; 1194 static const char * const modes[] = { 1195 "input", "output", "alternate", "analog" }; 1196 static const char * const speeds[] = { 1197 "low", "medium", "high", "very high" }; 1198 static const char * const biasing[] = { 1199 "floating", "pull up", "pull down", "" }; 1200 bool val; 1201 1202 range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin); 1203 if (!range) 1204 return; 1205 1206 bank = gpiochip_get_data(range->gc); 1207 offset = stm32_gpio_pin(pin); 1208 1209 if (!gpiochip_line_is_valid(range->gc, offset)) { 1210 seq_puts(s, "NO ACCESS"); 1211 return; 1212 } 1213 1214 stm32_pmx_get_mode(bank, offset, &mode, &alt); 1215 bias = stm32_pconf_get_bias(bank, offset); 1216 1217 seq_printf(s, "%s ", modes[mode]); 1218 1219 switch (mode) { 1220 /* input */ 1221 case 0: 1222 val = stm32_pconf_get(bank, offset, true); 1223 seq_printf(s, "- %s - %s", 1224 str_high_low(val), 1225 biasing[bias]); 1226 break; 1227 1228 /* output */ 1229 case 1: 1230 drive = stm32_pconf_get_driving(bank, offset); 1231 speed = stm32_pconf_get_speed(bank, offset); 1232 val = stm32_pconf_get(bank, offset, false); 1233 seq_printf(s, "- %s - %s - %s - %s %s", 1234 str_high_low(val), 1235 drive ? "open drain" : "push pull", 1236 biasing[bias], 1237 speeds[speed], "speed"); 1238 break; 1239 1240 /* alternate */ 1241 case 2: 1242 drive = stm32_pconf_get_driving(bank, offset); 1243 speed = stm32_pconf_get_speed(bank, offset); 1244 pin_desc = stm32_pconf_get_pin_desc_by_pin_number(pctl, pin); 1245 if (!pin_desc) 1246 return; 1247 1248 seq_printf(s, "%d (%s) - %s - %s - %s %s", alt, 1249 pin_desc->functions[alt + 1].name, 1250 drive ? "open drain" : "push pull", 1251 biasing[bias], 1252 speeds[speed], "speed"); 1253 break; 1254 1255 /* analog */ 1256 case 3: 1257 break; 1258 } 1259 } 1260 1261 static const struct pinconf_ops stm32_pconf_ops = { 1262 .pin_config_group_get = stm32_pconf_group_get, 1263 .pin_config_group_set = stm32_pconf_group_set, 1264 .pin_config_set = stm32_pconf_set, 1265 .pin_config_dbg_show = stm32_pconf_dbg_show, 1266 }; 1267 1268 static struct stm32_desc_pin *stm32_pctrl_get_desc_pin_from_gpio(struct stm32_pinctrl *pctl, 1269 struct stm32_gpio_bank *bank, 1270 unsigned int offset) 1271 { 1272 unsigned int stm32_pin_nb = bank->bank_nr * STM32_GPIO_PINS_PER_BANK + offset; 1273 struct stm32_desc_pin *pin_desc; 1274 int i; 1275 1276 /* With few exceptions (e.g. bank 'Z'), pin number matches with pin index in array */ 1277 if (stm32_pin_nb < pctl->npins) { 1278 pin_desc = pctl->pins + stm32_pin_nb; 1279 if (pin_desc->pin.number == stm32_pin_nb) 1280 return pin_desc; 1281 } 1282 1283 /* Otherwise, loop all array to find the pin with the right number */ 1284 for (i = 0; i < pctl->npins; i++) { 1285 pin_desc = pctl->pins + i; 1286 if (pin_desc->pin.number == stm32_pin_nb) 1287 return pin_desc; 1288 } 1289 return NULL; 1290 } 1291 1292 static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl, struct fwnode_handle *fwnode) 1293 { 1294 struct stm32_gpio_bank *bank = &pctl->banks[pctl->nbanks]; 1295 int bank_ioport_nr; 1296 struct pinctrl_gpio_range *range = &bank->range; 1297 struct fwnode_reference_args args; 1298 struct device *dev = pctl->dev; 1299 struct resource res; 1300 int npins = STM32_GPIO_PINS_PER_BANK; 1301 int bank_nr, err, i = 0; 1302 struct stm32_desc_pin *stm32_pin; 1303 char **names; 1304 1305 if (!IS_ERR(bank->rstc)) 1306 reset_control_deassert(bank->rstc); 1307 1308 if (of_address_to_resource(to_of_node(fwnode), 0, &res)) 1309 return -ENODEV; 1310 1311 bank->base = devm_ioremap_resource(dev, &res); 1312 if (IS_ERR(bank->base)) 1313 return PTR_ERR(bank->base); 1314 1315 bank->gpio_chip = stm32_gpio_template; 1316 1317 fwnode_property_read_string(fwnode, "st,bank-name", &bank->gpio_chip.label); 1318 1319 if (!fwnode_property_get_reference_args(fwnode, "gpio-ranges", NULL, 3, i, &args)) { 1320 bank_nr = args.args[1] / STM32_GPIO_PINS_PER_BANK; 1321 bank->gpio_chip.base = args.args[1]; 1322 1323 /* get the last defined gpio line (offset + nb of pins) */ 1324 npins = args.args[0] + args.args[2]; 1325 while (!fwnode_property_get_reference_args(fwnode, "gpio-ranges", NULL, 3, ++i, &args)) 1326 npins = max(npins, (int)(args.args[0] + args.args[2])); 1327 } else { 1328 bank_nr = pctl->nbanks; 1329 bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK; 1330 range->name = bank->gpio_chip.label; 1331 range->id = bank_nr; 1332 range->pin_base = range->id * STM32_GPIO_PINS_PER_BANK; 1333 range->base = range->id * STM32_GPIO_PINS_PER_BANK; 1334 range->npins = npins; 1335 range->gc = &bank->gpio_chip; 1336 pinctrl_add_gpio_range(pctl->pctl_dev, 1337 &pctl->banks[bank_nr].range); 1338 } 1339 1340 if (fwnode_property_read_u32(fwnode, "st,bank-ioport", &bank_ioport_nr)) 1341 bank_ioport_nr = bank_nr; 1342 1343 bank->gpio_chip.base = -1; 1344 1345 bank->gpio_chip.ngpio = npins; 1346 bank->gpio_chip.fwnode = fwnode; 1347 bank->gpio_chip.parent = dev; 1348 bank->bank_nr = bank_nr; 1349 bank->bank_ioport_nr = bank_ioport_nr; 1350 bank->secure_control = pctl->match_data->secure_control; 1351 spin_lock_init(&bank->lock); 1352 1353 if (pctl->domain) { 1354 /* create irq hierarchical domain */ 1355 bank->fwnode = fwnode; 1356 1357 bank->domain = irq_domain_create_hierarchy(pctl->domain, 0, STM32_GPIO_IRQ_LINE, 1358 bank->fwnode, &stm32_gpio_domain_ops, 1359 bank); 1360 1361 if (!bank->domain) 1362 return -ENODEV; 1363 } 1364 1365 names = devm_kcalloc(dev, npins, sizeof(char *), GFP_KERNEL); 1366 if (!names) 1367 return -ENOMEM; 1368 1369 for (i = 0; i < npins; i++) { 1370 stm32_pin = stm32_pctrl_get_desc_pin_from_gpio(pctl, bank, i); 1371 if (stm32_pin && stm32_pin->pin.name) { 1372 names[i] = devm_kasprintf(dev, GFP_KERNEL, "%s", stm32_pin->pin.name); 1373 if (!names[i]) 1374 return -ENOMEM; 1375 } else { 1376 names[i] = NULL; 1377 } 1378 } 1379 1380 bank->gpio_chip.names = (const char * const *)names; 1381 1382 err = gpiochip_add_data(&bank->gpio_chip, bank); 1383 if (err) { 1384 dev_err(dev, "Failed to add gpiochip(%d)!\n", bank_nr); 1385 return err; 1386 } 1387 1388 dev_info(dev, "%s bank added\n", bank->gpio_chip.label); 1389 return 0; 1390 } 1391 1392 static struct irq_domain *stm32_pctrl_get_irq_domain(struct platform_device *pdev) 1393 { 1394 struct device_node *np = pdev->dev.of_node; 1395 struct device_node *parent; 1396 struct irq_domain *domain; 1397 1398 if (!of_property_present(np, "interrupt-parent")) 1399 return NULL; 1400 1401 parent = of_irq_find_parent(np); 1402 if (!parent) 1403 return ERR_PTR(-ENXIO); 1404 1405 domain = irq_find_host(parent); 1406 of_node_put(parent); 1407 if (!domain) 1408 /* domain not registered yet */ 1409 return ERR_PTR(-EPROBE_DEFER); 1410 1411 return domain; 1412 } 1413 1414 static int stm32_pctrl_dt_setup_irq(struct platform_device *pdev, 1415 struct stm32_pinctrl *pctl) 1416 { 1417 struct device_node *np = pdev->dev.of_node; 1418 struct device *dev = &pdev->dev; 1419 struct regmap *rm; 1420 int offset, ret, i; 1421 int mask, mask_width; 1422 1423 pctl->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg"); 1424 if (IS_ERR(pctl->regmap)) 1425 return PTR_ERR(pctl->regmap); 1426 1427 rm = pctl->regmap; 1428 1429 ret = of_property_read_u32_index(np, "st,syscfg", 1, &offset); 1430 if (ret) 1431 return ret; 1432 1433 ret = of_property_read_u32_index(np, "st,syscfg", 2, &mask); 1434 if (ret) 1435 mask = SYSCFG_IRQMUX_MASK; 1436 1437 mask_width = fls(mask); 1438 1439 for (i = 0; i < STM32_GPIO_PINS_PER_BANK; i++) { 1440 struct reg_field mux; 1441 1442 mux.reg = offset + (i / 4) * 4; 1443 mux.lsb = (i % 4) * mask_width; 1444 mux.msb = mux.lsb + mask_width - 1; 1445 1446 dev_dbg(dev, "irqmux%d: reg:%#x, lsb:%d, msb:%d\n", 1447 i, mux.reg, mux.lsb, mux.msb); 1448 1449 pctl->irqmux[i] = devm_regmap_field_alloc(dev, rm, mux); 1450 if (IS_ERR(pctl->irqmux[i])) 1451 return PTR_ERR(pctl->irqmux[i]); 1452 } 1453 1454 return 0; 1455 } 1456 1457 static int stm32_pctrl_build_state(struct platform_device *pdev) 1458 { 1459 struct stm32_pinctrl *pctl = platform_get_drvdata(pdev); 1460 int i; 1461 1462 pctl->ngroups = pctl->npins; 1463 1464 /* Allocate groups */ 1465 pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups, 1466 sizeof(*pctl->groups), GFP_KERNEL); 1467 if (!pctl->groups) 1468 return -ENOMEM; 1469 1470 /* We assume that one pin is one group, use pin name as group name. */ 1471 pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups, 1472 sizeof(*pctl->grp_names), GFP_KERNEL); 1473 if (!pctl->grp_names) 1474 return -ENOMEM; 1475 1476 for (i = 0; i < pctl->npins; i++) { 1477 const struct stm32_desc_pin *pin = pctl->pins + i; 1478 struct stm32_pinctrl_group *group = pctl->groups + i; 1479 1480 group->name = pin->pin.name; 1481 group->pin = pin->pin.number; 1482 pctl->grp_names[i] = pin->pin.name; 1483 } 1484 1485 return 0; 1486 } 1487 1488 static int stm32_pctrl_create_pins_tab(struct stm32_pinctrl *pctl, 1489 struct stm32_desc_pin *pins) 1490 { 1491 const struct stm32_desc_pin *p; 1492 int i, nb_pins_available = 0; 1493 1494 for (i = 0; i < pctl->match_data->npins; i++) { 1495 p = pctl->match_data->pins + i; 1496 if (pctl->pkg && !(pctl->pkg & p->pkg)) 1497 continue; 1498 pins->pin = p->pin; 1499 memcpy((struct stm32_desc_pin *)pins->functions, p->functions, 1500 STM32_CONFIG_NUM * sizeof(struct stm32_desc_function)); 1501 pins++; 1502 nb_pins_available++; 1503 } 1504 1505 pctl->npins = nb_pins_available; 1506 1507 return 0; 1508 } 1509 1510 int stm32_pctl_probe(struct platform_device *pdev) 1511 { 1512 const struct stm32_pinctrl_match_data *match_data; 1513 struct fwnode_handle *child; 1514 struct device *dev = &pdev->dev; 1515 struct stm32_pinctrl *pctl; 1516 struct pinctrl_pin_desc *pins; 1517 int i, ret, hwlock_id; 1518 unsigned int banks; 1519 1520 match_data = device_get_match_data(dev); 1521 if (!match_data) 1522 return -EINVAL; 1523 1524 pctl = devm_kzalloc(dev, sizeof(*pctl), GFP_KERNEL); 1525 if (!pctl) 1526 return -ENOMEM; 1527 1528 platform_set_drvdata(pdev, pctl); 1529 1530 /* check for IRQ controller (may require deferred probe) */ 1531 pctl->domain = stm32_pctrl_get_irq_domain(pdev); 1532 if (IS_ERR(pctl->domain)) 1533 return PTR_ERR(pctl->domain); 1534 if (!pctl->domain) 1535 dev_warn(dev, "pinctrl without interrupt support\n"); 1536 1537 /* hwspinlock is optional */ 1538 hwlock_id = of_hwspin_lock_get_id(pdev->dev.of_node, 0); 1539 if (hwlock_id < 0) { 1540 if (hwlock_id == -EPROBE_DEFER) 1541 return hwlock_id; 1542 } else { 1543 pctl->hwlock = hwspin_lock_request_specific(hwlock_id); 1544 } 1545 1546 spin_lock_init(&pctl->irqmux_lock); 1547 1548 pctl->dev = dev; 1549 pctl->match_data = match_data; 1550 1551 /* get optional package information */ 1552 if (!device_property_read_u32(dev, "st,package", &pctl->pkg)) 1553 dev_dbg(pctl->dev, "package detected: %x\n", pctl->pkg); 1554 1555 pctl->pins = devm_kcalloc(pctl->dev, pctl->match_data->npins, 1556 sizeof(*pctl->pins), GFP_KERNEL); 1557 if (!pctl->pins) 1558 return -ENOMEM; 1559 1560 ret = stm32_pctrl_create_pins_tab(pctl, pctl->pins); 1561 if (ret) 1562 return ret; 1563 1564 ret = stm32_pctrl_build_state(pdev); 1565 if (ret) { 1566 dev_err(dev, "build state failed: %d\n", ret); 1567 return -EINVAL; 1568 } 1569 1570 if (pctl->domain) { 1571 ret = stm32_pctrl_dt_setup_irq(pdev, pctl); 1572 if (ret) 1573 return ret; 1574 } 1575 1576 pins = devm_kcalloc(&pdev->dev, pctl->npins, sizeof(*pins), 1577 GFP_KERNEL); 1578 if (!pins) 1579 return -ENOMEM; 1580 1581 for (i = 0; i < pctl->npins; i++) 1582 pins[i] = pctl->pins[i].pin; 1583 1584 pctl->pctl_desc.name = dev_name(&pdev->dev); 1585 pctl->pctl_desc.owner = THIS_MODULE; 1586 pctl->pctl_desc.pins = pins; 1587 pctl->pctl_desc.npins = pctl->npins; 1588 pctl->pctl_desc.link_consumers = true; 1589 pctl->pctl_desc.confops = &stm32_pconf_ops; 1590 pctl->pctl_desc.pctlops = &stm32_pctrl_ops; 1591 pctl->pctl_desc.pmxops = &stm32_pmx_ops; 1592 pctl->dev = &pdev->dev; 1593 1594 pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, &pctl->pctl_desc, 1595 pctl); 1596 1597 if (IS_ERR(pctl->pctl_dev)) { 1598 dev_err(&pdev->dev, "Failed pinctrl registration\n"); 1599 return PTR_ERR(pctl->pctl_dev); 1600 } 1601 1602 banks = gpiochip_node_count(dev); 1603 if (!banks) { 1604 dev_err(dev, "at least one GPIO bank is required\n"); 1605 return -EINVAL; 1606 } 1607 pctl->banks = devm_kcalloc(dev, banks, sizeof(*pctl->banks), 1608 GFP_KERNEL); 1609 if (!pctl->banks) 1610 return -ENOMEM; 1611 1612 pctl->clks = devm_kcalloc(dev, banks, sizeof(*pctl->clks), 1613 GFP_KERNEL); 1614 if (!pctl->clks) 1615 return -ENOMEM; 1616 1617 i = 0; 1618 for_each_gpiochip_node(dev, child) { 1619 struct stm32_gpio_bank *bank = &pctl->banks[i]; 1620 struct device_node *np = to_of_node(child); 1621 1622 bank->rstc = of_reset_control_get_exclusive(np, NULL); 1623 if (PTR_ERR(bank->rstc) == -EPROBE_DEFER) { 1624 fwnode_handle_put(child); 1625 return -EPROBE_DEFER; 1626 } 1627 1628 pctl->clks[i].clk = of_clk_get_by_name(np, NULL); 1629 if (IS_ERR(pctl->clks[i].clk)) { 1630 fwnode_handle_put(child); 1631 return dev_err_probe(dev, PTR_ERR(pctl->clks[i].clk), 1632 "failed to get clk\n"); 1633 } 1634 pctl->clks[i].id = "pctl"; 1635 i++; 1636 } 1637 1638 ret = clk_bulk_prepare_enable(banks, pctl->clks); 1639 if (ret) { 1640 dev_err(dev, "failed to prepare_enable clk (%d)\n", ret); 1641 return ret; 1642 } 1643 1644 for_each_gpiochip_node(dev, child) { 1645 ret = stm32_gpiolib_register_bank(pctl, child); 1646 if (ret) { 1647 fwnode_handle_put(child); 1648 goto err_register; 1649 } 1650 1651 pctl->nbanks++; 1652 } 1653 1654 dev_info(dev, "Pinctrl STM32 initialized\n"); 1655 1656 return 0; 1657 err_register: 1658 for (i = 0; i < pctl->nbanks; i++) { 1659 struct stm32_gpio_bank *bank = &pctl->banks[i]; 1660 1661 gpiochip_remove(&bank->gpio_chip); 1662 } 1663 1664 clk_bulk_disable_unprepare(banks, pctl->clks); 1665 return ret; 1666 } 1667 1668 static int __maybe_unused stm32_pinctrl_restore_gpio_regs( 1669 struct stm32_pinctrl *pctl, u32 pin) 1670 { 1671 const struct pin_desc *desc = pin_desc_get(pctl->pctl_dev, pin); 1672 u32 val, alt, mode, offset = stm32_gpio_pin(pin); 1673 struct pinctrl_gpio_range *range; 1674 struct stm32_gpio_bank *bank; 1675 bool pin_is_irq; 1676 int ret; 1677 1678 range = pinctrl_find_gpio_range_from_pin(pctl->pctl_dev, pin); 1679 if (!range) 1680 return 0; 1681 1682 if (!gpiochip_line_is_valid(range->gc, offset)) 1683 return 0; 1684 1685 pin_is_irq = gpiochip_line_is_irq(range->gc, offset); 1686 1687 if (!desc || (!pin_is_irq && !desc->gpio_owner)) 1688 return 0; 1689 1690 bank = gpiochip_get_data(range->gc); 1691 1692 alt = bank->pin_backup[offset] & STM32_GPIO_BKP_ALT_MASK; 1693 alt >>= STM32_GPIO_BKP_ALT_SHIFT; 1694 mode = bank->pin_backup[offset] & STM32_GPIO_BKP_MODE_MASK; 1695 mode >>= STM32_GPIO_BKP_MODE_SHIFT; 1696 1697 ret = stm32_pmx_set_mode(bank, offset, mode, alt); 1698 if (ret) 1699 return ret; 1700 1701 if (mode == 1) { 1702 val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_VAL); 1703 val = val >> STM32_GPIO_BKP_VAL; 1704 __stm32_gpio_set(bank, offset, val); 1705 } 1706 1707 val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_TYPE); 1708 val >>= STM32_GPIO_BKP_TYPE; 1709 ret = stm32_pconf_set_driving(bank, offset, val); 1710 if (ret) 1711 return ret; 1712 1713 val = bank->pin_backup[offset] & STM32_GPIO_BKP_SPEED_MASK; 1714 val >>= STM32_GPIO_BKP_SPEED_SHIFT; 1715 ret = stm32_pconf_set_speed(bank, offset, val); 1716 if (ret) 1717 return ret; 1718 1719 val = bank->pin_backup[offset] & STM32_GPIO_BKP_PUPD_MASK; 1720 val >>= STM32_GPIO_BKP_PUPD_SHIFT; 1721 ret = stm32_pconf_set_bias(bank, offset, val); 1722 if (ret) 1723 return ret; 1724 1725 if (pin_is_irq) 1726 regmap_field_write(pctl->irqmux[offset], bank->bank_ioport_nr); 1727 1728 return 0; 1729 } 1730 1731 int __maybe_unused stm32_pinctrl_suspend(struct device *dev) 1732 { 1733 struct stm32_pinctrl *pctl = dev_get_drvdata(dev); 1734 1735 clk_bulk_disable(pctl->nbanks, pctl->clks); 1736 1737 return 0; 1738 } 1739 1740 int __maybe_unused stm32_pinctrl_resume(struct device *dev) 1741 { 1742 struct stm32_pinctrl *pctl = dev_get_drvdata(dev); 1743 struct stm32_pinctrl_group *g = pctl->groups; 1744 int i, ret; 1745 1746 ret = clk_bulk_enable(pctl->nbanks, pctl->clks); 1747 if (ret) 1748 return ret; 1749 1750 for (i = 0; i < pctl->ngroups; i++, g++) 1751 stm32_pinctrl_restore_gpio_regs(pctl, g->pin); 1752 1753 return 0; 1754 } 1755