1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * GPIO driver for AMD 4 * 5 * Copyright (c) 2014,2015 AMD Corporation. 6 * Authors: Ken Xue <Ken.Xue@amd.com> 7 * Wu, Jeff <Jeff.Wu@amd.com> 8 * 9 */ 10 11 #include <linux/err.h> 12 #include <linux/bug.h> 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/spinlock.h> 16 #include <linux/compiler.h> 17 #include <linux/types.h> 18 #include <linux/errno.h> 19 #include <linux/log2.h> 20 #include <linux/io.h> 21 #include <linux/gpio/driver.h> 22 #include <linux/slab.h> 23 #include <linux/platform_device.h> 24 #include <linux/mutex.h> 25 #include <linux/acpi.h> 26 #include <linux/seq_file.h> 27 #include <linux/interrupt.h> 28 #include <linux/list.h> 29 #include <linux/bitops.h> 30 #include <linux/pinctrl/pinconf.h> 31 #include <linux/pinctrl/pinconf-generic.h> 32 #include <linux/pinctrl/pinmux.h> 33 #include <linux/string_choices.h> 34 #include <linux/suspend.h> 35 36 #include "core.h" 37 #include "pinctrl-utils.h" 38 #include "pinctrl-amd.h" 39 40 #ifdef CONFIG_SUSPEND 41 static struct amd_gpio *pinctrl_dev; 42 #endif 43 44 static int amd_gpio_get_direction(struct gpio_chip *gc, unsigned offset) 45 { 46 unsigned long flags; 47 u32 pin_reg; 48 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 49 50 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 51 pin_reg = readl(gpio_dev->base + offset * 4); 52 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 53 54 if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) 55 return GPIO_LINE_DIRECTION_OUT; 56 57 return GPIO_LINE_DIRECTION_IN; 58 } 59 60 static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset) 61 { 62 unsigned long flags; 63 u32 pin_reg; 64 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 65 66 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 67 pin_reg = readl(gpio_dev->base + offset * 4); 68 pin_reg &= ~BIT(OUTPUT_ENABLE_OFF); 69 writel(pin_reg, gpio_dev->base + offset * 4); 70 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 71 72 return 0; 73 } 74 75 static int amd_gpio_direction_output(struct gpio_chip *gc, unsigned offset, 76 int value) 77 { 78 u32 pin_reg; 79 unsigned long flags; 80 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 81 82 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 83 pin_reg = readl(gpio_dev->base + offset * 4); 84 pin_reg |= BIT(OUTPUT_ENABLE_OFF); 85 if (value) 86 pin_reg |= BIT(OUTPUT_VALUE_OFF); 87 else 88 pin_reg &= ~BIT(OUTPUT_VALUE_OFF); 89 writel(pin_reg, gpio_dev->base + offset * 4); 90 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 91 92 return 0; 93 } 94 95 static int amd_gpio_get_value(struct gpio_chip *gc, unsigned offset) 96 { 97 u32 pin_reg; 98 unsigned long flags; 99 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 100 101 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 102 pin_reg = readl(gpio_dev->base + offset * 4); 103 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 104 105 return !!(pin_reg & BIT(PIN_STS_OFF)); 106 } 107 108 static int amd_gpio_set_value(struct gpio_chip *gc, unsigned int offset, 109 int value) 110 { 111 u32 pin_reg; 112 unsigned long flags; 113 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 114 115 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 116 pin_reg = readl(gpio_dev->base + offset * 4); 117 if (value) 118 pin_reg |= BIT(OUTPUT_VALUE_OFF); 119 else 120 pin_reg &= ~BIT(OUTPUT_VALUE_OFF); 121 writel(pin_reg, gpio_dev->base + offset * 4); 122 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 123 124 return 0; 125 } 126 127 static int amd_gpio_set_debounce(struct amd_gpio *gpio_dev, unsigned int offset, 128 unsigned int debounce) 129 { 130 u32 time; 131 u32 pin_reg; 132 int ret = 0; 133 134 /* Use special handling for Pin0 debounce */ 135 if (offset == 0) { 136 pin_reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG); 137 if (pin_reg & INTERNAL_GPIO0_DEBOUNCE) 138 debounce = 0; 139 } 140 141 pin_reg = readl(gpio_dev->base + offset * 4); 142 143 if (debounce) { 144 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; 145 pin_reg &= ~DB_TMR_OUT_MASK; 146 /* 147 Debounce Debounce Timer Max 148 TmrLarge TmrOutUnit Unit Debounce 149 Time 150 0 0 61 usec (2 RtcClk) 976 usec 151 0 1 244 usec (8 RtcClk) 3.9 msec 152 1 0 15.6 msec (512 RtcClk) 250 msec 153 1 1 62.5 msec (2048 RtcClk) 1 sec 154 */ 155 156 if (debounce < 61) { 157 pin_reg |= 1; 158 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 159 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 160 } else if (debounce < 976) { 161 time = debounce / 61; 162 pin_reg |= time & DB_TMR_OUT_MASK; 163 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 164 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 165 } else if (debounce < 3900) { 166 time = debounce / 244; 167 pin_reg |= time & DB_TMR_OUT_MASK; 168 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); 169 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 170 } else if (debounce < 250000) { 171 time = debounce / 15625; 172 pin_reg |= time & DB_TMR_OUT_MASK; 173 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 174 pin_reg |= BIT(DB_TMR_LARGE_OFF); 175 } else if (debounce < 1000000) { 176 time = debounce / 62500; 177 pin_reg |= time & DB_TMR_OUT_MASK; 178 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); 179 pin_reg |= BIT(DB_TMR_LARGE_OFF); 180 } else { 181 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); 182 ret = -EINVAL; 183 } 184 } else { 185 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 186 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 187 pin_reg &= ~DB_TMR_OUT_MASK; 188 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); 189 } 190 writel(pin_reg, gpio_dev->base + offset * 4); 191 192 return ret; 193 } 194 195 #ifdef CONFIG_DEBUG_FS 196 static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc) 197 { 198 u32 pin_reg; 199 u32 db_cntrl; 200 unsigned long flags; 201 unsigned int bank, i, pin_num; 202 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 203 204 bool tmr_out_unit; 205 bool tmr_large; 206 207 char *level_trig; 208 char *active_level; 209 char *interrupt_mask; 210 char *wake_cntrl0; 211 char *wake_cntrl1; 212 char *wake_cntrl2; 213 char *pin_sts; 214 char *interrupt_sts; 215 char *wake_sts; 216 char *orientation; 217 char debounce_value[40]; 218 char *debounce_enable; 219 char *wake_cntrlz; 220 221 seq_printf(s, "WAKE_INT_MASTER_REG: 0x%08x\n", readl(gpio_dev->base + WAKE_INT_MASTER_REG)); 222 for (bank = 0; bank < gpio_dev->hwbank_num; bank++) { 223 unsigned int time = 0; 224 unsigned int unit = 0; 225 226 switch (bank) { 227 case 0: 228 i = 0; 229 pin_num = AMD_GPIO_PINS_BANK0; 230 break; 231 case 1: 232 i = 64; 233 pin_num = AMD_GPIO_PINS_BANK1 + i; 234 break; 235 case 2: 236 i = 128; 237 pin_num = AMD_GPIO_PINS_BANK2 + i; 238 break; 239 case 3: 240 i = 192; 241 pin_num = AMD_GPIO_PINS_BANK3 + i; 242 break; 243 default: 244 /* Illegal bank number, ignore */ 245 continue; 246 } 247 seq_printf(s, "GPIO bank%d\n", bank); 248 seq_puts(s, "gpio\t int|active|trigger|S0i3| S3|S4/S5| Z|wake|pull| orient| debounce|reg\n"); 249 for (; i < pin_num; i++) { 250 seq_printf(s, "#%d\t", i); 251 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 252 pin_reg = readl(gpio_dev->base + i * 4); 253 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 254 255 if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) { 256 u8 level = (pin_reg >> ACTIVE_LEVEL_OFF) & 257 ACTIVE_LEVEL_MASK; 258 259 if (level == ACTIVE_LEVEL_HIGH) 260 active_level = "↑"; 261 else if (level == ACTIVE_LEVEL_LOW) 262 active_level = "↓"; 263 else if (!(pin_reg & BIT(LEVEL_TRIG_OFF)) && 264 level == ACTIVE_LEVEL_BOTH) 265 active_level = "b"; 266 else 267 active_level = "?"; 268 269 if (pin_reg & BIT(LEVEL_TRIG_OFF)) 270 level_trig = "level"; 271 else 272 level_trig = " edge"; 273 274 if (pin_reg & BIT(INTERRUPT_MASK_OFF)) 275 interrupt_mask = "��"; 276 else 277 interrupt_mask = "��"; 278 279 if (pin_reg & BIT(INTERRUPT_STS_OFF)) 280 interrupt_sts = "��"; 281 else 282 interrupt_sts = " "; 283 284 seq_printf(s, "%s %s| %s| %s|", 285 interrupt_sts, 286 interrupt_mask, 287 active_level, 288 level_trig); 289 } else 290 seq_puts(s, " ∅| | |"); 291 292 if (pin_reg & BIT(WAKE_CNTRL_OFF_S0I3)) 293 wake_cntrl0 = "⏰"; 294 else 295 wake_cntrl0 = " "; 296 seq_printf(s, " %s| ", wake_cntrl0); 297 298 if (pin_reg & BIT(WAKE_CNTRL_OFF_S3)) 299 wake_cntrl1 = "⏰"; 300 else 301 wake_cntrl1 = " "; 302 seq_printf(s, "%s|", wake_cntrl1); 303 304 if (pin_reg & BIT(WAKE_CNTRL_OFF_S4)) 305 wake_cntrl2 = "⏰"; 306 else 307 wake_cntrl2 = " "; 308 seq_printf(s, " %s|", wake_cntrl2); 309 310 if (pin_reg & BIT(WAKECNTRL_Z_OFF)) 311 wake_cntrlz = "⏰"; 312 else 313 wake_cntrlz = " "; 314 seq_printf(s, "%s|", wake_cntrlz); 315 316 if (pin_reg & BIT(WAKE_STS_OFF)) 317 wake_sts = "��"; 318 else 319 wake_sts = " "; 320 seq_printf(s, " %s|", wake_sts); 321 322 if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) { 323 seq_puts(s, " ↑ |"); 324 } else if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF)) { 325 seq_puts(s, " ↓ |"); 326 } else { 327 seq_puts(s, " |"); 328 } 329 330 if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) { 331 pin_sts = "output"; 332 if (pin_reg & BIT(OUTPUT_VALUE_OFF)) 333 orientation = "↑"; 334 else 335 orientation = "↓"; 336 } else { 337 pin_sts = "input "; 338 if (pin_reg & BIT(PIN_STS_OFF)) 339 orientation = "↑"; 340 else 341 orientation = "↓"; 342 } 343 seq_printf(s, "%s %s|", pin_sts, orientation); 344 345 db_cntrl = (DB_CNTRl_MASK << DB_CNTRL_OFF) & pin_reg; 346 if (db_cntrl) { 347 tmr_out_unit = pin_reg & BIT(DB_TMR_OUT_UNIT_OFF); 348 tmr_large = pin_reg & BIT(DB_TMR_LARGE_OFF); 349 time = pin_reg & DB_TMR_OUT_MASK; 350 if (tmr_large) { 351 if (tmr_out_unit) 352 unit = 62500; 353 else 354 unit = 15625; 355 } else { 356 if (tmr_out_unit) 357 unit = 244; 358 else 359 unit = 61; 360 } 361 if ((DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF) == db_cntrl) 362 debounce_enable = "b"; 363 else if ((DB_TYPE_PRESERVE_LOW_GLITCH << DB_CNTRL_OFF) == db_cntrl) 364 debounce_enable = "↓"; 365 else 366 debounce_enable = "↑"; 367 snprintf(debounce_value, sizeof(debounce_value), "%06u", time * unit); 368 seq_printf(s, "%s (�� %sus)|", debounce_enable, debounce_value); 369 } else { 370 seq_puts(s, " |"); 371 } 372 seq_printf(s, "0x%x\n", pin_reg); 373 } 374 } 375 } 376 #else 377 #define amd_gpio_dbg_show NULL 378 #endif 379 380 static void amd_gpio_irq_enable(struct irq_data *d) 381 { 382 u32 pin_reg; 383 unsigned long flags; 384 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 385 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 386 387 gpiochip_enable_irq(gc, d->hwirq); 388 389 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 390 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 391 pin_reg |= BIT(INTERRUPT_ENABLE_OFF); 392 pin_reg |= BIT(INTERRUPT_MASK_OFF); 393 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 394 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 395 } 396 397 static void amd_gpio_irq_disable(struct irq_data *d) 398 { 399 u32 pin_reg; 400 unsigned long flags; 401 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 402 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 403 404 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 405 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 406 pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF); 407 pin_reg &= ~BIT(INTERRUPT_MASK_OFF); 408 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 409 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 410 411 gpiochip_disable_irq(gc, d->hwirq); 412 } 413 414 static void amd_gpio_irq_mask(struct irq_data *d) 415 { 416 u32 pin_reg; 417 unsigned long flags; 418 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 419 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 420 421 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 422 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 423 pin_reg &= ~BIT(INTERRUPT_MASK_OFF); 424 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 425 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 426 } 427 428 static void amd_gpio_irq_unmask(struct irq_data *d) 429 { 430 u32 pin_reg; 431 unsigned long flags; 432 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 433 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 434 435 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 436 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 437 pin_reg |= BIT(INTERRUPT_MASK_OFF); 438 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 439 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 440 } 441 442 static int amd_gpio_irq_set_wake(struct irq_data *d, unsigned int on) 443 { 444 u32 pin_reg; 445 unsigned long flags; 446 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 447 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 448 u32 wake_mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3); 449 int err; 450 451 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 452 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 453 454 if (on) 455 pin_reg |= wake_mask; 456 else 457 pin_reg &= ~wake_mask; 458 459 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 460 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 461 462 if (on) 463 err = enable_irq_wake(gpio_dev->irq); 464 else 465 err = disable_irq_wake(gpio_dev->irq); 466 467 if (err) 468 dev_err(&gpio_dev->pdev->dev, "failed to %s wake-up interrupt\n", 469 str_enable_disable(on)); 470 471 return 0; 472 } 473 474 static void amd_gpio_irq_eoi(struct irq_data *d) 475 { 476 u32 reg; 477 unsigned long flags; 478 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 479 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 480 481 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 482 reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG); 483 reg |= EOI_MASK; 484 writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG); 485 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 486 } 487 488 static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type) 489 { 490 int ret = 0; 491 u32 pin_reg, pin_reg_irq_en, mask; 492 unsigned long flags; 493 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 494 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 495 496 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 497 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 498 499 switch (type & IRQ_TYPE_SENSE_MASK) { 500 case IRQ_TYPE_EDGE_RISING: 501 pin_reg &= ~BIT(LEVEL_TRIG_OFF); 502 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 503 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; 504 irq_set_handler_locked(d, handle_edge_irq); 505 break; 506 507 case IRQ_TYPE_EDGE_FALLING: 508 pin_reg &= ~BIT(LEVEL_TRIG_OFF); 509 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 510 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; 511 irq_set_handler_locked(d, handle_edge_irq); 512 break; 513 514 case IRQ_TYPE_EDGE_BOTH: 515 pin_reg &= ~BIT(LEVEL_TRIG_OFF); 516 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 517 pin_reg |= BOTH_EDGES << ACTIVE_LEVEL_OFF; 518 irq_set_handler_locked(d, handle_edge_irq); 519 break; 520 521 case IRQ_TYPE_LEVEL_HIGH: 522 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF; 523 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 524 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; 525 irq_set_handler_locked(d, handle_level_irq); 526 break; 527 528 case IRQ_TYPE_LEVEL_LOW: 529 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF; 530 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 531 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; 532 irq_set_handler_locked(d, handle_level_irq); 533 break; 534 535 case IRQ_TYPE_NONE: 536 break; 537 538 default: 539 dev_err(&gpio_dev->pdev->dev, "Invalid type value\n"); 540 ret = -EINVAL; 541 } 542 543 pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF; 544 /* 545 * If WAKE_INT_MASTER_REG.MaskStsEn is set, a software write to the 546 * debounce registers of any GPIO will block wake/interrupt status 547 * generation for *all* GPIOs for a length of time that depends on 548 * WAKE_INT_MASTER_REG.MaskStsLength[11:0]. During this period the 549 * INTERRUPT_ENABLE bit will read as 0. 550 * 551 * We temporarily enable irq for the GPIO whose configuration is 552 * changing, and then wait for it to read back as 1 to know when 553 * debounce has settled and then disable the irq again. 554 * We do this polling with the spinlock held to ensure other GPIO 555 * access routines do not read an incorrect value for the irq enable 556 * bit of other GPIOs. We keep the GPIO masked while polling to avoid 557 * spurious irqs, and disable the irq again after polling. 558 */ 559 mask = BIT(INTERRUPT_ENABLE_OFF); 560 pin_reg_irq_en = pin_reg; 561 pin_reg_irq_en |= mask; 562 pin_reg_irq_en &= ~BIT(INTERRUPT_MASK_OFF); 563 writel(pin_reg_irq_en, gpio_dev->base + (d->hwirq)*4); 564 while ((readl(gpio_dev->base + (d->hwirq)*4) & mask) != mask) 565 continue; 566 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 567 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 568 569 return ret; 570 } 571 572 static void amd_irq_ack(struct irq_data *d) 573 { 574 /* 575 * based on HW design,there is no need to ack HW 576 * before handle current irq. But this routine is 577 * necessary for handle_edge_irq 578 */ 579 } 580 581 static const struct irq_chip amd_gpio_irqchip = { 582 .name = "amd_gpio", 583 .irq_ack = amd_irq_ack, 584 .irq_enable = amd_gpio_irq_enable, 585 .irq_disable = amd_gpio_irq_disable, 586 .irq_mask = amd_gpio_irq_mask, 587 .irq_unmask = amd_gpio_irq_unmask, 588 .irq_set_wake = amd_gpio_irq_set_wake, 589 .irq_eoi = amd_gpio_irq_eoi, 590 .irq_set_type = amd_gpio_irq_set_type, 591 /* 592 * We need to set IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND so that a wake event 593 * also generates an IRQ. We need the IRQ so the irq_handler can clear 594 * the wake event. Otherwise the wake event will never clear and 595 * prevent the system from suspending. 596 */ 597 .flags = IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND | IRQCHIP_IMMUTABLE, 598 GPIOCHIP_IRQ_RESOURCE_HELPERS, 599 }; 600 601 #define PIN_IRQ_PENDING (BIT(INTERRUPT_STS_OFF) | BIT(WAKE_STS_OFF)) 602 603 static bool do_amd_gpio_irq_handler(int irq, void *dev_id) 604 { 605 struct amd_gpio *gpio_dev = dev_id; 606 struct gpio_chip *gc = &gpio_dev->gc; 607 unsigned int i, irqnr; 608 unsigned long flags; 609 u32 __iomem *regs; 610 bool ret = false; 611 u32 regval; 612 u64 status, mask; 613 614 /* Read the wake status */ 615 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 616 status = readl(gpio_dev->base + WAKE_INT_STATUS_REG1); 617 status <<= 32; 618 status |= readl(gpio_dev->base + WAKE_INT_STATUS_REG0); 619 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 620 621 /* Bit 0-45 contain the relevant status bits */ 622 status &= (1ULL << 46) - 1; 623 regs = gpio_dev->base; 624 for (mask = 1, irqnr = 0; status; mask <<= 1, regs += 4, irqnr += 4) { 625 if (!(status & mask)) 626 continue; 627 status &= ~mask; 628 629 /* Each status bit covers four pins */ 630 for (i = 0; i < 4; i++) { 631 regval = readl(regs + i); 632 633 if (regval & PIN_IRQ_PENDING) 634 pm_pr_dbg("GPIO %d is active: 0x%x", 635 irqnr + i, regval); 636 637 /* caused wake on resume context for shared IRQ */ 638 if (irq < 0 && (regval & BIT(WAKE_STS_OFF))) 639 return true; 640 641 if (!(regval & PIN_IRQ_PENDING) || 642 !(regval & BIT(INTERRUPT_MASK_OFF))) 643 continue; 644 generic_handle_domain_irq_safe(gc->irq.domain, irqnr + i); 645 646 /* Clear interrupt. 647 * We must read the pin register again, in case the 648 * value was changed while executing 649 * generic_handle_domain_irq() above. 650 * If the line is not an irq, disable it in order to 651 * avoid a system hang caused by an interrupt storm. 652 */ 653 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 654 regval = readl(regs + i); 655 if (!gpiochip_line_is_irq(gc, irqnr + i)) { 656 regval &= ~BIT(INTERRUPT_MASK_OFF); 657 dev_dbg(&gpio_dev->pdev->dev, 658 "Disabling spurious GPIO IRQ %d\n", 659 irqnr + i); 660 } else { 661 ret = true; 662 } 663 writel(regval, regs + i); 664 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 665 } 666 } 667 /* did not cause wake on resume context for shared IRQ */ 668 if (irq < 0) 669 return false; 670 671 /* Signal EOI to the GPIO unit */ 672 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 673 regval = readl(gpio_dev->base + WAKE_INT_MASTER_REG); 674 regval |= EOI_MASK; 675 writel(regval, gpio_dev->base + WAKE_INT_MASTER_REG); 676 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 677 678 return ret; 679 } 680 681 static irqreturn_t amd_gpio_irq_handler(int irq, void *dev_id) 682 { 683 return IRQ_RETVAL(do_amd_gpio_irq_handler(irq, dev_id)); 684 } 685 686 static bool __maybe_unused amd_gpio_check_wake(void *dev_id) 687 { 688 return do_amd_gpio_irq_handler(-1, dev_id); 689 } 690 691 static int amd_get_groups_count(struct pinctrl_dev *pctldev) 692 { 693 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 694 695 return gpio_dev->ngroups; 696 } 697 698 static const char *amd_get_group_name(struct pinctrl_dev *pctldev, 699 unsigned group) 700 { 701 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 702 703 return gpio_dev->groups[group].name; 704 } 705 706 static int amd_get_group_pins(struct pinctrl_dev *pctldev, 707 unsigned group, 708 const unsigned **pins, 709 unsigned *num_pins) 710 { 711 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 712 713 *pins = gpio_dev->groups[group].pins; 714 *num_pins = gpio_dev->groups[group].npins; 715 return 0; 716 } 717 718 static const struct pinctrl_ops amd_pinctrl_ops = { 719 .get_groups_count = amd_get_groups_count, 720 .get_group_name = amd_get_group_name, 721 .get_group_pins = amd_get_group_pins, 722 #ifdef CONFIG_OF 723 .dt_node_to_map = pinconf_generic_dt_node_to_map_group, 724 .dt_free_map = pinctrl_utils_free_map, 725 #endif 726 }; 727 728 static int amd_pinconf_get(struct pinctrl_dev *pctldev, 729 unsigned int pin, 730 unsigned long *config) 731 { 732 u32 pin_reg; 733 unsigned arg; 734 unsigned long flags; 735 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 736 enum pin_config_param param = pinconf_to_config_param(*config); 737 738 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 739 pin_reg = readl(gpio_dev->base + pin*4); 740 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 741 switch (param) { 742 case PIN_CONFIG_INPUT_DEBOUNCE: 743 arg = pin_reg & DB_TMR_OUT_MASK; 744 break; 745 746 case PIN_CONFIG_BIAS_PULL_DOWN: 747 arg = (pin_reg >> PULL_DOWN_ENABLE_OFF) & BIT(0); 748 break; 749 750 case PIN_CONFIG_BIAS_PULL_UP: 751 arg = (pin_reg >> PULL_UP_ENABLE_OFF) & BIT(0); 752 break; 753 754 case PIN_CONFIG_DRIVE_STRENGTH: 755 arg = (pin_reg >> DRV_STRENGTH_SEL_OFF) & DRV_STRENGTH_SEL_MASK; 756 break; 757 758 default: 759 dev_dbg(&gpio_dev->pdev->dev, "Invalid config param %04x\n", 760 param); 761 return -ENOTSUPP; 762 } 763 764 *config = pinconf_to_config_packed(param, arg); 765 766 return 0; 767 } 768 769 static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 770 unsigned long *configs, unsigned int num_configs) 771 { 772 int i; 773 u32 arg; 774 int ret = 0; 775 u32 pin_reg; 776 unsigned long flags; 777 enum pin_config_param param; 778 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 779 780 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 781 for (i = 0; i < num_configs; i++) { 782 param = pinconf_to_config_param(configs[i]); 783 arg = pinconf_to_config_argument(configs[i]); 784 pin_reg = readl(gpio_dev->base + pin*4); 785 786 switch (param) { 787 case PIN_CONFIG_INPUT_DEBOUNCE: 788 ret = amd_gpio_set_debounce(gpio_dev, pin, arg); 789 goto out_unlock; 790 791 case PIN_CONFIG_BIAS_PULL_DOWN: 792 pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF); 793 pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF; 794 break; 795 796 case PIN_CONFIG_BIAS_PULL_UP: 797 pin_reg &= ~BIT(PULL_UP_ENABLE_OFF); 798 pin_reg |= (arg & BIT(0)) << PULL_UP_ENABLE_OFF; 799 break; 800 801 case PIN_CONFIG_DRIVE_STRENGTH: 802 pin_reg &= ~(DRV_STRENGTH_SEL_MASK 803 << DRV_STRENGTH_SEL_OFF); 804 pin_reg |= (arg & DRV_STRENGTH_SEL_MASK) 805 << DRV_STRENGTH_SEL_OFF; 806 break; 807 808 default: 809 dev_dbg(&gpio_dev->pdev->dev, 810 "Invalid config param %04x\n", param); 811 ret = -ENOTSUPP; 812 } 813 814 writel(pin_reg, gpio_dev->base + pin*4); 815 } 816 out_unlock: 817 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 818 819 return ret; 820 } 821 822 static int amd_pinconf_group_get(struct pinctrl_dev *pctldev, 823 unsigned int group, 824 unsigned long *config) 825 { 826 const unsigned *pins; 827 unsigned npins; 828 int ret; 829 830 ret = amd_get_group_pins(pctldev, group, &pins, &npins); 831 if (ret) 832 return ret; 833 834 if (amd_pinconf_get(pctldev, pins[0], config)) 835 return -ENOTSUPP; 836 837 return 0; 838 } 839 840 static int amd_pinconf_group_set(struct pinctrl_dev *pctldev, 841 unsigned group, unsigned long *configs, 842 unsigned num_configs) 843 { 844 const unsigned *pins; 845 unsigned npins; 846 int i, ret; 847 848 ret = amd_get_group_pins(pctldev, group, &pins, &npins); 849 if (ret) 850 return ret; 851 for (i = 0; i < npins; i++) { 852 if (amd_pinconf_set(pctldev, pins[i], configs, num_configs)) 853 return -ENOTSUPP; 854 } 855 return 0; 856 } 857 858 static int amd_gpio_set_config(struct gpio_chip *gc, unsigned int pin, 859 unsigned long config) 860 { 861 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 862 863 return amd_pinconf_set(gpio_dev->pctrl, pin, &config, 1); 864 } 865 866 static const struct pinconf_ops amd_pinconf_ops = { 867 .pin_config_get = amd_pinconf_get, 868 .pin_config_set = amd_pinconf_set, 869 .pin_config_group_get = amd_pinconf_group_get, 870 .pin_config_group_set = amd_pinconf_group_set, 871 }; 872 873 static void amd_gpio_irq_init(struct amd_gpio *gpio_dev) 874 { 875 struct pinctrl_desc *desc = gpio_dev->pctrl->desc; 876 unsigned long flags; 877 u32 pin_reg, mask; 878 int i; 879 880 mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3) | 881 BIT(WAKE_CNTRL_OFF_S4); 882 883 for (i = 0; i < desc->npins; i++) { 884 int pin = desc->pins[i].number; 885 const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin); 886 887 if (!pd) 888 continue; 889 890 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 891 892 pin_reg = readl(gpio_dev->base + pin * 4); 893 pin_reg &= ~mask; 894 writel(pin_reg, gpio_dev->base + pin * 4); 895 896 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 897 } 898 } 899 900 #if defined(CONFIG_SUSPEND) && defined(CONFIG_ACPI) 901 static void amd_gpio_check_pending(void) 902 { 903 struct amd_gpio *gpio_dev = pinctrl_dev; 904 struct pinctrl_desc *desc = gpio_dev->pctrl->desc; 905 int i; 906 907 if (!pm_debug_messages_on) 908 return; 909 910 for (i = 0; i < desc->npins; i++) { 911 int pin = desc->pins[i].number; 912 u32 tmp; 913 914 tmp = readl(gpio_dev->base + pin * 4); 915 if (tmp & PIN_IRQ_PENDING) 916 pm_pr_dbg("%s: GPIO %d is active: 0x%x.\n", __func__, pin, tmp); 917 } 918 } 919 920 static struct acpi_s2idle_dev_ops pinctrl_amd_s2idle_dev_ops = { 921 .check = amd_gpio_check_pending, 922 }; 923 924 static void amd_gpio_register_s2idle_ops(void) 925 { 926 acpi_register_lps0_dev(&pinctrl_amd_s2idle_dev_ops); 927 } 928 929 static void amd_gpio_unregister_s2idle_ops(void) 930 { 931 acpi_unregister_lps0_dev(&pinctrl_amd_s2idle_dev_ops); 932 } 933 #else 934 static inline void amd_gpio_register_s2idle_ops(void) {} 935 static inline void amd_gpio_unregister_s2idle_ops(void) {} 936 #endif 937 938 #ifdef CONFIG_PM_SLEEP 939 static bool amd_gpio_should_save(struct amd_gpio *gpio_dev, unsigned int pin) 940 { 941 const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin); 942 943 if (!pd) 944 return false; 945 946 /* 947 * Only restore the pin if it is actually in use by the kernel (or 948 * by userspace). 949 */ 950 if (pd->mux_owner || pd->gpio_owner || 951 gpiochip_line_is_irq(&gpio_dev->gc, pin)) 952 return true; 953 954 return false; 955 } 956 957 static int amd_gpio_suspend_hibernate_common(struct device *dev, bool is_suspend) 958 { 959 struct amd_gpio *gpio_dev = dev_get_drvdata(dev); 960 struct pinctrl_desc *desc = gpio_dev->pctrl->desc; 961 unsigned long flags; 962 int i; 963 u32 wake_mask = is_suspend ? WAKE_SOURCE_SUSPEND : WAKE_SOURCE_HIBERNATE; 964 965 for (i = 0; i < desc->npins; i++) { 966 int pin = desc->pins[i].number; 967 968 if (!amd_gpio_should_save(gpio_dev, pin)) 969 continue; 970 971 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 972 gpio_dev->saved_regs[i] = readl(gpio_dev->base + pin * 4) & ~PIN_IRQ_PENDING; 973 974 /* mask any interrupts not intended to be a wake source */ 975 if (!(gpio_dev->saved_regs[i] & wake_mask)) { 976 writel(gpio_dev->saved_regs[i] & ~BIT(INTERRUPT_MASK_OFF), 977 gpio_dev->base + pin * 4); 978 pm_pr_dbg("Disabling GPIO #%d interrupt for %s.\n", 979 pin, is_suspend ? "suspend" : "hibernate"); 980 } 981 982 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 983 } 984 985 return 0; 986 } 987 988 static int amd_gpio_suspend(struct device *dev) 989 { 990 #ifdef CONFIG_SUSPEND 991 pinctrl_dev = dev_get_drvdata(dev); 992 #endif 993 return amd_gpio_suspend_hibernate_common(dev, true); 994 } 995 996 static int amd_gpio_hibernate(struct device *dev) 997 { 998 return amd_gpio_suspend_hibernate_common(dev, false); 999 } 1000 1001 static int amd_gpio_resume(struct device *dev) 1002 { 1003 struct amd_gpio *gpio_dev = dev_get_drvdata(dev); 1004 struct pinctrl_desc *desc = gpio_dev->pctrl->desc; 1005 unsigned long flags; 1006 int i; 1007 1008 for (i = 0; i < desc->npins; i++) { 1009 int pin = desc->pins[i].number; 1010 1011 if (!amd_gpio_should_save(gpio_dev, pin)) 1012 continue; 1013 1014 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 1015 gpio_dev->saved_regs[i] |= readl(gpio_dev->base + pin * 4) & PIN_IRQ_PENDING; 1016 writel(gpio_dev->saved_regs[i], gpio_dev->base + pin * 4); 1017 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 1018 } 1019 1020 return 0; 1021 } 1022 1023 static const struct dev_pm_ops amd_gpio_pm_ops = { 1024 .suspend_late = amd_gpio_suspend, 1025 .resume_early = amd_gpio_resume, 1026 .freeze_late = amd_gpio_hibernate, 1027 .thaw_early = amd_gpio_resume, 1028 .poweroff_late = amd_gpio_hibernate, 1029 .restore_early = amd_gpio_resume, 1030 }; 1031 #endif 1032 1033 static int amd_get_functions_count(struct pinctrl_dev *pctldev) 1034 { 1035 return ARRAY_SIZE(pmx_functions); 1036 } 1037 1038 static const char *amd_get_fname(struct pinctrl_dev *pctrldev, unsigned int selector) 1039 { 1040 return pmx_functions[selector].name; 1041 } 1042 1043 static int amd_get_groups(struct pinctrl_dev *pctrldev, unsigned int selector, 1044 const char * const **groups, 1045 unsigned int * const num_groups) 1046 { 1047 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctrldev); 1048 1049 if (!gpio_dev->iomux_base) { 1050 dev_err(&gpio_dev->pdev->dev, "iomux function %d group not supported\n", selector); 1051 return -EINVAL; 1052 } 1053 1054 *groups = pmx_functions[selector].groups; 1055 *num_groups = pmx_functions[selector].ngroups; 1056 return 0; 1057 } 1058 1059 static int amd_set_mux(struct pinctrl_dev *pctrldev, unsigned int function, unsigned int group) 1060 { 1061 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctrldev); 1062 struct device *dev = &gpio_dev->pdev->dev; 1063 struct pin_desc *pd; 1064 int ind, index; 1065 1066 if (!gpio_dev->iomux_base) 1067 return -EINVAL; 1068 1069 for (index = 0; index < NSELECTS; index++) { 1070 if (strcmp(gpio_dev->groups[group].name, pmx_functions[function].groups[index])) 1071 continue; 1072 1073 if (readb(gpio_dev->iomux_base + pmx_functions[function].index) == 1074 FUNCTION_INVALID) { 1075 dev_err(dev, "IOMUX_GPIO 0x%x not present or supported\n", 1076 pmx_functions[function].index); 1077 return -EINVAL; 1078 } 1079 1080 writeb(index, gpio_dev->iomux_base + pmx_functions[function].index); 1081 1082 if (index != (readb(gpio_dev->iomux_base + pmx_functions[function].index) & 1083 FUNCTION_MASK)) { 1084 dev_err(dev, "IOMUX_GPIO 0x%x not present or supported\n", 1085 pmx_functions[function].index); 1086 return -EINVAL; 1087 } 1088 1089 for (ind = 0; ind < gpio_dev->groups[group].npins; ind++) { 1090 if (strncmp(gpio_dev->groups[group].name, "IMX_F", strlen("IMX_F"))) 1091 continue; 1092 1093 pd = pin_desc_get(gpio_dev->pctrl, gpio_dev->groups[group].pins[ind]); 1094 pd->mux_owner = gpio_dev->groups[group].name; 1095 } 1096 break; 1097 } 1098 1099 return 0; 1100 } 1101 1102 static const struct pinmux_ops amd_pmxops = { 1103 .get_functions_count = amd_get_functions_count, 1104 .get_function_name = amd_get_fname, 1105 .get_function_groups = amd_get_groups, 1106 .set_mux = amd_set_mux, 1107 }; 1108 1109 static struct pinctrl_desc amd_pinctrl_desc = { 1110 .pins = kerncz_pins, 1111 .npins = ARRAY_SIZE(kerncz_pins), 1112 .pctlops = &amd_pinctrl_ops, 1113 .pmxops = &amd_pmxops, 1114 .confops = &amd_pinconf_ops, 1115 .owner = THIS_MODULE, 1116 }; 1117 1118 static void amd_get_iomux_res(struct amd_gpio *gpio_dev) 1119 { 1120 struct pinctrl_desc *desc = &amd_pinctrl_desc; 1121 struct device *dev = &gpio_dev->pdev->dev; 1122 int index; 1123 1124 index = device_property_match_string(dev, "pinctrl-resource-names", "iomux"); 1125 if (index < 0) { 1126 dev_dbg(dev, "iomux not supported\n"); 1127 goto out_no_pinmux; 1128 } 1129 1130 gpio_dev->iomux_base = devm_platform_ioremap_resource(gpio_dev->pdev, index); 1131 if (IS_ERR(gpio_dev->iomux_base)) { 1132 dev_dbg(dev, "iomux not supported %d io resource\n", index); 1133 goto out_no_pinmux; 1134 } 1135 1136 return; 1137 1138 out_no_pinmux: 1139 desc->pmxops = NULL; 1140 } 1141 1142 static int amd_gpio_probe(struct platform_device *pdev) 1143 { 1144 int ret = 0; 1145 struct resource *res; 1146 struct amd_gpio *gpio_dev; 1147 struct gpio_irq_chip *girq; 1148 1149 gpio_dev = devm_kzalloc(&pdev->dev, 1150 sizeof(struct amd_gpio), GFP_KERNEL); 1151 if (!gpio_dev) 1152 return -ENOMEM; 1153 1154 raw_spin_lock_init(&gpio_dev->lock); 1155 1156 gpio_dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1157 if (IS_ERR(gpio_dev->base)) { 1158 dev_err(&pdev->dev, "Failed to get gpio io resource.\n"); 1159 return PTR_ERR(gpio_dev->base); 1160 } 1161 1162 gpio_dev->irq = platform_get_irq(pdev, 0); 1163 if (gpio_dev->irq < 0) 1164 return gpio_dev->irq; 1165 1166 #ifdef CONFIG_SUSPEND 1167 gpio_dev->saved_regs = devm_kcalloc(&pdev->dev, amd_pinctrl_desc.npins, 1168 sizeof(*gpio_dev->saved_regs), 1169 GFP_KERNEL); 1170 if (!gpio_dev->saved_regs) 1171 return -ENOMEM; 1172 #endif 1173 1174 gpio_dev->pdev = pdev; 1175 gpio_dev->gc.get_direction = amd_gpio_get_direction; 1176 gpio_dev->gc.direction_input = amd_gpio_direction_input; 1177 gpio_dev->gc.direction_output = amd_gpio_direction_output; 1178 gpio_dev->gc.get = amd_gpio_get_value; 1179 gpio_dev->gc.set_rv = amd_gpio_set_value; 1180 gpio_dev->gc.set_config = amd_gpio_set_config; 1181 gpio_dev->gc.dbg_show = amd_gpio_dbg_show; 1182 1183 gpio_dev->gc.base = -1; 1184 gpio_dev->gc.label = pdev->name; 1185 gpio_dev->gc.owner = THIS_MODULE; 1186 gpio_dev->gc.parent = &pdev->dev; 1187 gpio_dev->gc.ngpio = resource_size(res) / 4; 1188 1189 gpio_dev->hwbank_num = gpio_dev->gc.ngpio / 64; 1190 gpio_dev->groups = kerncz_groups; 1191 gpio_dev->ngroups = ARRAY_SIZE(kerncz_groups); 1192 1193 amd_pinctrl_desc.name = dev_name(&pdev->dev); 1194 amd_get_iomux_res(gpio_dev); 1195 gpio_dev->pctrl = devm_pinctrl_register(&pdev->dev, &amd_pinctrl_desc, 1196 gpio_dev); 1197 if (IS_ERR(gpio_dev->pctrl)) { 1198 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); 1199 return PTR_ERR(gpio_dev->pctrl); 1200 } 1201 1202 /* Disable and mask interrupts */ 1203 amd_gpio_irq_init(gpio_dev); 1204 1205 girq = &gpio_dev->gc.irq; 1206 gpio_irq_chip_set_chip(girq, &amd_gpio_irqchip); 1207 /* This will let us handle the parent IRQ in the driver */ 1208 girq->parent_handler = NULL; 1209 girq->num_parents = 0; 1210 girq->parents = NULL; 1211 girq->default_type = IRQ_TYPE_NONE; 1212 girq->handler = handle_simple_irq; 1213 1214 ret = gpiochip_add_data(&gpio_dev->gc, gpio_dev); 1215 if (ret) 1216 return ret; 1217 1218 ret = gpiochip_add_pin_range(&gpio_dev->gc, dev_name(&pdev->dev), 1219 0, 0, gpio_dev->gc.ngpio); 1220 if (ret) { 1221 dev_err(&pdev->dev, "Failed to add pin range\n"); 1222 goto out2; 1223 } 1224 1225 ret = devm_request_irq(&pdev->dev, gpio_dev->irq, amd_gpio_irq_handler, 1226 IRQF_SHARED | IRQF_COND_ONESHOT, KBUILD_MODNAME, gpio_dev); 1227 if (ret) 1228 goto out2; 1229 1230 platform_set_drvdata(pdev, gpio_dev); 1231 acpi_register_wakeup_handler(gpio_dev->irq, amd_gpio_check_wake, gpio_dev); 1232 amd_gpio_register_s2idle_ops(); 1233 1234 dev_dbg(&pdev->dev, "amd gpio driver loaded\n"); 1235 return ret; 1236 1237 out2: 1238 gpiochip_remove(&gpio_dev->gc); 1239 1240 return ret; 1241 } 1242 1243 static void amd_gpio_remove(struct platform_device *pdev) 1244 { 1245 struct amd_gpio *gpio_dev; 1246 1247 gpio_dev = platform_get_drvdata(pdev); 1248 1249 gpiochip_remove(&gpio_dev->gc); 1250 acpi_unregister_wakeup_handler(amd_gpio_check_wake, gpio_dev); 1251 amd_gpio_unregister_s2idle_ops(); 1252 } 1253 1254 #ifdef CONFIG_ACPI 1255 static const struct acpi_device_id amd_gpio_acpi_match[] = { 1256 { "AMD0030", 0 }, 1257 { "AMDI0030", 0}, 1258 { "AMDI0031", 0}, 1259 { }, 1260 }; 1261 MODULE_DEVICE_TABLE(acpi, amd_gpio_acpi_match); 1262 #endif 1263 1264 static struct platform_driver amd_gpio_driver = { 1265 .driver = { 1266 .name = "amd_gpio", 1267 .acpi_match_table = ACPI_PTR(amd_gpio_acpi_match), 1268 #ifdef CONFIG_PM_SLEEP 1269 .pm = &amd_gpio_pm_ops, 1270 #endif 1271 }, 1272 .probe = amd_gpio_probe, 1273 .remove = amd_gpio_remove, 1274 }; 1275 1276 module_platform_driver(amd_gpio_driver); 1277 1278 MODULE_AUTHOR("Ken Xue <Ken.Xue@amd.com>, Jeff Wu <Jeff.Wu@amd.com>"); 1279 MODULE_DESCRIPTION("AMD GPIO pinctrl driver"); 1280