1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Pinctrl GPIO driver for Intel Baytrail 4 * 5 * Copyright (c) 2012-2013, Intel Corporation 6 * Author: Mathias Nyman <mathias.nyman@linux.intel.com> 7 */ 8 9 #include <linux/acpi.h> 10 #include <linux/array_size.h> 11 #include <linux/bitops.h> 12 #include <linux/cleanup.h> 13 #include <linux/gpio/driver.h> 14 #include <linux/init.h> 15 #include <linux/interrupt.h> 16 #include <linux/io.h> 17 #include <linux/module.h> 18 #include <linux/types.h> 19 #include <linux/platform_device.h> 20 #include <linux/pm.h> 21 #include <linux/property.h> 22 #include <linux/seq_file.h> 23 #include <linux/string_helpers.h> 24 25 #include <linux/pinctrl/pinctrl.h> 26 #include <linux/pinctrl/pinmux.h> 27 #include <linux/pinctrl/pinconf.h> 28 #include <linux/pinctrl/pinconf-generic.h> 29 30 #include "pinctrl-intel.h" 31 32 /* memory mapped register offsets */ 33 #define BYT_CONF0_REG 0x000 34 #define BYT_CONF1_REG 0x004 35 #define BYT_VAL_REG 0x008 36 #define BYT_DFT_REG 0x00c 37 #define BYT_INT_STAT_REG 0x800 38 #define BYT_DIRECT_IRQ_REG 0x980 39 #define BYT_DEBOUNCE_REG 0x9d0 40 41 /* BYT_CONF0_REG register bits */ 42 #define BYT_IODEN BIT(31) 43 #define BYT_DIRECT_IRQ_EN BIT(27) 44 #define BYT_TRIG_MASK GENMASK(26, 24) 45 #define BYT_TRIG_NEG BIT(26) 46 #define BYT_TRIG_POS BIT(25) 47 #define BYT_TRIG_LVL BIT(24) 48 #define BYT_DEBOUNCE_EN BIT(20) 49 #define BYT_GLITCH_FILTER_EN BIT(19) 50 #define BYT_GLITCH_F_SLOW_CLK BIT(17) 51 #define BYT_GLITCH_F_FAST_CLK BIT(16) 52 #define BYT_PULL_STR_SHIFT 9 53 #define BYT_PULL_STR_MASK GENMASK(10, 9) 54 #define BYT_PULL_STR_2K (0 << BYT_PULL_STR_SHIFT) 55 #define BYT_PULL_STR_10K (1 << BYT_PULL_STR_SHIFT) 56 #define BYT_PULL_STR_20K (2 << BYT_PULL_STR_SHIFT) 57 #define BYT_PULL_STR_40K (3 << BYT_PULL_STR_SHIFT) 58 #define BYT_PULL_ASSIGN_MASK GENMASK(8, 7) 59 #define BYT_PULL_ASSIGN_DOWN BIT(8) 60 #define BYT_PULL_ASSIGN_UP BIT(7) 61 #define BYT_PIN_MUX GENMASK(2, 0) 62 63 /* BYT_VAL_REG register bits */ 64 #define BYT_DIR_MASK GENMASK(2, 1) 65 #define BYT_INPUT_EN BIT(2) /* 0: input enabled (active low)*/ 66 #define BYT_OUTPUT_EN BIT(1) /* 0: output enabled (active low)*/ 67 #define BYT_LEVEL BIT(0) 68 69 #define BYT_CONF0_RESTORE_MASK (BYT_DIRECT_IRQ_EN | BYT_TRIG_MASK | BYT_PIN_MUX) 70 #define BYT_VAL_RESTORE_MASK (BYT_DIR_MASK | BYT_LEVEL) 71 72 /* BYT_DEBOUNCE_REG bits */ 73 #define BYT_DEBOUNCE_PULSE_MASK GENMASK(2, 0) 74 #define BYT_DEBOUNCE_PULSE_375US 1 75 #define BYT_DEBOUNCE_PULSE_750US 2 76 #define BYT_DEBOUNCE_PULSE_1500US 3 77 #define BYT_DEBOUNCE_PULSE_3MS 4 78 #define BYT_DEBOUNCE_PULSE_6MS 5 79 #define BYT_DEBOUNCE_PULSE_12MS 6 80 #define BYT_DEBOUNCE_PULSE_24MS 7 81 82 #define BYT_NGPIO_SCORE 102 83 #define BYT_NGPIO_NCORE 28 84 #define BYT_NGPIO_SUS 44 85 86 #define BYT_SCORE_ACPI_UID "1" 87 #define BYT_NCORE_ACPI_UID "2" 88 #define BYT_SUS_ACPI_UID "3" 89 90 /* 91 * This is the function value most pins have for GPIO muxing. If the value 92 * differs from the default one, it must be explicitly mentioned. Otherwise, the 93 * pin control implementation will set the muxing value to default GPIO if it 94 * does not find a match for the requested function. 95 */ 96 #define BYT_DEFAULT_GPIO_MUX 0 97 #define BYT_ALTER_GPIO_MUX 1 98 99 struct intel_pad_context { 100 u32 conf0; 101 u32 val; 102 }; 103 104 #define COMMUNITY(p, n, map) \ 105 { \ 106 .pin_base = (p), \ 107 .npins = (n), \ 108 .pad_map = (map),\ 109 } 110 111 /* SCORE pins, aka GPIOC_<pin_no> or GPIO_S0_SC[<pin_no>] */ 112 static const struct pinctrl_pin_desc byt_score_pins[] = { 113 PINCTRL_PIN(0, "SATA_GP0"), 114 PINCTRL_PIN(1, "SATA_GP1"), 115 PINCTRL_PIN(2, "SATA_LED#"), 116 PINCTRL_PIN(3, "PCIE_CLKREQ0"), 117 PINCTRL_PIN(4, "PCIE_CLKREQ1"), 118 PINCTRL_PIN(5, "PCIE_CLKREQ2"), 119 PINCTRL_PIN(6, "PCIE_CLKREQ3"), 120 PINCTRL_PIN(7, "SD3_WP"), 121 PINCTRL_PIN(8, "HDA_RST"), 122 PINCTRL_PIN(9, "HDA_SYNC"), 123 PINCTRL_PIN(10, "HDA_CLK"), 124 PINCTRL_PIN(11, "HDA_SDO"), 125 PINCTRL_PIN(12, "HDA_SDI0"), 126 PINCTRL_PIN(13, "HDA_SDI1"), 127 PINCTRL_PIN(14, "GPIO_S0_SC14"), 128 PINCTRL_PIN(15, "GPIO_S0_SC15"), 129 PINCTRL_PIN(16, "MMC1_CLK"), 130 PINCTRL_PIN(17, "MMC1_D0"), 131 PINCTRL_PIN(18, "MMC1_D1"), 132 PINCTRL_PIN(19, "MMC1_D2"), 133 PINCTRL_PIN(20, "MMC1_D3"), 134 PINCTRL_PIN(21, "MMC1_D4"), 135 PINCTRL_PIN(22, "MMC1_D5"), 136 PINCTRL_PIN(23, "MMC1_D6"), 137 PINCTRL_PIN(24, "MMC1_D7"), 138 PINCTRL_PIN(25, "MMC1_CMD"), 139 PINCTRL_PIN(26, "MMC1_RST"), 140 PINCTRL_PIN(27, "SD2_CLK"), 141 PINCTRL_PIN(28, "SD2_D0"), 142 PINCTRL_PIN(29, "SD2_D1"), 143 PINCTRL_PIN(30, "SD2_D2"), 144 PINCTRL_PIN(31, "SD2_D3_CD"), 145 PINCTRL_PIN(32, "SD2_CMD"), 146 PINCTRL_PIN(33, "SD3_CLK"), 147 PINCTRL_PIN(34, "SD3_D0"), 148 PINCTRL_PIN(35, "SD3_D1"), 149 PINCTRL_PIN(36, "SD3_D2"), 150 PINCTRL_PIN(37, "SD3_D3"), 151 PINCTRL_PIN(38, "SD3_CD"), 152 PINCTRL_PIN(39, "SD3_CMD"), 153 PINCTRL_PIN(40, "SD3_1P8EN"), 154 PINCTRL_PIN(41, "SD3_PWREN#"), 155 PINCTRL_PIN(42, "ILB_LPC_AD0"), 156 PINCTRL_PIN(43, "ILB_LPC_AD1"), 157 PINCTRL_PIN(44, "ILB_LPC_AD2"), 158 PINCTRL_PIN(45, "ILB_LPC_AD3"), 159 PINCTRL_PIN(46, "ILB_LPC_FRAME"), 160 PINCTRL_PIN(47, "ILB_LPC_CLK0"), 161 PINCTRL_PIN(48, "ILB_LPC_CLK1"), 162 PINCTRL_PIN(49, "ILB_LPC_CLKRUN"), 163 PINCTRL_PIN(50, "ILB_LPC_SERIRQ"), 164 PINCTRL_PIN(51, "PCU_SMB_DATA"), 165 PINCTRL_PIN(52, "PCU_SMB_CLK"), 166 PINCTRL_PIN(53, "PCU_SMB_ALERT"), 167 PINCTRL_PIN(54, "ILB_8254_SPKR"), 168 PINCTRL_PIN(55, "GPIO_S0_SC55"), 169 PINCTRL_PIN(56, "GPIO_S0_SC56"), 170 PINCTRL_PIN(57, "GPIO_S0_SC57"), 171 PINCTRL_PIN(58, "GPIO_S0_SC58"), 172 PINCTRL_PIN(59, "GPIO_S0_SC59"), 173 PINCTRL_PIN(60, "GPIO_S0_SC60"), 174 PINCTRL_PIN(61, "GPIO_S0_SC61"), 175 PINCTRL_PIN(62, "LPE_I2S2_CLK"), 176 PINCTRL_PIN(63, "LPE_I2S2_FRM"), 177 PINCTRL_PIN(64, "LPE_I2S2_DATAIN"), 178 PINCTRL_PIN(65, "LPE_I2S2_DATAOUT"), 179 PINCTRL_PIN(66, "SIO_SPI_CS"), 180 PINCTRL_PIN(67, "SIO_SPI_MISO"), 181 PINCTRL_PIN(68, "SIO_SPI_MOSI"), 182 PINCTRL_PIN(69, "SIO_SPI_CLK"), 183 PINCTRL_PIN(70, "SIO_UART1_RXD"), 184 PINCTRL_PIN(71, "SIO_UART1_TXD"), 185 PINCTRL_PIN(72, "SIO_UART1_RTS"), 186 PINCTRL_PIN(73, "SIO_UART1_CTS"), 187 PINCTRL_PIN(74, "SIO_UART2_RXD"), 188 PINCTRL_PIN(75, "SIO_UART2_TXD"), 189 PINCTRL_PIN(76, "SIO_UART2_RTS"), 190 PINCTRL_PIN(77, "SIO_UART2_CTS"), 191 PINCTRL_PIN(78, "SIO_I2C0_DATA"), 192 PINCTRL_PIN(79, "SIO_I2C0_CLK"), 193 PINCTRL_PIN(80, "SIO_I2C1_DATA"), 194 PINCTRL_PIN(81, "SIO_I2C1_CLK"), 195 PINCTRL_PIN(82, "SIO_I2C2_DATA"), 196 PINCTRL_PIN(83, "SIO_I2C2_CLK"), 197 PINCTRL_PIN(84, "SIO_I2C3_DATA"), 198 PINCTRL_PIN(85, "SIO_I2C3_CLK"), 199 PINCTRL_PIN(86, "SIO_I2C4_DATA"), 200 PINCTRL_PIN(87, "SIO_I2C4_CLK"), 201 PINCTRL_PIN(88, "SIO_I2C5_DATA"), 202 PINCTRL_PIN(89, "SIO_I2C5_CLK"), 203 PINCTRL_PIN(90, "SIO_I2C6_DATA"), 204 PINCTRL_PIN(91, "SIO_I2C6_CLK"), 205 PINCTRL_PIN(92, "GPIO_S0_SC92"), 206 PINCTRL_PIN(93, "GPIO_S0_SC93"), 207 PINCTRL_PIN(94, "SIO_PWM0"), 208 PINCTRL_PIN(95, "SIO_PWM1"), 209 PINCTRL_PIN(96, "PMC_PLT_CLK0"), 210 PINCTRL_PIN(97, "PMC_PLT_CLK1"), 211 PINCTRL_PIN(98, "PMC_PLT_CLK2"), 212 PINCTRL_PIN(99, "PMC_PLT_CLK3"), 213 PINCTRL_PIN(100, "PMC_PLT_CLK4"), 214 PINCTRL_PIN(101, "PMC_PLT_CLK5"), 215 }; 216 217 static const unsigned int byt_score_pins_map[BYT_NGPIO_SCORE] = { 218 85, 89, 93, 96, 99, 102, 98, 101, 34, 37, 219 36, 38, 39, 35, 40, 84, 62, 61, 64, 59, 220 54, 56, 60, 55, 63, 57, 51, 50, 53, 47, 221 52, 49, 48, 43, 46, 41, 45, 42, 58, 44, 222 95, 105, 70, 68, 67, 66, 69, 71, 65, 72, 223 86, 90, 88, 92, 103, 77, 79, 83, 78, 81, 224 80, 82, 13, 12, 15, 14, 17, 18, 19, 16, 225 2, 1, 0, 4, 6, 7, 9, 8, 33, 32, 226 31, 30, 29, 27, 25, 28, 26, 23, 21, 20, 227 24, 22, 5, 3, 10, 11, 106, 87, 91, 104, 228 97, 100, 229 }; 230 231 /* SCORE groups */ 232 static const unsigned int byt_score_uart1_pins[] = { 70, 71, 72, 73 }; 233 static const unsigned int byt_score_uart2_pins[] = { 74, 75, 76, 77 }; 234 static const unsigned int byt_score_uart3_pins[] = { 57, 61 }; 235 236 static const unsigned int byt_score_pwm0_pins[] = { 94 }; 237 static const unsigned int byt_score_pwm1_pins[] = { 95 }; 238 239 static const unsigned int byt_score_sio_spi_pins[] = { 66, 67, 68, 69 }; 240 241 static const unsigned int byt_score_i2c5_pins[] = { 88, 89 }; 242 static const unsigned int byt_score_i2c6_pins[] = { 90, 91 }; 243 static const unsigned int byt_score_i2c4_pins[] = { 86, 87 }; 244 static const unsigned int byt_score_i2c3_pins[] = { 84, 85 }; 245 static const unsigned int byt_score_i2c2_pins[] = { 82, 83 }; 246 static const unsigned int byt_score_i2c1_pins[] = { 80, 81 }; 247 static const unsigned int byt_score_i2c0_pins[] = { 78, 79 }; 248 249 static const unsigned int byt_score_ssp0_pins[] = { 8, 9, 10, 11 }; 250 static const unsigned int byt_score_ssp1_pins[] = { 12, 13, 14, 15 }; 251 static const unsigned int byt_score_ssp2_pins[] = { 62, 63, 64, 65 }; 252 253 static const unsigned int byt_score_sdcard_pins[] = { 254 7, 33, 34, 35, 36, 37, 38, 39, 40, 41, 255 }; 256 static const unsigned int byt_score_sdcard_mux_values[] = { 257 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 258 }; 259 260 static const unsigned int byt_score_sdio_pins[] = { 27, 28, 29, 30, 31, 32 }; 261 262 static const unsigned int byt_score_emmc_pins[] = { 263 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 264 }; 265 266 static const unsigned int byt_score_ilb_lpc_pins[] = { 267 42, 43, 44, 45, 46, 47, 48, 49, 50, 268 }; 269 270 static const unsigned int byt_score_sata_pins[] = { 0, 1, 2 }; 271 272 static const unsigned int byt_score_plt_clk0_pins[] = { 96 }; 273 static const unsigned int byt_score_plt_clk1_pins[] = { 97 }; 274 static const unsigned int byt_score_plt_clk2_pins[] = { 98 }; 275 static const unsigned int byt_score_plt_clk3_pins[] = { 99 }; 276 static const unsigned int byt_score_plt_clk4_pins[] = { 100 }; 277 static const unsigned int byt_score_plt_clk5_pins[] = { 101 }; 278 279 static const unsigned int byt_score_smbus_pins[] = { 51, 52, 53 }; 280 281 static const struct intel_pingroup byt_score_groups[] = { 282 PIN_GROUP_GPIO("uart1_grp", byt_score_uart1_pins, 1), 283 PIN_GROUP_GPIO("uart2_grp", byt_score_uart2_pins, 1), 284 PIN_GROUP_GPIO("uart3_grp", byt_score_uart3_pins, 1), 285 PIN_GROUP_GPIO("pwm0_grp", byt_score_pwm0_pins, 1), 286 PIN_GROUP_GPIO("pwm1_grp", byt_score_pwm1_pins, 1), 287 PIN_GROUP_GPIO("ssp2_grp", byt_score_ssp2_pins, 1), 288 PIN_GROUP_GPIO("sio_spi_grp", byt_score_sio_spi_pins, 1), 289 PIN_GROUP_GPIO("i2c5_grp", byt_score_i2c5_pins, 1), 290 PIN_GROUP_GPIO("i2c6_grp", byt_score_i2c6_pins, 1), 291 PIN_GROUP_GPIO("i2c4_grp", byt_score_i2c4_pins, 1), 292 PIN_GROUP_GPIO("i2c3_grp", byt_score_i2c3_pins, 1), 293 PIN_GROUP_GPIO("i2c2_grp", byt_score_i2c2_pins, 1), 294 PIN_GROUP_GPIO("i2c1_grp", byt_score_i2c1_pins, 1), 295 PIN_GROUP_GPIO("i2c0_grp", byt_score_i2c0_pins, 1), 296 PIN_GROUP_GPIO("ssp0_grp", byt_score_ssp0_pins, 1), 297 PIN_GROUP_GPIO("ssp1_grp", byt_score_ssp1_pins, 1), 298 PIN_GROUP_GPIO("sdcard_grp", byt_score_sdcard_pins, byt_score_sdcard_mux_values), 299 PIN_GROUP_GPIO("sdio_grp", byt_score_sdio_pins, 1), 300 PIN_GROUP_GPIO("emmc_grp", byt_score_emmc_pins, 1), 301 PIN_GROUP_GPIO("lpc_grp", byt_score_ilb_lpc_pins, 1), 302 PIN_GROUP_GPIO("sata_grp", byt_score_sata_pins, 1), 303 PIN_GROUP_GPIO("plt_clk0_grp", byt_score_plt_clk0_pins, 1), 304 PIN_GROUP_GPIO("plt_clk1_grp", byt_score_plt_clk1_pins, 1), 305 PIN_GROUP_GPIO("plt_clk2_grp", byt_score_plt_clk2_pins, 1), 306 PIN_GROUP_GPIO("plt_clk3_grp", byt_score_plt_clk3_pins, 1), 307 PIN_GROUP_GPIO("plt_clk4_grp", byt_score_plt_clk4_pins, 1), 308 PIN_GROUP_GPIO("plt_clk5_grp", byt_score_plt_clk5_pins, 1), 309 PIN_GROUP_GPIO("smbus_grp", byt_score_smbus_pins, 1), 310 }; 311 312 static const char * const byt_score_uart_groups[] = { 313 "uart1_grp", "uart2_grp", "uart3_grp", 314 }; 315 static const char * const byt_score_pwm_groups[] = { 316 "pwm0_grp", "pwm1_grp", 317 }; 318 static const char * const byt_score_ssp_groups[] = { 319 "ssp0_grp", "ssp1_grp", "ssp2_grp", 320 }; 321 static const char * const byt_score_spi_groups[] = { "sio_spi_grp" }; 322 static const char * const byt_score_i2c_groups[] = { 323 "i2c0_grp", "i2c1_grp", "i2c2_grp", "i2c3_grp", "i2c4_grp", "i2c5_grp", 324 "i2c6_grp", 325 }; 326 static const char * const byt_score_sdcard_groups[] = { "sdcard_grp" }; 327 static const char * const byt_score_sdio_groups[] = { "sdio_grp" }; 328 static const char * const byt_score_emmc_groups[] = { "emmc_grp" }; 329 static const char * const byt_score_lpc_groups[] = { "lpc_grp" }; 330 static const char * const byt_score_sata_groups[] = { "sata_grp" }; 331 static const char * const byt_score_plt_clk_groups[] = { 332 "plt_clk0_grp", "plt_clk1_grp", "plt_clk2_grp", "plt_clk3_grp", 333 "plt_clk4_grp", "plt_clk5_grp", 334 }; 335 static const char * const byt_score_smbus_groups[] = { "smbus_grp" }; 336 static const char * const byt_score_gpio_groups[] = { 337 "uart1_grp_gpio", "uart2_grp_gpio", "uart3_grp_gpio", "pwm0_grp_gpio", 338 "pwm1_grp_gpio", "ssp0_grp_gpio", "ssp1_grp_gpio", "ssp2_grp_gpio", 339 "sio_spi_grp_gpio", "i2c0_grp_gpio", "i2c1_grp_gpio", "i2c2_grp_gpio", 340 "i2c3_grp_gpio", "i2c4_grp_gpio", "i2c5_grp_gpio", "i2c6_grp_gpio", 341 "sdcard_grp_gpio", "sdio_grp_gpio", "emmc_grp_gpio", "lpc_grp_gpio", 342 "sata_grp_gpio", "plt_clk0_grp_gpio", "plt_clk1_grp_gpio", 343 "plt_clk2_grp_gpio", "plt_clk3_grp_gpio", "plt_clk4_grp_gpio", 344 "plt_clk5_grp_gpio", "smbus_grp_gpio", 345 }; 346 347 static const struct intel_function byt_score_functions[] = { 348 FUNCTION("uart", byt_score_uart_groups), 349 FUNCTION("pwm", byt_score_pwm_groups), 350 FUNCTION("ssp", byt_score_ssp_groups), 351 FUNCTION("spi", byt_score_spi_groups), 352 FUNCTION("i2c", byt_score_i2c_groups), 353 FUNCTION("sdcard", byt_score_sdcard_groups), 354 FUNCTION("sdio", byt_score_sdio_groups), 355 FUNCTION("emmc", byt_score_emmc_groups), 356 FUNCTION("lpc", byt_score_lpc_groups), 357 FUNCTION("sata", byt_score_sata_groups), 358 FUNCTION("plt_clk", byt_score_plt_clk_groups), 359 FUNCTION("smbus", byt_score_smbus_groups), 360 FUNCTION("gpio", byt_score_gpio_groups), 361 }; 362 363 static const struct intel_community byt_score_communities[] = { 364 COMMUNITY(0, BYT_NGPIO_SCORE, byt_score_pins_map), 365 }; 366 367 static const struct intel_pinctrl_soc_data byt_score_soc_data = { 368 .uid = BYT_SCORE_ACPI_UID, 369 .pins = byt_score_pins, 370 .npins = ARRAY_SIZE(byt_score_pins), 371 .groups = byt_score_groups, 372 .ngroups = ARRAY_SIZE(byt_score_groups), 373 .functions = byt_score_functions, 374 .nfunctions = ARRAY_SIZE(byt_score_functions), 375 .communities = byt_score_communities, 376 .ncommunities = ARRAY_SIZE(byt_score_communities), 377 }; 378 379 /* SUS pins, aka GPIOS_<pin_no> or GPIO_S5[<pin_no>] */ 380 static const struct pinctrl_pin_desc byt_sus_pins[] = { 381 PINCTRL_PIN(0, "GPIO_S50"), 382 PINCTRL_PIN(1, "GPIO_S51"), 383 PINCTRL_PIN(2, "GPIO_S52"), 384 PINCTRL_PIN(3, "GPIO_S53"), 385 PINCTRL_PIN(4, "GPIO_S54"), 386 PINCTRL_PIN(5, "GPIO_S55"), 387 PINCTRL_PIN(6, "GPIO_S56"), 388 PINCTRL_PIN(7, "GPIO_S57"), 389 PINCTRL_PIN(8, "GPIO_S58"), 390 PINCTRL_PIN(9, "GPIO_S59"), 391 PINCTRL_PIN(10, "GPIO_S510"), 392 PINCTRL_PIN(11, "PMC_SUSPWRDNACK"), 393 PINCTRL_PIN(12, "PMC_SUSCLK0"), 394 PINCTRL_PIN(13, "GPIO_S513"), 395 PINCTRL_PIN(14, "USB_ULPI_RST"), 396 PINCTRL_PIN(15, "PMC_WAKE_PCIE0#"), 397 PINCTRL_PIN(16, "PMC_PWRBTN"), 398 PINCTRL_PIN(17, "GPIO_S517"), 399 PINCTRL_PIN(18, "PMC_SUS_STAT"), 400 PINCTRL_PIN(19, "USB_OC0"), 401 PINCTRL_PIN(20, "USB_OC1"), 402 PINCTRL_PIN(21, "PCU_SPI_CS1"), 403 PINCTRL_PIN(22, "GPIO_S522"), 404 PINCTRL_PIN(23, "GPIO_S523"), 405 PINCTRL_PIN(24, "GPIO_S524"), 406 PINCTRL_PIN(25, "GPIO_S525"), 407 PINCTRL_PIN(26, "GPIO_S526"), 408 PINCTRL_PIN(27, "GPIO_S527"), 409 PINCTRL_PIN(28, "GPIO_S528"), 410 PINCTRL_PIN(29, "GPIO_S529"), 411 PINCTRL_PIN(30, "GPIO_S530"), 412 PINCTRL_PIN(31, "USB_ULPI_CLK"), 413 PINCTRL_PIN(32, "USB_ULPI_DATA0"), 414 PINCTRL_PIN(33, "USB_ULPI_DATA1"), 415 PINCTRL_PIN(34, "USB_ULPI_DATA2"), 416 PINCTRL_PIN(35, "USB_ULPI_DATA3"), 417 PINCTRL_PIN(36, "USB_ULPI_DATA4"), 418 PINCTRL_PIN(37, "USB_ULPI_DATA5"), 419 PINCTRL_PIN(38, "USB_ULPI_DATA6"), 420 PINCTRL_PIN(39, "USB_ULPI_DATA7"), 421 PINCTRL_PIN(40, "USB_ULPI_DIR"), 422 PINCTRL_PIN(41, "USB_ULPI_NXT"), 423 PINCTRL_PIN(42, "USB_ULPI_STP"), 424 PINCTRL_PIN(43, "USB_ULPI_REFCLK"), 425 }; 426 427 static const unsigned int byt_sus_pins_map[BYT_NGPIO_SUS] = { 428 29, 33, 30, 31, 32, 34, 36, 35, 38, 37, 429 18, 7, 11, 20, 17, 1, 8, 10, 19, 12, 430 0, 2, 23, 39, 28, 27, 22, 21, 24, 25, 431 26, 51, 56, 54, 49, 55, 48, 57, 50, 58, 432 52, 53, 59, 40, 433 }; 434 435 static const unsigned int byt_sus_usb_over_current_pins[] = { 19, 20 }; 436 static const unsigned int byt_sus_usb_over_current_mode_values[] = { 0, 0 }; 437 static const unsigned int byt_sus_usb_over_current_gpio_mode_values[] = { 1, 1 }; 438 439 static const unsigned int byt_sus_usb_ulpi_pins[] = { 440 14, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 441 }; 442 static const unsigned int byt_sus_usb_ulpi_mode_values[] = { 443 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 444 }; 445 static const unsigned int byt_sus_usb_ulpi_gpio_mode_values[] = { 446 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 447 }; 448 449 static const unsigned int byt_sus_pcu_spi_pins[] = { 21 }; 450 static const unsigned int byt_sus_pcu_spi_mode_values[] = { 0 }; 451 static const unsigned int byt_sus_pcu_spi_gpio_mode_values[] = { 1 }; 452 453 static const unsigned int byt_sus_pmu_clk1_pins[] = { 5 }; 454 static const unsigned int byt_sus_pmu_clk2_pins[] = { 6 }; 455 456 static const struct intel_pingroup byt_sus_groups[] = { 457 PIN_GROUP("usb_oc_grp", byt_sus_usb_over_current_pins, byt_sus_usb_over_current_mode_values), 458 PIN_GROUP("usb_ulpi_grp", byt_sus_usb_ulpi_pins, byt_sus_usb_ulpi_mode_values), 459 PIN_GROUP("pcu_spi_grp", byt_sus_pcu_spi_pins, byt_sus_pcu_spi_mode_values), 460 PIN_GROUP("usb_oc_grp_gpio", byt_sus_usb_over_current_pins, byt_sus_usb_over_current_gpio_mode_values), 461 PIN_GROUP("usb_ulpi_grp_gpio", byt_sus_usb_ulpi_pins, byt_sus_usb_ulpi_gpio_mode_values), 462 PIN_GROUP("pcu_spi_grp_gpio", byt_sus_pcu_spi_pins, byt_sus_pcu_spi_gpio_mode_values), 463 PIN_GROUP_GPIO("pmu_clk1_grp", byt_sus_pmu_clk1_pins, 1), 464 PIN_GROUP_GPIO("pmu_clk2_grp", byt_sus_pmu_clk2_pins, 1), 465 }; 466 467 static const char * const byt_sus_usb_groups[] = { 468 "usb_oc_grp", "usb_ulpi_grp", 469 }; 470 static const char * const byt_sus_spi_groups[] = { "pcu_spi_grp" }; 471 static const char * const byt_sus_pmu_clk_groups[] = { 472 "pmu_clk1_grp", "pmu_clk2_grp", 473 }; 474 static const char * const byt_sus_gpio_groups[] = { 475 "usb_oc_grp_gpio", "usb_ulpi_grp_gpio", "pcu_spi_grp_gpio", 476 "pmu_clk1_grp_gpio", "pmu_clk2_grp_gpio", 477 }; 478 479 static const struct intel_function byt_sus_functions[] = { 480 FUNCTION("usb", byt_sus_usb_groups), 481 FUNCTION("spi", byt_sus_spi_groups), 482 FUNCTION("gpio", byt_sus_gpio_groups), 483 FUNCTION("pmu_clk", byt_sus_pmu_clk_groups), 484 }; 485 486 static const struct intel_community byt_sus_communities[] = { 487 COMMUNITY(0, BYT_NGPIO_SUS, byt_sus_pins_map), 488 }; 489 490 static const struct intel_pinctrl_soc_data byt_sus_soc_data = { 491 .uid = BYT_SUS_ACPI_UID, 492 .pins = byt_sus_pins, 493 .npins = ARRAY_SIZE(byt_sus_pins), 494 .groups = byt_sus_groups, 495 .ngroups = ARRAY_SIZE(byt_sus_groups), 496 .functions = byt_sus_functions, 497 .nfunctions = ARRAY_SIZE(byt_sus_functions), 498 .communities = byt_sus_communities, 499 .ncommunities = ARRAY_SIZE(byt_sus_communities), 500 }; 501 502 static const struct pinctrl_pin_desc byt_ncore_pins[] = { 503 PINCTRL_PIN(0, "HV_DDI0_HPD"), 504 PINCTRL_PIN(1, "HV_DDI0_DDC_SDA"), 505 PINCTRL_PIN(2, "HV_DDI0_DDC_SCL"), 506 PINCTRL_PIN(3, "PANEL0_VDDEN"), 507 PINCTRL_PIN(4, "PANEL0_BKLTEN"), 508 PINCTRL_PIN(5, "PANEL0_BKLTCTL"), 509 PINCTRL_PIN(6, "HV_DDI1_HPD"), 510 PINCTRL_PIN(7, "HV_DDI1_DDC_SDA"), 511 PINCTRL_PIN(8, "HV_DDI1_DDC_SCL"), 512 PINCTRL_PIN(9, "PANEL1_VDDEN"), 513 PINCTRL_PIN(10, "PANEL1_BKLTEN"), 514 PINCTRL_PIN(11, "PANEL1_BKLTCTL"), 515 PINCTRL_PIN(12, "GP_INTD_DSI_TE1"), 516 PINCTRL_PIN(13, "HV_DDI2_DDC_SDA"), 517 PINCTRL_PIN(14, "HV_DDI2_DDC_SCL"), 518 PINCTRL_PIN(15, "GP_CAMERASB00"), 519 PINCTRL_PIN(16, "GP_CAMERASB01"), 520 PINCTRL_PIN(17, "GP_CAMERASB02"), 521 PINCTRL_PIN(18, "GP_CAMERASB03"), 522 PINCTRL_PIN(19, "GP_CAMERASB04"), 523 PINCTRL_PIN(20, "GP_CAMERASB05"), 524 PINCTRL_PIN(21, "GP_CAMERASB06"), 525 PINCTRL_PIN(22, "GP_CAMERASB07"), 526 PINCTRL_PIN(23, "GP_CAMERASB08"), 527 PINCTRL_PIN(24, "GP_CAMERASB09"), 528 PINCTRL_PIN(25, "GP_CAMERASB10"), 529 PINCTRL_PIN(26, "GP_CAMERASB11"), 530 PINCTRL_PIN(27, "GP_INTD_DSI_TE2"), 531 }; 532 533 static const unsigned int byt_ncore_pins_map[BYT_NGPIO_NCORE] = { 534 19, 18, 17, 20, 21, 22, 24, 25, 23, 16, 535 14, 15, 12, 26, 27, 1, 4, 8, 11, 0, 536 3, 6, 10, 13, 2, 5, 9, 7, 537 }; 538 539 static const struct intel_community byt_ncore_communities[] = { 540 COMMUNITY(0, BYT_NGPIO_NCORE, byt_ncore_pins_map), 541 }; 542 543 static const struct intel_pinctrl_soc_data byt_ncore_soc_data = { 544 .uid = BYT_NCORE_ACPI_UID, 545 .pins = byt_ncore_pins, 546 .npins = ARRAY_SIZE(byt_ncore_pins), 547 .communities = byt_ncore_communities, 548 .ncommunities = ARRAY_SIZE(byt_ncore_communities), 549 }; 550 551 static const struct intel_pinctrl_soc_data *byt_soc_data[] = { 552 &byt_score_soc_data, 553 &byt_sus_soc_data, 554 &byt_ncore_soc_data, 555 NULL 556 }; 557 558 static DEFINE_RAW_SPINLOCK(byt_lock); 559 560 static void __iomem *byt_gpio_reg(struct intel_pinctrl *vg, unsigned int offset, 561 int reg) 562 { 563 const struct intel_community *comm; 564 u32 reg_offset; 565 566 comm = intel_get_community(vg, offset); 567 if (!comm) 568 return NULL; 569 570 offset -= comm->pin_base; 571 switch (reg) { 572 case BYT_INT_STAT_REG: 573 reg_offset = (offset / 32) * 4; 574 break; 575 case BYT_DEBOUNCE_REG: 576 reg_offset = 0; 577 break; 578 default: 579 reg_offset = comm->pad_map[offset] * 16; 580 break; 581 } 582 583 return comm->pad_regs + reg_offset + reg; 584 } 585 586 static const struct pinctrl_ops byt_pinctrl_ops = { 587 .get_groups_count = intel_get_groups_count, 588 .get_group_name = intel_get_group_name, 589 .get_group_pins = intel_get_group_pins, 590 }; 591 592 static void byt_set_group_simple_mux(struct intel_pinctrl *vg, 593 const struct intel_pingroup group, 594 unsigned int func) 595 { 596 int i; 597 598 guard(raw_spinlock_irqsave)(&byt_lock); 599 600 for (i = 0; i < group.grp.npins; i++) { 601 void __iomem *padcfg0; 602 u32 value; 603 604 padcfg0 = byt_gpio_reg(vg, group.grp.pins[i], BYT_CONF0_REG); 605 if (!padcfg0) { 606 dev_warn(vg->dev, "Group %s, pin %i not muxed (can't retrieve CONF0)\n", 607 group.grp.name, i); 608 continue; 609 } 610 611 value = readl(padcfg0); 612 value &= ~BYT_PIN_MUX; 613 value |= func; 614 writel(value, padcfg0); 615 } 616 } 617 618 static void byt_set_group_mixed_mux(struct intel_pinctrl *vg, 619 const struct intel_pingroup group, 620 const unsigned int *func) 621 { 622 int i; 623 624 guard(raw_spinlock_irqsave)(&byt_lock); 625 626 for (i = 0; i < group.grp.npins; i++) { 627 void __iomem *padcfg0; 628 u32 value; 629 630 padcfg0 = byt_gpio_reg(vg, group.grp.pins[i], BYT_CONF0_REG); 631 if (!padcfg0) { 632 dev_warn(vg->dev, "Group %s, pin %i not muxed (can't retrieve CONF0)\n", 633 group.grp.name, i); 634 continue; 635 } 636 637 value = readl(padcfg0); 638 value &= ~BYT_PIN_MUX; 639 value |= func[i]; 640 writel(value, padcfg0); 641 } 642 } 643 644 static int byt_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector, 645 unsigned int group_selector) 646 { 647 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev); 648 const struct intel_function func = vg->soc->functions[func_selector]; 649 const struct intel_pingroup group = vg->soc->groups[group_selector]; 650 651 if (group.modes) 652 byt_set_group_mixed_mux(vg, group, group.modes); 653 else if (!strcmp(func.func.name, "gpio")) 654 byt_set_group_simple_mux(vg, group, BYT_DEFAULT_GPIO_MUX); 655 else 656 byt_set_group_simple_mux(vg, group, group.mode); 657 658 return 0; 659 } 660 661 static u32 byt_get_gpio_mux(struct intel_pinctrl *vg, unsigned int offset) 662 { 663 /* SCORE pin 92-93 */ 664 if (!strcmp(vg->soc->uid, BYT_SCORE_ACPI_UID) && 665 offset >= 92 && offset <= 93) 666 return BYT_ALTER_GPIO_MUX; 667 668 /* SUS pin 11-21 */ 669 if (!strcmp(vg->soc->uid, BYT_SUS_ACPI_UID) && 670 offset >= 11 && offset <= 21) 671 return BYT_ALTER_GPIO_MUX; 672 673 return BYT_DEFAULT_GPIO_MUX; 674 } 675 676 static void byt_gpio_clear_triggering(struct intel_pinctrl *vg, unsigned int offset) 677 { 678 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); 679 u32 value; 680 681 guard(raw_spinlock_irqsave)(&byt_lock); 682 683 value = readl(reg); 684 685 /* Do not clear direct-irq enabled IRQs (from gpio_disable_free) */ 686 if (!(value & BYT_DIRECT_IRQ_EN)) 687 value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL); 688 689 writel(value, reg); 690 } 691 692 static int byt_gpio_request_enable(struct pinctrl_dev *pctl_dev, 693 struct pinctrl_gpio_range *range, 694 unsigned int offset) 695 { 696 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev); 697 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); 698 u32 value, gpio_mux; 699 700 guard(raw_spinlock_irqsave)(&byt_lock); 701 702 /* 703 * In most cases, func pin mux 000 means GPIO function. 704 * But, some pins may have func pin mux 001 represents 705 * GPIO function. 706 * 707 * Because there are devices out there where some pins were not 708 * configured correctly we allow changing the mux value from 709 * request (but print out warning about that). 710 */ 711 value = readl(reg) & BYT_PIN_MUX; 712 gpio_mux = byt_get_gpio_mux(vg, offset); 713 if (gpio_mux == value) 714 return 0; 715 716 value = readl(reg) & ~BYT_PIN_MUX; 717 value |= gpio_mux; 718 writel(value, reg); 719 720 dev_warn(vg->dev, FW_BUG "Pin %i: forcibly re-configured as GPIO\n", offset); 721 722 return 0; 723 } 724 725 static void byt_gpio_disable_free(struct pinctrl_dev *pctl_dev, 726 struct pinctrl_gpio_range *range, 727 unsigned int offset) 728 { 729 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev); 730 731 byt_gpio_clear_triggering(vg, offset); 732 } 733 734 static void byt_gpio_direct_irq_check(struct intel_pinctrl *vg, 735 unsigned int offset) 736 { 737 void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); 738 739 /* 740 * Before making any direction modifications, do a check if gpio is set 741 * for direct IRQ. On Bay Trail, setting GPIO to output does not make 742 * sense, so let's at least inform the caller before they shoot 743 * themselves in the foot. 744 */ 745 if (readl(conf_reg) & BYT_DIRECT_IRQ_EN) 746 dev_info_once(vg->dev, 747 "Potential Error: Pin %i: forcibly set GPIO with DIRECT_IRQ_EN to output\n", 748 offset); 749 } 750 751 static int byt_gpio_set_direction(struct pinctrl_dev *pctl_dev, 752 struct pinctrl_gpio_range *range, 753 unsigned int offset, 754 bool input) 755 { 756 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev); 757 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); 758 u32 value; 759 760 guard(raw_spinlock_irqsave)(&byt_lock); 761 762 value = readl(val_reg); 763 value &= ~BYT_DIR_MASK; 764 if (input) 765 value |= BYT_OUTPUT_EN; 766 else 767 byt_gpio_direct_irq_check(vg, offset); 768 769 writel(value, val_reg); 770 771 return 0; 772 } 773 774 static const struct pinmux_ops byt_pinmux_ops = { 775 .get_functions_count = intel_get_functions_count, 776 .get_function_name = intel_get_function_name, 777 .get_function_groups = intel_get_function_groups, 778 .set_mux = byt_set_mux, 779 .gpio_request_enable = byt_gpio_request_enable, 780 .gpio_disable_free = byt_gpio_disable_free, 781 .gpio_set_direction = byt_gpio_set_direction, 782 }; 783 784 static void byt_get_pull_strength(u32 reg, u16 *strength) 785 { 786 switch (reg & BYT_PULL_STR_MASK) { 787 case BYT_PULL_STR_2K: 788 *strength = 2000; 789 break; 790 case BYT_PULL_STR_10K: 791 *strength = 10000; 792 break; 793 case BYT_PULL_STR_20K: 794 *strength = 20000; 795 break; 796 case BYT_PULL_STR_40K: 797 *strength = 40000; 798 break; 799 } 800 } 801 802 static int byt_set_pull_strength(u32 *reg, u16 strength) 803 { 804 *reg &= ~BYT_PULL_STR_MASK; 805 806 switch (strength) { 807 case 1: /* Set default strength value in case none is given */ 808 case 2000: 809 *reg |= BYT_PULL_STR_2K; 810 break; 811 case 10000: 812 *reg |= BYT_PULL_STR_10K; 813 break; 814 case 20000: 815 *reg |= BYT_PULL_STR_20K; 816 break; 817 case 40000: 818 *reg |= BYT_PULL_STR_40K; 819 break; 820 default: 821 return -EINVAL; 822 } 823 824 return 0; 825 } 826 827 static void byt_gpio_force_input_mode(struct intel_pinctrl *vg, unsigned int offset) 828 { 829 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); 830 u32 value; 831 832 value = readl(reg); 833 if (!(value & BYT_INPUT_EN)) 834 return; 835 836 /* 837 * Pull assignment is only applicable in input mode. If 838 * chip is not in input mode, set it and warn about it. 839 */ 840 value &= ~BYT_INPUT_EN; 841 writel(value, reg); 842 dev_warn(vg->dev, "Pin %i: forcibly set to input mode\n", offset); 843 } 844 845 static int byt_pin_config_get(struct pinctrl_dev *pctl_dev, unsigned int offset, 846 unsigned long *config) 847 { 848 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev); 849 enum pin_config_param param = pinconf_to_config_param(*config); 850 void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); 851 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); 852 void __iomem *db_reg = byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG); 853 u32 conf, pull, val, debounce; 854 u16 arg = 0; 855 856 scoped_guard(raw_spinlock_irqsave, &byt_lock) { 857 conf = readl(conf_reg); 858 val = readl(val_reg); 859 } 860 861 pull = conf & BYT_PULL_ASSIGN_MASK; 862 863 switch (param) { 864 case PIN_CONFIG_BIAS_DISABLE: 865 if (pull) 866 return -EINVAL; 867 break; 868 case PIN_CONFIG_BIAS_PULL_DOWN: 869 /* Pull assignment is only applicable in input mode */ 870 if ((val & BYT_INPUT_EN) || pull != BYT_PULL_ASSIGN_DOWN) 871 return -EINVAL; 872 873 byt_get_pull_strength(conf, &arg); 874 875 break; 876 case PIN_CONFIG_BIAS_PULL_UP: 877 /* Pull assignment is only applicable in input mode */ 878 if ((val & BYT_INPUT_EN) || pull != BYT_PULL_ASSIGN_UP) 879 return -EINVAL; 880 881 byt_get_pull_strength(conf, &arg); 882 883 break; 884 case PIN_CONFIG_INPUT_DEBOUNCE: 885 if (!(conf & BYT_DEBOUNCE_EN)) 886 return -EINVAL; 887 888 scoped_guard(raw_spinlock_irqsave, &byt_lock) 889 debounce = readl(db_reg); 890 891 switch (debounce & BYT_DEBOUNCE_PULSE_MASK) { 892 case BYT_DEBOUNCE_PULSE_375US: 893 arg = 375; 894 break; 895 case BYT_DEBOUNCE_PULSE_750US: 896 arg = 750; 897 break; 898 case BYT_DEBOUNCE_PULSE_1500US: 899 arg = 1500; 900 break; 901 case BYT_DEBOUNCE_PULSE_3MS: 902 arg = 3000; 903 break; 904 case BYT_DEBOUNCE_PULSE_6MS: 905 arg = 6000; 906 break; 907 case BYT_DEBOUNCE_PULSE_12MS: 908 arg = 12000; 909 break; 910 case BYT_DEBOUNCE_PULSE_24MS: 911 arg = 24000; 912 break; 913 default: 914 return -EINVAL; 915 } 916 917 break; 918 default: 919 return -ENOTSUPP; 920 } 921 922 *config = pinconf_to_config_packed(param, arg); 923 924 return 0; 925 } 926 927 static int byt_pin_config_set(struct pinctrl_dev *pctl_dev, 928 unsigned int offset, 929 unsigned long *configs, 930 unsigned int num_configs) 931 { 932 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev); 933 void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); 934 void __iomem *db_reg = byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG); 935 u32 conf, db_pulse, debounce; 936 enum pin_config_param param; 937 int i, ret; 938 u32 arg; 939 940 guard(raw_spinlock_irqsave)(&byt_lock); 941 942 conf = readl(conf_reg); 943 944 for (i = 0; i < num_configs; i++) { 945 param = pinconf_to_config_param(configs[i]); 946 arg = pinconf_to_config_argument(configs[i]); 947 948 switch (param) { 949 case PIN_CONFIG_BIAS_DISABLE: 950 conf &= ~BYT_PULL_ASSIGN_MASK; 951 break; 952 case PIN_CONFIG_BIAS_PULL_DOWN: 953 byt_gpio_force_input_mode(vg, offset); 954 955 conf &= ~BYT_PULL_ASSIGN_MASK; 956 conf |= BYT_PULL_ASSIGN_DOWN; 957 ret = byt_set_pull_strength(&conf, arg); 958 if (ret) 959 return ret; 960 961 break; 962 case PIN_CONFIG_BIAS_PULL_UP: 963 byt_gpio_force_input_mode(vg, offset); 964 965 conf &= ~BYT_PULL_ASSIGN_MASK; 966 conf |= BYT_PULL_ASSIGN_UP; 967 ret = byt_set_pull_strength(&conf, arg); 968 if (ret) 969 return ret; 970 971 break; 972 case PIN_CONFIG_INPUT_DEBOUNCE: 973 switch (arg) { 974 case 0: 975 db_pulse = 0; 976 break; 977 case 375: 978 db_pulse = BYT_DEBOUNCE_PULSE_375US; 979 break; 980 case 750: 981 db_pulse = BYT_DEBOUNCE_PULSE_750US; 982 break; 983 case 1500: 984 db_pulse = BYT_DEBOUNCE_PULSE_1500US; 985 break; 986 case 3000: 987 db_pulse = BYT_DEBOUNCE_PULSE_3MS; 988 break; 989 case 6000: 990 db_pulse = BYT_DEBOUNCE_PULSE_6MS; 991 break; 992 case 12000: 993 db_pulse = BYT_DEBOUNCE_PULSE_12MS; 994 break; 995 case 24000: 996 db_pulse = BYT_DEBOUNCE_PULSE_24MS; 997 break; 998 default: 999 return -EINVAL; 1000 } 1001 1002 if (db_pulse) { 1003 debounce = readl(db_reg); 1004 debounce = (debounce & ~BYT_DEBOUNCE_PULSE_MASK) | db_pulse; 1005 writel(debounce, db_reg); 1006 1007 conf |= BYT_DEBOUNCE_EN; 1008 } else { 1009 conf &= ~BYT_DEBOUNCE_EN; 1010 } 1011 1012 break; 1013 default: 1014 return -ENOTSUPP; 1015 } 1016 } 1017 1018 writel(conf, conf_reg); 1019 1020 return 0; 1021 } 1022 1023 static const struct pinconf_ops byt_pinconf_ops = { 1024 .is_generic = true, 1025 .pin_config_get = byt_pin_config_get, 1026 .pin_config_set = byt_pin_config_set, 1027 }; 1028 1029 static const struct pinctrl_desc byt_pinctrl_desc = { 1030 .pctlops = &byt_pinctrl_ops, 1031 .pmxops = &byt_pinmux_ops, 1032 .confops = &byt_pinconf_ops, 1033 .owner = THIS_MODULE, 1034 }; 1035 1036 static int byt_gpio_get(struct gpio_chip *chip, unsigned int offset) 1037 { 1038 struct intel_pinctrl *vg = gpiochip_get_data(chip); 1039 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); 1040 u32 val; 1041 1042 scoped_guard(raw_spinlock_irqsave, &byt_lock) 1043 val = readl(reg); 1044 1045 return !!(val & BYT_LEVEL); 1046 } 1047 1048 static void byt_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) 1049 { 1050 struct intel_pinctrl *vg = gpiochip_get_data(chip); 1051 void __iomem *reg; 1052 u32 old_val; 1053 1054 reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); 1055 if (!reg) 1056 return; 1057 1058 guard(raw_spinlock_irqsave)(&byt_lock); 1059 1060 old_val = readl(reg); 1061 if (value) 1062 writel(old_val | BYT_LEVEL, reg); 1063 else 1064 writel(old_val & ~BYT_LEVEL, reg); 1065 } 1066 1067 static int byt_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 1068 { 1069 struct intel_pinctrl *vg = gpiochip_get_data(chip); 1070 void __iomem *reg; 1071 u32 value; 1072 1073 reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); 1074 if (!reg) 1075 return -EINVAL; 1076 1077 scoped_guard(raw_spinlock_irqsave, &byt_lock) 1078 value = readl(reg); 1079 1080 if (!(value & BYT_OUTPUT_EN)) 1081 return GPIO_LINE_DIRECTION_OUT; 1082 if (!(value & BYT_INPUT_EN)) 1083 return GPIO_LINE_DIRECTION_IN; 1084 1085 return -EINVAL; 1086 } 1087 1088 static int byt_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) 1089 { 1090 struct intel_pinctrl *vg = gpiochip_get_data(chip); 1091 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); 1092 u32 reg; 1093 1094 guard(raw_spinlock_irqsave)(&byt_lock); 1095 1096 reg = readl(val_reg); 1097 reg &= ~BYT_DIR_MASK; 1098 reg |= BYT_OUTPUT_EN; 1099 writel(reg, val_reg); 1100 1101 return 0; 1102 } 1103 1104 /* 1105 * Note despite the temptation this MUST NOT be converted into a call to 1106 * pinctrl_gpio_direction_output() + byt_gpio_set() that does not work this 1107 * MUST be done as a single BYT_VAL_REG register write. 1108 * See the commit message of the commit adding this comment for details. 1109 */ 1110 static int byt_gpio_direction_output(struct gpio_chip *chip, 1111 unsigned int offset, int value) 1112 { 1113 struct intel_pinctrl *vg = gpiochip_get_data(chip); 1114 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); 1115 u32 reg; 1116 1117 guard(raw_spinlock_irqsave)(&byt_lock); 1118 1119 byt_gpio_direct_irq_check(vg, offset); 1120 1121 reg = readl(val_reg); 1122 reg &= ~BYT_DIR_MASK; 1123 if (value) 1124 reg |= BYT_LEVEL; 1125 else 1126 reg &= ~BYT_LEVEL; 1127 1128 writel(reg, val_reg); 1129 1130 return 0; 1131 } 1132 1133 static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 1134 { 1135 struct intel_pinctrl *vg = gpiochip_get_data(chip); 1136 int i; 1137 u32 conf0, val; 1138 1139 for (i = 0; i < vg->soc->npins; i++) { 1140 const struct intel_community *comm; 1141 void __iomem *conf_reg, *val_reg; 1142 const char *pull_str = NULL; 1143 const char *pull = NULL; 1144 unsigned int pin; 1145 1146 pin = vg->soc->pins[i].number; 1147 1148 conf_reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG); 1149 if (!conf_reg) { 1150 seq_printf(s, "Pin %i: can't retrieve CONF0\n", pin); 1151 continue; 1152 } 1153 1154 val_reg = byt_gpio_reg(vg, pin, BYT_VAL_REG); 1155 if (!val_reg) { 1156 seq_printf(s, "Pin %i: can't retrieve VAL\n", pin); 1157 continue; 1158 } 1159 1160 scoped_guard(raw_spinlock_irqsave, &byt_lock) { 1161 conf0 = readl(conf_reg); 1162 val = readl(val_reg); 1163 } 1164 1165 comm = intel_get_community(vg, pin); 1166 if (!comm) { 1167 seq_printf(s, "Pin %i: can't retrieve community\n", pin); 1168 continue; 1169 } 1170 1171 char *label __free(kfree) = gpiochip_dup_line_label(chip, i); 1172 if (IS_ERR(label)) 1173 continue; 1174 1175 switch (conf0 & BYT_PULL_ASSIGN_MASK) { 1176 case BYT_PULL_ASSIGN_UP: 1177 pull = "up"; 1178 break; 1179 case BYT_PULL_ASSIGN_DOWN: 1180 pull = "down"; 1181 break; 1182 } 1183 1184 switch (conf0 & BYT_PULL_STR_MASK) { 1185 case BYT_PULL_STR_2K: 1186 pull_str = "2k"; 1187 break; 1188 case BYT_PULL_STR_10K: 1189 pull_str = "10k"; 1190 break; 1191 case BYT_PULL_STR_20K: 1192 pull_str = "20k"; 1193 break; 1194 case BYT_PULL_STR_40K: 1195 pull_str = "40k"; 1196 break; 1197 } 1198 1199 seq_printf(s, 1200 " gpio-%-3d (%-20.20s) %s %s %s pad-%-3d offset:0x%03x mux:%d %s%s%s", 1201 pin, 1202 label ?: "Unrequested", 1203 val & BYT_INPUT_EN ? " " : "in", 1204 val & BYT_OUTPUT_EN ? " " : "out", 1205 str_hi_lo(val & BYT_LEVEL), 1206 comm->pad_map[i], comm->pad_map[i] * 16, 1207 conf0 & 0x7, 1208 conf0 & BYT_TRIG_NEG ? " fall" : " ", 1209 conf0 & BYT_TRIG_POS ? " rise" : " ", 1210 conf0 & BYT_TRIG_LVL ? " level" : " "); 1211 1212 if (pull && pull_str) 1213 seq_printf(s, " %-4s %-3s", pull, pull_str); 1214 else 1215 seq_puts(s, " "); 1216 1217 if (conf0 & BYT_IODEN) 1218 seq_puts(s, " open-drain"); 1219 1220 seq_puts(s, "\n"); 1221 } 1222 } 1223 1224 static const struct gpio_chip byt_gpio_chip = { 1225 .owner = THIS_MODULE, 1226 .request = gpiochip_generic_request, 1227 .free = gpiochip_generic_free, 1228 .get_direction = byt_gpio_get_direction, 1229 .direction_input = byt_gpio_direction_input, 1230 .direction_output = byt_gpio_direction_output, 1231 .get = byt_gpio_get, 1232 .set = byt_gpio_set, 1233 .set_config = gpiochip_generic_config, 1234 .dbg_show = byt_gpio_dbg_show, 1235 }; 1236 1237 static void byt_irq_ack(struct irq_data *d) 1238 { 1239 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1240 struct intel_pinctrl *vg = gpiochip_get_data(gc); 1241 irq_hw_number_t hwirq = irqd_to_hwirq(d); 1242 void __iomem *reg; 1243 1244 reg = byt_gpio_reg(vg, hwirq, BYT_INT_STAT_REG); 1245 if (!reg) 1246 return; 1247 1248 guard(raw_spinlock)(&byt_lock); 1249 1250 writel(BIT(hwirq % 32), reg); 1251 } 1252 1253 static void byt_irq_mask(struct irq_data *d) 1254 { 1255 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1256 struct intel_pinctrl *vg = gpiochip_get_data(gc); 1257 irq_hw_number_t hwirq = irqd_to_hwirq(d); 1258 1259 byt_gpio_clear_triggering(vg, hwirq); 1260 gpiochip_disable_irq(gc, hwirq); 1261 } 1262 1263 static void byt_irq_unmask(struct irq_data *d) 1264 { 1265 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1266 struct intel_pinctrl *vg = gpiochip_get_data(gc); 1267 irq_hw_number_t hwirq = irqd_to_hwirq(d); 1268 void __iomem *reg; 1269 u32 value; 1270 1271 gpiochip_enable_irq(gc, hwirq); 1272 1273 reg = byt_gpio_reg(vg, hwirq, BYT_CONF0_REG); 1274 if (!reg) 1275 return; 1276 1277 guard(raw_spinlock_irqsave)(&byt_lock); 1278 1279 value = readl(reg); 1280 1281 switch (irqd_get_trigger_type(d)) { 1282 case IRQ_TYPE_LEVEL_HIGH: 1283 value |= BYT_TRIG_LVL; 1284 fallthrough; 1285 case IRQ_TYPE_EDGE_RISING: 1286 value |= BYT_TRIG_POS; 1287 break; 1288 case IRQ_TYPE_LEVEL_LOW: 1289 value |= BYT_TRIG_LVL; 1290 fallthrough; 1291 case IRQ_TYPE_EDGE_FALLING: 1292 value |= BYT_TRIG_NEG; 1293 break; 1294 case IRQ_TYPE_EDGE_BOTH: 1295 value |= (BYT_TRIG_NEG | BYT_TRIG_POS); 1296 break; 1297 } 1298 1299 writel(value, reg); 1300 } 1301 1302 static int byt_irq_type(struct irq_data *d, unsigned int type) 1303 { 1304 struct intel_pinctrl *vg = gpiochip_get_data(irq_data_get_irq_chip_data(d)); 1305 irq_hw_number_t hwirq = irqd_to_hwirq(d); 1306 void __iomem *reg; 1307 u32 value; 1308 1309 reg = byt_gpio_reg(vg, hwirq, BYT_CONF0_REG); 1310 if (!reg) 1311 return -EINVAL; 1312 1313 guard(raw_spinlock_irqsave)(&byt_lock); 1314 1315 value = readl(reg); 1316 1317 WARN(value & BYT_DIRECT_IRQ_EN, 1318 "Bad pad config for IO mode, force DIRECT_IRQ_EN bit clearing"); 1319 1320 /* For level trigges the BYT_TRIG_POS and BYT_TRIG_NEG bits 1321 * are used to indicate high and low level triggering 1322 */ 1323 value &= ~(BYT_DIRECT_IRQ_EN | BYT_TRIG_POS | BYT_TRIG_NEG | 1324 BYT_TRIG_LVL); 1325 /* Enable glitch filtering */ 1326 value |= BYT_GLITCH_FILTER_EN | BYT_GLITCH_F_SLOW_CLK | 1327 BYT_GLITCH_F_FAST_CLK; 1328 1329 writel(value, reg); 1330 1331 if (type & IRQ_TYPE_EDGE_BOTH) 1332 irq_set_handler_locked(d, handle_edge_irq); 1333 else if (type & IRQ_TYPE_LEVEL_MASK) 1334 irq_set_handler_locked(d, handle_level_irq); 1335 1336 return 0; 1337 } 1338 1339 static const struct irq_chip byt_gpio_irq_chip = { 1340 .name = "BYT-GPIO", 1341 .irq_ack = byt_irq_ack, 1342 .irq_mask = byt_irq_mask, 1343 .irq_unmask = byt_irq_unmask, 1344 .irq_set_type = byt_irq_type, 1345 .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_SET_TYPE_MASKED | IRQCHIP_IMMUTABLE, 1346 GPIOCHIP_IRQ_RESOURCE_HELPERS, 1347 }; 1348 1349 static void byt_gpio_irq_handler(struct irq_desc *desc) 1350 { 1351 struct irq_data *data = irq_desc_get_irq_data(desc); 1352 struct intel_pinctrl *vg = gpiochip_get_data(irq_desc_get_handler_data(desc)); 1353 struct irq_chip *chip = irq_data_get_irq_chip(data); 1354 u32 base, pin; 1355 void __iomem *reg; 1356 unsigned long pending; 1357 1358 chained_irq_enter(chip, desc); 1359 1360 /* check from GPIO controller which pin triggered the interrupt */ 1361 for (base = 0; base < vg->chip.ngpio; base += 32) { 1362 reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG); 1363 1364 if (!reg) { 1365 dev_warn(vg->dev, "Pin %i: can't retrieve INT_STAT%u\n", base / 32, base); 1366 continue; 1367 } 1368 1369 scoped_guard(raw_spinlock, &byt_lock) 1370 pending = readl(reg); 1371 for_each_set_bit(pin, &pending, 32) 1372 generic_handle_domain_irq(vg->chip.irq.domain, base + pin); 1373 } 1374 1375 chained_irq_exit(chip, desc); 1376 } 1377 1378 static bool byt_direct_irq_sanity_check(struct intel_pinctrl *vg, int pin, u32 conf0) 1379 { 1380 int direct_irq, ioapic_direct_irq_base; 1381 u8 *match, direct_irq_mux[16]; 1382 u32 trig; 1383 1384 memcpy_fromio(direct_irq_mux, vg->communities->pad_regs + BYT_DIRECT_IRQ_REG, 1385 sizeof(direct_irq_mux)); 1386 match = memchr(direct_irq_mux, pin, sizeof(direct_irq_mux)); 1387 if (!match) { 1388 dev_warn(vg->dev, FW_BUG "Pin %i: DIRECT_IRQ_EN set but no IRQ assigned, clearing\n", pin); 1389 return false; 1390 } 1391 1392 direct_irq = match - direct_irq_mux; 1393 /* Base IO-APIC pin numbers come from atom-e3800-family-datasheet.pdf */ 1394 ioapic_direct_irq_base = (vg->communities->npins == BYT_NGPIO_SCORE) ? 51 : 67; 1395 dev_dbg(vg->dev, "Pin %i: uses direct IRQ %d (IO-APIC %d)\n", pin, 1396 direct_irq, direct_irq + ioapic_direct_irq_base); 1397 1398 /* 1399 * Testing has shown that the way direct IRQs work is that the combination of the 1400 * direct-irq-en flag and the direct IRQ mux connect the output of the GPIO's IRQ 1401 * trigger block, which normally sets the status flag in the IRQ status reg at 1402 * 0x800, to one of the IO-APIC pins according to the mux registers. 1403 * 1404 * This means that: 1405 * 1. The TRIG_MASK bits must be set to configure the GPIO's IRQ trigger block 1406 * 2. The TRIG_LVL bit *must* be set, so that the GPIO's input value is directly 1407 * passed (1:1 or inverted) to the IO-APIC pin, if TRIG_LVL is not set, 1408 * selecting edge mode operation then on the first edge the IO-APIC pin goes 1409 * high, but since no write-to-clear write will be done to the IRQ status reg 1410 * at 0x800, the detected edge condition will never get cleared. 1411 */ 1412 trig = conf0 & BYT_TRIG_MASK; 1413 if (trig != (BYT_TRIG_POS | BYT_TRIG_LVL) && 1414 trig != (BYT_TRIG_NEG | BYT_TRIG_LVL)) { 1415 dev_warn(vg->dev, 1416 FW_BUG "Pin %i: DIRECT_IRQ_EN set without trigger (CONF0: %#08x), clearing\n", 1417 pin, conf0); 1418 return false; 1419 } 1420 1421 return true; 1422 } 1423 1424 static void byt_init_irq_valid_mask(struct gpio_chip *chip, 1425 unsigned long *valid_mask, 1426 unsigned int ngpios) 1427 { 1428 struct intel_pinctrl *vg = gpiochip_get_data(chip); 1429 void __iomem *reg; 1430 u32 value; 1431 int i; 1432 1433 /* 1434 * Clear interrupt triggers for all pins that are GPIOs and 1435 * do not use direct IRQ mode. This will prevent spurious 1436 * interrupts from misconfigured pins. 1437 */ 1438 for (i = 0; i < vg->soc->npins; i++) { 1439 unsigned int pin = vg->soc->pins[i].number; 1440 1441 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG); 1442 if (!reg) { 1443 dev_warn(vg->dev, "Pin %i: could not retrieve CONF0\n", i); 1444 continue; 1445 } 1446 1447 value = readl(reg); 1448 if (value & BYT_DIRECT_IRQ_EN) { 1449 if (byt_direct_irq_sanity_check(vg, i, value)) { 1450 clear_bit(i, valid_mask); 1451 } else { 1452 value &= ~(BYT_DIRECT_IRQ_EN | BYT_TRIG_POS | 1453 BYT_TRIG_NEG | BYT_TRIG_LVL); 1454 writel(value, reg); 1455 } 1456 } else if ((value & BYT_PIN_MUX) == byt_get_gpio_mux(vg, i)) { 1457 byt_gpio_clear_triggering(vg, i); 1458 dev_dbg(vg->dev, "disabling GPIO %d\n", i); 1459 } 1460 } 1461 } 1462 1463 static int byt_gpio_irq_init_hw(struct gpio_chip *chip) 1464 { 1465 struct intel_pinctrl *vg = gpiochip_get_data(chip); 1466 void __iomem *reg; 1467 u32 base, value; 1468 1469 /* clear interrupt status trigger registers */ 1470 for (base = 0; base < vg->soc->npins; base += 32) { 1471 reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG); 1472 1473 if (!reg) { 1474 dev_warn(vg->dev, "Pin %i: can't retrieve INT_STAT%u\n", base / 32, base); 1475 continue; 1476 } 1477 1478 writel(0xffffffff, reg); 1479 /* make sure trigger bits are cleared, if not then a pin 1480 might be misconfigured in bios */ 1481 value = readl(reg); 1482 if (value) 1483 dev_err(vg->dev, 1484 "GPIO interrupt error, pins misconfigured. INT_STAT%u: %#08x\n", 1485 base / 32, value); 1486 } 1487 1488 return 0; 1489 } 1490 1491 static int byt_gpio_add_pin_ranges(struct gpio_chip *chip) 1492 { 1493 struct intel_pinctrl *vg = gpiochip_get_data(chip); 1494 struct device *dev = vg->dev; 1495 int ret; 1496 1497 ret = gpiochip_add_pin_range(chip, dev_name(dev), 0, 0, vg->soc->npins); 1498 if (ret) 1499 dev_err(dev, "failed to add GPIO pin range\n"); 1500 1501 return ret; 1502 } 1503 1504 static int byt_gpio_probe(struct intel_pinctrl *vg) 1505 { 1506 struct platform_device *pdev = to_platform_device(vg->dev); 1507 struct gpio_chip *gc; 1508 int irq, ret; 1509 1510 /* Set up gpio chip */ 1511 vg->chip = byt_gpio_chip; 1512 gc = &vg->chip; 1513 gc->label = dev_name(vg->dev); 1514 gc->base = -1; 1515 gc->can_sleep = false; 1516 gc->add_pin_ranges = byt_gpio_add_pin_ranges; 1517 gc->parent = vg->dev; 1518 gc->ngpio = vg->soc->npins; 1519 1520 #ifdef CONFIG_PM_SLEEP 1521 vg->context.pads = devm_kcalloc(vg->dev, gc->ngpio, sizeof(*vg->context.pads), 1522 GFP_KERNEL); 1523 if (!vg->context.pads) 1524 return -ENOMEM; 1525 #endif 1526 1527 /* set up interrupts */ 1528 irq = platform_get_irq_optional(pdev, 0); 1529 if (irq > 0) { 1530 struct gpio_irq_chip *girq; 1531 1532 girq = &gc->irq; 1533 gpio_irq_chip_set_chip(girq, &byt_gpio_irq_chip); 1534 girq->init_hw = byt_gpio_irq_init_hw; 1535 girq->init_valid_mask = byt_init_irq_valid_mask; 1536 girq->parent_handler = byt_gpio_irq_handler; 1537 girq->num_parents = 1; 1538 girq->parents = devm_kcalloc(vg->dev, girq->num_parents, 1539 sizeof(*girq->parents), GFP_KERNEL); 1540 if (!girq->parents) 1541 return -ENOMEM; 1542 girq->parents[0] = irq; 1543 girq->default_type = IRQ_TYPE_NONE; 1544 girq->handler = handle_bad_irq; 1545 } 1546 1547 ret = devm_gpiochip_add_data(vg->dev, gc, vg); 1548 if (ret) 1549 dev_err(vg->dev, "failed adding byt-gpio chip\n"); 1550 1551 return ret; 1552 } 1553 1554 static int byt_set_soc_data(struct intel_pinctrl *vg, 1555 const struct intel_pinctrl_soc_data *soc) 1556 { 1557 struct platform_device *pdev = to_platform_device(vg->dev); 1558 int i; 1559 1560 vg->soc = soc; 1561 1562 vg->ncommunities = vg->soc->ncommunities; 1563 vg->communities = devm_kmemdup_array(vg->dev, vg->soc->communities, vg->ncommunities, 1564 sizeof(*vg->soc->communities), GFP_KERNEL); 1565 if (!vg->communities) 1566 return -ENOMEM; 1567 1568 for (i = 0; i < vg->soc->ncommunities; i++) { 1569 struct intel_community *comm = vg->communities + i; 1570 1571 comm->pad_regs = devm_platform_ioremap_resource(pdev, 0); 1572 if (IS_ERR(comm->pad_regs)) 1573 return PTR_ERR(comm->pad_regs); 1574 } 1575 1576 return 0; 1577 } 1578 1579 static const struct acpi_device_id byt_gpio_acpi_match[] = { 1580 { "INT33B2", (kernel_ulong_t)byt_soc_data }, 1581 { "INT33FC", (kernel_ulong_t)byt_soc_data }, 1582 { } 1583 }; 1584 1585 static int byt_pinctrl_probe(struct platform_device *pdev) 1586 { 1587 const struct intel_pinctrl_soc_data *soc_data; 1588 struct device *dev = &pdev->dev; 1589 struct intel_pinctrl *vg; 1590 int ret; 1591 1592 soc_data = intel_pinctrl_get_soc_data(pdev); 1593 if (IS_ERR(soc_data)) 1594 return PTR_ERR(soc_data); 1595 1596 vg = devm_kzalloc(dev, sizeof(*vg), GFP_KERNEL); 1597 if (!vg) 1598 return -ENOMEM; 1599 1600 vg->dev = dev; 1601 ret = byt_set_soc_data(vg, soc_data); 1602 if (ret) { 1603 dev_err(dev, "failed to set soc data\n"); 1604 return ret; 1605 } 1606 1607 vg->pctldesc = byt_pinctrl_desc; 1608 vg->pctldesc.name = dev_name(dev); 1609 vg->pctldesc.pins = vg->soc->pins; 1610 vg->pctldesc.npins = vg->soc->npins; 1611 1612 vg->pctldev = devm_pinctrl_register(dev, &vg->pctldesc, vg); 1613 if (IS_ERR(vg->pctldev)) { 1614 dev_err(dev, "failed to register pinctrl driver\n"); 1615 return PTR_ERR(vg->pctldev); 1616 } 1617 1618 ret = byt_gpio_probe(vg); 1619 if (ret) 1620 return ret; 1621 1622 platform_set_drvdata(pdev, vg); 1623 1624 return 0; 1625 } 1626 1627 static int byt_gpio_suspend(struct device *dev) 1628 { 1629 struct intel_pinctrl *vg = dev_get_drvdata(dev); 1630 int i; 1631 1632 guard(raw_spinlock_irqsave)(&byt_lock); 1633 1634 for (i = 0; i < vg->soc->npins; i++) { 1635 void __iomem *reg; 1636 u32 value; 1637 unsigned int pin = vg->soc->pins[i].number; 1638 1639 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG); 1640 if (!reg) { 1641 dev_warn(vg->dev, "Pin %i: can't retrieve CONF0\n", i); 1642 continue; 1643 } 1644 value = readl(reg) & BYT_CONF0_RESTORE_MASK; 1645 vg->context.pads[i].conf0 = value; 1646 1647 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG); 1648 if (!reg) { 1649 dev_warn(vg->dev, "Pin %i: can't retrieve VAL\n", i); 1650 continue; 1651 } 1652 value = readl(reg) & BYT_VAL_RESTORE_MASK; 1653 vg->context.pads[i].val = value; 1654 } 1655 1656 return 0; 1657 } 1658 1659 static int byt_gpio_resume(struct device *dev) 1660 { 1661 struct intel_pinctrl *vg = dev_get_drvdata(dev); 1662 int i; 1663 1664 guard(raw_spinlock_irqsave)(&byt_lock); 1665 1666 for (i = 0; i < vg->soc->npins; i++) { 1667 void __iomem *reg; 1668 u32 value; 1669 unsigned int pin = vg->soc->pins[i].number; 1670 1671 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG); 1672 if (!reg) { 1673 dev_warn(vg->dev, "Pin %i: can't retrieve CONF0\n", i); 1674 continue; 1675 } 1676 value = readl(reg); 1677 if ((value & BYT_CONF0_RESTORE_MASK) != 1678 vg->context.pads[i].conf0) { 1679 value &= ~BYT_CONF0_RESTORE_MASK; 1680 value |= vg->context.pads[i].conf0; 1681 writel(value, reg); 1682 dev_info(dev, "restored pin %d CONF0 %#08x", i, value); 1683 } 1684 1685 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG); 1686 if (!reg) { 1687 dev_warn(vg->dev, "Pin %i: can't retrieve VAL\n", i); 1688 continue; 1689 } 1690 value = readl(reg); 1691 if ((value & BYT_VAL_RESTORE_MASK) != 1692 vg->context.pads[i].val) { 1693 u32 v; 1694 1695 v = value & ~BYT_VAL_RESTORE_MASK; 1696 v |= vg->context.pads[i].val; 1697 if (v != value) { 1698 writel(v, reg); 1699 dev_dbg(dev, "restored pin %d VAL %#08x\n", i, v); 1700 } 1701 } 1702 } 1703 1704 return 0; 1705 } 1706 1707 static const struct dev_pm_ops byt_gpio_pm_ops = { 1708 LATE_SYSTEM_SLEEP_PM_OPS(byt_gpio_suspend, byt_gpio_resume) 1709 }; 1710 1711 static struct platform_driver byt_gpio_driver = { 1712 .probe = byt_pinctrl_probe, 1713 .driver = { 1714 .name = "byt_gpio", 1715 .pm = pm_sleep_ptr(&byt_gpio_pm_ops), 1716 .acpi_match_table = byt_gpio_acpi_match, 1717 .suppress_bind_attrs = true, 1718 }, 1719 }; 1720 1721 static int __init byt_gpio_init(void) 1722 { 1723 return platform_driver_register(&byt_gpio_driver); 1724 } 1725 subsys_initcall(byt_gpio_init); 1726 1727 MODULE_IMPORT_NS("PINCTRL_INTEL"); 1728