1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Standard Hot Plug Controller Driver 4 * 5 * Copyright (C) 1995,2001 Compaq Computer Corporation 6 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com) 7 * Copyright (C) 2001 IBM 8 * Copyright (C) 2003-2004 Intel Corporation 9 * 10 * All rights reserved. 11 * 12 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com> 13 * 14 */ 15 #ifndef _SHPCHP_H 16 #define _SHPCHP_H 17 18 #include <linux/types.h> 19 #include <linux/pci.h> 20 #include <linux/pci_hotplug.h> 21 #include <linux/delay.h> 22 #include <linux/sched/signal.h> /* signal_pending(), struct timer_list */ 23 #include <linux/mutex.h> 24 #include <linux/workqueue.h> 25 26 #if !defined(MODULE) 27 #define MY_NAME "shpchp" 28 #else 29 #define MY_NAME THIS_MODULE->name 30 #endif 31 32 extern bool shpchp_poll_mode; 33 extern int shpchp_poll_time; 34 extern bool shpchp_debug; 35 36 #define ctrl_dbg(ctrl, format, arg...) \ 37 pci_dbg(ctrl->pci_dev, format, ## arg) 38 #define ctrl_err(ctrl, format, arg...) \ 39 pci_err(ctrl->pci_dev, format, ## arg) 40 #define ctrl_info(ctrl, format, arg...) \ 41 pci_info(ctrl->pci_dev, format, ## arg) 42 #define ctrl_warn(ctrl, format, arg...) \ 43 pci_warn(ctrl->pci_dev, format, ## arg) 44 45 46 #define SLOT_NAME_SIZE 10 47 struct slot { 48 u8 bus; 49 u8 device; 50 u16 status; 51 u32 number; 52 u8 is_a_board; 53 u8 state; 54 u8 attention_save; 55 u8 presence_save; 56 u8 latch_save; 57 u8 pwr_save; 58 struct controller *ctrl; 59 struct hotplug_slot hotplug_slot; 60 struct list_head slot_list; 61 struct delayed_work work; /* work for button event */ 62 struct mutex lock; 63 struct workqueue_struct *wq; 64 u8 hp_slot; 65 }; 66 67 struct event_info { 68 u32 event_type; 69 struct slot *p_slot; 70 struct work_struct work; 71 }; 72 73 struct controller { 74 struct mutex crit_sect; /* critical section mutex */ 75 struct mutex cmd_lock; /* command lock */ 76 int num_slots; /* Number of slots on ctlr */ 77 int slot_num_inc; /* 1 or -1 */ 78 struct pci_dev *pci_dev; 79 struct list_head slot_list; 80 wait_queue_head_t queue; /* sleep & wake process */ 81 u8 slot_device_offset; 82 u32 pcix_misc2_reg; /* for amd pogo errata */ 83 u32 first_slot; /* First physical slot number */ 84 u32 cap_offset; 85 unsigned long mmio_base; 86 unsigned long mmio_size; 87 void __iomem *creg; 88 struct timer_list poll_timer; 89 }; 90 91 /* Define AMD SHPC ID */ 92 #define PCI_DEVICE_ID_AMD_POGO_7458 0x7458 93 94 /* AMD PCI-X bridge registers */ 95 #define PCIX_MEM_BASE_LIMIT_OFFSET 0x1C 96 #define PCIX_MISCII_OFFSET 0x48 97 #define PCIX_MISC_BRIDGE_ERRORS_OFFSET 0x80 98 99 /* AMD PCIX_MISCII masks and offsets */ 100 #define PERRNONFATALENABLE_MASK 0x00040000 101 #define PERRFATALENABLE_MASK 0x00080000 102 #define PERRFLOODENABLE_MASK 0x00100000 103 #define SERRNONFATALENABLE_MASK 0x00200000 104 #define SERRFATALENABLE_MASK 0x00400000 105 106 /* AMD PCIX_MISC_BRIDGE_ERRORS masks and offsets */ 107 #define PERR_OBSERVED_MASK 0x00000001 108 109 /* AMD PCIX_MEM_BASE_LIMIT masks */ 110 #define RSE_MASK 0x40000000 111 112 #define INT_BUTTON_IGNORE 0 113 #define INT_PRESENCE_ON 1 114 #define INT_PRESENCE_OFF 2 115 #define INT_SWITCH_CLOSE 3 116 #define INT_SWITCH_OPEN 4 117 #define INT_POWER_FAULT 5 118 #define INT_POWER_FAULT_CLEAR 6 119 #define INT_BUTTON_PRESS 7 120 #define INT_BUTTON_RELEASE 8 121 #define INT_BUTTON_CANCEL 9 122 123 #define STATIC_STATE 0 124 #define BLINKINGON_STATE 1 125 #define BLINKINGOFF_STATE 2 126 #define POWERON_STATE 3 127 #define POWEROFF_STATE 4 128 129 /* Error messages */ 130 #define INTERLOCK_OPEN 0x00000002 131 #define ADD_NOT_SUPPORTED 0x00000003 132 #define CARD_FUNCTIONING 0x00000005 133 #define ADAPTER_NOT_SAME 0x00000006 134 #define NO_ADAPTER_PRESENT 0x00000009 135 #define NOT_ENOUGH_RESOURCES 0x0000000B 136 #define DEVICE_TYPE_NOT_SUPPORTED 0x0000000C 137 #define WRONG_BUS_FREQUENCY 0x0000000D 138 #define POWER_FAILURE 0x0000000E 139 140 int __must_check shpchp_create_ctrl_files(struct controller *ctrl); 141 void shpchp_remove_ctrl_files(struct controller *ctrl); 142 int shpchp_sysfs_enable_slot(struct slot *slot); 143 int shpchp_sysfs_disable_slot(struct slot *slot); 144 u8 shpchp_handle_attention_button(u8 hp_slot, struct controller *ctrl); 145 u8 shpchp_handle_switch_change(u8 hp_slot, struct controller *ctrl); 146 u8 shpchp_handle_presence_change(u8 hp_slot, struct controller *ctrl); 147 u8 shpchp_handle_power_fault(u8 hp_slot, struct controller *ctrl); 148 int shpchp_configure_device(struct slot *p_slot); 149 void shpchp_unconfigure_device(struct slot *p_slot); 150 void cleanup_slots(struct controller *ctrl); 151 void shpchp_queue_pushbutton_work(struct work_struct *work); 152 int shpc_init(struct controller *ctrl, struct pci_dev *pdev); 153 154 static inline const char *slot_name(struct slot *slot) 155 { 156 return hotplug_slot_name(&slot->hotplug_slot); 157 } 158 159 struct ctrl_reg { 160 volatile u32 base_offset; 161 volatile u32 slot_avail1; 162 volatile u32 slot_avail2; 163 volatile u32 slot_config; 164 volatile u16 sec_bus_config; 165 volatile u8 msi_ctrl; 166 volatile u8 prog_interface; 167 volatile u16 cmd; 168 volatile u16 cmd_status; 169 volatile u32 intr_loc; 170 volatile u32 serr_loc; 171 volatile u32 serr_intr_enable; 172 volatile u32 slot1; 173 } __attribute__ ((packed)); 174 175 /* offsets to the controller registers based on the above structure layout */ 176 enum ctrl_offsets { 177 BASE_OFFSET = offsetof(struct ctrl_reg, base_offset), 178 SLOT_AVAIL1 = offsetof(struct ctrl_reg, slot_avail1), 179 SLOT_AVAIL2 = offsetof(struct ctrl_reg, slot_avail2), 180 SLOT_CONFIG = offsetof(struct ctrl_reg, slot_config), 181 SEC_BUS_CONFIG = offsetof(struct ctrl_reg, sec_bus_config), 182 MSI_CTRL = offsetof(struct ctrl_reg, msi_ctrl), 183 PROG_INTERFACE = offsetof(struct ctrl_reg, prog_interface), 184 CMD = offsetof(struct ctrl_reg, cmd), 185 CMD_STATUS = offsetof(struct ctrl_reg, cmd_status), 186 INTR_LOC = offsetof(struct ctrl_reg, intr_loc), 187 SERR_LOC = offsetof(struct ctrl_reg, serr_loc), 188 SERR_INTR_ENABLE = offsetof(struct ctrl_reg, serr_intr_enable), 189 SLOT1 = offsetof(struct ctrl_reg, slot1), 190 }; 191 192 static inline struct slot *get_slot(struct hotplug_slot *hotplug_slot) 193 { 194 return container_of(hotplug_slot, struct slot, hotplug_slot); 195 } 196 197 static inline struct slot *shpchp_find_slot(struct controller *ctrl, u8 device) 198 { 199 struct slot *slot; 200 201 list_for_each_entry(slot, &ctrl->slot_list, slot_list) { 202 if (slot->device == device) 203 return slot; 204 } 205 206 ctrl_err(ctrl, "Slot (device=0x%02x) not found\n", device); 207 return NULL; 208 } 209 210 static inline void amd_pogo_errata_save_misc_reg(struct slot *p_slot) 211 { 212 u32 pcix_misc2_temp; 213 214 /* save MiscII register */ 215 pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, &pcix_misc2_temp); 216 217 p_slot->ctrl->pcix_misc2_reg = pcix_misc2_temp; 218 219 /* clear SERR/PERR enable bits */ 220 pcix_misc2_temp &= ~SERRFATALENABLE_MASK; 221 pcix_misc2_temp &= ~SERRNONFATALENABLE_MASK; 222 pcix_misc2_temp &= ~PERRFLOODENABLE_MASK; 223 pcix_misc2_temp &= ~PERRFATALENABLE_MASK; 224 pcix_misc2_temp &= ~PERRNONFATALENABLE_MASK; 225 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, pcix_misc2_temp); 226 } 227 228 static inline void amd_pogo_errata_restore_misc_reg(struct slot *p_slot) 229 { 230 u32 pcix_misc2_temp; 231 u32 pcix_bridge_errors_reg; 232 u32 pcix_mem_base_reg; 233 u8 perr_set; 234 u8 rse_set; 235 236 /* write-one-to-clear Bridge_Errors[ PERR_OBSERVED ] */ 237 pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, &pcix_bridge_errors_reg); 238 perr_set = pcix_bridge_errors_reg & PERR_OBSERVED_MASK; 239 if (perr_set) { 240 ctrl_dbg(p_slot->ctrl, 241 "Bridge_Errors[ PERR_OBSERVED = %08X] (W1C)\n", 242 perr_set); 243 244 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, perr_set); 245 } 246 247 /* write-one-to-clear Memory_Base_Limit[ RSE ] */ 248 pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, &pcix_mem_base_reg); 249 rse_set = pcix_mem_base_reg & RSE_MASK; 250 if (rse_set) { 251 ctrl_dbg(p_slot->ctrl, "Memory_Base_Limit[ RSE ] (W1C)\n"); 252 253 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, rse_set); 254 } 255 /* restore MiscII register */ 256 pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, &pcix_misc2_temp); 257 258 if (p_slot->ctrl->pcix_misc2_reg & SERRFATALENABLE_MASK) 259 pcix_misc2_temp |= SERRFATALENABLE_MASK; 260 else 261 pcix_misc2_temp &= ~SERRFATALENABLE_MASK; 262 263 if (p_slot->ctrl->pcix_misc2_reg & SERRNONFATALENABLE_MASK) 264 pcix_misc2_temp |= SERRNONFATALENABLE_MASK; 265 else 266 pcix_misc2_temp &= ~SERRNONFATALENABLE_MASK; 267 268 if (p_slot->ctrl->pcix_misc2_reg & PERRFLOODENABLE_MASK) 269 pcix_misc2_temp |= PERRFLOODENABLE_MASK; 270 else 271 pcix_misc2_temp &= ~PERRFLOODENABLE_MASK; 272 273 if (p_slot->ctrl->pcix_misc2_reg & PERRFATALENABLE_MASK) 274 pcix_misc2_temp |= PERRFATALENABLE_MASK; 275 else 276 pcix_misc2_temp &= ~PERRFATALENABLE_MASK; 277 278 if (p_slot->ctrl->pcix_misc2_reg & PERRNONFATALENABLE_MASK) 279 pcix_misc2_temp |= PERRNONFATALENABLE_MASK; 280 else 281 pcix_misc2_temp &= ~PERRNONFATALENABLE_MASK; 282 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, pcix_misc2_temp); 283 } 284 285 int shpchp_power_on_slot(struct slot *slot); 286 int shpchp_slot_enable(struct slot *slot); 287 int shpchp_slot_disable(struct slot *slot); 288 int shpchp_set_bus_speed_mode(struct slot *slot, enum pci_bus_speed speed); 289 int shpchp_get_power_status(struct slot *slot, u8 *status); 290 int shpchp_get_attention_status(struct slot *slot, u8 *status); 291 int shpchp_set_attention_status(struct slot *slot, u8 status); 292 int shpchp_get_latch_status(struct slot *slot, u8 *status); 293 int shpchp_get_adapter_status(struct slot *slot, u8 *status); 294 int shpchp_get_adapter_speed(struct slot *slot, enum pci_bus_speed *speed); 295 int shpchp_get_prog_int(struct slot *slot, u8 *prog_int); 296 int shpchp_query_power_fault(struct slot *slot); 297 void shpchp_green_led_on(struct slot *slot); 298 void shpchp_green_led_off(struct slot *slot); 299 void shpchp_green_led_blink(struct slot *slot); 300 void shpchp_release_ctlr(struct controller *ctrl); 301 int shpchp_check_cmd_status(struct controller *ctrl); 302 303 #endif /* _SHPCHP_H */ 304