1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * MediaTek PCIe host controller driver. 4 * 5 * Copyright (c) 2020 MediaTek Inc. 6 * Author: Jianjun Wang <jianjun.wang@mediatek.com> 7 */ 8 9 #include <linux/bitfield.h> 10 #include <linux/clk.h> 11 #include <linux/clk-provider.h> 12 #include <linux/delay.h> 13 #include <linux/iopoll.h> 14 #include <linux/irq.h> 15 #include <linux/irqchip/chained_irq.h> 16 #include <linux/irqdomain.h> 17 #include <linux/kernel.h> 18 #include <linux/mfd/syscon.h> 19 #include <linux/module.h> 20 #include <linux/msi.h> 21 #include <linux/of_device.h> 22 #include <linux/of_pci.h> 23 #include <linux/pci.h> 24 #include <linux/phy/phy.h> 25 #include <linux/platform_device.h> 26 #include <linux/pm_domain.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/regmap.h> 29 #include <linux/reset.h> 30 31 #include "../pci.h" 32 33 #define PCIE_BASE_CFG_REG 0x14 34 #define PCIE_BASE_CFG_SPEED GENMASK(15, 8) 35 36 #define PCIE_SETTING_REG 0x80 37 #define PCIE_SETTING_LINK_WIDTH GENMASK(11, 8) 38 #define PCIE_SETTING_GEN_SUPPORT GENMASK(14, 12) 39 #define PCIE_PCI_IDS_1 0x9c 40 #define PCI_CLASS(class) (class << 8) 41 #define PCIE_RC_MODE BIT(0) 42 43 #define PCIE_EQ_PRESET_01_REG 0x100 44 #define PCIE_VAL_LN0_DOWNSTREAM GENMASK(6, 0) 45 #define PCIE_VAL_LN0_UPSTREAM GENMASK(14, 8) 46 #define PCIE_VAL_LN1_DOWNSTREAM GENMASK(22, 16) 47 #define PCIE_VAL_LN1_UPSTREAM GENMASK(30, 24) 48 49 #define PCIE_CFGNUM_REG 0x140 50 #define PCIE_CFG_DEVFN(devfn) ((devfn) & GENMASK(7, 0)) 51 #define PCIE_CFG_BUS(bus) (((bus) << 8) & GENMASK(15, 8)) 52 #define PCIE_CFG_BYTE_EN(bytes) (((bytes) << 16) & GENMASK(19, 16)) 53 #define PCIE_CFG_FORCE_BYTE_EN BIT(20) 54 #define PCIE_CFG_OFFSET_ADDR 0x1000 55 #define PCIE_CFG_HEADER(bus, devfn) \ 56 (PCIE_CFG_BUS(bus) | PCIE_CFG_DEVFN(devfn)) 57 58 #define PCIE_RST_CTRL_REG 0x148 59 #define PCIE_MAC_RSTB BIT(0) 60 #define PCIE_PHY_RSTB BIT(1) 61 #define PCIE_BRG_RSTB BIT(2) 62 #define PCIE_PE_RSTB BIT(3) 63 64 #define PCIE_LTSSM_STATUS_REG 0x150 65 #define PCIE_LTSSM_STATE_MASK GENMASK(28, 24) 66 #define PCIE_LTSSM_STATE(val) ((val & PCIE_LTSSM_STATE_MASK) >> 24) 67 #define PCIE_LTSSM_STATE_L2_IDLE 0x14 68 69 #define PCIE_LINK_STATUS_REG 0x154 70 #define PCIE_PORT_LINKUP BIT(8) 71 72 #define PCIE_MSI_SET_NUM 8 73 #define PCIE_MSI_IRQS_PER_SET 32 74 #define PCIE_MSI_IRQS_NUM \ 75 (PCIE_MSI_IRQS_PER_SET * PCIE_MSI_SET_NUM) 76 77 #define PCIE_INT_ENABLE_REG 0x180 78 #define PCIE_MSI_ENABLE GENMASK(PCIE_MSI_SET_NUM + 8 - 1, 8) 79 #define PCIE_MSI_SHIFT 8 80 #define PCIE_INTX_SHIFT 24 81 #define PCIE_INTX_ENABLE \ 82 GENMASK(PCIE_INTX_SHIFT + PCI_NUM_INTX - 1, PCIE_INTX_SHIFT) 83 84 #define PCIE_INT_STATUS_REG 0x184 85 #define PCIE_MSI_SET_ENABLE_REG 0x190 86 #define PCIE_MSI_SET_ENABLE GENMASK(PCIE_MSI_SET_NUM - 1, 0) 87 88 #define PCIE_PIPE4_PIE8_REG 0x338 89 #define PCIE_K_FINETUNE_MAX GENMASK(5, 0) 90 #define PCIE_K_FINETUNE_ERR GENMASK(7, 6) 91 #define PCIE_K_PRESET_TO_USE GENMASK(18, 8) 92 #define PCIE_K_PHYPARAM_QUERY BIT(19) 93 #define PCIE_K_QUERY_TIMEOUT BIT(20) 94 #define PCIE_K_PRESET_TO_USE_16G GENMASK(31, 21) 95 96 #define PCIE_MSI_SET_BASE_REG 0xc00 97 #define PCIE_MSI_SET_OFFSET 0x10 98 #define PCIE_MSI_SET_STATUS_OFFSET 0x04 99 #define PCIE_MSI_SET_ENABLE_OFFSET 0x08 100 101 #define PCIE_MSI_SET_ADDR_HI_BASE 0xc80 102 #define PCIE_MSI_SET_ADDR_HI_OFFSET 0x04 103 104 #define PCIE_ICMD_PM_REG 0x198 105 #define PCIE_TURN_OFF_LINK BIT(4) 106 107 #define PCIE_MISC_CTRL_REG 0x348 108 #define PCIE_DISABLE_DVFSRC_VLT_REQ BIT(1) 109 110 #define PCIE_TRANS_TABLE_BASE_REG 0x800 111 #define PCIE_ATR_SRC_ADDR_MSB_OFFSET 0x4 112 #define PCIE_ATR_TRSL_ADDR_LSB_OFFSET 0x8 113 #define PCIE_ATR_TRSL_ADDR_MSB_OFFSET 0xc 114 #define PCIE_ATR_TRSL_PARAM_OFFSET 0x10 115 #define PCIE_ATR_TLB_SET_OFFSET 0x20 116 117 #define PCIE_MAX_TRANS_TABLES 8 118 #define PCIE_ATR_EN BIT(0) 119 #define PCIE_ATR_SIZE(size) \ 120 (((((size) - 1) << 1) & GENMASK(6, 1)) | PCIE_ATR_EN) 121 #define PCIE_ATR_ID(id) ((id) & GENMASK(3, 0)) 122 #define PCIE_ATR_TYPE_MEM PCIE_ATR_ID(0) 123 #define PCIE_ATR_TYPE_IO PCIE_ATR_ID(1) 124 #define PCIE_ATR_TLP_TYPE(type) (((type) << 16) & GENMASK(18, 16)) 125 #define PCIE_ATR_TLP_TYPE_MEM PCIE_ATR_TLP_TYPE(0) 126 #define PCIE_ATR_TLP_TYPE_IO PCIE_ATR_TLP_TYPE(2) 127 128 #define MAX_NUM_PHY_RESETS 3 129 130 #define PCIE_MTK_RESET_TIME_US 10 131 132 /* Time in ms needed to complete PCIe reset on EN7581 SoC */ 133 #define PCIE_EN7581_RESET_TIME_MS 100 134 135 struct mtk_gen3_pcie; 136 137 #define PCIE_CONF_LINK2_CTL_STS (PCIE_CFG_OFFSET_ADDR + 0xb0) 138 #define PCIE_CONF_LINK2_LCR2_LINK_SPEED GENMASK(3, 0) 139 140 enum mtk_gen3_pcie_flags { 141 SKIP_PCIE_RSTB = BIT(0), /* Skip PERST# assertion during device 142 * probing or suspend/resume phase to 143 * avoid hw bugs/issues. 144 */ 145 }; 146 147 /** 148 * struct mtk_gen3_pcie_pdata - differentiate between host generations 149 * @power_up: pcie power_up callback 150 * @phy_resets: phy reset lines SoC data. 151 * @flags: pcie device flags. 152 */ 153 struct mtk_gen3_pcie_pdata { 154 int (*power_up)(struct mtk_gen3_pcie *pcie); 155 struct { 156 const char *id[MAX_NUM_PHY_RESETS]; 157 int num_resets; 158 } phy_resets; 159 u32 flags; 160 }; 161 162 /** 163 * struct mtk_msi_set - MSI information for each set 164 * @base: IO mapped register base 165 * @msg_addr: MSI message address 166 * @saved_irq_state: IRQ enable state saved at suspend time 167 */ 168 struct mtk_msi_set { 169 void __iomem *base; 170 phys_addr_t msg_addr; 171 u32 saved_irq_state; 172 }; 173 174 /** 175 * struct mtk_gen3_pcie - PCIe port information 176 * @dev: pointer to PCIe device 177 * @base: IO mapped register base 178 * @reg_base: physical register base 179 * @mac_reset: MAC reset control 180 * @phy_resets: PHY reset controllers 181 * @phy: PHY controller block 182 * @clks: PCIe clocks 183 * @num_clks: PCIe clocks count for this port 184 * @max_link_speed: Maximum link speed (PCIe Gen) for this port 185 * @num_lanes: Number of PCIe lanes for this port 186 * @irq: PCIe controller interrupt number 187 * @saved_irq_state: IRQ enable state saved at suspend time 188 * @irq_lock: lock protecting IRQ register access 189 * @intx_domain: legacy INTx IRQ domain 190 * @msi_domain: MSI IRQ domain 191 * @msi_bottom_domain: MSI IRQ bottom domain 192 * @msi_sets: MSI sets information 193 * @lock: lock protecting IRQ bit map 194 * @msi_irq_in_use: bit map for assigned MSI IRQ 195 * @soc: pointer to SoC-dependent operations 196 */ 197 struct mtk_gen3_pcie { 198 struct device *dev; 199 void __iomem *base; 200 phys_addr_t reg_base; 201 struct reset_control *mac_reset; 202 struct reset_control_bulk_data phy_resets[MAX_NUM_PHY_RESETS]; 203 struct phy *phy; 204 struct clk_bulk_data *clks; 205 int num_clks; 206 u8 max_link_speed; 207 u8 num_lanes; 208 209 int irq; 210 u32 saved_irq_state; 211 raw_spinlock_t irq_lock; 212 struct irq_domain *intx_domain; 213 struct irq_domain *msi_domain; 214 struct irq_domain *msi_bottom_domain; 215 struct mtk_msi_set msi_sets[PCIE_MSI_SET_NUM]; 216 struct mutex lock; 217 DECLARE_BITMAP(msi_irq_in_use, PCIE_MSI_IRQS_NUM); 218 219 const struct mtk_gen3_pcie_pdata *soc; 220 }; 221 222 /* LTSSM state in PCIE_LTSSM_STATUS_REG bit[28:24] */ 223 static const char *const ltssm_str[] = { 224 "detect.quiet", /* 0x00 */ 225 "detect.active", /* 0x01 */ 226 "polling.active", /* 0x02 */ 227 "polling.compliance", /* 0x03 */ 228 "polling.configuration", /* 0x04 */ 229 "config.linkwidthstart", /* 0x05 */ 230 "config.linkwidthaccept", /* 0x06 */ 231 "config.lanenumwait", /* 0x07 */ 232 "config.lanenumaccept", /* 0x08 */ 233 "config.complete", /* 0x09 */ 234 "config.idle", /* 0x0A */ 235 "recovery.receiverlock", /* 0x0B */ 236 "recovery.equalization", /* 0x0C */ 237 "recovery.speed", /* 0x0D */ 238 "recovery.receiverconfig", /* 0x0E */ 239 "recovery.idle", /* 0x0F */ 240 "L0", /* 0x10 */ 241 "L0s", /* 0x11 */ 242 "L1.entry", /* 0x12 */ 243 "L1.idle", /* 0x13 */ 244 "L2.idle", /* 0x14 */ 245 "L2.transmitwake", /* 0x15 */ 246 "disable", /* 0x16 */ 247 "loopback.entry", /* 0x17 */ 248 "loopback.active", /* 0x18 */ 249 "loopback.exit", /* 0x19 */ 250 "hotreset", /* 0x1A */ 251 }; 252 253 /** 254 * mtk_pcie_config_tlp_header() - Configure a configuration TLP header 255 * @bus: PCI bus to query 256 * @devfn: device/function number 257 * @where: offset in config space 258 * @size: data size in TLP header 259 * 260 * Set byte enable field and device information in configuration TLP header. 261 */ 262 static void mtk_pcie_config_tlp_header(struct pci_bus *bus, unsigned int devfn, 263 int where, int size) 264 { 265 struct mtk_gen3_pcie *pcie = bus->sysdata; 266 int bytes; 267 u32 val; 268 269 bytes = (GENMASK(size - 1, 0) & 0xf) << (where & 0x3); 270 271 val = PCIE_CFG_FORCE_BYTE_EN | PCIE_CFG_BYTE_EN(bytes) | 272 PCIE_CFG_HEADER(bus->number, devfn); 273 274 writel_relaxed(val, pcie->base + PCIE_CFGNUM_REG); 275 } 276 277 static void __iomem *mtk_pcie_map_bus(struct pci_bus *bus, unsigned int devfn, 278 int where) 279 { 280 struct mtk_gen3_pcie *pcie = bus->sysdata; 281 282 return pcie->base + PCIE_CFG_OFFSET_ADDR + where; 283 } 284 285 static int mtk_pcie_config_read(struct pci_bus *bus, unsigned int devfn, 286 int where, int size, u32 *val) 287 { 288 mtk_pcie_config_tlp_header(bus, devfn, where, size); 289 290 return pci_generic_config_read32(bus, devfn, where, size, val); 291 } 292 293 static int mtk_pcie_config_write(struct pci_bus *bus, unsigned int devfn, 294 int where, int size, u32 val) 295 { 296 mtk_pcie_config_tlp_header(bus, devfn, where, size); 297 298 if (size <= 2) 299 val <<= (where & 0x3) * 8; 300 301 return pci_generic_config_write32(bus, devfn, where, 4, val); 302 } 303 304 static struct pci_ops mtk_pcie_ops = { 305 .map_bus = mtk_pcie_map_bus, 306 .read = mtk_pcie_config_read, 307 .write = mtk_pcie_config_write, 308 }; 309 310 static int mtk_pcie_set_trans_table(struct mtk_gen3_pcie *pcie, 311 resource_size_t cpu_addr, 312 resource_size_t pci_addr, 313 resource_size_t size, 314 unsigned long type, int *num) 315 { 316 resource_size_t remaining = size; 317 resource_size_t table_size; 318 resource_size_t addr_align; 319 const char *range_type; 320 void __iomem *table; 321 u32 val; 322 323 while (remaining && (*num < PCIE_MAX_TRANS_TABLES)) { 324 /* Table size needs to be a power of 2 */ 325 table_size = BIT(fls(remaining) - 1); 326 327 if (cpu_addr > 0) { 328 addr_align = BIT(ffs(cpu_addr) - 1); 329 table_size = min(table_size, addr_align); 330 } 331 332 /* Minimum size of translate table is 4KiB */ 333 if (table_size < 0x1000) { 334 dev_err(pcie->dev, "illegal table size %#llx\n", 335 (unsigned long long)table_size); 336 return -EINVAL; 337 } 338 339 table = pcie->base + PCIE_TRANS_TABLE_BASE_REG + *num * PCIE_ATR_TLB_SET_OFFSET; 340 writel_relaxed(lower_32_bits(cpu_addr) | PCIE_ATR_SIZE(fls(table_size) - 1), table); 341 writel_relaxed(upper_32_bits(cpu_addr), table + PCIE_ATR_SRC_ADDR_MSB_OFFSET); 342 writel_relaxed(lower_32_bits(pci_addr), table + PCIE_ATR_TRSL_ADDR_LSB_OFFSET); 343 writel_relaxed(upper_32_bits(pci_addr), table + PCIE_ATR_TRSL_ADDR_MSB_OFFSET); 344 345 if (type == IORESOURCE_IO) { 346 val = PCIE_ATR_TYPE_IO | PCIE_ATR_TLP_TYPE_IO; 347 range_type = "IO"; 348 } else { 349 val = PCIE_ATR_TYPE_MEM | PCIE_ATR_TLP_TYPE_MEM; 350 range_type = "MEM"; 351 } 352 353 writel_relaxed(val, table + PCIE_ATR_TRSL_PARAM_OFFSET); 354 355 dev_dbg(pcie->dev, "set %s trans window[%d]: cpu_addr = %#llx, pci_addr = %#llx, size = %#llx\n", 356 range_type, *num, (unsigned long long)cpu_addr, 357 (unsigned long long)pci_addr, 358 (unsigned long long)table_size); 359 360 cpu_addr += table_size; 361 pci_addr += table_size; 362 remaining -= table_size; 363 (*num)++; 364 } 365 366 if (remaining) 367 dev_warn(pcie->dev, "not enough translate table for addr: %#llx, limited to [%d]\n", 368 (unsigned long long)cpu_addr, PCIE_MAX_TRANS_TABLES); 369 370 return 0; 371 } 372 373 static void mtk_pcie_enable_msi(struct mtk_gen3_pcie *pcie) 374 { 375 int i; 376 u32 val; 377 378 for (i = 0; i < PCIE_MSI_SET_NUM; i++) { 379 struct mtk_msi_set *msi_set = &pcie->msi_sets[i]; 380 381 msi_set->base = pcie->base + PCIE_MSI_SET_BASE_REG + 382 i * PCIE_MSI_SET_OFFSET; 383 msi_set->msg_addr = pcie->reg_base + PCIE_MSI_SET_BASE_REG + 384 i * PCIE_MSI_SET_OFFSET; 385 386 /* Configure the MSI capture address */ 387 writel_relaxed(lower_32_bits(msi_set->msg_addr), msi_set->base); 388 writel_relaxed(upper_32_bits(msi_set->msg_addr), 389 pcie->base + PCIE_MSI_SET_ADDR_HI_BASE + 390 i * PCIE_MSI_SET_ADDR_HI_OFFSET); 391 } 392 393 val = readl_relaxed(pcie->base + PCIE_MSI_SET_ENABLE_REG); 394 val |= PCIE_MSI_SET_ENABLE; 395 writel_relaxed(val, pcie->base + PCIE_MSI_SET_ENABLE_REG); 396 397 val = readl_relaxed(pcie->base + PCIE_INT_ENABLE_REG); 398 val |= PCIE_MSI_ENABLE; 399 writel_relaxed(val, pcie->base + PCIE_INT_ENABLE_REG); 400 } 401 402 static int mtk_pcie_startup_port(struct mtk_gen3_pcie *pcie) 403 { 404 struct resource_entry *entry; 405 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie); 406 unsigned int table_index = 0; 407 int err; 408 u32 val; 409 410 /* Set as RC mode and set controller PCIe Gen speed restriction, if any */ 411 val = readl_relaxed(pcie->base + PCIE_SETTING_REG); 412 val |= PCIE_RC_MODE; 413 if (pcie->max_link_speed) { 414 val &= ~PCIE_SETTING_GEN_SUPPORT; 415 416 /* Can enable link speed support only from Gen2 onwards */ 417 if (pcie->max_link_speed >= 2) 418 val |= FIELD_PREP(PCIE_SETTING_GEN_SUPPORT, 419 GENMASK(pcie->max_link_speed - 2, 0)); 420 } 421 if (pcie->num_lanes) { 422 val &= ~PCIE_SETTING_LINK_WIDTH; 423 424 /* Zero means one lane, each bit activates x2/x4/x8/x16 */ 425 if (pcie->num_lanes > 1) 426 val |= FIELD_PREP(PCIE_SETTING_LINK_WIDTH, 427 GENMASK(fls(pcie->num_lanes >> 2), 0)); 428 } 429 writel_relaxed(val, pcie->base + PCIE_SETTING_REG); 430 431 /* Set Link Control 2 (LNKCTL2) speed restriction, if any */ 432 if (pcie->max_link_speed) { 433 val = readl_relaxed(pcie->base + PCIE_CONF_LINK2_CTL_STS); 434 val &= ~PCIE_CONF_LINK2_LCR2_LINK_SPEED; 435 val |= FIELD_PREP(PCIE_CONF_LINK2_LCR2_LINK_SPEED, pcie->max_link_speed); 436 writel_relaxed(val, pcie->base + PCIE_CONF_LINK2_CTL_STS); 437 } 438 439 /* Set class code */ 440 val = readl_relaxed(pcie->base + PCIE_PCI_IDS_1); 441 val &= ~GENMASK(31, 8); 442 val |= PCI_CLASS(PCI_CLASS_BRIDGE_PCI_NORMAL); 443 writel_relaxed(val, pcie->base + PCIE_PCI_IDS_1); 444 445 /* Mask all INTx interrupts */ 446 val = readl_relaxed(pcie->base + PCIE_INT_ENABLE_REG); 447 val &= ~PCIE_INTX_ENABLE; 448 writel_relaxed(val, pcie->base + PCIE_INT_ENABLE_REG); 449 450 /* Disable DVFSRC voltage request */ 451 val = readl_relaxed(pcie->base + PCIE_MISC_CTRL_REG); 452 val |= PCIE_DISABLE_DVFSRC_VLT_REQ; 453 writel_relaxed(val, pcie->base + PCIE_MISC_CTRL_REG); 454 455 /* 456 * Airoha EN7581 has a hw bug asserting/releasing PCIE_PE_RSTB signal 457 * causing occasional PCIe link down. In order to overcome the issue, 458 * PCIE_RSTB signals are not asserted/released at this stage and the 459 * PCIe block is reset using en7523_reset_assert() and 460 * en7581_pci_enable(). 461 */ 462 if (!(pcie->soc->flags & SKIP_PCIE_RSTB)) { 463 /* Assert all reset signals */ 464 val = readl_relaxed(pcie->base + PCIE_RST_CTRL_REG); 465 val |= PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | 466 PCIE_PE_RSTB; 467 writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG); 468 469 /* 470 * Described in PCIe CEM specification revision 6.0. 471 * 472 * The deassertion of PERST# should be delayed 100ms (TPVPERL) 473 * for the power and clock to become stable. 474 */ 475 msleep(PCIE_T_PVPERL_MS); 476 477 /* De-assert reset signals */ 478 val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | 479 PCIE_PE_RSTB); 480 writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG); 481 } 482 483 /* Check if the link is up or not */ 484 err = readl_poll_timeout(pcie->base + PCIE_LINK_STATUS_REG, val, 485 !!(val & PCIE_PORT_LINKUP), 20, 486 PCI_PM_D3COLD_WAIT * USEC_PER_MSEC); 487 if (err) { 488 const char *ltssm_state; 489 int ltssm_index; 490 491 val = readl_relaxed(pcie->base + PCIE_LTSSM_STATUS_REG); 492 ltssm_index = PCIE_LTSSM_STATE(val); 493 ltssm_state = ltssm_index >= ARRAY_SIZE(ltssm_str) ? 494 "Unknown state" : ltssm_str[ltssm_index]; 495 dev_err(pcie->dev, 496 "PCIe link down, current LTSSM state: %s (%#x)\n", 497 ltssm_state, val); 498 return err; 499 } 500 501 mtk_pcie_enable_msi(pcie); 502 503 /* Set PCIe translation windows */ 504 resource_list_for_each_entry(entry, &host->windows) { 505 struct resource *res = entry->res; 506 unsigned long type = resource_type(res); 507 resource_size_t cpu_addr; 508 resource_size_t pci_addr; 509 resource_size_t size; 510 511 if (type == IORESOURCE_IO) 512 cpu_addr = pci_pio_to_address(res->start); 513 else if (type == IORESOURCE_MEM) 514 cpu_addr = res->start; 515 else 516 continue; 517 518 pci_addr = res->start - entry->offset; 519 size = resource_size(res); 520 err = mtk_pcie_set_trans_table(pcie, cpu_addr, pci_addr, size, 521 type, &table_index); 522 if (err) 523 return err; 524 } 525 526 return 0; 527 } 528 529 static void mtk_pcie_msi_irq_mask(struct irq_data *data) 530 { 531 pci_msi_mask_irq(data); 532 irq_chip_mask_parent(data); 533 } 534 535 static void mtk_pcie_msi_irq_unmask(struct irq_data *data) 536 { 537 pci_msi_unmask_irq(data); 538 irq_chip_unmask_parent(data); 539 } 540 541 static struct irq_chip mtk_msi_irq_chip = { 542 .irq_ack = irq_chip_ack_parent, 543 .irq_mask = mtk_pcie_msi_irq_mask, 544 .irq_unmask = mtk_pcie_msi_irq_unmask, 545 .name = "MSI", 546 }; 547 548 static struct msi_domain_info mtk_msi_domain_info = { 549 .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | 550 MSI_FLAG_NO_AFFINITY | MSI_FLAG_PCI_MSIX | 551 MSI_FLAG_MULTI_PCI_MSI, 552 .chip = &mtk_msi_irq_chip, 553 }; 554 555 static void mtk_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) 556 { 557 struct mtk_msi_set *msi_set = irq_data_get_irq_chip_data(data); 558 struct mtk_gen3_pcie *pcie = data->domain->host_data; 559 unsigned long hwirq; 560 561 hwirq = data->hwirq % PCIE_MSI_IRQS_PER_SET; 562 563 msg->address_hi = upper_32_bits(msi_set->msg_addr); 564 msg->address_lo = lower_32_bits(msi_set->msg_addr); 565 msg->data = hwirq; 566 dev_dbg(pcie->dev, "msi#%#lx address_hi %#x address_lo %#x data %d\n", 567 hwirq, msg->address_hi, msg->address_lo, msg->data); 568 } 569 570 static void mtk_msi_bottom_irq_ack(struct irq_data *data) 571 { 572 struct mtk_msi_set *msi_set = irq_data_get_irq_chip_data(data); 573 unsigned long hwirq; 574 575 hwirq = data->hwirq % PCIE_MSI_IRQS_PER_SET; 576 577 writel_relaxed(BIT(hwirq), msi_set->base + PCIE_MSI_SET_STATUS_OFFSET); 578 } 579 580 static void mtk_msi_bottom_irq_mask(struct irq_data *data) 581 { 582 struct mtk_msi_set *msi_set = irq_data_get_irq_chip_data(data); 583 struct mtk_gen3_pcie *pcie = data->domain->host_data; 584 unsigned long hwirq, flags; 585 u32 val; 586 587 hwirq = data->hwirq % PCIE_MSI_IRQS_PER_SET; 588 589 raw_spin_lock_irqsave(&pcie->irq_lock, flags); 590 val = readl_relaxed(msi_set->base + PCIE_MSI_SET_ENABLE_OFFSET); 591 val &= ~BIT(hwirq); 592 writel_relaxed(val, msi_set->base + PCIE_MSI_SET_ENABLE_OFFSET); 593 raw_spin_unlock_irqrestore(&pcie->irq_lock, flags); 594 } 595 596 static void mtk_msi_bottom_irq_unmask(struct irq_data *data) 597 { 598 struct mtk_msi_set *msi_set = irq_data_get_irq_chip_data(data); 599 struct mtk_gen3_pcie *pcie = data->domain->host_data; 600 unsigned long hwirq, flags; 601 u32 val; 602 603 hwirq = data->hwirq % PCIE_MSI_IRQS_PER_SET; 604 605 raw_spin_lock_irqsave(&pcie->irq_lock, flags); 606 val = readl_relaxed(msi_set->base + PCIE_MSI_SET_ENABLE_OFFSET); 607 val |= BIT(hwirq); 608 writel_relaxed(val, msi_set->base + PCIE_MSI_SET_ENABLE_OFFSET); 609 raw_spin_unlock_irqrestore(&pcie->irq_lock, flags); 610 } 611 612 static struct irq_chip mtk_msi_bottom_irq_chip = { 613 .irq_ack = mtk_msi_bottom_irq_ack, 614 .irq_mask = mtk_msi_bottom_irq_mask, 615 .irq_unmask = mtk_msi_bottom_irq_unmask, 616 .irq_compose_msi_msg = mtk_compose_msi_msg, 617 .name = "MSI", 618 }; 619 620 static int mtk_msi_bottom_domain_alloc(struct irq_domain *domain, 621 unsigned int virq, unsigned int nr_irqs, 622 void *arg) 623 { 624 struct mtk_gen3_pcie *pcie = domain->host_data; 625 struct mtk_msi_set *msi_set; 626 int i, hwirq, set_idx; 627 628 mutex_lock(&pcie->lock); 629 630 hwirq = bitmap_find_free_region(pcie->msi_irq_in_use, PCIE_MSI_IRQS_NUM, 631 order_base_2(nr_irqs)); 632 633 mutex_unlock(&pcie->lock); 634 635 if (hwirq < 0) 636 return -ENOSPC; 637 638 set_idx = hwirq / PCIE_MSI_IRQS_PER_SET; 639 msi_set = &pcie->msi_sets[set_idx]; 640 641 for (i = 0; i < nr_irqs; i++) 642 irq_domain_set_info(domain, virq + i, hwirq + i, 643 &mtk_msi_bottom_irq_chip, msi_set, 644 handle_edge_irq, NULL, NULL); 645 646 return 0; 647 } 648 649 static void mtk_msi_bottom_domain_free(struct irq_domain *domain, 650 unsigned int virq, unsigned int nr_irqs) 651 { 652 struct mtk_gen3_pcie *pcie = domain->host_data; 653 struct irq_data *data = irq_domain_get_irq_data(domain, virq); 654 655 mutex_lock(&pcie->lock); 656 657 bitmap_release_region(pcie->msi_irq_in_use, data->hwirq, 658 order_base_2(nr_irqs)); 659 660 mutex_unlock(&pcie->lock); 661 662 irq_domain_free_irqs_common(domain, virq, nr_irqs); 663 } 664 665 static const struct irq_domain_ops mtk_msi_bottom_domain_ops = { 666 .alloc = mtk_msi_bottom_domain_alloc, 667 .free = mtk_msi_bottom_domain_free, 668 }; 669 670 static void mtk_intx_mask(struct irq_data *data) 671 { 672 struct mtk_gen3_pcie *pcie = irq_data_get_irq_chip_data(data); 673 unsigned long flags; 674 u32 val; 675 676 raw_spin_lock_irqsave(&pcie->irq_lock, flags); 677 val = readl_relaxed(pcie->base + PCIE_INT_ENABLE_REG); 678 val &= ~BIT(data->hwirq + PCIE_INTX_SHIFT); 679 writel_relaxed(val, pcie->base + PCIE_INT_ENABLE_REG); 680 raw_spin_unlock_irqrestore(&pcie->irq_lock, flags); 681 } 682 683 static void mtk_intx_unmask(struct irq_data *data) 684 { 685 struct mtk_gen3_pcie *pcie = irq_data_get_irq_chip_data(data); 686 unsigned long flags; 687 u32 val; 688 689 raw_spin_lock_irqsave(&pcie->irq_lock, flags); 690 val = readl_relaxed(pcie->base + PCIE_INT_ENABLE_REG); 691 val |= BIT(data->hwirq + PCIE_INTX_SHIFT); 692 writel_relaxed(val, pcie->base + PCIE_INT_ENABLE_REG); 693 raw_spin_unlock_irqrestore(&pcie->irq_lock, flags); 694 } 695 696 /** 697 * mtk_intx_eoi() - Clear INTx IRQ status at the end of interrupt 698 * @data: pointer to chip specific data 699 * 700 * As an emulated level IRQ, its interrupt status will remain 701 * until the corresponding de-assert message is received; hence that 702 * the status can only be cleared when the interrupt has been serviced. 703 */ 704 static void mtk_intx_eoi(struct irq_data *data) 705 { 706 struct mtk_gen3_pcie *pcie = irq_data_get_irq_chip_data(data); 707 unsigned long hwirq; 708 709 hwirq = data->hwirq + PCIE_INTX_SHIFT; 710 writel_relaxed(BIT(hwirq), pcie->base + PCIE_INT_STATUS_REG); 711 } 712 713 static struct irq_chip mtk_intx_irq_chip = { 714 .irq_mask = mtk_intx_mask, 715 .irq_unmask = mtk_intx_unmask, 716 .irq_eoi = mtk_intx_eoi, 717 .name = "INTx", 718 }; 719 720 static int mtk_pcie_intx_map(struct irq_domain *domain, unsigned int irq, 721 irq_hw_number_t hwirq) 722 { 723 irq_set_chip_data(irq, domain->host_data); 724 irq_set_chip_and_handler_name(irq, &mtk_intx_irq_chip, 725 handle_fasteoi_irq, "INTx"); 726 return 0; 727 } 728 729 static const struct irq_domain_ops intx_domain_ops = { 730 .map = mtk_pcie_intx_map, 731 }; 732 733 static int mtk_pcie_init_irq_domains(struct mtk_gen3_pcie *pcie) 734 { 735 struct device *dev = pcie->dev; 736 struct device_node *intc_node, *node = dev->of_node; 737 int ret; 738 739 raw_spin_lock_init(&pcie->irq_lock); 740 741 /* Setup INTx */ 742 intc_node = of_get_child_by_name(node, "interrupt-controller"); 743 if (!intc_node) { 744 dev_err(dev, "missing interrupt-controller node\n"); 745 return -ENODEV; 746 } 747 748 pcie->intx_domain = irq_domain_add_linear(intc_node, PCI_NUM_INTX, 749 &intx_domain_ops, pcie); 750 if (!pcie->intx_domain) { 751 dev_err(dev, "failed to create INTx IRQ domain\n"); 752 ret = -ENODEV; 753 goto out_put_node; 754 } 755 756 /* Setup MSI */ 757 mutex_init(&pcie->lock); 758 759 pcie->msi_bottom_domain = irq_domain_add_linear(node, PCIE_MSI_IRQS_NUM, 760 &mtk_msi_bottom_domain_ops, pcie); 761 if (!pcie->msi_bottom_domain) { 762 dev_err(dev, "failed to create MSI bottom domain\n"); 763 ret = -ENODEV; 764 goto err_msi_bottom_domain; 765 } 766 767 pcie->msi_domain = pci_msi_create_irq_domain(dev->fwnode, 768 &mtk_msi_domain_info, 769 pcie->msi_bottom_domain); 770 if (!pcie->msi_domain) { 771 dev_err(dev, "failed to create MSI domain\n"); 772 ret = -ENODEV; 773 goto err_msi_domain; 774 } 775 776 of_node_put(intc_node); 777 return 0; 778 779 err_msi_domain: 780 irq_domain_remove(pcie->msi_bottom_domain); 781 err_msi_bottom_domain: 782 irq_domain_remove(pcie->intx_domain); 783 out_put_node: 784 of_node_put(intc_node); 785 return ret; 786 } 787 788 static void mtk_pcie_irq_teardown(struct mtk_gen3_pcie *pcie) 789 { 790 irq_set_chained_handler_and_data(pcie->irq, NULL, NULL); 791 792 if (pcie->intx_domain) 793 irq_domain_remove(pcie->intx_domain); 794 795 if (pcie->msi_domain) 796 irq_domain_remove(pcie->msi_domain); 797 798 if (pcie->msi_bottom_domain) 799 irq_domain_remove(pcie->msi_bottom_domain); 800 801 irq_dispose_mapping(pcie->irq); 802 } 803 804 static void mtk_pcie_msi_handler(struct mtk_gen3_pcie *pcie, int set_idx) 805 { 806 struct mtk_msi_set *msi_set = &pcie->msi_sets[set_idx]; 807 unsigned long msi_enable, msi_status; 808 irq_hw_number_t bit, hwirq; 809 810 msi_enable = readl_relaxed(msi_set->base + PCIE_MSI_SET_ENABLE_OFFSET); 811 812 do { 813 msi_status = readl_relaxed(msi_set->base + 814 PCIE_MSI_SET_STATUS_OFFSET); 815 msi_status &= msi_enable; 816 if (!msi_status) 817 break; 818 819 for_each_set_bit(bit, &msi_status, PCIE_MSI_IRQS_PER_SET) { 820 hwirq = bit + set_idx * PCIE_MSI_IRQS_PER_SET; 821 generic_handle_domain_irq(pcie->msi_bottom_domain, hwirq); 822 } 823 } while (true); 824 } 825 826 static void mtk_pcie_irq_handler(struct irq_desc *desc) 827 { 828 struct mtk_gen3_pcie *pcie = irq_desc_get_handler_data(desc); 829 struct irq_chip *irqchip = irq_desc_get_chip(desc); 830 unsigned long status; 831 irq_hw_number_t irq_bit = PCIE_INTX_SHIFT; 832 833 chained_irq_enter(irqchip, desc); 834 835 status = readl_relaxed(pcie->base + PCIE_INT_STATUS_REG); 836 for_each_set_bit_from(irq_bit, &status, PCI_NUM_INTX + 837 PCIE_INTX_SHIFT) 838 generic_handle_domain_irq(pcie->intx_domain, 839 irq_bit - PCIE_INTX_SHIFT); 840 841 irq_bit = PCIE_MSI_SHIFT; 842 for_each_set_bit_from(irq_bit, &status, PCIE_MSI_SET_NUM + 843 PCIE_MSI_SHIFT) { 844 mtk_pcie_msi_handler(pcie, irq_bit - PCIE_MSI_SHIFT); 845 846 writel_relaxed(BIT(irq_bit), pcie->base + PCIE_INT_STATUS_REG); 847 } 848 849 chained_irq_exit(irqchip, desc); 850 } 851 852 static int mtk_pcie_setup_irq(struct mtk_gen3_pcie *pcie) 853 { 854 struct device *dev = pcie->dev; 855 struct platform_device *pdev = to_platform_device(dev); 856 int err; 857 858 err = mtk_pcie_init_irq_domains(pcie); 859 if (err) 860 return err; 861 862 pcie->irq = platform_get_irq(pdev, 0); 863 if (pcie->irq < 0) 864 return pcie->irq; 865 866 irq_set_chained_handler_and_data(pcie->irq, mtk_pcie_irq_handler, pcie); 867 868 return 0; 869 } 870 871 static int mtk_pcie_parse_port(struct mtk_gen3_pcie *pcie) 872 { 873 int i, ret, num_resets = pcie->soc->phy_resets.num_resets; 874 struct device *dev = pcie->dev; 875 struct platform_device *pdev = to_platform_device(dev); 876 struct resource *regs; 877 u32 num_lanes; 878 879 regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pcie-mac"); 880 if (!regs) 881 return -EINVAL; 882 pcie->base = devm_ioremap_resource(dev, regs); 883 if (IS_ERR(pcie->base)) { 884 dev_err(dev, "failed to map register base\n"); 885 return PTR_ERR(pcie->base); 886 } 887 888 pcie->reg_base = regs->start; 889 890 for (i = 0; i < num_resets; i++) 891 pcie->phy_resets[i].id = pcie->soc->phy_resets.id[i]; 892 893 ret = devm_reset_control_bulk_get_optional_shared(dev, num_resets, 894 pcie->phy_resets); 895 if (ret) { 896 dev_err(dev, "failed to get PHY bulk reset\n"); 897 return ret; 898 } 899 900 pcie->mac_reset = devm_reset_control_get_optional_exclusive(dev, "mac"); 901 if (IS_ERR(pcie->mac_reset)) { 902 ret = PTR_ERR(pcie->mac_reset); 903 if (ret != -EPROBE_DEFER) 904 dev_err(dev, "failed to get MAC reset\n"); 905 906 return ret; 907 } 908 909 pcie->phy = devm_phy_optional_get(dev, "pcie-phy"); 910 if (IS_ERR(pcie->phy)) { 911 ret = PTR_ERR(pcie->phy); 912 if (ret != -EPROBE_DEFER) 913 dev_err(dev, "failed to get PHY\n"); 914 915 return ret; 916 } 917 918 pcie->num_clks = devm_clk_bulk_get_all(dev, &pcie->clks); 919 if (pcie->num_clks < 0) { 920 dev_err(dev, "failed to get clocks\n"); 921 return pcie->num_clks; 922 } 923 924 ret = of_property_read_u32(dev->of_node, "num-lanes", &num_lanes); 925 if (ret == 0) { 926 if (num_lanes == 0 || num_lanes > 16 || 927 (num_lanes != 1 && num_lanes % 2)) 928 dev_warn(dev, "invalid num-lanes, using controller defaults\n"); 929 else 930 pcie->num_lanes = num_lanes; 931 } 932 933 return 0; 934 } 935 936 static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie) 937 { 938 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie); 939 struct device *dev = pcie->dev; 940 struct resource_entry *entry; 941 struct regmap *pbus_regmap; 942 u32 val, args[2], size; 943 resource_size_t addr; 944 int err; 945 946 /* 947 * The controller may have been left out of reset by the bootloader 948 * so make sure that we get a clean start by asserting resets here. 949 */ 950 reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, 951 pcie->phy_resets); 952 953 /* Wait for the time needed to complete the reset lines assert. */ 954 msleep(PCIE_EN7581_RESET_TIME_MS); 955 956 /* 957 * Configure PBus base address and base address mask to allow the 958 * hw to detect if a given address is accessible on PCIe controller. 959 */ 960 pbus_regmap = syscon_regmap_lookup_by_phandle_args(dev->of_node, 961 "mediatek,pbus-csr", 962 ARRAY_SIZE(args), 963 args); 964 if (IS_ERR(pbus_regmap)) 965 return PTR_ERR(pbus_regmap); 966 967 entry = resource_list_first_type(&host->windows, IORESOURCE_MEM); 968 if (!entry) 969 return -ENODEV; 970 971 addr = entry->res->start - entry->offset; 972 regmap_write(pbus_regmap, args[0], lower_32_bits(addr)); 973 size = lower_32_bits(resource_size(entry->res)); 974 regmap_write(pbus_regmap, args[1], GENMASK(31, __fls(size))); 975 976 /* 977 * Unlike the other MediaTek Gen3 controllers, the Airoha EN7581 978 * requires PHY initialization and power-on before PHY reset deassert. 979 */ 980 err = phy_init(pcie->phy); 981 if (err) { 982 dev_err(dev, "failed to initialize PHY\n"); 983 return err; 984 } 985 986 err = phy_power_on(pcie->phy); 987 if (err) { 988 dev_err(dev, "failed to power on PHY\n"); 989 goto err_phy_on; 990 } 991 992 err = reset_control_bulk_deassert(pcie->soc->phy_resets.num_resets, 993 pcie->phy_resets); 994 if (err) { 995 dev_err(dev, "failed to deassert PHYs\n"); 996 goto err_phy_deassert; 997 } 998 999 /* 1000 * Wait for the time needed to complete the bulk de-assert above. 1001 * This time is specific for EN7581 SoC. 1002 */ 1003 msleep(PCIE_EN7581_RESET_TIME_MS); 1004 1005 pm_runtime_enable(dev); 1006 pm_runtime_get_sync(dev); 1007 1008 val = FIELD_PREP(PCIE_VAL_LN0_DOWNSTREAM, 0x47) | 1009 FIELD_PREP(PCIE_VAL_LN1_DOWNSTREAM, 0x47) | 1010 FIELD_PREP(PCIE_VAL_LN0_UPSTREAM, 0x41) | 1011 FIELD_PREP(PCIE_VAL_LN1_UPSTREAM, 0x41); 1012 writel_relaxed(val, pcie->base + PCIE_EQ_PRESET_01_REG); 1013 1014 val = PCIE_K_PHYPARAM_QUERY | PCIE_K_QUERY_TIMEOUT | 1015 FIELD_PREP(PCIE_K_PRESET_TO_USE_16G, 0x80) | 1016 FIELD_PREP(PCIE_K_PRESET_TO_USE, 0x2) | 1017 FIELD_PREP(PCIE_K_FINETUNE_MAX, 0xf); 1018 writel_relaxed(val, pcie->base + PCIE_PIPE4_PIE8_REG); 1019 1020 err = clk_bulk_prepare_enable(pcie->num_clks, pcie->clks); 1021 if (err) { 1022 dev_err(dev, "failed to prepare clock\n"); 1023 goto err_clk_prepare_enable; 1024 } 1025 1026 /* 1027 * Airoha EN7581 performs PCIe reset via clk callbacks since it has a 1028 * hw issue with PCIE_PE_RSTB signal. Add wait for the time needed to 1029 * complete the PCIe reset. 1030 */ 1031 msleep(PCIE_T_PVPERL_MS); 1032 1033 return 0; 1034 1035 err_clk_prepare_enable: 1036 pm_runtime_put_sync(dev); 1037 pm_runtime_disable(dev); 1038 reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, 1039 pcie->phy_resets); 1040 err_phy_deassert: 1041 phy_power_off(pcie->phy); 1042 err_phy_on: 1043 phy_exit(pcie->phy); 1044 1045 return err; 1046 } 1047 1048 static int mtk_pcie_power_up(struct mtk_gen3_pcie *pcie) 1049 { 1050 struct device *dev = pcie->dev; 1051 int err; 1052 1053 /* 1054 * The controller may have been left out of reset by the bootloader 1055 * so make sure that we get a clean start by asserting resets here. 1056 */ 1057 reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, 1058 pcie->phy_resets); 1059 reset_control_assert(pcie->mac_reset); 1060 usleep_range(PCIE_MTK_RESET_TIME_US, 2 * PCIE_MTK_RESET_TIME_US); 1061 1062 /* PHY power on and enable pipe clock */ 1063 err = reset_control_bulk_deassert(pcie->soc->phy_resets.num_resets, 1064 pcie->phy_resets); 1065 if (err) { 1066 dev_err(dev, "failed to deassert PHYs\n"); 1067 return err; 1068 } 1069 1070 err = phy_init(pcie->phy); 1071 if (err) { 1072 dev_err(dev, "failed to initialize PHY\n"); 1073 goto err_phy_init; 1074 } 1075 1076 err = phy_power_on(pcie->phy); 1077 if (err) { 1078 dev_err(dev, "failed to power on PHY\n"); 1079 goto err_phy_on; 1080 } 1081 1082 /* MAC power on and enable transaction layer clocks */ 1083 reset_control_deassert(pcie->mac_reset); 1084 1085 pm_runtime_enable(dev); 1086 pm_runtime_get_sync(dev); 1087 1088 err = clk_bulk_prepare_enable(pcie->num_clks, pcie->clks); 1089 if (err) { 1090 dev_err(dev, "failed to enable clocks\n"); 1091 goto err_clk_init; 1092 } 1093 1094 return 0; 1095 1096 err_clk_init: 1097 pm_runtime_put_sync(dev); 1098 pm_runtime_disable(dev); 1099 reset_control_assert(pcie->mac_reset); 1100 phy_power_off(pcie->phy); 1101 err_phy_on: 1102 phy_exit(pcie->phy); 1103 err_phy_init: 1104 reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, 1105 pcie->phy_resets); 1106 1107 return err; 1108 } 1109 1110 static void mtk_pcie_power_down(struct mtk_gen3_pcie *pcie) 1111 { 1112 clk_bulk_disable_unprepare(pcie->num_clks, pcie->clks); 1113 1114 pm_runtime_put_sync(pcie->dev); 1115 pm_runtime_disable(pcie->dev); 1116 reset_control_assert(pcie->mac_reset); 1117 1118 phy_power_off(pcie->phy); 1119 phy_exit(pcie->phy); 1120 reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, 1121 pcie->phy_resets); 1122 } 1123 1124 static int mtk_pcie_get_controller_max_link_speed(struct mtk_gen3_pcie *pcie) 1125 { 1126 u32 val; 1127 int ret; 1128 1129 val = readl_relaxed(pcie->base + PCIE_BASE_CFG_REG); 1130 val = FIELD_GET(PCIE_BASE_CFG_SPEED, val); 1131 ret = fls(val); 1132 1133 return ret > 0 ? ret : -EINVAL; 1134 } 1135 1136 static int mtk_pcie_setup(struct mtk_gen3_pcie *pcie) 1137 { 1138 int err, max_speed; 1139 1140 err = mtk_pcie_parse_port(pcie); 1141 if (err) 1142 return err; 1143 1144 /* 1145 * Deassert the line in order to avoid unbalance in deassert_count 1146 * counter since the bulk is shared. 1147 */ 1148 reset_control_bulk_deassert(pcie->soc->phy_resets.num_resets, 1149 pcie->phy_resets); 1150 1151 /* Don't touch the hardware registers before power up */ 1152 err = pcie->soc->power_up(pcie); 1153 if (err) 1154 return err; 1155 1156 err = of_pci_get_max_link_speed(pcie->dev->of_node); 1157 if (err) { 1158 /* Get the maximum speed supported by the controller */ 1159 max_speed = mtk_pcie_get_controller_max_link_speed(pcie); 1160 1161 /* Set max_link_speed only if the controller supports it */ 1162 if (max_speed >= 0 && max_speed <= err) { 1163 pcie->max_link_speed = err; 1164 dev_info(pcie->dev, 1165 "maximum controller link speed Gen%d, overriding to Gen%u", 1166 max_speed, pcie->max_link_speed); 1167 } 1168 } 1169 1170 /* Try link up */ 1171 err = mtk_pcie_startup_port(pcie); 1172 if (err) 1173 goto err_setup; 1174 1175 err = mtk_pcie_setup_irq(pcie); 1176 if (err) 1177 goto err_setup; 1178 1179 return 0; 1180 1181 err_setup: 1182 mtk_pcie_power_down(pcie); 1183 1184 return err; 1185 } 1186 1187 static int mtk_pcie_probe(struct platform_device *pdev) 1188 { 1189 struct device *dev = &pdev->dev; 1190 struct mtk_gen3_pcie *pcie; 1191 struct pci_host_bridge *host; 1192 int err; 1193 1194 host = devm_pci_alloc_host_bridge(dev, sizeof(*pcie)); 1195 if (!host) 1196 return -ENOMEM; 1197 1198 pcie = pci_host_bridge_priv(host); 1199 1200 pcie->dev = dev; 1201 pcie->soc = device_get_match_data(dev); 1202 platform_set_drvdata(pdev, pcie); 1203 1204 err = mtk_pcie_setup(pcie); 1205 if (err) 1206 return err; 1207 1208 host->ops = &mtk_pcie_ops; 1209 host->sysdata = pcie; 1210 1211 err = pci_host_probe(host); 1212 if (err) { 1213 mtk_pcie_irq_teardown(pcie); 1214 mtk_pcie_power_down(pcie); 1215 return err; 1216 } 1217 1218 return 0; 1219 } 1220 1221 static void mtk_pcie_remove(struct platform_device *pdev) 1222 { 1223 struct mtk_gen3_pcie *pcie = platform_get_drvdata(pdev); 1224 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie); 1225 1226 pci_lock_rescan_remove(); 1227 pci_stop_root_bus(host->bus); 1228 pci_remove_root_bus(host->bus); 1229 pci_unlock_rescan_remove(); 1230 1231 mtk_pcie_irq_teardown(pcie); 1232 mtk_pcie_power_down(pcie); 1233 } 1234 1235 static void mtk_pcie_irq_save(struct mtk_gen3_pcie *pcie) 1236 { 1237 int i; 1238 1239 raw_spin_lock(&pcie->irq_lock); 1240 1241 pcie->saved_irq_state = readl_relaxed(pcie->base + PCIE_INT_ENABLE_REG); 1242 1243 for (i = 0; i < PCIE_MSI_SET_NUM; i++) { 1244 struct mtk_msi_set *msi_set = &pcie->msi_sets[i]; 1245 1246 msi_set->saved_irq_state = readl_relaxed(msi_set->base + 1247 PCIE_MSI_SET_ENABLE_OFFSET); 1248 } 1249 1250 raw_spin_unlock(&pcie->irq_lock); 1251 } 1252 1253 static void mtk_pcie_irq_restore(struct mtk_gen3_pcie *pcie) 1254 { 1255 int i; 1256 1257 raw_spin_lock(&pcie->irq_lock); 1258 1259 writel_relaxed(pcie->saved_irq_state, pcie->base + PCIE_INT_ENABLE_REG); 1260 1261 for (i = 0; i < PCIE_MSI_SET_NUM; i++) { 1262 struct mtk_msi_set *msi_set = &pcie->msi_sets[i]; 1263 1264 writel_relaxed(msi_set->saved_irq_state, 1265 msi_set->base + PCIE_MSI_SET_ENABLE_OFFSET); 1266 } 1267 1268 raw_spin_unlock(&pcie->irq_lock); 1269 } 1270 1271 static int mtk_pcie_turn_off_link(struct mtk_gen3_pcie *pcie) 1272 { 1273 u32 val; 1274 1275 val = readl_relaxed(pcie->base + PCIE_ICMD_PM_REG); 1276 val |= PCIE_TURN_OFF_LINK; 1277 writel_relaxed(val, pcie->base + PCIE_ICMD_PM_REG); 1278 1279 /* Check the link is L2 */ 1280 return readl_poll_timeout(pcie->base + PCIE_LTSSM_STATUS_REG, val, 1281 (PCIE_LTSSM_STATE(val) == 1282 PCIE_LTSSM_STATE_L2_IDLE), 20, 1283 50 * USEC_PER_MSEC); 1284 } 1285 1286 static int mtk_pcie_suspend_noirq(struct device *dev) 1287 { 1288 struct mtk_gen3_pcie *pcie = dev_get_drvdata(dev); 1289 int err; 1290 u32 val; 1291 1292 /* Trigger link to L2 state */ 1293 err = mtk_pcie_turn_off_link(pcie); 1294 if (err) { 1295 dev_err(pcie->dev, "cannot enter L2 state\n"); 1296 return err; 1297 } 1298 1299 if (!(pcie->soc->flags & SKIP_PCIE_RSTB)) { 1300 /* Assert the PERST# pin */ 1301 val = readl_relaxed(pcie->base + PCIE_RST_CTRL_REG); 1302 val |= PCIE_PE_RSTB; 1303 writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG); 1304 } 1305 1306 dev_dbg(pcie->dev, "entered L2 states successfully"); 1307 1308 mtk_pcie_irq_save(pcie); 1309 mtk_pcie_power_down(pcie); 1310 1311 return 0; 1312 } 1313 1314 static int mtk_pcie_resume_noirq(struct device *dev) 1315 { 1316 struct mtk_gen3_pcie *pcie = dev_get_drvdata(dev); 1317 int err; 1318 1319 err = pcie->soc->power_up(pcie); 1320 if (err) 1321 return err; 1322 1323 err = mtk_pcie_startup_port(pcie); 1324 if (err) { 1325 mtk_pcie_power_down(pcie); 1326 return err; 1327 } 1328 1329 mtk_pcie_irq_restore(pcie); 1330 1331 return 0; 1332 } 1333 1334 static const struct dev_pm_ops mtk_pcie_pm_ops = { 1335 NOIRQ_SYSTEM_SLEEP_PM_OPS(mtk_pcie_suspend_noirq, 1336 mtk_pcie_resume_noirq) 1337 }; 1338 1339 static const struct mtk_gen3_pcie_pdata mtk_pcie_soc_mt8192 = { 1340 .power_up = mtk_pcie_power_up, 1341 .phy_resets = { 1342 .id[0] = "phy", 1343 .num_resets = 1, 1344 }, 1345 }; 1346 1347 static const struct mtk_gen3_pcie_pdata mtk_pcie_soc_en7581 = { 1348 .power_up = mtk_pcie_en7581_power_up, 1349 .phy_resets = { 1350 .id[0] = "phy-lane0", 1351 .id[1] = "phy-lane1", 1352 .id[2] = "phy-lane2", 1353 .num_resets = 3, 1354 }, 1355 .flags = SKIP_PCIE_RSTB, 1356 }; 1357 1358 static const struct of_device_id mtk_pcie_of_match[] = { 1359 { .compatible = "airoha,en7581-pcie", .data = &mtk_pcie_soc_en7581 }, 1360 { .compatible = "mediatek,mt8192-pcie", .data = &mtk_pcie_soc_mt8192 }, 1361 {}, 1362 }; 1363 MODULE_DEVICE_TABLE(of, mtk_pcie_of_match); 1364 1365 static struct platform_driver mtk_pcie_driver = { 1366 .probe = mtk_pcie_probe, 1367 .remove = mtk_pcie_remove, 1368 .driver = { 1369 .name = "mtk-pcie-gen3", 1370 .of_match_table = mtk_pcie_of_match, 1371 .pm = &mtk_pcie_pm_ops, 1372 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 1373 }, 1374 }; 1375 1376 module_platform_driver(mtk_pcie_driver); 1377 MODULE_DESCRIPTION("MediaTek Gen3 PCIe host controller driver"); 1378 MODULE_LICENSE("GPL v2"); 1379