1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * APM X-Gene MSI Driver 4 * 5 * Copyright (c) 2014, Applied Micro Circuits Corporation 6 * Author: Tanmay Inamdar <tinamdar@apm.com> 7 * Duc Dang <dhdang@apm.com> 8 */ 9 #include <linux/cpu.h> 10 #include <linux/interrupt.h> 11 #include <linux/irqdomain.h> 12 #include <linux/module.h> 13 #include <linux/msi.h> 14 #include <linux/irqchip/chained_irq.h> 15 #include <linux/irqchip/irq-msi-lib.h> 16 #include <linux/pci.h> 17 #include <linux/platform_device.h> 18 #include <linux/of_pci.h> 19 20 #define MSI_IR0 0x000000 21 #define MSI_INT0 0x800000 22 #define IDX_PER_GROUP 8 23 #define IRQS_PER_IDX 16 24 #define NR_HW_IRQS 16 25 #define NR_MSI_VEC (IDX_PER_GROUP * IRQS_PER_IDX * NR_HW_IRQS) 26 27 struct xgene_msi_group { 28 struct xgene_msi *msi; 29 int gic_irq; 30 u32 msi_grp; 31 }; 32 33 struct xgene_msi { 34 struct device_node *node; 35 struct irq_domain *inner_domain; 36 u64 msi_addr; 37 void __iomem *msi_regs; 38 unsigned long *bitmap; 39 struct mutex bitmap_lock; 40 struct xgene_msi_group *msi_groups; 41 int num_cpus; 42 }; 43 44 /* Global data */ 45 static struct xgene_msi xgene_msi_ctrl; 46 47 /* 48 * X-Gene v1 has 16 groups of MSI termination registers MSInIRx, where 49 * n is group number (0..F), x is index of registers in each group (0..7) 50 * The register layout is as follows: 51 * MSI0IR0 base_addr 52 * MSI0IR1 base_addr + 0x10000 53 * ... ... 54 * MSI0IR6 base_addr + 0x60000 55 * MSI0IR7 base_addr + 0x70000 56 * MSI1IR0 base_addr + 0x80000 57 * MSI1IR1 base_addr + 0x90000 58 * ... ... 59 * MSI1IR7 base_addr + 0xF0000 60 * MSI2IR0 base_addr + 0x100000 61 * ... ... 62 * MSIFIR0 base_addr + 0x780000 63 * MSIFIR1 base_addr + 0x790000 64 * ... ... 65 * MSIFIR7 base_addr + 0x7F0000 66 * MSIINT0 base_addr + 0x800000 67 * MSIINT1 base_addr + 0x810000 68 * ... ... 69 * MSIINTF base_addr + 0x8F0000 70 * 71 * Each index register supports 16 MSI vectors (0..15) to generate interrupt. 72 * There are total 16 GIC IRQs assigned for these 16 groups of MSI termination 73 * registers. 74 * 75 * Each MSI termination group has 1 MSIINTn register (n is 0..15) to indicate 76 * the MSI pending status caused by 1 of its 8 index registers. 77 */ 78 79 /* MSInIRx read helper */ 80 static u32 xgene_msi_ir_read(struct xgene_msi *msi, 81 u32 msi_grp, u32 msir_idx) 82 { 83 return readl_relaxed(msi->msi_regs + MSI_IR0 + 84 (msi_grp << 19) + (msir_idx << 16)); 85 } 86 87 /* MSIINTn read helper */ 88 static u32 xgene_msi_int_read(struct xgene_msi *msi, u32 msi_grp) 89 { 90 return readl_relaxed(msi->msi_regs + MSI_INT0 + (msi_grp << 16)); 91 } 92 93 /* 94 * With 2048 MSI vectors supported, the MSI message can be constructed using 95 * following scheme: 96 * - Divide into 8 256-vector groups 97 * Group 0: 0-255 98 * Group 1: 256-511 99 * Group 2: 512-767 100 * ... 101 * Group 7: 1792-2047 102 * - Each 256-vector group is divided into 16 16-vector groups 103 * As an example: 16 16-vector groups for 256-vector group 0-255 is 104 * Group 0: 0-15 105 * Group 1: 16-32 106 * ... 107 * Group 15: 240-255 108 * - The termination address of MSI vector in 256-vector group n and 16-vector 109 * group x is the address of MSIxIRn 110 * - The data for MSI vector in 16-vector group x is x 111 */ 112 static u32 hwirq_to_reg_set(unsigned long hwirq) 113 { 114 return (hwirq / (NR_HW_IRQS * IRQS_PER_IDX)); 115 } 116 117 static u32 hwirq_to_group(unsigned long hwirq) 118 { 119 return (hwirq % NR_HW_IRQS); 120 } 121 122 static u32 hwirq_to_msi_data(unsigned long hwirq) 123 { 124 return ((hwirq / NR_HW_IRQS) % IRQS_PER_IDX); 125 } 126 127 static void xgene_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) 128 { 129 struct xgene_msi *msi = irq_data_get_irq_chip_data(data); 130 u32 reg_set = hwirq_to_reg_set(data->hwirq); 131 u32 group = hwirq_to_group(data->hwirq); 132 u64 target_addr = msi->msi_addr + (((8 * group) + reg_set) << 16); 133 134 msg->address_hi = upper_32_bits(target_addr); 135 msg->address_lo = lower_32_bits(target_addr); 136 msg->data = hwirq_to_msi_data(data->hwirq); 137 } 138 139 /* 140 * X-Gene v1 only has 16 MSI GIC IRQs for 2048 MSI vectors. To maintain 141 * the expected behaviour of .set_affinity for each MSI interrupt, the 16 142 * MSI GIC IRQs are statically allocated to 8 X-Gene v1 cores (2 GIC IRQs 143 * for each core). The MSI vector is moved from 1 MSI GIC IRQ to another 144 * MSI GIC IRQ to steer its MSI interrupt to correct X-Gene v1 core. As a 145 * consequence, the total MSI vectors that X-Gene v1 supports will be 146 * reduced to 256 (2048/8) vectors. 147 */ 148 static int hwirq_to_cpu(unsigned long hwirq) 149 { 150 return (hwirq % xgene_msi_ctrl.num_cpus); 151 } 152 153 static unsigned long hwirq_to_canonical_hwirq(unsigned long hwirq) 154 { 155 return (hwirq - hwirq_to_cpu(hwirq)); 156 } 157 158 static int xgene_msi_set_affinity(struct irq_data *irqdata, 159 const struct cpumask *mask, bool force) 160 { 161 int target_cpu = cpumask_first(mask); 162 int curr_cpu; 163 164 curr_cpu = hwirq_to_cpu(irqdata->hwirq); 165 if (curr_cpu == target_cpu) 166 return IRQ_SET_MASK_OK_DONE; 167 168 /* Update MSI number to target the new CPU */ 169 irqdata->hwirq = hwirq_to_canonical_hwirq(irqdata->hwirq) + target_cpu; 170 171 return IRQ_SET_MASK_OK; 172 } 173 174 static struct irq_chip xgene_msi_bottom_irq_chip = { 175 .name = "MSI", 176 .irq_set_affinity = xgene_msi_set_affinity, 177 .irq_compose_msi_msg = xgene_compose_msi_msg, 178 }; 179 180 static int xgene_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, 181 unsigned int nr_irqs, void *args) 182 { 183 struct xgene_msi *msi = domain->host_data; 184 int msi_irq; 185 186 mutex_lock(&msi->bitmap_lock); 187 188 msi_irq = bitmap_find_next_zero_area(msi->bitmap, NR_MSI_VEC, 0, 189 msi->num_cpus, 0); 190 if (msi_irq < NR_MSI_VEC) 191 bitmap_set(msi->bitmap, msi_irq, msi->num_cpus); 192 else 193 msi_irq = -ENOSPC; 194 195 mutex_unlock(&msi->bitmap_lock); 196 197 if (msi_irq < 0) 198 return msi_irq; 199 200 irq_domain_set_info(domain, virq, msi_irq, 201 &xgene_msi_bottom_irq_chip, domain->host_data, 202 handle_simple_irq, NULL, NULL); 203 204 return 0; 205 } 206 207 static void xgene_irq_domain_free(struct irq_domain *domain, 208 unsigned int virq, unsigned int nr_irqs) 209 { 210 struct irq_data *d = irq_domain_get_irq_data(domain, virq); 211 struct xgene_msi *msi = irq_data_get_irq_chip_data(d); 212 u32 hwirq; 213 214 mutex_lock(&msi->bitmap_lock); 215 216 hwirq = hwirq_to_canonical_hwirq(d->hwirq); 217 bitmap_clear(msi->bitmap, hwirq, msi->num_cpus); 218 219 mutex_unlock(&msi->bitmap_lock); 220 221 irq_domain_free_irqs_parent(domain, virq, nr_irqs); 222 } 223 224 static const struct irq_domain_ops xgene_msi_domain_ops = { 225 .alloc = xgene_irq_domain_alloc, 226 .free = xgene_irq_domain_free, 227 }; 228 229 static const struct msi_parent_ops xgene_msi_parent_ops = { 230 .supported_flags = (MSI_GENERIC_FLAGS_MASK | 231 MSI_FLAG_PCI_MSIX), 232 .required_flags = (MSI_FLAG_USE_DEF_DOM_OPS | 233 MSI_FLAG_USE_DEF_CHIP_OPS), 234 .bus_select_token = DOMAIN_BUS_PCI_MSI, 235 .init_dev_msi_info = msi_lib_init_dev_msi_info, 236 }; 237 238 static int xgene_allocate_domains(struct xgene_msi *msi) 239 { 240 struct irq_domain_info info = { 241 .fwnode = of_fwnode_handle(msi->node), 242 .ops = &xgene_msi_domain_ops, 243 .size = NR_MSI_VEC, 244 .host_data = msi, 245 }; 246 247 msi->inner_domain = msi_create_parent_irq_domain(&info, &xgene_msi_parent_ops); 248 return msi->inner_domain ? 0 : -ENOMEM; 249 } 250 251 static void xgene_free_domains(struct xgene_msi *msi) 252 { 253 if (msi->inner_domain) 254 irq_domain_remove(msi->inner_domain); 255 } 256 257 static int xgene_msi_init_allocator(struct xgene_msi *xgene_msi) 258 { 259 xgene_msi->bitmap = bitmap_zalloc(NR_MSI_VEC, GFP_KERNEL); 260 if (!xgene_msi->bitmap) 261 return -ENOMEM; 262 263 mutex_init(&xgene_msi->bitmap_lock); 264 265 xgene_msi->msi_groups = kcalloc(NR_HW_IRQS, 266 sizeof(struct xgene_msi_group), 267 GFP_KERNEL); 268 if (!xgene_msi->msi_groups) 269 return -ENOMEM; 270 271 return 0; 272 } 273 274 static void xgene_msi_isr(struct irq_desc *desc) 275 { 276 struct irq_chip *chip = irq_desc_get_chip(desc); 277 struct xgene_msi_group *msi_groups; 278 struct xgene_msi *xgene_msi; 279 int msir_index, msir_val, hw_irq, ret; 280 u32 intr_index, grp_select, msi_grp; 281 282 chained_irq_enter(chip, desc); 283 284 msi_groups = irq_desc_get_handler_data(desc); 285 xgene_msi = msi_groups->msi; 286 msi_grp = msi_groups->msi_grp; 287 288 /* 289 * MSIINTn (n is 0..F) indicates if there is a pending MSI interrupt 290 * If bit x of this register is set (x is 0..7), one or more interrupts 291 * corresponding to MSInIRx is set. 292 */ 293 grp_select = xgene_msi_int_read(xgene_msi, msi_grp); 294 while (grp_select) { 295 msir_index = ffs(grp_select) - 1; 296 /* 297 * Calculate MSInIRx address to read to check for interrupts 298 * (refer to termination address and data assignment 299 * described in xgene_compose_msi_msg() ) 300 */ 301 msir_val = xgene_msi_ir_read(xgene_msi, msi_grp, msir_index); 302 while (msir_val) { 303 intr_index = ffs(msir_val) - 1; 304 /* 305 * Calculate MSI vector number (refer to the termination 306 * address and data assignment described in 307 * xgene_compose_msi_msg function) 308 */ 309 hw_irq = (((msir_index * IRQS_PER_IDX) + intr_index) * 310 NR_HW_IRQS) + msi_grp; 311 /* 312 * As we have multiple hw_irq that maps to single MSI, 313 * always look up the virq using the hw_irq as seen from 314 * CPU0 315 */ 316 hw_irq = hwirq_to_canonical_hwirq(hw_irq); 317 ret = generic_handle_domain_irq(xgene_msi->inner_domain, hw_irq); 318 WARN_ON_ONCE(ret); 319 msir_val &= ~(1 << intr_index); 320 } 321 grp_select &= ~(1 << msir_index); 322 323 if (!grp_select) { 324 /* 325 * We handled all interrupts happened in this group, 326 * resample this group MSI_INTx register in case 327 * something else has been made pending in the meantime 328 */ 329 grp_select = xgene_msi_int_read(xgene_msi, msi_grp); 330 } 331 } 332 333 chained_irq_exit(chip, desc); 334 } 335 336 static enum cpuhp_state pci_xgene_online; 337 338 static void xgene_msi_remove(struct platform_device *pdev) 339 { 340 struct xgene_msi *msi = platform_get_drvdata(pdev); 341 342 if (pci_xgene_online) 343 cpuhp_remove_state(pci_xgene_online); 344 cpuhp_remove_state(CPUHP_PCI_XGENE_DEAD); 345 346 kfree(msi->msi_groups); 347 348 bitmap_free(msi->bitmap); 349 msi->bitmap = NULL; 350 351 xgene_free_domains(msi); 352 } 353 354 static int xgene_msi_hwirq_alloc(unsigned int cpu) 355 { 356 struct xgene_msi *msi = &xgene_msi_ctrl; 357 struct xgene_msi_group *msi_group; 358 cpumask_var_t mask; 359 int i; 360 int err; 361 362 for (i = cpu; i < NR_HW_IRQS; i += msi->num_cpus) { 363 msi_group = &msi->msi_groups[i]; 364 if (!msi_group->gic_irq) 365 continue; 366 367 irq_set_chained_handler_and_data(msi_group->gic_irq, 368 xgene_msi_isr, msi_group); 369 370 /* 371 * Statically allocate MSI GIC IRQs to each CPU core. 372 * With 8-core X-Gene v1, 2 MSI GIC IRQs are allocated 373 * to each core. 374 */ 375 if (alloc_cpumask_var(&mask, GFP_KERNEL)) { 376 cpumask_clear(mask); 377 cpumask_set_cpu(cpu, mask); 378 err = irq_set_affinity(msi_group->gic_irq, mask); 379 if (err) 380 pr_err("failed to set affinity for GIC IRQ"); 381 free_cpumask_var(mask); 382 } else { 383 pr_err("failed to alloc CPU mask for affinity\n"); 384 err = -EINVAL; 385 } 386 387 if (err) { 388 irq_set_chained_handler_and_data(msi_group->gic_irq, 389 NULL, NULL); 390 return err; 391 } 392 } 393 394 return 0; 395 } 396 397 static int xgene_msi_hwirq_free(unsigned int cpu) 398 { 399 struct xgene_msi *msi = &xgene_msi_ctrl; 400 struct xgene_msi_group *msi_group; 401 int i; 402 403 for (i = cpu; i < NR_HW_IRQS; i += msi->num_cpus) { 404 msi_group = &msi->msi_groups[i]; 405 if (!msi_group->gic_irq) 406 continue; 407 408 irq_set_chained_handler_and_data(msi_group->gic_irq, NULL, 409 NULL); 410 } 411 return 0; 412 } 413 414 static const struct of_device_id xgene_msi_match_table[] = { 415 {.compatible = "apm,xgene1-msi"}, 416 {}, 417 }; 418 419 static int xgene_msi_probe(struct platform_device *pdev) 420 { 421 struct resource *res; 422 int rc, irq_index; 423 struct xgene_msi *xgene_msi; 424 int virt_msir; 425 u32 msi_val, msi_idx; 426 427 xgene_msi = &xgene_msi_ctrl; 428 429 platform_set_drvdata(pdev, xgene_msi); 430 431 xgene_msi->msi_regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 432 if (IS_ERR(xgene_msi->msi_regs)) { 433 rc = PTR_ERR(xgene_msi->msi_regs); 434 goto error; 435 } 436 xgene_msi->msi_addr = res->start; 437 xgene_msi->node = pdev->dev.of_node; 438 xgene_msi->num_cpus = num_possible_cpus(); 439 440 rc = xgene_msi_init_allocator(xgene_msi); 441 if (rc) { 442 dev_err(&pdev->dev, "Error allocating MSI bitmap\n"); 443 goto error; 444 } 445 446 rc = xgene_allocate_domains(xgene_msi); 447 if (rc) { 448 dev_err(&pdev->dev, "Failed to allocate MSI domain\n"); 449 goto error; 450 } 451 452 for (irq_index = 0; irq_index < NR_HW_IRQS; irq_index++) { 453 virt_msir = platform_get_irq(pdev, irq_index); 454 if (virt_msir < 0) { 455 rc = virt_msir; 456 goto error; 457 } 458 xgene_msi->msi_groups[irq_index].gic_irq = virt_msir; 459 xgene_msi->msi_groups[irq_index].msi_grp = irq_index; 460 xgene_msi->msi_groups[irq_index].msi = xgene_msi; 461 } 462 463 /* 464 * MSInIRx registers are read-to-clear; before registering 465 * interrupt handlers, read all of them to clear spurious 466 * interrupts that may occur before the driver is probed. 467 */ 468 for (irq_index = 0; irq_index < NR_HW_IRQS; irq_index++) { 469 for (msi_idx = 0; msi_idx < IDX_PER_GROUP; msi_idx++) 470 xgene_msi_ir_read(xgene_msi, irq_index, msi_idx); 471 472 /* Read MSIINTn to confirm */ 473 msi_val = xgene_msi_int_read(xgene_msi, irq_index); 474 if (msi_val) { 475 dev_err(&pdev->dev, "Failed to clear spurious IRQ\n"); 476 rc = -EINVAL; 477 goto error; 478 } 479 } 480 481 rc = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "pci/xgene:online", 482 xgene_msi_hwirq_alloc, NULL); 483 if (rc < 0) 484 goto err_cpuhp; 485 pci_xgene_online = rc; 486 rc = cpuhp_setup_state(CPUHP_PCI_XGENE_DEAD, "pci/xgene:dead", NULL, 487 xgene_msi_hwirq_free); 488 if (rc) 489 goto err_cpuhp; 490 491 dev_info(&pdev->dev, "APM X-Gene PCIe MSI driver loaded\n"); 492 493 return 0; 494 495 err_cpuhp: 496 dev_err(&pdev->dev, "failed to add CPU MSI notifier\n"); 497 error: 498 xgene_msi_remove(pdev); 499 return rc; 500 } 501 502 static struct platform_driver xgene_msi_driver = { 503 .driver = { 504 .name = "xgene-msi", 505 .of_match_table = xgene_msi_match_table, 506 }, 507 .probe = xgene_msi_probe, 508 .remove = xgene_msi_remove, 509 }; 510 511 static int __init xgene_pcie_msi_init(void) 512 { 513 return platform_driver_register(&xgene_msi_driver); 514 } 515 subsys_initcall(xgene_pcie_msi_init); 516