1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2015, 2016 Cavium, Inc. 4 */ 5 6 #include <linux/kernel.h> 7 #include <linux/init.h> 8 #include <linux/ioport.h> 9 #include <linux/of_pci.h> 10 #include <linux/of.h> 11 #include <linux/pci-ecam.h> 12 #include <linux/platform_device.h> 13 14 #include "pci-host-common.h" 15 16 #if defined(CONFIG_PCI_HOST_THUNDER_ECAM) || (defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)) 17 18 static void set_val(u32 v, int where, int size, u32 *val) 19 { 20 int shift = (where & 3) * 8; 21 22 pr_debug("set_val %04x: %08x\n", (unsigned int)(where & ~3), v); 23 v >>= shift; 24 if (size == 1) 25 v &= 0xff; 26 else if (size == 2) 27 v &= 0xffff; 28 *val = v; 29 } 30 31 static int handle_ea_bar(u32 e0, int bar, struct pci_bus *bus, 32 unsigned int devfn, int where, int size, u32 *val) 33 { 34 void __iomem *addr; 35 u32 v; 36 37 /* Entries are 16-byte aligned; bits[2,3] select word in entry */ 38 int where_a = where & 0xc; 39 40 if (where_a == 0) { 41 set_val(e0, where, size, val); 42 return PCIBIOS_SUCCESSFUL; 43 } 44 if (where_a == 0x4) { 45 addr = bus->ops->map_bus(bus, devfn, bar); /* BAR 0 */ 46 if (!addr) 47 return PCIBIOS_DEVICE_NOT_FOUND; 48 49 v = readl(addr); 50 v &= ~0xf; 51 v |= 2; /* EA entry-1. Base-L */ 52 set_val(v, where, size, val); 53 return PCIBIOS_SUCCESSFUL; 54 } 55 if (where_a == 0x8) { 56 u32 barl_orig; 57 u32 barl_rb; 58 59 addr = bus->ops->map_bus(bus, devfn, bar); /* BAR 0 */ 60 if (!addr) 61 return PCIBIOS_DEVICE_NOT_FOUND; 62 63 barl_orig = readl(addr + 0); 64 writel(0xffffffff, addr + 0); 65 barl_rb = readl(addr + 0); 66 writel(barl_orig, addr + 0); 67 /* zeros in unsettable bits */ 68 v = ~barl_rb & ~3; 69 v |= 0xc; /* EA entry-2. Offset-L */ 70 set_val(v, where, size, val); 71 return PCIBIOS_SUCCESSFUL; 72 } 73 if (where_a == 0xc) { 74 addr = bus->ops->map_bus(bus, devfn, bar + 4); /* BAR 1 */ 75 if (!addr) 76 return PCIBIOS_DEVICE_NOT_FOUND; 77 78 v = readl(addr); /* EA entry-3. Base-H */ 79 set_val(v, where, size, val); 80 return PCIBIOS_SUCCESSFUL; 81 } 82 return PCIBIOS_DEVICE_NOT_FOUND; 83 } 84 85 static int thunder_ecam_p2_config_read(struct pci_bus *bus, unsigned int devfn, 86 int where, int size, u32 *val) 87 { 88 struct pci_config_window *cfg = bus->sysdata; 89 int where_a = where & ~3; 90 void __iomem *addr; 91 u32 node_bits; 92 u32 v; 93 94 /* EA Base[63:32] may be missing some bits ... */ 95 switch (where_a) { 96 case 0xa8: 97 case 0xbc: 98 case 0xd0: 99 case 0xe4: 100 break; 101 default: 102 return pci_generic_config_read(bus, devfn, where, size, val); 103 } 104 105 addr = bus->ops->map_bus(bus, devfn, where_a); 106 if (!addr) 107 return PCIBIOS_DEVICE_NOT_FOUND; 108 109 v = readl(addr); 110 111 /* 112 * Bit 44 of the 64-bit Base must match the same bit in 113 * the config space access window. Since we are working with 114 * the high-order 32 bits, shift everything down by 32 bits. 115 */ 116 node_bits = upper_32_bits(cfg->res.start) & (1 << 12); 117 118 v |= node_bits; 119 set_val(v, where, size, val); 120 121 return PCIBIOS_SUCCESSFUL; 122 } 123 124 static int thunder_ecam_config_read(struct pci_bus *bus, unsigned int devfn, 125 int where, int size, u32 *val) 126 { 127 u32 v; 128 u32 vendor_device; 129 u32 class_rev; 130 void __iomem *addr; 131 int cfg_type; 132 int where_a = where & ~3; 133 134 addr = bus->ops->map_bus(bus, devfn, 0xc); 135 if (!addr) 136 return PCIBIOS_DEVICE_NOT_FOUND; 137 138 v = readl(addr); 139 140 /* Check for non type-00 header */ 141 cfg_type = (v >> 16) & 0x7f; 142 143 addr = bus->ops->map_bus(bus, devfn, 8); 144 if (!addr) 145 return PCIBIOS_DEVICE_NOT_FOUND; 146 147 class_rev = readl(addr); 148 if (class_rev == 0xffffffff) 149 goto no_emulation; 150 151 if ((class_rev & 0xff) >= 8) { 152 /* Pass-2 handling */ 153 if (cfg_type) 154 goto no_emulation; 155 return thunder_ecam_p2_config_read(bus, devfn, where, 156 size, val); 157 } 158 159 /* 160 * All BARs have fixed addresses specified by the EA 161 * capability; they must return zero on read. 162 */ 163 if (cfg_type == 0 && 164 ((where >= 0x10 && where < 0x2c) || 165 (where >= 0x1a4 && where < 0x1bc))) { 166 /* BAR or SR-IOV BAR */ 167 *val = 0; 168 return PCIBIOS_SUCCESSFUL; 169 } 170 171 addr = bus->ops->map_bus(bus, devfn, 0); 172 if (!addr) 173 return PCIBIOS_DEVICE_NOT_FOUND; 174 175 vendor_device = readl(addr); 176 if (vendor_device == 0xffffffff) 177 goto no_emulation; 178 179 pr_debug("%04x:%04x - Fix pass#: %08x, where: %03x, devfn: %03x\n", 180 vendor_device & 0xffff, vendor_device >> 16, class_rev, 181 (unsigned int)where, devfn); 182 183 /* Check for non type-00 header */ 184 if (cfg_type == 0) { 185 bool has_msix; 186 bool is_nic = (vendor_device == 0xa01e177d); 187 bool is_tns = (vendor_device == 0xa01f177d); 188 189 addr = bus->ops->map_bus(bus, devfn, 0x70); 190 if (!addr) 191 return PCIBIOS_DEVICE_NOT_FOUND; 192 193 /* E_CAP */ 194 v = readl(addr); 195 has_msix = (v & 0xff00) != 0; 196 197 if (!has_msix && where_a == 0x70) { 198 v |= 0xbc00; /* next capability is EA at 0xbc */ 199 set_val(v, where, size, val); 200 return PCIBIOS_SUCCESSFUL; 201 } 202 if (where_a == 0xb0) { 203 addr = bus->ops->map_bus(bus, devfn, where_a); 204 if (!addr) 205 return PCIBIOS_DEVICE_NOT_FOUND; 206 207 v = readl(addr); 208 if (v & 0xff00) 209 pr_err("Bad MSI-X cap header: %08x\n", v); 210 v |= 0xbc00; /* next capability is EA at 0xbc */ 211 set_val(v, where, size, val); 212 return PCIBIOS_SUCCESSFUL; 213 } 214 if (where_a == 0xbc) { 215 if (is_nic) 216 v = 0x40014; /* EA last in chain, 4 entries */ 217 else if (is_tns) 218 v = 0x30014; /* EA last in chain, 3 entries */ 219 else if (has_msix) 220 v = 0x20014; /* EA last in chain, 2 entries */ 221 else 222 v = 0x10014; /* EA last in chain, 1 entry */ 223 set_val(v, where, size, val); 224 return PCIBIOS_SUCCESSFUL; 225 } 226 if (where_a >= 0xc0 && where_a < 0xd0) 227 /* EA entry-0. PP=0, BAR0 Size:3 */ 228 return handle_ea_bar(0x80ff0003, 229 0x10, bus, devfn, where, 230 size, val); 231 if (where_a >= 0xd0 && where_a < 0xe0 && has_msix) 232 /* EA entry-1. PP=0, BAR4 Size:3 */ 233 return handle_ea_bar(0x80ff0043, 234 0x20, bus, devfn, where, 235 size, val); 236 if (where_a >= 0xe0 && where_a < 0xf0 && is_tns) 237 /* EA entry-2. PP=0, BAR2, Size:3 */ 238 return handle_ea_bar(0x80ff0023, 239 0x18, bus, devfn, where, 240 size, val); 241 if (where_a >= 0xe0 && where_a < 0xf0 && is_nic) 242 /* EA entry-2. PP=4, VF_BAR0 (9), Size:3 */ 243 return handle_ea_bar(0x80ff0493, 244 0x1a4, bus, devfn, where, 245 size, val); 246 if (where_a >= 0xf0 && where_a < 0x100 && is_nic) 247 /* EA entry-3. PP=4, VF_BAR4 (d), Size:3 */ 248 return handle_ea_bar(0x80ff04d3, 249 0x1b4, bus, devfn, where, 250 size, val); 251 } else if (cfg_type == 1) { 252 bool is_rsl_bridge = devfn == 0x08; 253 bool is_rad_bridge = devfn == 0xa0; 254 bool is_zip_bridge = devfn == 0xa8; 255 bool is_dfa_bridge = devfn == 0xb0; 256 bool is_nic_bridge = devfn == 0x10; 257 258 if (where_a == 0x70) { 259 addr = bus->ops->map_bus(bus, devfn, where_a); 260 if (!addr) 261 return PCIBIOS_DEVICE_NOT_FOUND; 262 263 v = readl(addr); 264 if (v & 0xff00) 265 pr_err("Bad PCIe cap header: %08x\n", v); 266 v |= 0xbc00; /* next capability is EA at 0xbc */ 267 set_val(v, where, size, val); 268 return PCIBIOS_SUCCESSFUL; 269 } 270 if (where_a == 0xbc) { 271 if (is_nic_bridge) 272 v = 0x10014; /* EA last in chain, 1 entry */ 273 else 274 v = 0x00014; /* EA last in chain, no entries */ 275 set_val(v, where, size, val); 276 return PCIBIOS_SUCCESSFUL; 277 } 278 if (where_a == 0xc0) { 279 if (is_rsl_bridge || is_nic_bridge) 280 v = 0x0101; /* subordinate:secondary = 1:1 */ 281 else if (is_rad_bridge) 282 v = 0x0202; /* subordinate:secondary = 2:2 */ 283 else if (is_zip_bridge) 284 v = 0x0303; /* subordinate:secondary = 3:3 */ 285 else if (is_dfa_bridge) 286 v = 0x0404; /* subordinate:secondary = 4:4 */ 287 set_val(v, where, size, val); 288 return PCIBIOS_SUCCESSFUL; 289 } 290 if (where_a == 0xc4 && is_nic_bridge) { 291 /* Enabled, not-Write, SP=ff, PP=05, BEI=6, ES=4 */ 292 v = 0x80ff0564; 293 set_val(v, where, size, val); 294 return PCIBIOS_SUCCESSFUL; 295 } 296 if (where_a == 0xc8 && is_nic_bridge) { 297 v = 0x00000002; /* Base-L 64-bit */ 298 set_val(v, where, size, val); 299 return PCIBIOS_SUCCESSFUL; 300 } 301 if (where_a == 0xcc && is_nic_bridge) { 302 v = 0xfffffffe; /* MaxOffset-L 64-bit */ 303 set_val(v, where, size, val); 304 return PCIBIOS_SUCCESSFUL; 305 } 306 if (where_a == 0xd0 && is_nic_bridge) { 307 v = 0x00008430; /* NIC Base-H */ 308 set_val(v, where, size, val); 309 return PCIBIOS_SUCCESSFUL; 310 } 311 if (where_a == 0xd4 && is_nic_bridge) { 312 v = 0x0000000f; /* MaxOffset-H */ 313 set_val(v, where, size, val); 314 return PCIBIOS_SUCCESSFUL; 315 } 316 } 317 no_emulation: 318 return pci_generic_config_read(bus, devfn, where, size, val); 319 } 320 321 static int thunder_ecam_config_write(struct pci_bus *bus, unsigned int devfn, 322 int where, int size, u32 val) 323 { 324 /* 325 * All BARs have fixed addresses; ignore BAR writes so they 326 * don't get corrupted. 327 */ 328 if ((where >= 0x10 && where < 0x2c) || 329 (where >= 0x1a4 && where < 0x1bc)) 330 /* BAR or SR-IOV BAR */ 331 return PCIBIOS_SUCCESSFUL; 332 333 return pci_generic_config_write(bus, devfn, where, size, val); 334 } 335 336 const struct pci_ecam_ops pci_thunder_ecam_ops = { 337 .pci_ops = { 338 .map_bus = pci_ecam_map_bus, 339 .read = thunder_ecam_config_read, 340 .write = thunder_ecam_config_write, 341 } 342 }; 343 344 #ifdef CONFIG_PCI_HOST_THUNDER_ECAM 345 346 static const struct of_device_id thunder_ecam_of_match[] = { 347 { 348 .compatible = "cavium,pci-host-thunder-ecam", 349 .data = &pci_thunder_ecam_ops, 350 }, 351 { }, 352 }; 353 354 static struct platform_driver thunder_ecam_driver = { 355 .driver = { 356 .name = KBUILD_MODNAME, 357 .of_match_table = thunder_ecam_of_match, 358 .suppress_bind_attrs = true, 359 }, 360 .probe = pci_host_common_probe, 361 }; 362 builtin_platform_driver(thunder_ecam_driver); 363 364 #endif 365 #endif 366