1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * PCIe Gen4 host controller driver for NXP Layerscape SoCs 4 * 5 * Copyright 2019-2020 NXP 6 * 7 * Author: Zhiqiang Hou <Zhiqiang.Hou@nxp.com> 8 */ 9 10 #include <linux/kernel.h> 11 #include <linux/interrupt.h> 12 #include <linux/init.h> 13 #include <linux/of_pci.h> 14 #include <linux/of_platform.h> 15 #include <linux/of_irq.h> 16 #include <linux/of_address.h> 17 #include <linux/pci.h> 18 #include <linux/platform_device.h> 19 #include <linux/resource.h> 20 #include <linux/mfd/syscon.h> 21 #include <linux/regmap.h> 22 23 #include "pcie-mobiveil.h" 24 25 /* LUT and PF control registers */ 26 #define PCIE_LUT_OFF 0x80000 27 #define PCIE_PF_OFF 0xc0000 28 #define PCIE_PF_INT_STAT 0x18 29 #define PF_INT_STAT_PABRST BIT(31) 30 31 #define PCIE_PF_DBG 0x7fc 32 #define PF_DBG_LTSSM_MASK 0x3f 33 #define PF_DBG_LTSSM_L0 0x2d /* L0 state */ 34 #define PF_DBG_WE BIT(31) 35 #define PF_DBG_PABR BIT(27) 36 37 #define to_ls_g4_pcie(x) platform_get_drvdata((x)->pdev) 38 39 struct ls_g4_pcie { 40 struct mobiveil_pcie pci; 41 struct delayed_work dwork; 42 int irq; 43 }; 44 45 static inline u32 ls_g4_pcie_pf_readl(struct ls_g4_pcie *pcie, u32 off) 46 { 47 return ioread32(pcie->pci.csr_axi_slave_base + PCIE_PF_OFF + off); 48 } 49 50 static inline void ls_g4_pcie_pf_writel(struct ls_g4_pcie *pcie, 51 u32 off, u32 val) 52 { 53 iowrite32(val, pcie->pci.csr_axi_slave_base + PCIE_PF_OFF + off); 54 } 55 56 static bool ls_g4_pcie_link_up(struct mobiveil_pcie *pci) 57 { 58 struct ls_g4_pcie *pcie = to_ls_g4_pcie(pci); 59 u32 state; 60 61 state = ls_g4_pcie_pf_readl(pcie, PCIE_PF_DBG); 62 return (state & PF_DBG_LTSSM_MASK) == PF_DBG_LTSSM_L0; 63 } 64 65 static void ls_g4_pcie_disable_interrupt(struct ls_g4_pcie *pcie) 66 { 67 struct mobiveil_pcie *mv_pci = &pcie->pci; 68 69 mobiveil_csr_writel(mv_pci, 0, PAB_INTP_AMBA_MISC_ENB); 70 } 71 72 static void ls_g4_pcie_enable_interrupt(struct ls_g4_pcie *pcie) 73 { 74 struct mobiveil_pcie *mv_pci = &pcie->pci; 75 u32 val; 76 77 /* Clear the interrupt status */ 78 mobiveil_csr_writel(mv_pci, 0xffffffff, PAB_INTP_AMBA_MISC_STAT); 79 80 val = PAB_INTP_INTX_MASK | PAB_INTP_MSI | PAB_INTP_RESET | 81 PAB_INTP_PCIE_UE | PAB_INTP_IE_PMREDI | PAB_INTP_IE_EC; 82 mobiveil_csr_writel(mv_pci, val, PAB_INTP_AMBA_MISC_ENB); 83 } 84 85 static int ls_g4_pcie_reinit_hw(struct ls_g4_pcie *pcie) 86 { 87 struct mobiveil_pcie *mv_pci = &pcie->pci; 88 struct device *dev = &mv_pci->pdev->dev; 89 u32 val, act_stat; 90 int to = 100; 91 92 /* Poll for pab_csb_reset to set and PAB activity to clear */ 93 do { 94 usleep_range(10, 15); 95 val = ls_g4_pcie_pf_readl(pcie, PCIE_PF_INT_STAT); 96 act_stat = mobiveil_csr_readl(mv_pci, PAB_ACTIVITY_STAT); 97 } while (((val & PF_INT_STAT_PABRST) == 0 || act_stat) && to--); 98 if (to < 0) { 99 dev_err(dev, "Poll PABRST&PABACT timeout\n"); 100 return -EIO; 101 } 102 103 /* clear PEX_RESET bit in PEX_PF0_DBG register */ 104 val = ls_g4_pcie_pf_readl(pcie, PCIE_PF_DBG); 105 val |= PF_DBG_WE; 106 ls_g4_pcie_pf_writel(pcie, PCIE_PF_DBG, val); 107 108 val = ls_g4_pcie_pf_readl(pcie, PCIE_PF_DBG); 109 val |= PF_DBG_PABR; 110 ls_g4_pcie_pf_writel(pcie, PCIE_PF_DBG, val); 111 112 val = ls_g4_pcie_pf_readl(pcie, PCIE_PF_DBG); 113 val &= ~PF_DBG_WE; 114 ls_g4_pcie_pf_writel(pcie, PCIE_PF_DBG, val); 115 116 mobiveil_host_init(mv_pci, true); 117 118 to = 100; 119 while (!ls_g4_pcie_link_up(mv_pci) && to--) 120 usleep_range(200, 250); 121 if (to < 0) { 122 dev_err(dev, "PCIe link training timeout\n"); 123 return -EIO; 124 } 125 126 return 0; 127 } 128 129 static irqreturn_t ls_g4_pcie_isr(int irq, void *dev_id) 130 { 131 struct ls_g4_pcie *pcie = (struct ls_g4_pcie *)dev_id; 132 struct mobiveil_pcie *mv_pci = &pcie->pci; 133 u32 val; 134 135 val = mobiveil_csr_readl(mv_pci, PAB_INTP_AMBA_MISC_STAT); 136 if (!val) 137 return IRQ_NONE; 138 139 if (val & PAB_INTP_RESET) { 140 ls_g4_pcie_disable_interrupt(pcie); 141 schedule_delayed_work(&pcie->dwork, msecs_to_jiffies(1)); 142 } 143 144 mobiveil_csr_writel(mv_pci, val, PAB_INTP_AMBA_MISC_STAT); 145 146 return IRQ_HANDLED; 147 } 148 149 static int ls_g4_pcie_interrupt_init(struct mobiveil_pcie *mv_pci) 150 { 151 struct ls_g4_pcie *pcie = to_ls_g4_pcie(mv_pci); 152 struct platform_device *pdev = mv_pci->pdev; 153 struct device *dev = &pdev->dev; 154 int ret; 155 156 pcie->irq = platform_get_irq_byname(pdev, "intr"); 157 if (pcie->irq < 0) 158 return pcie->irq; 159 160 ret = devm_request_irq(dev, pcie->irq, ls_g4_pcie_isr, 161 IRQF_SHARED, pdev->name, pcie); 162 if (ret) { 163 dev_err(dev, "Can't register PCIe IRQ, errno = %d\n", ret); 164 return ret; 165 } 166 167 return 0; 168 } 169 170 static void ls_g4_pcie_reset(struct work_struct *work) 171 { 172 struct delayed_work *dwork = to_delayed_work(work); 173 struct ls_g4_pcie *pcie = container_of(dwork, struct ls_g4_pcie, dwork); 174 struct mobiveil_pcie *mv_pci = &pcie->pci; 175 u16 ctrl; 176 177 ctrl = mobiveil_csr_readw(mv_pci, PCI_BRIDGE_CONTROL); 178 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET; 179 mobiveil_csr_writew(mv_pci, ctrl, PCI_BRIDGE_CONTROL); 180 181 if (!ls_g4_pcie_reinit_hw(pcie)) 182 return; 183 184 ls_g4_pcie_enable_interrupt(pcie); 185 } 186 187 static const struct mobiveil_rp_ops ls_g4_pcie_rp_ops = { 188 .interrupt_init = ls_g4_pcie_interrupt_init, 189 }; 190 191 static const struct mobiveil_pab_ops ls_g4_pcie_pab_ops = { 192 .link_up = ls_g4_pcie_link_up, 193 }; 194 195 static int __init ls_g4_pcie_probe(struct platform_device *pdev) 196 { 197 struct device *dev = &pdev->dev; 198 struct pci_host_bridge *bridge; 199 struct mobiveil_pcie *mv_pci; 200 struct ls_g4_pcie *pcie; 201 struct device_node *np = dev->of_node; 202 int ret; 203 204 if (!of_parse_phandle(np, "msi-parent", 0)) { 205 dev_err(dev, "Failed to find msi-parent\n"); 206 return -EINVAL; 207 } 208 209 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie)); 210 if (!bridge) 211 return -ENOMEM; 212 213 pcie = pci_host_bridge_priv(bridge); 214 mv_pci = &pcie->pci; 215 216 mv_pci->pdev = pdev; 217 mv_pci->ops = &ls_g4_pcie_pab_ops; 218 mv_pci->rp.ops = &ls_g4_pcie_rp_ops; 219 mv_pci->rp.bridge = bridge; 220 221 platform_set_drvdata(pdev, pcie); 222 223 INIT_DELAYED_WORK(&pcie->dwork, ls_g4_pcie_reset); 224 225 ret = mobiveil_pcie_host_probe(mv_pci); 226 if (ret) { 227 dev_err(dev, "Fail to probe\n"); 228 return ret; 229 } 230 231 ls_g4_pcie_enable_interrupt(pcie); 232 233 return 0; 234 } 235 236 static const struct of_device_id ls_g4_pcie_of_match[] = { 237 { .compatible = "fsl,lx2160a-pcie", }, 238 { }, 239 }; 240 241 static struct platform_driver ls_g4_pcie_driver = { 242 .driver = { 243 .name = "layerscape-pcie-gen4", 244 .of_match_table = ls_g4_pcie_of_match, 245 .suppress_bind_attrs = true, 246 }, 247 }; 248 249 builtin_platform_driver_probe(ls_g4_pcie_driver, ls_g4_pcie_probe); 250