1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #include "acpi.h" 6 #include "chan.h" 7 #include "coex.h" 8 #include "debug.h" 9 #include "fw.h" 10 #include "mac.h" 11 #include "phy.h" 12 #include "ps.h" 13 #include "reg.h" 14 #include "sar.h" 15 #include "txrx.h" 16 #include "util.h" 17 18 static u32 rtw89_phy0_phy1_offset(struct rtw89_dev *rtwdev, u32 addr) 19 { 20 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 21 22 return phy->phy0_phy1_offset(rtwdev, addr); 23 } 24 25 static u16 get_max_amsdu_len(struct rtw89_dev *rtwdev, 26 const struct rtw89_ra_report *report) 27 { 28 u32 bit_rate = report->bit_rate; 29 30 /* lower than ofdm, do not aggregate */ 31 if (bit_rate < 550) 32 return 1; 33 34 /* avoid AMSDU for legacy rate */ 35 if (report->might_fallback_legacy) 36 return 1; 37 38 /* lower than 20M vht 2ss mcs8, make it small */ 39 if (bit_rate < 1800) 40 return 1200; 41 42 /* lower than 40M vht 2ss mcs9, make it medium */ 43 if (bit_rate < 4000) 44 return 2600; 45 46 /* not yet 80M vht 2ss mcs8/9, make it twice regular packet size */ 47 if (bit_rate < 7000) 48 return 3500; 49 50 return rtwdev->chip->max_amsdu_limit; 51 } 52 53 static u64 get_mcs_ra_mask(u16 mcs_map, u8 highest_mcs, u8 gap) 54 { 55 u64 ra_mask = 0; 56 u8 mcs_cap; 57 int i, nss; 58 59 for (i = 0, nss = 12; i < 4; i++, mcs_map >>= 2, nss += 12) { 60 mcs_cap = mcs_map & 0x3; 61 switch (mcs_cap) { 62 case 2: 63 ra_mask |= GENMASK_ULL(highest_mcs, 0) << nss; 64 break; 65 case 1: 66 ra_mask |= GENMASK_ULL(highest_mcs - gap, 0) << nss; 67 break; 68 case 0: 69 ra_mask |= GENMASK_ULL(highest_mcs - gap * 2, 0) << nss; 70 break; 71 default: 72 break; 73 } 74 } 75 76 return ra_mask; 77 } 78 79 static u64 get_he_ra_mask(struct ieee80211_link_sta *link_sta) 80 { 81 struct ieee80211_sta_he_cap cap = link_sta->he_cap; 82 u16 mcs_map; 83 84 switch (link_sta->bandwidth) { 85 case IEEE80211_STA_RX_BW_160: 86 if (cap.he_cap_elem.phy_cap_info[0] & 87 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_80PLUS80_MHZ_IN_5G) 88 mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_80p80); 89 else 90 mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_160); 91 break; 92 default: 93 mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_80); 94 } 95 96 /* MCS11, MCS9, MCS7 */ 97 return get_mcs_ra_mask(mcs_map, 11, 2); 98 } 99 100 static u64 get_eht_mcs_ra_mask(u8 *max_nss, u8 start_mcs, u8 n_nss) 101 { 102 u64 nss_mcs_shift; 103 u64 nss_mcs_val; 104 u64 mask = 0; 105 int i, j; 106 u8 nss; 107 108 for (i = 0; i < n_nss; i++) { 109 nss = u8_get_bits(max_nss[i], IEEE80211_EHT_MCS_NSS_RX); 110 if (!nss) 111 continue; 112 113 nss_mcs_val = GENMASK_ULL(start_mcs + i * 2, 0); 114 115 for (j = 0, nss_mcs_shift = 12; j < nss; j++, nss_mcs_shift += 16) 116 mask |= nss_mcs_val << nss_mcs_shift; 117 } 118 119 return mask; 120 } 121 122 static u64 get_eht_ra_mask(struct ieee80211_link_sta *link_sta) 123 { 124 struct ieee80211_sta_eht_cap *eht_cap = &link_sta->eht_cap; 125 struct ieee80211_eht_mcs_nss_supp_20mhz_only *mcs_nss_20mhz; 126 struct ieee80211_eht_mcs_nss_supp_bw *mcs_nss; 127 u8 *he_phy_cap = link_sta->he_cap.he_cap_elem.phy_cap_info; 128 129 switch (link_sta->bandwidth) { 130 case IEEE80211_STA_RX_BW_320: 131 mcs_nss = &eht_cap->eht_mcs_nss_supp.bw._320; 132 /* MCS 9, 11, 13 */ 133 return get_eht_mcs_ra_mask(mcs_nss->rx_tx_max_nss, 9, 3); 134 case IEEE80211_STA_RX_BW_160: 135 mcs_nss = &eht_cap->eht_mcs_nss_supp.bw._160; 136 /* MCS 9, 11, 13 */ 137 return get_eht_mcs_ra_mask(mcs_nss->rx_tx_max_nss, 9, 3); 138 case IEEE80211_STA_RX_BW_20: 139 if (!(he_phy_cap[0] & 140 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_MASK_ALL)) { 141 mcs_nss_20mhz = &eht_cap->eht_mcs_nss_supp.only_20mhz; 142 /* MCS 7, 9, 11, 13 */ 143 return get_eht_mcs_ra_mask(mcs_nss_20mhz->rx_tx_max_nss, 7, 4); 144 } 145 fallthrough; 146 case IEEE80211_STA_RX_BW_80: 147 default: 148 mcs_nss = &eht_cap->eht_mcs_nss_supp.bw._80; 149 /* MCS 9, 11, 13 */ 150 return get_eht_mcs_ra_mask(mcs_nss->rx_tx_max_nss, 9, 3); 151 } 152 } 153 154 #define RA_FLOOR_TABLE_SIZE 7 155 #define RA_FLOOR_UP_GAP 3 156 static u64 rtw89_phy_ra_mask_rssi(struct rtw89_dev *rtwdev, u8 rssi, 157 u8 ratr_state) 158 { 159 u8 rssi_lv_t[RA_FLOOR_TABLE_SIZE] = {30, 44, 48, 52, 56, 60, 100}; 160 u8 rssi_lv = 0; 161 u8 i; 162 163 rssi >>= 1; 164 for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) { 165 if (i >= ratr_state) 166 rssi_lv_t[i] += RA_FLOOR_UP_GAP; 167 if (rssi < rssi_lv_t[i]) { 168 rssi_lv = i; 169 break; 170 } 171 } 172 if (rssi_lv == 0) 173 return 0xffffffffffffffffULL; 174 else if (rssi_lv == 1) 175 return 0xfffffffffffffff0ULL; 176 else if (rssi_lv == 2) 177 return 0xffffffffffffefe0ULL; 178 else if (rssi_lv == 3) 179 return 0xffffffffffffcfc0ULL; 180 else if (rssi_lv == 4) 181 return 0xffffffffffff8f80ULL; 182 else if (rssi_lv >= 5) 183 return 0xffffffffffff0f00ULL; 184 185 return 0xffffffffffffffffULL; 186 } 187 188 static u64 rtw89_phy_ra_mask_recover(u64 ra_mask, u64 ra_mask_bak) 189 { 190 if ((ra_mask & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)) == 0) 191 ra_mask |= (ra_mask_bak & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)); 192 193 if (ra_mask == 0) 194 ra_mask |= (ra_mask_bak & (RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)); 195 196 return ra_mask; 197 } 198 199 static u64 rtw89_phy_ra_mask_cfg(struct rtw89_dev *rtwdev, 200 struct rtw89_sta_link *rtwsta_link, 201 struct ieee80211_link_sta *link_sta, 202 const struct rtw89_chan *chan) 203 { 204 struct cfg80211_bitrate_mask *mask = &rtwsta_link->mask; 205 enum nl80211_band band; 206 u64 cfg_mask; 207 208 if (!rtwsta_link->use_cfg_mask) 209 return -1; 210 211 switch (chan->band_type) { 212 case RTW89_BAND_2G: 213 band = NL80211_BAND_2GHZ; 214 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_2GHZ].legacy, 215 RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES); 216 break; 217 case RTW89_BAND_5G: 218 band = NL80211_BAND_5GHZ; 219 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_5GHZ].legacy, 220 RA_MASK_OFDM_RATES); 221 break; 222 case RTW89_BAND_6G: 223 band = NL80211_BAND_6GHZ; 224 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_6GHZ].legacy, 225 RA_MASK_OFDM_RATES); 226 break; 227 default: 228 rtw89_warn(rtwdev, "unhandled band type %d\n", chan->band_type); 229 return -1; 230 } 231 232 if (link_sta->he_cap.has_he) { 233 cfg_mask |= u64_encode_bits(mask->control[band].he_mcs[0], 234 RA_MASK_HE_1SS_RATES); 235 cfg_mask |= u64_encode_bits(mask->control[band].he_mcs[1], 236 RA_MASK_HE_2SS_RATES); 237 } else if (link_sta->vht_cap.vht_supported) { 238 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[0], 239 RA_MASK_VHT_1SS_RATES); 240 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[1], 241 RA_MASK_VHT_2SS_RATES); 242 } else if (link_sta->ht_cap.ht_supported) { 243 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[0], 244 RA_MASK_HT_1SS_RATES); 245 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[1], 246 RA_MASK_HT_2SS_RATES); 247 } 248 249 return cfg_mask; 250 } 251 252 static const u64 253 rtw89_ra_mask_ht_rates[4] = {RA_MASK_HT_1SS_RATES, RA_MASK_HT_2SS_RATES, 254 RA_MASK_HT_3SS_RATES, RA_MASK_HT_4SS_RATES}; 255 static const u64 256 rtw89_ra_mask_vht_rates[4] = {RA_MASK_VHT_1SS_RATES, RA_MASK_VHT_2SS_RATES, 257 RA_MASK_VHT_3SS_RATES, RA_MASK_VHT_4SS_RATES}; 258 static const u64 259 rtw89_ra_mask_he_rates[4] = {RA_MASK_HE_1SS_RATES, RA_MASK_HE_2SS_RATES, 260 RA_MASK_HE_3SS_RATES, RA_MASK_HE_4SS_RATES}; 261 static const u64 262 rtw89_ra_mask_eht_rates[4] = {RA_MASK_EHT_1SS_RATES, RA_MASK_EHT_2SS_RATES, 263 RA_MASK_EHT_3SS_RATES, RA_MASK_EHT_4SS_RATES}; 264 static const u64 265 rtw89_ra_mask_eht_mcs0_11[4] = {RA_MASK_EHT_1SS_MCS0_11, RA_MASK_EHT_2SS_MCS0_11, 266 RA_MASK_EHT_3SS_MCS0_11, RA_MASK_EHT_4SS_MCS0_11}; 267 268 static void rtw89_phy_ra_gi_ltf(struct rtw89_dev *rtwdev, 269 struct rtw89_sta_link *rtwsta_link, 270 struct ieee80211_link_sta *link_sta, 271 const struct rtw89_chan *chan, 272 bool *fix_giltf_en, u8 *fix_giltf) 273 { 274 struct cfg80211_bitrate_mask *mask = &rtwsta_link->mask; 275 u8 band = chan->band_type; 276 enum nl80211_band nl_band = rtw89_hw_to_nl80211_band(band); 277 u8 he_ltf = mask->control[nl_band].he_ltf; 278 u8 he_gi = mask->control[nl_band].he_gi; 279 280 *fix_giltf_en = true; 281 282 if (rtwdev->chip->chip_id == RTL8852C && 283 chan->band_width == RTW89_CHANNEL_WIDTH_160 && 284 rtw89_sta_link_has_su_mu_4xhe08(link_sta)) 285 *fix_giltf = RTW89_GILTF_SGI_4XHE08; 286 else 287 *fix_giltf = RTW89_GILTF_2XHE08; 288 289 if (!(rtwsta_link->use_cfg_mask && link_sta->he_cap.has_he)) 290 return; 291 292 if (he_ltf == 2 && he_gi == 2) { 293 *fix_giltf = RTW89_GILTF_LGI_4XHE32; 294 } else if (he_ltf == 2 && he_gi == 0) { 295 *fix_giltf = RTW89_GILTF_SGI_4XHE08; 296 } else if (he_ltf == 1 && he_gi == 1) { 297 *fix_giltf = RTW89_GILTF_2XHE16; 298 } else if (he_ltf == 1 && he_gi == 0) { 299 *fix_giltf = RTW89_GILTF_2XHE08; 300 } else if (he_ltf == 0 && he_gi == 1) { 301 *fix_giltf = RTW89_GILTF_1XHE16; 302 } else if (he_ltf == 0 && he_gi == 0) { 303 *fix_giltf = RTW89_GILTF_1XHE08; 304 } 305 } 306 307 static void rtw89_phy_ra_sta_update(struct rtw89_dev *rtwdev, 308 struct rtw89_vif_link *rtwvif_link, 309 struct rtw89_sta_link *rtwsta_link, 310 struct ieee80211_link_sta *link_sta, 311 bool p2p, bool csi) 312 { 313 struct rtw89_phy_rate_pattern *rate_pattern = &rtwvif_link->rate_pattern; 314 struct rtw89_ra_info *ra = &rtwsta_link->ra; 315 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, 316 rtwvif_link->chanctx_idx); 317 const u64 *high_rate_masks = rtw89_ra_mask_ht_rates; 318 u8 rssi = ewma_rssi_read(&rtwsta_link->avg_rssi); 319 u64 ra_mask = 0; 320 u64 ra_mask_bak; 321 u8 mode = 0; 322 u8 csi_mode = RTW89_RA_RPT_MODE_LEGACY; 323 u8 bw_mode = 0; 324 u8 stbc_en = 0; 325 u8 ldpc_en = 0; 326 u8 fix_giltf = 0; 327 u8 i; 328 bool sgi = false; 329 bool fix_giltf_en = false; 330 331 memset(ra, 0, sizeof(*ra)); 332 /* Set the ra mask from sta's capability */ 333 if (link_sta->eht_cap.has_eht) { 334 mode |= RTW89_RA_MODE_EHT; 335 ra_mask |= get_eht_ra_mask(link_sta); 336 337 if (rtwdev->hal.no_mcs_12_13) 338 high_rate_masks = rtw89_ra_mask_eht_mcs0_11; 339 else 340 high_rate_masks = rtw89_ra_mask_eht_rates; 341 342 rtw89_phy_ra_gi_ltf(rtwdev, rtwsta_link, link_sta, 343 chan, &fix_giltf_en, &fix_giltf); 344 } else if (link_sta->he_cap.has_he) { 345 mode |= RTW89_RA_MODE_HE; 346 csi_mode = RTW89_RA_RPT_MODE_HE; 347 ra_mask |= get_he_ra_mask(link_sta); 348 high_rate_masks = rtw89_ra_mask_he_rates; 349 if (link_sta->he_cap.he_cap_elem.phy_cap_info[2] & 350 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ) 351 stbc_en = 1; 352 if (link_sta->he_cap.he_cap_elem.phy_cap_info[1] & 353 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD) 354 ldpc_en = 1; 355 rtw89_phy_ra_gi_ltf(rtwdev, rtwsta_link, link_sta, 356 chan, &fix_giltf_en, &fix_giltf); 357 } else if (link_sta->vht_cap.vht_supported) { 358 u16 mcs_map = le16_to_cpu(link_sta->vht_cap.vht_mcs.rx_mcs_map); 359 360 mode |= RTW89_RA_MODE_VHT; 361 csi_mode = RTW89_RA_RPT_MODE_VHT; 362 /* MCS9 (non-20MHz), MCS8, MCS7 */ 363 if (link_sta->bandwidth == IEEE80211_STA_RX_BW_20) 364 ra_mask |= get_mcs_ra_mask(mcs_map, 8, 1); 365 else 366 ra_mask |= get_mcs_ra_mask(mcs_map, 9, 1); 367 high_rate_masks = rtw89_ra_mask_vht_rates; 368 if (link_sta->vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK) 369 stbc_en = 1; 370 if (link_sta->vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC) 371 ldpc_en = 1; 372 } else if (link_sta->ht_cap.ht_supported) { 373 mode |= RTW89_RA_MODE_HT; 374 csi_mode = RTW89_RA_RPT_MODE_HT; 375 ra_mask |= ((u64)link_sta->ht_cap.mcs.rx_mask[3] << 48) | 376 ((u64)link_sta->ht_cap.mcs.rx_mask[2] << 36) | 377 ((u64)link_sta->ht_cap.mcs.rx_mask[1] << 24) | 378 ((u64)link_sta->ht_cap.mcs.rx_mask[0] << 12); 379 high_rate_masks = rtw89_ra_mask_ht_rates; 380 if (link_sta->ht_cap.cap & IEEE80211_HT_CAP_RX_STBC) 381 stbc_en = 1; 382 if (link_sta->ht_cap.cap & IEEE80211_HT_CAP_LDPC_CODING) 383 ldpc_en = 1; 384 } 385 386 switch (chan->band_type) { 387 case RTW89_BAND_2G: 388 ra_mask |= link_sta->supp_rates[NL80211_BAND_2GHZ]; 389 if (link_sta->supp_rates[NL80211_BAND_2GHZ] & 0xf) 390 mode |= RTW89_RA_MODE_CCK; 391 if (link_sta->supp_rates[NL80211_BAND_2GHZ] & 0xff0) 392 mode |= RTW89_RA_MODE_OFDM; 393 break; 394 case RTW89_BAND_5G: 395 ra_mask |= (u64)link_sta->supp_rates[NL80211_BAND_5GHZ] << 4; 396 mode |= RTW89_RA_MODE_OFDM; 397 break; 398 case RTW89_BAND_6G: 399 ra_mask |= (u64)link_sta->supp_rates[NL80211_BAND_6GHZ] << 4; 400 mode |= RTW89_RA_MODE_OFDM; 401 break; 402 default: 403 rtw89_err(rtwdev, "Unknown band type\n"); 404 break; 405 } 406 407 ra_mask_bak = ra_mask; 408 409 if (mode >= RTW89_RA_MODE_HT) { 410 u64 mask = 0; 411 for (i = 0; i < rtwdev->hal.tx_nss; i++) 412 mask |= high_rate_masks[i]; 413 if (mode & RTW89_RA_MODE_OFDM) 414 mask |= RA_MASK_SUBOFDM_RATES; 415 if (mode & RTW89_RA_MODE_CCK) 416 mask |= RA_MASK_SUBCCK_RATES; 417 ra_mask &= mask; 418 } else if (mode & RTW89_RA_MODE_OFDM) { 419 ra_mask &= (RA_MASK_OFDM_RATES | RA_MASK_SUBCCK_RATES); 420 } 421 422 if (mode != RTW89_RA_MODE_CCK) 423 ra_mask &= rtw89_phy_ra_mask_rssi(rtwdev, rssi, 0); 424 425 ra_mask = rtw89_phy_ra_mask_recover(ra_mask, ra_mask_bak); 426 ra_mask &= rtw89_phy_ra_mask_cfg(rtwdev, rtwsta_link, link_sta, chan); 427 428 switch (link_sta->bandwidth) { 429 case IEEE80211_STA_RX_BW_160: 430 bw_mode = RTW89_CHANNEL_WIDTH_160; 431 sgi = link_sta->vht_cap.vht_supported && 432 (link_sta->vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_160); 433 break; 434 case IEEE80211_STA_RX_BW_80: 435 bw_mode = RTW89_CHANNEL_WIDTH_80; 436 sgi = link_sta->vht_cap.vht_supported && 437 (link_sta->vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_80); 438 break; 439 case IEEE80211_STA_RX_BW_40: 440 bw_mode = RTW89_CHANNEL_WIDTH_40; 441 sgi = link_sta->ht_cap.ht_supported && 442 (link_sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40); 443 break; 444 default: 445 bw_mode = RTW89_CHANNEL_WIDTH_20; 446 sgi = link_sta->ht_cap.ht_supported && 447 (link_sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20); 448 break; 449 } 450 451 if (link_sta->he_cap.he_cap_elem.phy_cap_info[3] & 452 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_16_QAM) 453 ra->dcm_cap = 1; 454 455 if (rate_pattern->enable && !p2p) { 456 ra_mask = rtw89_phy_ra_mask_cfg(rtwdev, rtwsta_link, link_sta, chan); 457 ra_mask &= rate_pattern->ra_mask; 458 mode = rate_pattern->ra_mode; 459 } 460 461 ra->bw_cap = bw_mode; 462 ra->er_cap = rtwsta_link->er_cap; 463 ra->mode_ctrl = mode; 464 ra->macid = rtwsta_link->mac_id; 465 ra->stbc_cap = stbc_en; 466 ra->ldpc_cap = ldpc_en; 467 ra->ss_num = min(link_sta->rx_nss, rtwdev->hal.tx_nss) - 1; 468 ra->en_sgi = sgi; 469 ra->ra_mask = ra_mask; 470 ra->fix_giltf_en = fix_giltf_en; 471 ra->fix_giltf = fix_giltf; 472 473 if (!csi) 474 return; 475 476 ra->fixed_csi_rate_en = false; 477 ra->ra_csi_rate_en = true; 478 ra->cr_tbl_sel = false; 479 ra->band_num = rtwvif_link->phy_idx; 480 ra->csi_bw = bw_mode; 481 ra->csi_gi_ltf = RTW89_GILTF_LGI_4XHE32; 482 ra->csi_mcs_ss_idx = 5; 483 ra->csi_mode = csi_mode; 484 } 485 486 void rtw89_phy_ra_update_sta_link(struct rtw89_dev *rtwdev, 487 struct rtw89_sta_link *rtwsta_link, 488 u32 changed) 489 { 490 struct rtw89_vif_link *rtwvif_link = rtwsta_link->rtwvif_link; 491 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 492 struct rtw89_ra_info *ra = &rtwsta_link->ra; 493 struct ieee80211_link_sta *link_sta; 494 495 rcu_read_lock(); 496 497 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, false); 498 rtw89_phy_ra_sta_update(rtwdev, rtwvif_link, rtwsta_link, 499 link_sta, vif->p2p, false); 500 501 rcu_read_unlock(); 502 503 if (changed & IEEE80211_RC_SUPP_RATES_CHANGED) 504 ra->upd_mask = 1; 505 if (changed & (IEEE80211_RC_BW_CHANGED | IEEE80211_RC_NSS_CHANGED)) 506 ra->upd_bw_nss_mask = 1; 507 508 rtw89_debug(rtwdev, RTW89_DBG_RA, 509 "ra updat: macid = %d, bw = %d, nss = %d, gi = %d %d", 510 ra->macid, 511 ra->bw_cap, 512 ra->ss_num, 513 ra->en_sgi, 514 ra->giltf); 515 516 rtw89_fw_h2c_ra(rtwdev, ra, false); 517 } 518 519 void rtw89_phy_ra_update_sta(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta, 520 u32 changed) 521 { 522 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta); 523 struct rtw89_sta_link *rtwsta_link; 524 unsigned int link_id; 525 526 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) 527 rtw89_phy_ra_update_sta_link(rtwdev, rtwsta_link, changed); 528 } 529 530 static bool __check_rate_pattern(struct rtw89_phy_rate_pattern *next, 531 u16 rate_base, u64 ra_mask, u8 ra_mode, 532 u32 rate_ctrl, u32 ctrl_skip, bool force) 533 { 534 u8 n, c; 535 536 if (rate_ctrl == ctrl_skip) 537 return true; 538 539 n = hweight32(rate_ctrl); 540 if (n == 0) 541 return true; 542 543 if (force && n != 1) 544 return false; 545 546 if (next->enable) 547 return false; 548 549 c = __fls(rate_ctrl); 550 next->rate = rate_base + c; 551 next->ra_mode = ra_mode; 552 next->ra_mask = ra_mask; 553 next->enable = true; 554 555 return true; 556 } 557 558 #define RTW89_HW_RATE_BY_CHIP_GEN(rate) \ 559 { \ 560 [RTW89_CHIP_AX] = RTW89_HW_RATE_ ## rate, \ 561 [RTW89_CHIP_BE] = RTW89_HW_RATE_V1_ ## rate, \ 562 } 563 564 static 565 void __rtw89_phy_rate_pattern_vif(struct rtw89_dev *rtwdev, 566 struct rtw89_vif_link *rtwvif_link, 567 const struct cfg80211_bitrate_mask *mask) 568 { 569 struct ieee80211_supported_band *sband; 570 struct rtw89_phy_rate_pattern next_pattern = {0}; 571 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, 572 rtwvif_link->chanctx_idx); 573 static const u16 hw_rate_he[][RTW89_CHIP_GEN_NUM] = { 574 RTW89_HW_RATE_BY_CHIP_GEN(HE_NSS1_MCS0), 575 RTW89_HW_RATE_BY_CHIP_GEN(HE_NSS2_MCS0), 576 RTW89_HW_RATE_BY_CHIP_GEN(HE_NSS3_MCS0), 577 RTW89_HW_RATE_BY_CHIP_GEN(HE_NSS4_MCS0), 578 }; 579 static const u16 hw_rate_vht[][RTW89_CHIP_GEN_NUM] = { 580 RTW89_HW_RATE_BY_CHIP_GEN(VHT_NSS1_MCS0), 581 RTW89_HW_RATE_BY_CHIP_GEN(VHT_NSS2_MCS0), 582 RTW89_HW_RATE_BY_CHIP_GEN(VHT_NSS3_MCS0), 583 RTW89_HW_RATE_BY_CHIP_GEN(VHT_NSS4_MCS0), 584 }; 585 static const u16 hw_rate_ht[][RTW89_CHIP_GEN_NUM] = { 586 RTW89_HW_RATE_BY_CHIP_GEN(MCS0), 587 RTW89_HW_RATE_BY_CHIP_GEN(MCS8), 588 RTW89_HW_RATE_BY_CHIP_GEN(MCS16), 589 RTW89_HW_RATE_BY_CHIP_GEN(MCS24), 590 }; 591 u8 band = chan->band_type; 592 enum nl80211_band nl_band = rtw89_hw_to_nl80211_band(band); 593 enum rtw89_chip_gen chip_gen = rtwdev->chip->chip_gen; 594 u8 tx_nss = rtwdev->hal.tx_nss; 595 u8 i; 596 597 for (i = 0; i < tx_nss; i++) 598 if (!__check_rate_pattern(&next_pattern, hw_rate_he[i][chip_gen], 599 RA_MASK_HE_RATES, RTW89_RA_MODE_HE, 600 mask->control[nl_band].he_mcs[i], 601 0, true)) 602 goto out; 603 604 for (i = 0; i < tx_nss; i++) 605 if (!__check_rate_pattern(&next_pattern, hw_rate_vht[i][chip_gen], 606 RA_MASK_VHT_RATES, RTW89_RA_MODE_VHT, 607 mask->control[nl_band].vht_mcs[i], 608 0, true)) 609 goto out; 610 611 for (i = 0; i < tx_nss; i++) 612 if (!__check_rate_pattern(&next_pattern, hw_rate_ht[i][chip_gen], 613 RA_MASK_HT_RATES, RTW89_RA_MODE_HT, 614 mask->control[nl_band].ht_mcs[i], 615 0, true)) 616 goto out; 617 618 /* lagacy cannot be empty for nl80211_parse_tx_bitrate_mask, and 619 * require at least one basic rate for ieee80211_set_bitrate_mask, 620 * so the decision just depends on if all bitrates are set or not. 621 */ 622 sband = rtwdev->hw->wiphy->bands[nl_band]; 623 if (band == RTW89_BAND_2G) { 624 if (!__check_rate_pattern(&next_pattern, RTW89_HW_RATE_CCK1, 625 RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES, 626 RTW89_RA_MODE_CCK | RTW89_RA_MODE_OFDM, 627 mask->control[nl_band].legacy, 628 BIT(sband->n_bitrates) - 1, false)) 629 goto out; 630 } else { 631 if (!__check_rate_pattern(&next_pattern, RTW89_HW_RATE_OFDM6, 632 RA_MASK_OFDM_RATES, RTW89_RA_MODE_OFDM, 633 mask->control[nl_band].legacy, 634 BIT(sband->n_bitrates) - 1, false)) 635 goto out; 636 } 637 638 if (!next_pattern.enable) 639 goto out; 640 641 rtwvif_link->rate_pattern = next_pattern; 642 rtw89_debug(rtwdev, RTW89_DBG_RA, 643 "configure pattern: rate 0x%x, mask 0x%llx, mode 0x%x\n", 644 next_pattern.rate, 645 next_pattern.ra_mask, 646 next_pattern.ra_mode); 647 return; 648 649 out: 650 rtwvif_link->rate_pattern.enable = false; 651 rtw89_debug(rtwdev, RTW89_DBG_RA, "unset rate pattern\n"); 652 } 653 654 void rtw89_phy_rate_pattern_vif(struct rtw89_dev *rtwdev, 655 struct ieee80211_vif *vif, 656 const struct cfg80211_bitrate_mask *mask) 657 { 658 struct rtw89_vif *rtwvif = vif_to_rtwvif(vif); 659 struct rtw89_vif_link *rtwvif_link; 660 unsigned int link_id; 661 662 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) 663 __rtw89_phy_rate_pattern_vif(rtwdev, rtwvif_link, mask); 664 } 665 666 static void rtw89_phy_ra_update_sta_iter(void *data, struct ieee80211_sta *sta) 667 { 668 struct rtw89_dev *rtwdev = (struct rtw89_dev *)data; 669 670 rtw89_phy_ra_update_sta(rtwdev, sta, IEEE80211_RC_SUPP_RATES_CHANGED); 671 } 672 673 void rtw89_phy_ra_update(struct rtw89_dev *rtwdev) 674 { 675 ieee80211_iterate_stations_atomic(rtwdev->hw, 676 rtw89_phy_ra_update_sta_iter, 677 rtwdev); 678 } 679 680 void rtw89_phy_ra_assoc(struct rtw89_dev *rtwdev, struct rtw89_sta_link *rtwsta_link) 681 { 682 struct rtw89_vif_link *rtwvif_link = rtwsta_link->rtwvif_link; 683 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 684 struct rtw89_ra_info *ra = &rtwsta_link->ra; 685 u8 rssi = ewma_rssi_read(&rtwsta_link->avg_rssi) >> RSSI_FACTOR; 686 struct ieee80211_link_sta *link_sta; 687 bool csi; 688 689 rcu_read_lock(); 690 691 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true); 692 csi = rtw89_sta_has_beamformer_cap(link_sta); 693 694 rtw89_phy_ra_sta_update(rtwdev, rtwvif_link, rtwsta_link, 695 link_sta, vif->p2p, csi); 696 697 rcu_read_unlock(); 698 699 if (rssi > 40) 700 ra->init_rate_lv = 1; 701 else if (rssi > 20) 702 ra->init_rate_lv = 2; 703 else if (rssi > 1) 704 ra->init_rate_lv = 3; 705 else 706 ra->init_rate_lv = 0; 707 ra->upd_all = 1; 708 rtw89_debug(rtwdev, RTW89_DBG_RA, 709 "ra assoc: macid = %d, mode = %d, bw = %d, nss = %d, lv = %d", 710 ra->macid, 711 ra->mode_ctrl, 712 ra->bw_cap, 713 ra->ss_num, 714 ra->init_rate_lv); 715 rtw89_debug(rtwdev, RTW89_DBG_RA, 716 "ra assoc: dcm = %d, er = %d, ldpc = %d, stbc = %d, gi = %d %d", 717 ra->dcm_cap, 718 ra->er_cap, 719 ra->ldpc_cap, 720 ra->stbc_cap, 721 ra->en_sgi, 722 ra->giltf); 723 724 rtw89_fw_h2c_ra(rtwdev, ra, csi); 725 } 726 727 u8 rtw89_phy_get_txsc(struct rtw89_dev *rtwdev, 728 const struct rtw89_chan *chan, 729 enum rtw89_bandwidth dbw) 730 { 731 enum rtw89_bandwidth cbw = chan->band_width; 732 u8 pri_ch = chan->primary_channel; 733 u8 central_ch = chan->channel; 734 u8 txsc_idx = 0; 735 u8 tmp = 0; 736 737 if (cbw == dbw || cbw == RTW89_CHANNEL_WIDTH_20) 738 return txsc_idx; 739 740 switch (cbw) { 741 case RTW89_CHANNEL_WIDTH_40: 742 txsc_idx = pri_ch > central_ch ? 1 : 2; 743 break; 744 case RTW89_CHANNEL_WIDTH_80: 745 if (dbw == RTW89_CHANNEL_WIDTH_20) { 746 if (pri_ch > central_ch) 747 txsc_idx = (pri_ch - central_ch) >> 1; 748 else 749 txsc_idx = ((central_ch - pri_ch) >> 1) + 1; 750 } else { 751 txsc_idx = pri_ch > central_ch ? 9 : 10; 752 } 753 break; 754 case RTW89_CHANNEL_WIDTH_160: 755 if (pri_ch > central_ch) 756 tmp = (pri_ch - central_ch) >> 1; 757 else 758 tmp = ((central_ch - pri_ch) >> 1) + 1; 759 760 if (dbw == RTW89_CHANNEL_WIDTH_20) { 761 txsc_idx = tmp; 762 } else if (dbw == RTW89_CHANNEL_WIDTH_40) { 763 if (tmp == 1 || tmp == 3) 764 txsc_idx = 9; 765 else if (tmp == 5 || tmp == 7) 766 txsc_idx = 11; 767 else if (tmp == 2 || tmp == 4) 768 txsc_idx = 10; 769 else if (tmp == 6 || tmp == 8) 770 txsc_idx = 12; 771 else 772 return 0xff; 773 } else { 774 txsc_idx = pri_ch > central_ch ? 13 : 14; 775 } 776 break; 777 case RTW89_CHANNEL_WIDTH_80_80: 778 if (dbw == RTW89_CHANNEL_WIDTH_20) { 779 if (pri_ch > central_ch) 780 txsc_idx = (10 - (pri_ch - central_ch)) >> 1; 781 else 782 txsc_idx = ((central_ch - pri_ch) >> 1) + 5; 783 } else if (dbw == RTW89_CHANNEL_WIDTH_40) { 784 txsc_idx = pri_ch > central_ch ? 10 : 12; 785 } else { 786 txsc_idx = 14; 787 } 788 break; 789 default: 790 break; 791 } 792 793 return txsc_idx; 794 } 795 EXPORT_SYMBOL(rtw89_phy_get_txsc); 796 797 u8 rtw89_phy_get_txsb(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan, 798 enum rtw89_bandwidth dbw) 799 { 800 enum rtw89_bandwidth cbw = chan->band_width; 801 u8 pri_ch = chan->primary_channel; 802 u8 central_ch = chan->channel; 803 u8 txsb_idx = 0; 804 805 if (cbw == dbw || cbw == RTW89_CHANNEL_WIDTH_20) 806 return txsb_idx; 807 808 switch (cbw) { 809 case RTW89_CHANNEL_WIDTH_40: 810 txsb_idx = pri_ch > central_ch ? 1 : 0; 811 break; 812 case RTW89_CHANNEL_WIDTH_80: 813 if (dbw == RTW89_CHANNEL_WIDTH_20) 814 txsb_idx = (pri_ch - central_ch + 6) / 4; 815 else 816 txsb_idx = pri_ch > central_ch ? 1 : 0; 817 break; 818 case RTW89_CHANNEL_WIDTH_160: 819 if (dbw == RTW89_CHANNEL_WIDTH_20) 820 txsb_idx = (pri_ch - central_ch + 14) / 4; 821 else if (dbw == RTW89_CHANNEL_WIDTH_40) 822 txsb_idx = (pri_ch - central_ch + 12) / 8; 823 else 824 txsb_idx = pri_ch > central_ch ? 1 : 0; 825 break; 826 case RTW89_CHANNEL_WIDTH_320: 827 if (dbw == RTW89_CHANNEL_WIDTH_20) 828 txsb_idx = (pri_ch - central_ch + 30) / 4; 829 else if (dbw == RTW89_CHANNEL_WIDTH_40) 830 txsb_idx = (pri_ch - central_ch + 28) / 8; 831 else if (dbw == RTW89_CHANNEL_WIDTH_80) 832 txsb_idx = (pri_ch - central_ch + 24) / 16; 833 else 834 txsb_idx = pri_ch > central_ch ? 1 : 0; 835 break; 836 default: 837 break; 838 } 839 840 return txsb_idx; 841 } 842 EXPORT_SYMBOL(rtw89_phy_get_txsb); 843 844 static bool rtw89_phy_check_swsi_busy(struct rtw89_dev *rtwdev) 845 { 846 return !!rtw89_phy_read32_mask(rtwdev, R_SWSI_V1, B_SWSI_W_BUSY_V1) || 847 !!rtw89_phy_read32_mask(rtwdev, R_SWSI_V1, B_SWSI_R_BUSY_V1); 848 } 849 850 u32 rtw89_phy_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 851 u32 addr, u32 mask) 852 { 853 const struct rtw89_chip_info *chip = rtwdev->chip; 854 const u32 *base_addr = chip->rf_base_addr; 855 u32 val, direct_addr; 856 857 if (rf_path >= rtwdev->chip->rf_path_num) { 858 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 859 return INV_RF_DATA; 860 } 861 862 addr &= 0xff; 863 direct_addr = base_addr[rf_path] + (addr << 2); 864 mask &= RFREG_MASK; 865 866 val = rtw89_phy_read32_mask(rtwdev, direct_addr, mask); 867 868 return val; 869 } 870 EXPORT_SYMBOL(rtw89_phy_read_rf); 871 872 static u32 rtw89_phy_read_rf_a(struct rtw89_dev *rtwdev, 873 enum rtw89_rf_path rf_path, u32 addr, u32 mask) 874 { 875 bool busy; 876 bool done; 877 u32 val; 878 int ret; 879 880 ret = read_poll_timeout_atomic(rtw89_phy_check_swsi_busy, busy, !busy, 881 1, 30, false, rtwdev); 882 if (ret) { 883 rtw89_err(rtwdev, "read rf busy swsi\n"); 884 return INV_RF_DATA; 885 } 886 887 mask &= RFREG_MASK; 888 889 val = FIELD_PREP(B_SWSI_READ_ADDR_PATH_V1, rf_path) | 890 FIELD_PREP(B_SWSI_READ_ADDR_ADDR_V1, addr); 891 rtw89_phy_write32_mask(rtwdev, R_SWSI_READ_ADDR_V1, B_SWSI_READ_ADDR_V1, val); 892 udelay(2); 893 894 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, done, done, 1, 895 30, false, rtwdev, R_SWSI_V1, 896 B_SWSI_R_DATA_DONE_V1); 897 if (ret) { 898 rtw89_err(rtwdev, "read swsi busy\n"); 899 return INV_RF_DATA; 900 } 901 902 return rtw89_phy_read32_mask(rtwdev, R_SWSI_V1, mask); 903 } 904 905 u32 rtw89_phy_read_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 906 u32 addr, u32 mask) 907 { 908 bool ad_sel = FIELD_GET(RTW89_RF_ADDR_ADSEL_MASK, addr); 909 910 if (rf_path >= rtwdev->chip->rf_path_num) { 911 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 912 return INV_RF_DATA; 913 } 914 915 if (ad_sel) 916 return rtw89_phy_read_rf(rtwdev, rf_path, addr, mask); 917 else 918 return rtw89_phy_read_rf_a(rtwdev, rf_path, addr, mask); 919 } 920 EXPORT_SYMBOL(rtw89_phy_read_rf_v1); 921 922 static u32 rtw89_phy_read_full_rf_v2_a(struct rtw89_dev *rtwdev, 923 enum rtw89_rf_path rf_path, u32 addr) 924 { 925 static const u16 r_addr_ofst[2] = {0x2C24, 0x2D24}; 926 static const u16 addr_ofst[2] = {0x2ADC, 0x2BDC}; 927 bool busy, done; 928 int ret; 929 u32 val; 930 931 rtw89_phy_write32_mask(rtwdev, addr_ofst[rf_path], B_HWSI_ADD_CTL_MASK, 0x1); 932 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, busy, !busy, 933 1, 3800, false, 934 rtwdev, r_addr_ofst[rf_path], B_HWSI_VAL_BUSY); 935 if (ret) { 936 rtw89_warn(rtwdev, "poll HWSI is busy\n"); 937 return INV_RF_DATA; 938 } 939 940 rtw89_phy_write32_mask(rtwdev, addr_ofst[rf_path], B_HWSI_ADD_MASK, addr); 941 rtw89_phy_write32_mask(rtwdev, addr_ofst[rf_path], B_HWSI_ADD_RD, 0x1); 942 udelay(2); 943 944 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, done, done, 945 1, 3800, false, 946 rtwdev, r_addr_ofst[rf_path], B_HWSI_VAL_RDONE); 947 if (ret) { 948 rtw89_warn(rtwdev, "read HWSI is busy\n"); 949 val = INV_RF_DATA; 950 goto out; 951 } 952 953 val = rtw89_phy_read32_mask(rtwdev, r_addr_ofst[rf_path], RFREG_MASK); 954 out: 955 rtw89_phy_write32_mask(rtwdev, addr_ofst[rf_path], B_HWSI_ADD_POLL_MASK, 0); 956 957 return val; 958 } 959 960 static u32 rtw89_phy_read_rf_v2_a(struct rtw89_dev *rtwdev, 961 enum rtw89_rf_path rf_path, u32 addr, u32 mask) 962 { 963 u32 val; 964 965 val = rtw89_phy_read_full_rf_v2_a(rtwdev, rf_path, addr); 966 967 return (val & mask) >> __ffs(mask); 968 } 969 970 u32 rtw89_phy_read_rf_v2(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 971 u32 addr, u32 mask) 972 { 973 bool ad_sel = u32_get_bits(addr, RTW89_RF_ADDR_ADSEL_MASK); 974 975 if (rf_path >= rtwdev->chip->rf_path_num) { 976 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 977 return INV_RF_DATA; 978 } 979 980 if (ad_sel) 981 return rtw89_phy_read_rf(rtwdev, rf_path, addr, mask); 982 else 983 return rtw89_phy_read_rf_v2_a(rtwdev, rf_path, addr, mask); 984 } 985 EXPORT_SYMBOL(rtw89_phy_read_rf_v2); 986 987 bool rtw89_phy_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 988 u32 addr, u32 mask, u32 data) 989 { 990 const struct rtw89_chip_info *chip = rtwdev->chip; 991 const u32 *base_addr = chip->rf_base_addr; 992 u32 direct_addr; 993 994 if (rf_path >= rtwdev->chip->rf_path_num) { 995 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 996 return false; 997 } 998 999 addr &= 0xff; 1000 direct_addr = base_addr[rf_path] + (addr << 2); 1001 mask &= RFREG_MASK; 1002 1003 rtw89_phy_write32_mask(rtwdev, direct_addr, mask, data); 1004 1005 /* delay to ensure writing properly */ 1006 udelay(1); 1007 1008 return true; 1009 } 1010 EXPORT_SYMBOL(rtw89_phy_write_rf); 1011 1012 static bool rtw89_phy_write_rf_a(struct rtw89_dev *rtwdev, 1013 enum rtw89_rf_path rf_path, u32 addr, u32 mask, 1014 u32 data) 1015 { 1016 u8 bit_shift; 1017 u32 val; 1018 bool busy, b_msk_en = false; 1019 int ret; 1020 1021 ret = read_poll_timeout_atomic(rtw89_phy_check_swsi_busy, busy, !busy, 1022 1, 30, false, rtwdev); 1023 if (ret) { 1024 rtw89_err(rtwdev, "write rf busy swsi\n"); 1025 return false; 1026 } 1027 1028 data &= RFREG_MASK; 1029 mask &= RFREG_MASK; 1030 1031 if (mask != RFREG_MASK) { 1032 b_msk_en = true; 1033 rtw89_phy_write32_mask(rtwdev, R_SWSI_BIT_MASK_V1, RFREG_MASK, 1034 mask); 1035 bit_shift = __ffs(mask); 1036 data = (data << bit_shift) & RFREG_MASK; 1037 } 1038 1039 val = FIELD_PREP(B_SWSI_DATA_BIT_MASK_EN_V1, b_msk_en) | 1040 FIELD_PREP(B_SWSI_DATA_PATH_V1, rf_path) | 1041 FIELD_PREP(B_SWSI_DATA_ADDR_V1, addr) | 1042 FIELD_PREP(B_SWSI_DATA_VAL_V1, data); 1043 1044 rtw89_phy_write32_mask(rtwdev, R_SWSI_DATA_V1, MASKDWORD, val); 1045 1046 return true; 1047 } 1048 1049 bool rtw89_phy_write_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 1050 u32 addr, u32 mask, u32 data) 1051 { 1052 bool ad_sel = FIELD_GET(RTW89_RF_ADDR_ADSEL_MASK, addr); 1053 1054 if (rf_path >= rtwdev->chip->rf_path_num) { 1055 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 1056 return false; 1057 } 1058 1059 if (ad_sel) 1060 return rtw89_phy_write_rf(rtwdev, rf_path, addr, mask, data); 1061 else 1062 return rtw89_phy_write_rf_a(rtwdev, rf_path, addr, mask, data); 1063 } 1064 EXPORT_SYMBOL(rtw89_phy_write_rf_v1); 1065 1066 static 1067 bool rtw89_phy_write_full_rf_v2_a(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 1068 u32 addr, u32 data) 1069 { 1070 static const u32 addr_is_idle[2] = {0x2C24, 0x2D24}; 1071 static const u32 addr_ofst[2] = {0x2AE0, 0x2BE0}; 1072 bool busy; 1073 u32 val; 1074 int ret; 1075 1076 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, busy, !busy, 1077 1, 3800, false, 1078 rtwdev, addr_is_idle[rf_path], BIT(29)); 1079 if (ret) { 1080 rtw89_warn(rtwdev, "[%s] HWSI is busy\n", __func__); 1081 return false; 1082 } 1083 1084 val = u32_encode_bits(addr, B_HWSI_DATA_ADDR) | 1085 u32_encode_bits(data, B_HWSI_DATA_VAL); 1086 1087 rtw89_phy_write32(rtwdev, addr_ofst[rf_path], val); 1088 1089 return true; 1090 } 1091 1092 static 1093 bool rtw89_phy_write_rf_a_v2(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 1094 u32 addr, u32 mask, u32 data) 1095 { 1096 u32 val; 1097 1098 if (mask == RFREG_MASK) { 1099 val = data; 1100 } else { 1101 val = rtw89_phy_read_full_rf_v2_a(rtwdev, rf_path, addr); 1102 val &= ~mask; 1103 val |= (data << __ffs(mask)) & mask; 1104 } 1105 1106 return rtw89_phy_write_full_rf_v2_a(rtwdev, rf_path, addr, val); 1107 } 1108 1109 bool rtw89_phy_write_rf_v2(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 1110 u32 addr, u32 mask, u32 data) 1111 { 1112 bool ad_sel = u32_get_bits(addr, RTW89_RF_ADDR_ADSEL_MASK); 1113 1114 if (rf_path >= rtwdev->chip->rf_path_num) { 1115 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 1116 return INV_RF_DATA; 1117 } 1118 1119 if (ad_sel) 1120 return rtw89_phy_write_rf(rtwdev, rf_path, addr, mask, data); 1121 else 1122 return rtw89_phy_write_rf_a_v2(rtwdev, rf_path, addr, mask, data); 1123 } 1124 EXPORT_SYMBOL(rtw89_phy_write_rf_v2); 1125 1126 static bool rtw89_chip_rf_v1(struct rtw89_dev *rtwdev) 1127 { 1128 return rtwdev->chip->ops->write_rf == rtw89_phy_write_rf_v1; 1129 } 1130 1131 static void __rtw89_phy_bb_reset(struct rtw89_dev *rtwdev, 1132 enum rtw89_phy_idx phy_idx) 1133 { 1134 const struct rtw89_chip_info *chip = rtwdev->chip; 1135 1136 chip->ops->bb_reset(rtwdev, phy_idx); 1137 } 1138 1139 static void rtw89_phy_bb_reset(struct rtw89_dev *rtwdev) 1140 { 1141 __rtw89_phy_bb_reset(rtwdev, RTW89_PHY_0); 1142 if (rtwdev->dbcc_en) 1143 __rtw89_phy_bb_reset(rtwdev, RTW89_PHY_1); 1144 } 1145 1146 static void rtw89_phy_config_bb_reg(struct rtw89_dev *rtwdev, 1147 const struct rtw89_reg2_def *reg, 1148 enum rtw89_rf_path rf_path, 1149 void *extra_data) 1150 { 1151 u32 addr; 1152 1153 if (reg->addr == 0xfe) { 1154 mdelay(50); 1155 } else if (reg->addr == 0xfd) { 1156 mdelay(5); 1157 } else if (reg->addr == 0xfc) { 1158 mdelay(1); 1159 } else if (reg->addr == 0xfb) { 1160 udelay(50); 1161 } else if (reg->addr == 0xfa) { 1162 udelay(5); 1163 } else if (reg->addr == 0xf9) { 1164 udelay(1); 1165 } else if (reg->data == BYPASS_CR_DATA) { 1166 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "Bypass CR 0x%x\n", reg->addr); 1167 } else { 1168 addr = reg->addr; 1169 1170 if ((uintptr_t)extra_data == RTW89_PHY_1) 1171 addr += rtw89_phy0_phy1_offset(rtwdev, reg->addr); 1172 1173 rtw89_phy_write32(rtwdev, addr, reg->data); 1174 } 1175 } 1176 1177 union rtw89_phy_bb_gain_arg { 1178 u32 addr; 1179 struct { 1180 union { 1181 u8 type; 1182 struct { 1183 u8 rxsc_start:4; 1184 u8 bw:4; 1185 }; 1186 }; 1187 u8 path; 1188 u8 gain_band; 1189 u8 cfg_type; 1190 }; 1191 } __packed; 1192 1193 static void 1194 rtw89_phy_cfg_bb_gain_error(struct rtw89_dev *rtwdev, 1195 union rtw89_phy_bb_gain_arg arg, u32 data) 1196 { 1197 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax; 1198 u8 type = arg.type; 1199 u8 path = arg.path; 1200 u8 gband = arg.gain_band; 1201 int i; 1202 1203 switch (type) { 1204 case 0: 1205 for (i = 0; i < 4; i++, data >>= 8) 1206 gain->lna_gain[gband][path][i] = data & 0xff; 1207 break; 1208 case 1: 1209 for (i = 4; i < 7; i++, data >>= 8) 1210 gain->lna_gain[gband][path][i] = data & 0xff; 1211 break; 1212 case 2: 1213 for (i = 0; i < 2; i++, data >>= 8) 1214 gain->tia_gain[gband][path][i] = data & 0xff; 1215 break; 1216 default: 1217 rtw89_warn(rtwdev, 1218 "bb gain error {0x%x:0x%x} with unknown type: %d\n", 1219 arg.addr, data, type); 1220 break; 1221 } 1222 } 1223 1224 enum rtw89_phy_bb_rxsc_start_idx { 1225 RTW89_BB_RXSC_START_IDX_FULL = 0, 1226 RTW89_BB_RXSC_START_IDX_20 = 1, 1227 RTW89_BB_RXSC_START_IDX_20_1 = 5, 1228 RTW89_BB_RXSC_START_IDX_40 = 9, 1229 RTW89_BB_RXSC_START_IDX_80 = 13, 1230 }; 1231 1232 static void 1233 rtw89_phy_cfg_bb_rpl_ofst(struct rtw89_dev *rtwdev, 1234 union rtw89_phy_bb_gain_arg arg, u32 data) 1235 { 1236 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax; 1237 u8 rxsc_start = arg.rxsc_start; 1238 u8 bw = arg.bw; 1239 u8 path = arg.path; 1240 u8 gband = arg.gain_band; 1241 u8 rxsc; 1242 s8 ofst; 1243 int i; 1244 1245 switch (bw) { 1246 case RTW89_CHANNEL_WIDTH_20: 1247 gain->rpl_ofst_20[gband][path] = (s8)data; 1248 break; 1249 case RTW89_CHANNEL_WIDTH_40: 1250 if (rxsc_start == RTW89_BB_RXSC_START_IDX_FULL) { 1251 gain->rpl_ofst_40[gband][path][0] = (s8)data; 1252 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20) { 1253 for (i = 0; i < 2; i++, data >>= 8) { 1254 rxsc = RTW89_BB_RXSC_START_IDX_20 + i; 1255 ofst = (s8)(data & 0xff); 1256 gain->rpl_ofst_40[gband][path][rxsc] = ofst; 1257 } 1258 } 1259 break; 1260 case RTW89_CHANNEL_WIDTH_80: 1261 if (rxsc_start == RTW89_BB_RXSC_START_IDX_FULL) { 1262 gain->rpl_ofst_80[gband][path][0] = (s8)data; 1263 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20) { 1264 for (i = 0; i < 4; i++, data >>= 8) { 1265 rxsc = RTW89_BB_RXSC_START_IDX_20 + i; 1266 ofst = (s8)(data & 0xff); 1267 gain->rpl_ofst_80[gband][path][rxsc] = ofst; 1268 } 1269 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_40) { 1270 for (i = 0; i < 2; i++, data >>= 8) { 1271 rxsc = RTW89_BB_RXSC_START_IDX_40 + i; 1272 ofst = (s8)(data & 0xff); 1273 gain->rpl_ofst_80[gband][path][rxsc] = ofst; 1274 } 1275 } 1276 break; 1277 case RTW89_CHANNEL_WIDTH_160: 1278 if (rxsc_start == RTW89_BB_RXSC_START_IDX_FULL) { 1279 gain->rpl_ofst_160[gband][path][0] = (s8)data; 1280 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20) { 1281 for (i = 0; i < 4; i++, data >>= 8) { 1282 rxsc = RTW89_BB_RXSC_START_IDX_20 + i; 1283 ofst = (s8)(data & 0xff); 1284 gain->rpl_ofst_160[gband][path][rxsc] = ofst; 1285 } 1286 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20_1) { 1287 for (i = 0; i < 4; i++, data >>= 8) { 1288 rxsc = RTW89_BB_RXSC_START_IDX_20_1 + i; 1289 ofst = (s8)(data & 0xff); 1290 gain->rpl_ofst_160[gband][path][rxsc] = ofst; 1291 } 1292 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_40) { 1293 for (i = 0; i < 4; i++, data >>= 8) { 1294 rxsc = RTW89_BB_RXSC_START_IDX_40 + i; 1295 ofst = (s8)(data & 0xff); 1296 gain->rpl_ofst_160[gband][path][rxsc] = ofst; 1297 } 1298 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_80) { 1299 for (i = 0; i < 2; i++, data >>= 8) { 1300 rxsc = RTW89_BB_RXSC_START_IDX_80 + i; 1301 ofst = (s8)(data & 0xff); 1302 gain->rpl_ofst_160[gband][path][rxsc] = ofst; 1303 } 1304 } 1305 break; 1306 default: 1307 rtw89_warn(rtwdev, 1308 "bb rpl ofst {0x%x:0x%x} with unknown bw: %d\n", 1309 arg.addr, data, bw); 1310 break; 1311 } 1312 } 1313 1314 static void 1315 rtw89_phy_cfg_bb_gain_bypass(struct rtw89_dev *rtwdev, 1316 union rtw89_phy_bb_gain_arg arg, u32 data) 1317 { 1318 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax; 1319 u8 type = arg.type; 1320 u8 path = arg.path; 1321 u8 gband = arg.gain_band; 1322 int i; 1323 1324 switch (type) { 1325 case 0: 1326 for (i = 0; i < 4; i++, data >>= 8) 1327 gain->lna_gain_bypass[gband][path][i] = data & 0xff; 1328 break; 1329 case 1: 1330 for (i = 4; i < 7; i++, data >>= 8) 1331 gain->lna_gain_bypass[gband][path][i] = data & 0xff; 1332 break; 1333 default: 1334 rtw89_warn(rtwdev, 1335 "bb gain bypass {0x%x:0x%x} with unknown type: %d\n", 1336 arg.addr, data, type); 1337 break; 1338 } 1339 } 1340 1341 static void 1342 rtw89_phy_cfg_bb_gain_op1db(struct rtw89_dev *rtwdev, 1343 union rtw89_phy_bb_gain_arg arg, u32 data) 1344 { 1345 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax; 1346 u8 type = arg.type; 1347 u8 path = arg.path; 1348 u8 gband = arg.gain_band; 1349 int i; 1350 1351 switch (type) { 1352 case 0: 1353 for (i = 0; i < 4; i++, data >>= 8) 1354 gain->lna_op1db[gband][path][i] = data & 0xff; 1355 break; 1356 case 1: 1357 for (i = 4; i < 7; i++, data >>= 8) 1358 gain->lna_op1db[gband][path][i] = data & 0xff; 1359 break; 1360 case 2: 1361 for (i = 0; i < 4; i++, data >>= 8) 1362 gain->tia_lna_op1db[gband][path][i] = data & 0xff; 1363 break; 1364 case 3: 1365 for (i = 4; i < 8; i++, data >>= 8) 1366 gain->tia_lna_op1db[gband][path][i] = data & 0xff; 1367 break; 1368 default: 1369 rtw89_warn(rtwdev, 1370 "bb gain op1db {0x%x:0x%x} with unknown type: %d\n", 1371 arg.addr, data, type); 1372 break; 1373 } 1374 } 1375 1376 static void rtw89_phy_config_bb_gain_ax(struct rtw89_dev *rtwdev, 1377 const struct rtw89_reg2_def *reg, 1378 enum rtw89_rf_path rf_path, 1379 void *extra_data) 1380 { 1381 const struct rtw89_chip_info *chip = rtwdev->chip; 1382 union rtw89_phy_bb_gain_arg arg = { .addr = reg->addr }; 1383 struct rtw89_efuse *efuse = &rtwdev->efuse; 1384 1385 if (arg.gain_band >= RTW89_BB_GAIN_BAND_NR) 1386 return; 1387 1388 if (arg.path >= chip->rf_path_num) 1389 return; 1390 1391 if (arg.addr >= 0xf9 && arg.addr <= 0xfe) { 1392 rtw89_warn(rtwdev, "bb gain table with flow ctrl\n"); 1393 return; 1394 } 1395 1396 switch (arg.cfg_type) { 1397 case 0: 1398 rtw89_phy_cfg_bb_gain_error(rtwdev, arg, reg->data); 1399 break; 1400 case 1: 1401 rtw89_phy_cfg_bb_rpl_ofst(rtwdev, arg, reg->data); 1402 break; 1403 case 2: 1404 rtw89_phy_cfg_bb_gain_bypass(rtwdev, arg, reg->data); 1405 break; 1406 case 3: 1407 rtw89_phy_cfg_bb_gain_op1db(rtwdev, arg, reg->data); 1408 break; 1409 case 4: 1410 /* This cfg_type is only used by rfe_type >= 50 with eFEM */ 1411 if (efuse->rfe_type < 50) 1412 break; 1413 fallthrough; 1414 default: 1415 rtw89_warn(rtwdev, 1416 "bb gain {0x%x:0x%x} with unknown cfg type: %d\n", 1417 arg.addr, reg->data, arg.cfg_type); 1418 break; 1419 } 1420 } 1421 1422 static void 1423 rtw89_phy_cofig_rf_reg_store(struct rtw89_dev *rtwdev, 1424 const struct rtw89_reg2_def *reg, 1425 enum rtw89_rf_path rf_path, 1426 struct rtw89_fw_h2c_rf_reg_info *info) 1427 { 1428 u16 idx = info->curr_idx % RTW89_H2C_RF_PAGE_SIZE; 1429 u8 page = info->curr_idx / RTW89_H2C_RF_PAGE_SIZE; 1430 1431 if (page >= RTW89_H2C_RF_PAGE_NUM) { 1432 rtw89_warn(rtwdev, "RF parameters exceed size. path=%d, idx=%d", 1433 rf_path, info->curr_idx); 1434 return; 1435 } 1436 1437 info->rtw89_phy_config_rf_h2c[page][idx] = 1438 cpu_to_le32((reg->addr << 20) | reg->data); 1439 info->curr_idx++; 1440 } 1441 1442 static int rtw89_phy_config_rf_reg_fw(struct rtw89_dev *rtwdev, 1443 struct rtw89_fw_h2c_rf_reg_info *info) 1444 { 1445 u16 remain = info->curr_idx; 1446 u16 len = 0; 1447 u8 i; 1448 int ret = 0; 1449 1450 if (remain > RTW89_H2C_RF_PAGE_NUM * RTW89_H2C_RF_PAGE_SIZE) { 1451 rtw89_warn(rtwdev, 1452 "rf reg h2c total len %d larger than %d\n", 1453 remain, RTW89_H2C_RF_PAGE_NUM * RTW89_H2C_RF_PAGE_SIZE); 1454 ret = -EINVAL; 1455 goto out; 1456 } 1457 1458 for (i = 0; i < RTW89_H2C_RF_PAGE_NUM && remain; i++, remain -= len) { 1459 len = remain > RTW89_H2C_RF_PAGE_SIZE ? RTW89_H2C_RF_PAGE_SIZE : remain; 1460 ret = rtw89_fw_h2c_rf_reg(rtwdev, info, len * 4, i); 1461 if (ret) 1462 goto out; 1463 } 1464 out: 1465 info->curr_idx = 0; 1466 1467 return ret; 1468 } 1469 1470 static void rtw89_phy_config_rf_reg_noio(struct rtw89_dev *rtwdev, 1471 const struct rtw89_reg2_def *reg, 1472 enum rtw89_rf_path rf_path, 1473 void *extra_data) 1474 { 1475 u32 addr = reg->addr; 1476 1477 if (addr == 0xfe || addr == 0xfd || addr == 0xfc || addr == 0xfb || 1478 addr == 0xfa || addr == 0xf9) 1479 return; 1480 1481 if (rtw89_chip_rf_v1(rtwdev) && addr < 0x100) 1482 return; 1483 1484 rtw89_phy_cofig_rf_reg_store(rtwdev, reg, rf_path, 1485 (struct rtw89_fw_h2c_rf_reg_info *)extra_data); 1486 } 1487 1488 static void rtw89_phy_config_rf_reg(struct rtw89_dev *rtwdev, 1489 const struct rtw89_reg2_def *reg, 1490 enum rtw89_rf_path rf_path, 1491 void *extra_data) 1492 { 1493 if (reg->addr == 0xfe) { 1494 mdelay(50); 1495 } else if (reg->addr == 0xfd) { 1496 mdelay(5); 1497 } else if (reg->addr == 0xfc) { 1498 mdelay(1); 1499 } else if (reg->addr == 0xfb) { 1500 udelay(50); 1501 } else if (reg->addr == 0xfa) { 1502 udelay(5); 1503 } else if (reg->addr == 0xf9) { 1504 udelay(1); 1505 } else { 1506 rtw89_write_rf(rtwdev, rf_path, reg->addr, 0xfffff, reg->data); 1507 rtw89_phy_cofig_rf_reg_store(rtwdev, reg, rf_path, 1508 (struct rtw89_fw_h2c_rf_reg_info *)extra_data); 1509 } 1510 } 1511 1512 void rtw89_phy_config_rf_reg_v1(struct rtw89_dev *rtwdev, 1513 const struct rtw89_reg2_def *reg, 1514 enum rtw89_rf_path rf_path, 1515 void *extra_data) 1516 { 1517 rtw89_write_rf(rtwdev, rf_path, reg->addr, RFREG_MASK, reg->data); 1518 1519 if (reg->addr < 0x100) 1520 return; 1521 1522 rtw89_phy_cofig_rf_reg_store(rtwdev, reg, rf_path, 1523 (struct rtw89_fw_h2c_rf_reg_info *)extra_data); 1524 } 1525 EXPORT_SYMBOL(rtw89_phy_config_rf_reg_v1); 1526 1527 static int rtw89_phy_sel_headline(struct rtw89_dev *rtwdev, 1528 const struct rtw89_phy_table *table, 1529 u32 *headline_size, u32 *headline_idx, 1530 u8 rfe, u8 cv) 1531 { 1532 const struct rtw89_reg2_def *reg; 1533 u32 headline; 1534 u32 compare, target; 1535 u8 rfe_para, cv_para; 1536 u8 cv_max = 0; 1537 bool case_matched = false; 1538 u32 i; 1539 1540 for (i = 0; i < table->n_regs; i++) { 1541 reg = &table->regs[i]; 1542 headline = get_phy_headline(reg->addr); 1543 if (headline != PHY_HEADLINE_VALID) 1544 break; 1545 } 1546 *headline_size = i; 1547 if (*headline_size == 0) 1548 return 0; 1549 1550 /* case 1: RFE match, CV match */ 1551 compare = get_phy_compare(rfe, cv); 1552 for (i = 0; i < *headline_size; i++) { 1553 reg = &table->regs[i]; 1554 target = get_phy_target(reg->addr); 1555 if (target == compare) { 1556 *headline_idx = i; 1557 return 0; 1558 } 1559 } 1560 1561 /* case 2: RFE match, CV don't care */ 1562 compare = get_phy_compare(rfe, PHY_COND_DONT_CARE); 1563 for (i = 0; i < *headline_size; i++) { 1564 reg = &table->regs[i]; 1565 target = get_phy_target(reg->addr); 1566 if (target == compare) { 1567 *headline_idx = i; 1568 return 0; 1569 } 1570 } 1571 1572 /* case 3: RFE match, CV max in table */ 1573 for (i = 0; i < *headline_size; i++) { 1574 reg = &table->regs[i]; 1575 rfe_para = get_phy_cond_rfe(reg->addr); 1576 cv_para = get_phy_cond_cv(reg->addr); 1577 if (rfe_para == rfe) { 1578 if (cv_para >= cv_max) { 1579 cv_max = cv_para; 1580 *headline_idx = i; 1581 case_matched = true; 1582 } 1583 } 1584 } 1585 1586 if (case_matched) 1587 return 0; 1588 1589 /* case 4: RFE don't care, CV max in table */ 1590 for (i = 0; i < *headline_size; i++) { 1591 reg = &table->regs[i]; 1592 rfe_para = get_phy_cond_rfe(reg->addr); 1593 cv_para = get_phy_cond_cv(reg->addr); 1594 if (rfe_para == PHY_COND_DONT_CARE) { 1595 if (cv_para >= cv_max) { 1596 cv_max = cv_para; 1597 *headline_idx = i; 1598 case_matched = true; 1599 } 1600 } 1601 } 1602 1603 if (case_matched) 1604 return 0; 1605 1606 return -EINVAL; 1607 } 1608 1609 static void rtw89_phy_init_reg(struct rtw89_dev *rtwdev, 1610 const struct rtw89_phy_table *table, 1611 void (*config)(struct rtw89_dev *rtwdev, 1612 const struct rtw89_reg2_def *reg, 1613 enum rtw89_rf_path rf_path, 1614 void *data), 1615 void *extra_data) 1616 { 1617 const struct rtw89_reg2_def *reg; 1618 enum rtw89_rf_path rf_path = table->rf_path; 1619 u8 rfe = rtwdev->efuse.rfe_type; 1620 u8 cv = rtwdev->hal.cv; 1621 u32 i; 1622 u32 headline_size = 0, headline_idx = 0; 1623 u32 target = 0, cfg_target; 1624 u8 cond; 1625 bool is_matched = true; 1626 bool target_found = false; 1627 int ret; 1628 1629 ret = rtw89_phy_sel_headline(rtwdev, table, &headline_size, 1630 &headline_idx, rfe, cv); 1631 if (ret) { 1632 rtw89_err(rtwdev, "invalid PHY package: %d/%d\n", rfe, cv); 1633 return; 1634 } 1635 1636 cfg_target = get_phy_target(table->regs[headline_idx].addr); 1637 for (i = headline_size; i < table->n_regs; i++) { 1638 reg = &table->regs[i]; 1639 cond = get_phy_cond(reg->addr); 1640 switch (cond) { 1641 case PHY_COND_BRANCH_IF: 1642 case PHY_COND_BRANCH_ELIF: 1643 target = get_phy_target(reg->addr); 1644 break; 1645 case PHY_COND_BRANCH_ELSE: 1646 is_matched = false; 1647 if (!target_found) { 1648 rtw89_warn(rtwdev, "failed to load CR %x/%x\n", 1649 reg->addr, reg->data); 1650 return; 1651 } 1652 break; 1653 case PHY_COND_BRANCH_END: 1654 is_matched = true; 1655 target_found = false; 1656 break; 1657 case PHY_COND_CHECK: 1658 if (target_found) { 1659 is_matched = false; 1660 break; 1661 } 1662 1663 if (target == cfg_target) { 1664 is_matched = true; 1665 target_found = true; 1666 } else { 1667 is_matched = false; 1668 target_found = false; 1669 } 1670 break; 1671 default: 1672 if (is_matched) 1673 config(rtwdev, reg, rf_path, extra_data); 1674 break; 1675 } 1676 } 1677 } 1678 1679 void rtw89_phy_init_bb_reg(struct rtw89_dev *rtwdev) 1680 { 1681 struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info; 1682 const struct rtw89_chip_info *chip = rtwdev->chip; 1683 const struct rtw89_phy_table *bb_table; 1684 const struct rtw89_phy_table *bb_gain_table; 1685 1686 bb_table = elm_info->bb_tbl ? elm_info->bb_tbl : chip->bb_table; 1687 rtw89_phy_init_reg(rtwdev, bb_table, rtw89_phy_config_bb_reg, NULL); 1688 if (rtwdev->dbcc_en) 1689 rtw89_phy_init_reg(rtwdev, bb_table, rtw89_phy_config_bb_reg, 1690 (void *)RTW89_PHY_1); 1691 1692 rtw89_chip_init_txpwr_unit(rtwdev); 1693 1694 bb_gain_table = elm_info->bb_gain ? elm_info->bb_gain : chip->bb_gain_table; 1695 if (bb_gain_table) 1696 rtw89_phy_init_reg(rtwdev, bb_gain_table, 1697 chip->phy_def->config_bb_gain, NULL); 1698 1699 rtw89_phy_bb_reset(rtwdev); 1700 } 1701 1702 static u32 rtw89_phy_nctl_poll(struct rtw89_dev *rtwdev) 1703 { 1704 rtw89_phy_write32(rtwdev, 0x8080, 0x4); 1705 udelay(1); 1706 return rtw89_phy_read32(rtwdev, 0x8080); 1707 } 1708 1709 void rtw89_phy_init_rf_reg(struct rtw89_dev *rtwdev, bool noio) 1710 { 1711 void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg, 1712 enum rtw89_rf_path rf_path, void *data); 1713 struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info; 1714 const struct rtw89_chip_info *chip = rtwdev->chip; 1715 const struct rtw89_phy_table *rf_table; 1716 struct rtw89_fw_h2c_rf_reg_info *rf_reg_info; 1717 u8 path; 1718 1719 rf_reg_info = kzalloc(sizeof(*rf_reg_info), GFP_KERNEL); 1720 if (!rf_reg_info) 1721 return; 1722 1723 for (path = RF_PATH_A; path < chip->rf_path_num; path++) { 1724 rf_table = elm_info->rf_radio[path] ? 1725 elm_info->rf_radio[path] : chip->rf_table[path]; 1726 rf_reg_info->rf_path = rf_table->rf_path; 1727 if (noio) 1728 config = rtw89_phy_config_rf_reg_noio; 1729 else 1730 config = rf_table->config ? rf_table->config : 1731 rtw89_phy_config_rf_reg; 1732 rtw89_phy_init_reg(rtwdev, rf_table, config, (void *)rf_reg_info); 1733 if (rtw89_phy_config_rf_reg_fw(rtwdev, rf_reg_info)) 1734 rtw89_warn(rtwdev, "rf path %d reg h2c config failed\n", 1735 rf_reg_info->rf_path); 1736 } 1737 kfree(rf_reg_info); 1738 } 1739 1740 static void rtw89_phy_preinit_rf_nctl_ax(struct rtw89_dev *rtwdev) 1741 { 1742 const struct rtw89_chip_info *chip = rtwdev->chip; 1743 u32 val; 1744 int ret; 1745 1746 /* IQK/DPK clock & reset */ 1747 rtw89_phy_write32_set(rtwdev, R_IOQ_IQK_DPK, 0x3); 1748 rtw89_phy_write32_set(rtwdev, R_GNT_BT_WGT_EN, 0x1); 1749 rtw89_phy_write32_set(rtwdev, R_P0_PATH_RST, 0x8000000); 1750 if (chip->chip_id != RTL8851B) 1751 rtw89_phy_write32_set(rtwdev, R_P1_PATH_RST, 0x8000000); 1752 if (chip->chip_id == RTL8852B || chip->chip_id == RTL8852BT) 1753 rtw89_phy_write32_set(rtwdev, R_IOQ_IQK_DPK, 0x2); 1754 1755 /* check 0x8080 */ 1756 rtw89_phy_write32(rtwdev, R_NCTL_CFG, 0x8); 1757 1758 ret = read_poll_timeout(rtw89_phy_nctl_poll, val, val == 0x4, 10, 1759 1000, false, rtwdev); 1760 if (ret) 1761 rtw89_err(rtwdev, "failed to poll nctl block\n"); 1762 } 1763 1764 static void rtw89_phy_init_rf_nctl(struct rtw89_dev *rtwdev) 1765 { 1766 struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info; 1767 const struct rtw89_chip_info *chip = rtwdev->chip; 1768 const struct rtw89_phy_table *nctl_table; 1769 1770 rtw89_phy_preinit_rf_nctl(rtwdev); 1771 1772 nctl_table = elm_info->rf_nctl ? elm_info->rf_nctl : chip->nctl_table; 1773 rtw89_phy_init_reg(rtwdev, nctl_table, rtw89_phy_config_bb_reg, NULL); 1774 1775 if (chip->nctl_post_table) 1776 rtw89_rfk_parser(rtwdev, chip->nctl_post_table); 1777 } 1778 1779 static u32 rtw89_phy0_phy1_offset_ax(struct rtw89_dev *rtwdev, u32 addr) 1780 { 1781 u32 phy_page = addr >> 8; 1782 u32 ofst = 0; 1783 1784 switch (phy_page) { 1785 case 0x6: 1786 case 0x7: 1787 case 0x8: 1788 case 0x9: 1789 case 0xa: 1790 case 0xb: 1791 case 0xc: 1792 case 0xd: 1793 case 0x19: 1794 case 0x1a: 1795 case 0x1b: 1796 ofst = 0x2000; 1797 break; 1798 default: 1799 /* warning case */ 1800 ofst = 0; 1801 break; 1802 } 1803 1804 if (phy_page >= 0x40 && phy_page <= 0x4f) 1805 ofst = 0x2000; 1806 1807 return ofst; 1808 } 1809 1810 void rtw89_phy_write32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 1811 u32 data, enum rtw89_phy_idx phy_idx) 1812 { 1813 if (rtwdev->dbcc_en && phy_idx == RTW89_PHY_1) 1814 addr += rtw89_phy0_phy1_offset(rtwdev, addr); 1815 rtw89_phy_write32_mask(rtwdev, addr, mask, data); 1816 } 1817 EXPORT_SYMBOL(rtw89_phy_write32_idx); 1818 1819 void rtw89_phy_write32_idx_set(struct rtw89_dev *rtwdev, u32 addr, u32 bits, 1820 enum rtw89_phy_idx phy_idx) 1821 { 1822 if (rtwdev->dbcc_en && phy_idx == RTW89_PHY_1) 1823 addr += rtw89_phy0_phy1_offset(rtwdev, addr); 1824 rtw89_phy_write32_set(rtwdev, addr, bits); 1825 } 1826 EXPORT_SYMBOL(rtw89_phy_write32_idx_set); 1827 1828 void rtw89_phy_write32_idx_clr(struct rtw89_dev *rtwdev, u32 addr, u32 bits, 1829 enum rtw89_phy_idx phy_idx) 1830 { 1831 if (rtwdev->dbcc_en && phy_idx == RTW89_PHY_1) 1832 addr += rtw89_phy0_phy1_offset(rtwdev, addr); 1833 rtw89_phy_write32_clr(rtwdev, addr, bits); 1834 } 1835 EXPORT_SYMBOL(rtw89_phy_write32_idx_clr); 1836 1837 u32 rtw89_phy_read32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 1838 enum rtw89_phy_idx phy_idx) 1839 { 1840 if (rtwdev->dbcc_en && phy_idx == RTW89_PHY_1) 1841 addr += rtw89_phy0_phy1_offset(rtwdev, addr); 1842 return rtw89_phy_read32_mask(rtwdev, addr, mask); 1843 } 1844 EXPORT_SYMBOL(rtw89_phy_read32_idx); 1845 1846 void rtw89_phy_set_phy_regs(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 1847 u32 val) 1848 { 1849 rtw89_phy_write32_idx(rtwdev, addr, mask, val, RTW89_PHY_0); 1850 1851 if (!rtwdev->dbcc_en) 1852 return; 1853 1854 rtw89_phy_write32_idx(rtwdev, addr, mask, val, RTW89_PHY_1); 1855 } 1856 EXPORT_SYMBOL(rtw89_phy_set_phy_regs); 1857 1858 void rtw89_phy_write_reg3_tbl(struct rtw89_dev *rtwdev, 1859 const struct rtw89_phy_reg3_tbl *tbl) 1860 { 1861 const struct rtw89_reg3_def *reg3; 1862 int i; 1863 1864 for (i = 0; i < tbl->size; i++) { 1865 reg3 = &tbl->reg3[i]; 1866 rtw89_phy_write32_mask(rtwdev, reg3->addr, reg3->mask, reg3->data); 1867 } 1868 } 1869 EXPORT_SYMBOL(rtw89_phy_write_reg3_tbl); 1870 1871 static u8 rtw89_phy_ant_gain_domain_to_regd(struct rtw89_dev *rtwdev, u8 ant_gain_regd) 1872 { 1873 switch (ant_gain_regd) { 1874 case RTW89_ANT_GAIN_ETSI: 1875 return RTW89_ETSI; 1876 default: 1877 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 1878 "unknown antenna gain domain: %d\n", 1879 ant_gain_regd); 1880 return RTW89_REGD_NUM; 1881 } 1882 } 1883 1884 /* antenna gain in unit of 0.25 dbm */ 1885 #define RTW89_ANT_GAIN_2GHZ_MIN -8 1886 #define RTW89_ANT_GAIN_2GHZ_MAX 14 1887 #define RTW89_ANT_GAIN_5GHZ_MIN -8 1888 #define RTW89_ANT_GAIN_5GHZ_MAX 20 1889 #define RTW89_ANT_GAIN_6GHZ_MIN -8 1890 #define RTW89_ANT_GAIN_6GHZ_MAX 20 1891 1892 #define RTW89_ANT_GAIN_REF_2GHZ 14 1893 #define RTW89_ANT_GAIN_REF_5GHZ 20 1894 #define RTW89_ANT_GAIN_REF_6GHZ 20 1895 1896 void rtw89_phy_ant_gain_init(struct rtw89_dev *rtwdev) 1897 { 1898 struct rtw89_ant_gain_info *ant_gain = &rtwdev->ant_gain; 1899 const struct rtw89_chip_info *chip = rtwdev->chip; 1900 struct rtw89_acpi_rtag_result res = {}; 1901 u32 domain; 1902 int ret; 1903 u8 i, j; 1904 u8 regd; 1905 u8 val; 1906 1907 if (!chip->support_ant_gain) 1908 return; 1909 1910 ret = rtw89_acpi_evaluate_rtag(rtwdev, &res); 1911 if (ret) { 1912 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 1913 "acpi: cannot eval rtag: %d\n", ret); 1914 return; 1915 } 1916 1917 if (res.revision != 0) { 1918 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 1919 "unknown rtag revision: %d\n", res.revision); 1920 return; 1921 } 1922 1923 domain = get_unaligned_le32(&res.domain); 1924 1925 for (i = 0; i < RTW89_ANT_GAIN_DOMAIN_NUM; i++) { 1926 if (!(domain & BIT(i))) 1927 continue; 1928 1929 regd = rtw89_phy_ant_gain_domain_to_regd(rtwdev, i); 1930 if (regd >= RTW89_REGD_NUM) 1931 continue; 1932 ant_gain->regd_enabled |= BIT(regd); 1933 } 1934 1935 for (i = 0; i < RTW89_ANT_GAIN_CHAIN_NUM; i++) { 1936 for (j = 0; j < RTW89_ANT_GAIN_SUBBAND_NR; j++) { 1937 val = res.ant_gain_table[i][j]; 1938 switch (j) { 1939 default: 1940 case RTW89_ANT_GAIN_2GHZ_SUBBAND: 1941 val = RTW89_ANT_GAIN_REF_2GHZ - 1942 clamp_t(s8, val, 1943 RTW89_ANT_GAIN_2GHZ_MIN, 1944 RTW89_ANT_GAIN_2GHZ_MAX); 1945 break; 1946 case RTW89_ANT_GAIN_5GHZ_SUBBAND_1: 1947 case RTW89_ANT_GAIN_5GHZ_SUBBAND_2: 1948 case RTW89_ANT_GAIN_5GHZ_SUBBAND_2E: 1949 case RTW89_ANT_GAIN_5GHZ_SUBBAND_3_4: 1950 val = RTW89_ANT_GAIN_REF_5GHZ - 1951 clamp_t(s8, val, 1952 RTW89_ANT_GAIN_5GHZ_MIN, 1953 RTW89_ANT_GAIN_5GHZ_MAX); 1954 break; 1955 case RTW89_ANT_GAIN_6GHZ_SUBBAND_5_L: 1956 case RTW89_ANT_GAIN_6GHZ_SUBBAND_5_H: 1957 case RTW89_ANT_GAIN_6GHZ_SUBBAND_6: 1958 case RTW89_ANT_GAIN_6GHZ_SUBBAND_7_L: 1959 case RTW89_ANT_GAIN_6GHZ_SUBBAND_7_H: 1960 case RTW89_ANT_GAIN_6GHZ_SUBBAND_8: 1961 val = RTW89_ANT_GAIN_REF_6GHZ - 1962 clamp_t(s8, val, 1963 RTW89_ANT_GAIN_6GHZ_MIN, 1964 RTW89_ANT_GAIN_6GHZ_MAX); 1965 } 1966 ant_gain->offset[i][j] = val; 1967 } 1968 } 1969 } 1970 1971 static 1972 enum rtw89_ant_gain_subband rtw89_phy_ant_gain_get_subband(struct rtw89_dev *rtwdev, 1973 u32 center_freq) 1974 { 1975 switch (center_freq) { 1976 default: 1977 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 1978 "center freq: %u to antenna gain subband is unhandled\n", 1979 center_freq); 1980 fallthrough; 1981 case 2412 ... 2484: 1982 return RTW89_ANT_GAIN_2GHZ_SUBBAND; 1983 case 5180 ... 5240: 1984 return RTW89_ANT_GAIN_5GHZ_SUBBAND_1; 1985 case 5250 ... 5320: 1986 return RTW89_ANT_GAIN_5GHZ_SUBBAND_2; 1987 case 5500 ... 5720: 1988 return RTW89_ANT_GAIN_5GHZ_SUBBAND_2E; 1989 case 5745 ... 5885: 1990 return RTW89_ANT_GAIN_5GHZ_SUBBAND_3_4; 1991 case 5955 ... 6155: 1992 return RTW89_ANT_GAIN_6GHZ_SUBBAND_5_L; 1993 case 6175 ... 6415: 1994 return RTW89_ANT_GAIN_6GHZ_SUBBAND_5_H; 1995 case 6435 ... 6515: 1996 return RTW89_ANT_GAIN_6GHZ_SUBBAND_6; 1997 case 6535 ... 6695: 1998 return RTW89_ANT_GAIN_6GHZ_SUBBAND_7_L; 1999 case 6715 ... 6855: 2000 return RTW89_ANT_GAIN_6GHZ_SUBBAND_7_H; 2001 2002 /* freq 6875 (ch 185, 20MHz) spans RTW89_ANT_GAIN_6GHZ_SUBBAND_7_H 2003 * and RTW89_ANT_GAIN_6GHZ_SUBBAND_8, so directly describe it with 2004 * struct rtw89_6ghz_span. 2005 */ 2006 2007 case 6895 ... 7115: 2008 return RTW89_ANT_GAIN_6GHZ_SUBBAND_8; 2009 } 2010 } 2011 2012 static s8 rtw89_phy_ant_gain_query(struct rtw89_dev *rtwdev, 2013 enum rtw89_rf_path path, u32 center_freq) 2014 { 2015 struct rtw89_ant_gain_info *ant_gain = &rtwdev->ant_gain; 2016 enum rtw89_ant_gain_subband subband_l, subband_h; 2017 const struct rtw89_6ghz_span *span; 2018 2019 span = rtw89_get_6ghz_span(rtwdev, center_freq); 2020 2021 if (span && RTW89_ANT_GAIN_SPAN_VALID(span)) { 2022 subband_l = span->ant_gain_subband_low; 2023 subband_h = span->ant_gain_subband_high; 2024 } else { 2025 subband_l = rtw89_phy_ant_gain_get_subband(rtwdev, center_freq); 2026 subband_h = subband_l; 2027 } 2028 2029 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 2030 "center_freq %u: antenna gain subband {%u, %u}\n", 2031 center_freq, subband_l, subband_h); 2032 2033 return min(ant_gain->offset[path][subband_l], 2034 ant_gain->offset[path][subband_h]); 2035 } 2036 2037 static s8 rtw89_phy_ant_gain_offset(struct rtw89_dev *rtwdev, u32 center_freq) 2038 { 2039 s8 offset_patha, offset_pathb; 2040 2041 offset_patha = rtw89_phy_ant_gain_query(rtwdev, RF_PATH_A, center_freq); 2042 offset_pathb = rtw89_phy_ant_gain_query(rtwdev, RF_PATH_B, center_freq); 2043 2044 if (RTW89_CHK_FW_FEATURE(NO_POWER_DIFFERENCE, &rtwdev->fw)) 2045 return min(offset_patha, offset_pathb); 2046 2047 return max(offset_patha, offset_pathb); 2048 } 2049 2050 static bool rtw89_can_apply_ant_gain(struct rtw89_dev *rtwdev, u8 band) 2051 { 2052 const struct rtw89_rfe_parms *rfe_parms = rtwdev->rfe_parms; 2053 struct rtw89_ant_gain_info *ant_gain = &rtwdev->ant_gain; 2054 const struct rtw89_chip_info *chip = rtwdev->chip; 2055 u8 regd = rtw89_regd_get(rtwdev, band); 2056 2057 if (!chip->support_ant_gain) 2058 return false; 2059 2060 if (ant_gain->block_country || !(ant_gain->regd_enabled & BIT(regd))) 2061 return false; 2062 2063 if (!rfe_parms->has_da) 2064 return false; 2065 2066 return true; 2067 } 2068 2069 s16 rtw89_phy_ant_gain_pwr_offset(struct rtw89_dev *rtwdev, 2070 const struct rtw89_chan *chan) 2071 { 2072 s8 offset_patha, offset_pathb; 2073 2074 if (!rtw89_can_apply_ant_gain(rtwdev, chan->band_type)) 2075 return 0; 2076 2077 if (RTW89_CHK_FW_FEATURE(NO_POWER_DIFFERENCE, &rtwdev->fw)) 2078 return 0; 2079 2080 offset_patha = rtw89_phy_ant_gain_query(rtwdev, RF_PATH_A, chan->freq); 2081 offset_pathb = rtw89_phy_ant_gain_query(rtwdev, RF_PATH_B, chan->freq); 2082 2083 return rtw89_phy_txpwr_rf_to_bb(rtwdev, offset_patha - offset_pathb); 2084 } 2085 EXPORT_SYMBOL(rtw89_phy_ant_gain_pwr_offset); 2086 2087 int rtw89_print_ant_gain(struct rtw89_dev *rtwdev, char *buf, size_t bufsz, 2088 const struct rtw89_chan *chan) 2089 { 2090 char *p = buf, *end = buf + bufsz; 2091 s8 offset_patha, offset_pathb; 2092 2093 if (!rtw89_can_apply_ant_gain(rtwdev, chan->band_type)) { 2094 p += scnprintf(p, end - p, "no DAG is applied\n"); 2095 goto out; 2096 } 2097 2098 offset_patha = rtw89_phy_ant_gain_query(rtwdev, RF_PATH_A, chan->freq); 2099 offset_pathb = rtw89_phy_ant_gain_query(rtwdev, RF_PATH_B, chan->freq); 2100 2101 p += scnprintf(p, end - p, "ChainA offset: %d dBm\n", offset_patha); 2102 p += scnprintf(p, end - p, "ChainB offset: %d dBm\n", offset_pathb); 2103 2104 out: 2105 return p - buf; 2106 } 2107 2108 static const u8 rtw89_rs_idx_num_ax[] = { 2109 [RTW89_RS_CCK] = RTW89_RATE_CCK_NUM, 2110 [RTW89_RS_OFDM] = RTW89_RATE_OFDM_NUM, 2111 [RTW89_RS_MCS] = RTW89_RATE_MCS_NUM_AX, 2112 [RTW89_RS_HEDCM] = RTW89_RATE_HEDCM_NUM, 2113 [RTW89_RS_OFFSET] = RTW89_RATE_OFFSET_NUM_AX, 2114 }; 2115 2116 static const u8 rtw89_rs_nss_num_ax[] = { 2117 [RTW89_RS_CCK] = 1, 2118 [RTW89_RS_OFDM] = 1, 2119 [RTW89_RS_MCS] = RTW89_NSS_NUM, 2120 [RTW89_RS_HEDCM] = RTW89_NSS_HEDCM_NUM, 2121 [RTW89_RS_OFFSET] = 1, 2122 }; 2123 2124 s8 *rtw89_phy_raw_byr_seek(struct rtw89_dev *rtwdev, 2125 struct rtw89_txpwr_byrate *head, 2126 const struct rtw89_rate_desc *desc) 2127 { 2128 switch (desc->rs) { 2129 case RTW89_RS_CCK: 2130 return &head->cck[desc->idx]; 2131 case RTW89_RS_OFDM: 2132 return &head->ofdm[desc->idx]; 2133 case RTW89_RS_MCS: 2134 return &head->mcs[desc->ofdma][desc->nss][desc->idx]; 2135 case RTW89_RS_HEDCM: 2136 return &head->hedcm[desc->ofdma][desc->nss][desc->idx]; 2137 case RTW89_RS_OFFSET: 2138 return &head->offset[desc->idx]; 2139 default: 2140 rtw89_warn(rtwdev, "unrecognized byr rs: %d\n", desc->rs); 2141 return &head->trap; 2142 } 2143 } 2144 2145 void rtw89_phy_load_txpwr_byrate(struct rtw89_dev *rtwdev, 2146 const struct rtw89_txpwr_table *tbl) 2147 { 2148 const struct rtw89_txpwr_byrate_cfg *cfg = tbl->data; 2149 const struct rtw89_txpwr_byrate_cfg *end = cfg + tbl->size; 2150 struct rtw89_txpwr_byrate *byr_head; 2151 struct rtw89_rate_desc desc = {}; 2152 s8 *byr; 2153 u32 data; 2154 u8 i; 2155 2156 for (; cfg < end; cfg++) { 2157 byr_head = &rtwdev->byr[cfg->band][0]; 2158 desc.rs = cfg->rs; 2159 desc.nss = cfg->nss; 2160 data = cfg->data; 2161 2162 for (i = 0; i < cfg->len; i++, data >>= 8) { 2163 desc.idx = cfg->shf + i; 2164 byr = rtw89_phy_raw_byr_seek(rtwdev, byr_head, &desc); 2165 *byr = data & 0xff; 2166 } 2167 } 2168 } 2169 EXPORT_SYMBOL(rtw89_phy_load_txpwr_byrate); 2170 2171 static s8 rtw89_phy_txpwr_dbm_without_tolerance(s8 dbm) 2172 { 2173 const u8 tssi_deviation_point = 0; 2174 const u8 tssi_max_deviation = 2; 2175 2176 if (dbm <= tssi_deviation_point) 2177 dbm -= tssi_max_deviation; 2178 2179 return dbm; 2180 } 2181 2182 static s8 rtw89_phy_get_tpe_constraint(struct rtw89_dev *rtwdev, u8 band) 2183 { 2184 struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory; 2185 const struct rtw89_reg_6ghz_tpe *tpe = ®ulatory->reg_6ghz_tpe; 2186 s8 cstr = S8_MAX; 2187 2188 if (band == RTW89_BAND_6G && tpe->valid) 2189 cstr = rtw89_phy_txpwr_dbm_without_tolerance(tpe->constraint); 2190 2191 return rtw89_phy_txpwr_dbm_to_mac(rtwdev, cstr); 2192 } 2193 2194 s8 rtw89_phy_read_txpwr_byrate(struct rtw89_dev *rtwdev, u8 band, u8 bw, 2195 const struct rtw89_rate_desc *rate_desc) 2196 { 2197 struct rtw89_txpwr_byrate *byr_head; 2198 s8 *byr; 2199 2200 if (rate_desc->rs == RTW89_RS_CCK) 2201 band = RTW89_BAND_2G; 2202 2203 byr_head = &rtwdev->byr[band][bw]; 2204 byr = rtw89_phy_raw_byr_seek(rtwdev, byr_head, rate_desc); 2205 2206 return rtw89_phy_txpwr_rf_to_mac(rtwdev, *byr); 2207 } 2208 2209 static u8 rtw89_channel_6g_to_idx(struct rtw89_dev *rtwdev, u8 channel_6g) 2210 { 2211 switch (channel_6g) { 2212 case 1 ... 29: 2213 return (channel_6g - 1) / 2; 2214 case 33 ... 61: 2215 return (channel_6g - 3) / 2; 2216 case 65 ... 93: 2217 return (channel_6g - 5) / 2; 2218 case 97 ... 125: 2219 return (channel_6g - 7) / 2; 2220 case 129 ... 157: 2221 return (channel_6g - 9) / 2; 2222 case 161 ... 189: 2223 return (channel_6g - 11) / 2; 2224 case 193 ... 221: 2225 return (channel_6g - 13) / 2; 2226 case 225 ... 253: 2227 return (channel_6g - 15) / 2; 2228 default: 2229 rtw89_warn(rtwdev, "unknown 6g channel: %d\n", channel_6g); 2230 return 0; 2231 } 2232 } 2233 2234 static u8 rtw89_channel_to_idx(struct rtw89_dev *rtwdev, u8 band, u8 channel) 2235 { 2236 if (band == RTW89_BAND_6G) 2237 return rtw89_channel_6g_to_idx(rtwdev, channel); 2238 2239 switch (channel) { 2240 case 1 ... 14: 2241 return channel - 1; 2242 case 36 ... 64: 2243 return (channel - 36) / 2; 2244 case 100 ... 144: 2245 return ((channel - 100) / 2) + 15; 2246 case 149 ... 177: 2247 return ((channel - 149) / 2) + 38; 2248 default: 2249 rtw89_warn(rtwdev, "unknown channel: %d\n", channel); 2250 return 0; 2251 } 2252 } 2253 2254 s8 rtw89_phy_read_txpwr_limit(struct rtw89_dev *rtwdev, u8 band, 2255 u8 bw, u8 ntx, u8 rs, u8 bf, u8 ch) 2256 { 2257 const struct rtw89_rfe_parms *rfe_parms = rtwdev->rfe_parms; 2258 const struct rtw89_txpwr_rule_2ghz *rule_da_2ghz = &rfe_parms->rule_da_2ghz; 2259 const struct rtw89_txpwr_rule_5ghz *rule_da_5ghz = &rfe_parms->rule_da_5ghz; 2260 const struct rtw89_txpwr_rule_6ghz *rule_da_6ghz = &rfe_parms->rule_da_6ghz; 2261 const struct rtw89_txpwr_rule_2ghz *rule_2ghz = &rfe_parms->rule_2ghz; 2262 const struct rtw89_txpwr_rule_5ghz *rule_5ghz = &rfe_parms->rule_5ghz; 2263 const struct rtw89_txpwr_rule_6ghz *rule_6ghz = &rfe_parms->rule_6ghz; 2264 struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory; 2265 enum nl80211_band nl_band = rtw89_hw_to_nl80211_band(band); 2266 bool has_ant_gain = rtw89_can_apply_ant_gain(rtwdev, band); 2267 u32 freq = ieee80211_channel_to_frequency(ch, nl_band); 2268 u8 ch_idx = rtw89_channel_to_idx(rtwdev, band, ch); 2269 s8 lmt = 0, da_lmt = S8_MAX, sar, offset = 0; 2270 u8 regd = rtw89_regd_get(rtwdev, band); 2271 u8 reg6 = regulatory->reg_6ghz_power; 2272 struct rtw89_sar_parm sar_parm = { 2273 .center_freq = freq, 2274 .ntx = ntx, 2275 }; 2276 s8 cstr; 2277 2278 switch (band) { 2279 case RTW89_BAND_2G: 2280 if (has_ant_gain) 2281 da_lmt = (*rule_da_2ghz->lmt)[bw][ntx][rs][bf][regd][ch_idx]; 2282 2283 lmt = (*rule_2ghz->lmt)[bw][ntx][rs][bf][regd][ch_idx]; 2284 if (lmt) 2285 break; 2286 2287 lmt = (*rule_2ghz->lmt)[bw][ntx][rs][bf][RTW89_WW][ch_idx]; 2288 break; 2289 case RTW89_BAND_5G: 2290 if (has_ant_gain) 2291 da_lmt = (*rule_da_5ghz->lmt)[bw][ntx][rs][bf][regd][ch_idx]; 2292 2293 lmt = (*rule_5ghz->lmt)[bw][ntx][rs][bf][regd][ch_idx]; 2294 if (lmt) 2295 break; 2296 2297 lmt = (*rule_5ghz->lmt)[bw][ntx][rs][bf][RTW89_WW][ch_idx]; 2298 break; 2299 case RTW89_BAND_6G: 2300 if (has_ant_gain) 2301 da_lmt = (*rule_da_6ghz->lmt)[bw][ntx][rs][bf][regd][reg6][ch_idx]; 2302 2303 lmt = (*rule_6ghz->lmt)[bw][ntx][rs][bf][regd][reg6][ch_idx]; 2304 if (lmt) 2305 break; 2306 2307 lmt = (*rule_6ghz->lmt)[bw][ntx][rs][bf][RTW89_WW] 2308 [RTW89_REG_6GHZ_POWER_DFLT] 2309 [ch_idx]; 2310 break; 2311 default: 2312 rtw89_warn(rtwdev, "unknown band type: %d\n", band); 2313 return 0; 2314 } 2315 2316 da_lmt = da_lmt ?: S8_MAX; 2317 if (da_lmt != S8_MAX) 2318 offset = rtw89_phy_ant_gain_offset(rtwdev, freq); 2319 2320 lmt = rtw89_phy_txpwr_rf_to_mac(rtwdev, min(lmt + offset, da_lmt)); 2321 sar = rtw89_query_sar(rtwdev, &sar_parm); 2322 cstr = rtw89_phy_get_tpe_constraint(rtwdev, band); 2323 2324 return min3(lmt, sar, cstr); 2325 } 2326 EXPORT_SYMBOL(rtw89_phy_read_txpwr_limit); 2327 2328 #define __fill_txpwr_limit_nonbf_bf(ptr, band, bw, ntx, rs, ch) \ 2329 do { \ 2330 u8 __i; \ 2331 for (__i = 0; __i < RTW89_BF_NUM; __i++) \ 2332 ptr[__i] = rtw89_phy_read_txpwr_limit(rtwdev, \ 2333 band, \ 2334 bw, ntx, \ 2335 rs, __i, \ 2336 (ch)); \ 2337 } while (0) 2338 2339 static void rtw89_phy_fill_txpwr_limit_20m_ax(struct rtw89_dev *rtwdev, 2340 struct rtw89_txpwr_limit_ax *lmt, 2341 u8 band, u8 ntx, u8 ch) 2342 { 2343 __fill_txpwr_limit_nonbf_bf(lmt->cck_20m, band, RTW89_CHANNEL_WIDTH_20, 2344 ntx, RTW89_RS_CCK, ch); 2345 __fill_txpwr_limit_nonbf_bf(lmt->cck_40m, band, RTW89_CHANNEL_WIDTH_40, 2346 ntx, RTW89_RS_CCK, ch); 2347 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20, 2348 ntx, RTW89_RS_OFDM, ch); 2349 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band, 2350 RTW89_CHANNEL_WIDTH_20, 2351 ntx, RTW89_RS_MCS, ch); 2352 } 2353 2354 static void rtw89_phy_fill_txpwr_limit_40m_ax(struct rtw89_dev *rtwdev, 2355 struct rtw89_txpwr_limit_ax *lmt, 2356 u8 band, u8 ntx, u8 ch, u8 pri_ch) 2357 { 2358 __fill_txpwr_limit_nonbf_bf(lmt->cck_20m, band, RTW89_CHANNEL_WIDTH_20, 2359 ntx, RTW89_RS_CCK, ch - 2); 2360 __fill_txpwr_limit_nonbf_bf(lmt->cck_40m, band, RTW89_CHANNEL_WIDTH_40, 2361 ntx, RTW89_RS_CCK, ch); 2362 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20, 2363 ntx, RTW89_RS_OFDM, pri_ch); 2364 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band, 2365 RTW89_CHANNEL_WIDTH_20, 2366 ntx, RTW89_RS_MCS, ch - 2); 2367 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], band, 2368 RTW89_CHANNEL_WIDTH_20, 2369 ntx, RTW89_RS_MCS, ch + 2); 2370 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], band, 2371 RTW89_CHANNEL_WIDTH_40, 2372 ntx, RTW89_RS_MCS, ch); 2373 } 2374 2375 static void rtw89_phy_fill_txpwr_limit_80m_ax(struct rtw89_dev *rtwdev, 2376 struct rtw89_txpwr_limit_ax *lmt, 2377 u8 band, u8 ntx, u8 ch, u8 pri_ch) 2378 { 2379 s8 val_0p5_n[RTW89_BF_NUM]; 2380 s8 val_0p5_p[RTW89_BF_NUM]; 2381 u8 i; 2382 2383 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20, 2384 ntx, RTW89_RS_OFDM, pri_ch); 2385 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band, 2386 RTW89_CHANNEL_WIDTH_20, 2387 ntx, RTW89_RS_MCS, ch - 6); 2388 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], band, 2389 RTW89_CHANNEL_WIDTH_20, 2390 ntx, RTW89_RS_MCS, ch - 2); 2391 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[2], band, 2392 RTW89_CHANNEL_WIDTH_20, 2393 ntx, RTW89_RS_MCS, ch + 2); 2394 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[3], band, 2395 RTW89_CHANNEL_WIDTH_20, 2396 ntx, RTW89_RS_MCS, ch + 6); 2397 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], band, 2398 RTW89_CHANNEL_WIDTH_40, 2399 ntx, RTW89_RS_MCS, ch - 4); 2400 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[1], band, 2401 RTW89_CHANNEL_WIDTH_40, 2402 ntx, RTW89_RS_MCS, ch + 4); 2403 __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[0], band, 2404 RTW89_CHANNEL_WIDTH_80, 2405 ntx, RTW89_RS_MCS, ch); 2406 2407 __fill_txpwr_limit_nonbf_bf(val_0p5_n, band, RTW89_CHANNEL_WIDTH_40, 2408 ntx, RTW89_RS_MCS, ch - 4); 2409 __fill_txpwr_limit_nonbf_bf(val_0p5_p, band, RTW89_CHANNEL_WIDTH_40, 2410 ntx, RTW89_RS_MCS, ch + 4); 2411 2412 for (i = 0; i < RTW89_BF_NUM; i++) 2413 lmt->mcs_40m_0p5[i] = min_t(s8, val_0p5_n[i], val_0p5_p[i]); 2414 } 2415 2416 static void rtw89_phy_fill_txpwr_limit_160m_ax(struct rtw89_dev *rtwdev, 2417 struct rtw89_txpwr_limit_ax *lmt, 2418 u8 band, u8 ntx, u8 ch, u8 pri_ch) 2419 { 2420 s8 val_0p5_n[RTW89_BF_NUM]; 2421 s8 val_0p5_p[RTW89_BF_NUM]; 2422 s8 val_2p5_n[RTW89_BF_NUM]; 2423 s8 val_2p5_p[RTW89_BF_NUM]; 2424 u8 i; 2425 2426 /* fill ofdm section */ 2427 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20, 2428 ntx, RTW89_RS_OFDM, pri_ch); 2429 2430 /* fill mcs 20m section */ 2431 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band, 2432 RTW89_CHANNEL_WIDTH_20, 2433 ntx, RTW89_RS_MCS, ch - 14); 2434 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], band, 2435 RTW89_CHANNEL_WIDTH_20, 2436 ntx, RTW89_RS_MCS, ch - 10); 2437 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[2], band, 2438 RTW89_CHANNEL_WIDTH_20, 2439 ntx, RTW89_RS_MCS, ch - 6); 2440 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[3], band, 2441 RTW89_CHANNEL_WIDTH_20, 2442 ntx, RTW89_RS_MCS, ch - 2); 2443 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[4], band, 2444 RTW89_CHANNEL_WIDTH_20, 2445 ntx, RTW89_RS_MCS, ch + 2); 2446 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[5], band, 2447 RTW89_CHANNEL_WIDTH_20, 2448 ntx, RTW89_RS_MCS, ch + 6); 2449 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[6], band, 2450 RTW89_CHANNEL_WIDTH_20, 2451 ntx, RTW89_RS_MCS, ch + 10); 2452 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[7], band, 2453 RTW89_CHANNEL_WIDTH_20, 2454 ntx, RTW89_RS_MCS, ch + 14); 2455 2456 /* fill mcs 40m section */ 2457 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], band, 2458 RTW89_CHANNEL_WIDTH_40, 2459 ntx, RTW89_RS_MCS, ch - 12); 2460 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[1], band, 2461 RTW89_CHANNEL_WIDTH_40, 2462 ntx, RTW89_RS_MCS, ch - 4); 2463 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[2], band, 2464 RTW89_CHANNEL_WIDTH_40, 2465 ntx, RTW89_RS_MCS, ch + 4); 2466 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[3], band, 2467 RTW89_CHANNEL_WIDTH_40, 2468 ntx, RTW89_RS_MCS, ch + 12); 2469 2470 /* fill mcs 80m section */ 2471 __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[0], band, 2472 RTW89_CHANNEL_WIDTH_80, 2473 ntx, RTW89_RS_MCS, ch - 8); 2474 __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[1], band, 2475 RTW89_CHANNEL_WIDTH_80, 2476 ntx, RTW89_RS_MCS, ch + 8); 2477 2478 /* fill mcs 160m section */ 2479 __fill_txpwr_limit_nonbf_bf(lmt->mcs_160m, band, 2480 RTW89_CHANNEL_WIDTH_160, 2481 ntx, RTW89_RS_MCS, ch); 2482 2483 /* fill mcs 40m 0p5 section */ 2484 __fill_txpwr_limit_nonbf_bf(val_0p5_n, band, RTW89_CHANNEL_WIDTH_40, 2485 ntx, RTW89_RS_MCS, ch - 4); 2486 __fill_txpwr_limit_nonbf_bf(val_0p5_p, band, RTW89_CHANNEL_WIDTH_40, 2487 ntx, RTW89_RS_MCS, ch + 4); 2488 2489 for (i = 0; i < RTW89_BF_NUM; i++) 2490 lmt->mcs_40m_0p5[i] = min_t(s8, val_0p5_n[i], val_0p5_p[i]); 2491 2492 /* fill mcs 40m 2p5 section */ 2493 __fill_txpwr_limit_nonbf_bf(val_2p5_n, band, RTW89_CHANNEL_WIDTH_40, 2494 ntx, RTW89_RS_MCS, ch - 8); 2495 __fill_txpwr_limit_nonbf_bf(val_2p5_p, band, RTW89_CHANNEL_WIDTH_40, 2496 ntx, RTW89_RS_MCS, ch + 8); 2497 2498 for (i = 0; i < RTW89_BF_NUM; i++) 2499 lmt->mcs_40m_2p5[i] = min_t(s8, val_2p5_n[i], val_2p5_p[i]); 2500 } 2501 2502 static 2503 void rtw89_phy_fill_txpwr_limit_ax(struct rtw89_dev *rtwdev, 2504 const struct rtw89_chan *chan, 2505 struct rtw89_txpwr_limit_ax *lmt, 2506 u8 ntx) 2507 { 2508 u8 band = chan->band_type; 2509 u8 pri_ch = chan->primary_channel; 2510 u8 ch = chan->channel; 2511 u8 bw = chan->band_width; 2512 2513 memset(lmt, 0, sizeof(*lmt)); 2514 2515 switch (bw) { 2516 case RTW89_CHANNEL_WIDTH_20: 2517 rtw89_phy_fill_txpwr_limit_20m_ax(rtwdev, lmt, band, ntx, ch); 2518 break; 2519 case RTW89_CHANNEL_WIDTH_40: 2520 rtw89_phy_fill_txpwr_limit_40m_ax(rtwdev, lmt, band, ntx, ch, 2521 pri_ch); 2522 break; 2523 case RTW89_CHANNEL_WIDTH_80: 2524 rtw89_phy_fill_txpwr_limit_80m_ax(rtwdev, lmt, band, ntx, ch, 2525 pri_ch); 2526 break; 2527 case RTW89_CHANNEL_WIDTH_160: 2528 rtw89_phy_fill_txpwr_limit_160m_ax(rtwdev, lmt, band, ntx, ch, 2529 pri_ch); 2530 break; 2531 } 2532 } 2533 2534 s8 rtw89_phy_read_txpwr_limit_ru(struct rtw89_dev *rtwdev, u8 band, 2535 u8 ru, u8 ntx, u8 ch) 2536 { 2537 const struct rtw89_rfe_parms *rfe_parms = rtwdev->rfe_parms; 2538 const struct rtw89_txpwr_rule_2ghz *rule_da_2ghz = &rfe_parms->rule_da_2ghz; 2539 const struct rtw89_txpwr_rule_5ghz *rule_da_5ghz = &rfe_parms->rule_da_5ghz; 2540 const struct rtw89_txpwr_rule_6ghz *rule_da_6ghz = &rfe_parms->rule_da_6ghz; 2541 const struct rtw89_txpwr_rule_2ghz *rule_2ghz = &rfe_parms->rule_2ghz; 2542 const struct rtw89_txpwr_rule_5ghz *rule_5ghz = &rfe_parms->rule_5ghz; 2543 const struct rtw89_txpwr_rule_6ghz *rule_6ghz = &rfe_parms->rule_6ghz; 2544 struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory; 2545 enum nl80211_band nl_band = rtw89_hw_to_nl80211_band(band); 2546 bool has_ant_gain = rtw89_can_apply_ant_gain(rtwdev, band); 2547 u32 freq = ieee80211_channel_to_frequency(ch, nl_band); 2548 u8 ch_idx = rtw89_channel_to_idx(rtwdev, band, ch); 2549 s8 lmt_ru = 0, da_lmt_ru = S8_MAX, sar, offset = 0; 2550 u8 regd = rtw89_regd_get(rtwdev, band); 2551 u8 reg6 = regulatory->reg_6ghz_power; 2552 struct rtw89_sar_parm sar_parm = { 2553 .center_freq = freq, 2554 .ntx = ntx, 2555 }; 2556 s8 cstr; 2557 2558 switch (band) { 2559 case RTW89_BAND_2G: 2560 if (has_ant_gain) 2561 da_lmt_ru = (*rule_da_2ghz->lmt_ru)[ru][ntx][regd][ch_idx]; 2562 2563 lmt_ru = (*rule_2ghz->lmt_ru)[ru][ntx][regd][ch_idx]; 2564 if (lmt_ru) 2565 break; 2566 2567 lmt_ru = (*rule_2ghz->lmt_ru)[ru][ntx][RTW89_WW][ch_idx]; 2568 break; 2569 case RTW89_BAND_5G: 2570 if (has_ant_gain) 2571 da_lmt_ru = (*rule_da_5ghz->lmt_ru)[ru][ntx][regd][ch_idx]; 2572 2573 lmt_ru = (*rule_5ghz->lmt_ru)[ru][ntx][regd][ch_idx]; 2574 if (lmt_ru) 2575 break; 2576 2577 lmt_ru = (*rule_5ghz->lmt_ru)[ru][ntx][RTW89_WW][ch_idx]; 2578 break; 2579 case RTW89_BAND_6G: 2580 if (has_ant_gain) 2581 da_lmt_ru = (*rule_da_6ghz->lmt_ru)[ru][ntx][regd][reg6][ch_idx]; 2582 2583 lmt_ru = (*rule_6ghz->lmt_ru)[ru][ntx][regd][reg6][ch_idx]; 2584 if (lmt_ru) 2585 break; 2586 2587 lmt_ru = (*rule_6ghz->lmt_ru)[ru][ntx][RTW89_WW] 2588 [RTW89_REG_6GHZ_POWER_DFLT] 2589 [ch_idx]; 2590 break; 2591 default: 2592 rtw89_warn(rtwdev, "unknown band type: %d\n", band); 2593 return 0; 2594 } 2595 2596 da_lmt_ru = da_lmt_ru ?: S8_MAX; 2597 if (da_lmt_ru != S8_MAX) 2598 offset = rtw89_phy_ant_gain_offset(rtwdev, freq); 2599 2600 lmt_ru = rtw89_phy_txpwr_rf_to_mac(rtwdev, min(lmt_ru + offset, da_lmt_ru)); 2601 sar = rtw89_query_sar(rtwdev, &sar_parm); 2602 cstr = rtw89_phy_get_tpe_constraint(rtwdev, band); 2603 2604 return min3(lmt_ru, sar, cstr); 2605 } 2606 2607 static void 2608 rtw89_phy_fill_txpwr_limit_ru_20m_ax(struct rtw89_dev *rtwdev, 2609 struct rtw89_txpwr_limit_ru_ax *lmt_ru, 2610 u8 band, u8 ntx, u8 ch) 2611 { 2612 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2613 RTW89_RU26, 2614 ntx, ch); 2615 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2616 RTW89_RU52, 2617 ntx, ch); 2618 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2619 RTW89_RU106, 2620 ntx, ch); 2621 } 2622 2623 static void 2624 rtw89_phy_fill_txpwr_limit_ru_40m_ax(struct rtw89_dev *rtwdev, 2625 struct rtw89_txpwr_limit_ru_ax *lmt_ru, 2626 u8 band, u8 ntx, u8 ch) 2627 { 2628 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2629 RTW89_RU26, 2630 ntx, ch - 2); 2631 lmt_ru->ru26[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2632 RTW89_RU26, 2633 ntx, ch + 2); 2634 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2635 RTW89_RU52, 2636 ntx, ch - 2); 2637 lmt_ru->ru52[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2638 RTW89_RU52, 2639 ntx, ch + 2); 2640 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2641 RTW89_RU106, 2642 ntx, ch - 2); 2643 lmt_ru->ru106[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2644 RTW89_RU106, 2645 ntx, ch + 2); 2646 } 2647 2648 static void 2649 rtw89_phy_fill_txpwr_limit_ru_80m_ax(struct rtw89_dev *rtwdev, 2650 struct rtw89_txpwr_limit_ru_ax *lmt_ru, 2651 u8 band, u8 ntx, u8 ch) 2652 { 2653 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2654 RTW89_RU26, 2655 ntx, ch - 6); 2656 lmt_ru->ru26[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2657 RTW89_RU26, 2658 ntx, ch - 2); 2659 lmt_ru->ru26[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2660 RTW89_RU26, 2661 ntx, ch + 2); 2662 lmt_ru->ru26[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2663 RTW89_RU26, 2664 ntx, ch + 6); 2665 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2666 RTW89_RU52, 2667 ntx, ch - 6); 2668 lmt_ru->ru52[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2669 RTW89_RU52, 2670 ntx, ch - 2); 2671 lmt_ru->ru52[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2672 RTW89_RU52, 2673 ntx, ch + 2); 2674 lmt_ru->ru52[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2675 RTW89_RU52, 2676 ntx, ch + 6); 2677 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2678 RTW89_RU106, 2679 ntx, ch - 6); 2680 lmt_ru->ru106[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2681 RTW89_RU106, 2682 ntx, ch - 2); 2683 lmt_ru->ru106[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2684 RTW89_RU106, 2685 ntx, ch + 2); 2686 lmt_ru->ru106[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2687 RTW89_RU106, 2688 ntx, ch + 6); 2689 } 2690 2691 static void 2692 rtw89_phy_fill_txpwr_limit_ru_160m_ax(struct rtw89_dev *rtwdev, 2693 struct rtw89_txpwr_limit_ru_ax *lmt_ru, 2694 u8 band, u8 ntx, u8 ch) 2695 { 2696 static const int ofst[] = { -14, -10, -6, -2, 2, 6, 10, 14 }; 2697 int i; 2698 2699 static_assert(ARRAY_SIZE(ofst) == RTW89_RU_SEC_NUM_AX); 2700 for (i = 0; i < RTW89_RU_SEC_NUM_AX; i++) { 2701 lmt_ru->ru26[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2702 RTW89_RU26, 2703 ntx, 2704 ch + ofst[i]); 2705 lmt_ru->ru52[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2706 RTW89_RU52, 2707 ntx, 2708 ch + ofst[i]); 2709 lmt_ru->ru106[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2710 RTW89_RU106, 2711 ntx, 2712 ch + ofst[i]); 2713 } 2714 } 2715 2716 static 2717 void rtw89_phy_fill_txpwr_limit_ru_ax(struct rtw89_dev *rtwdev, 2718 const struct rtw89_chan *chan, 2719 struct rtw89_txpwr_limit_ru_ax *lmt_ru, 2720 u8 ntx) 2721 { 2722 u8 band = chan->band_type; 2723 u8 ch = chan->channel; 2724 u8 bw = chan->band_width; 2725 2726 memset(lmt_ru, 0, sizeof(*lmt_ru)); 2727 2728 switch (bw) { 2729 case RTW89_CHANNEL_WIDTH_20: 2730 rtw89_phy_fill_txpwr_limit_ru_20m_ax(rtwdev, lmt_ru, band, ntx, 2731 ch); 2732 break; 2733 case RTW89_CHANNEL_WIDTH_40: 2734 rtw89_phy_fill_txpwr_limit_ru_40m_ax(rtwdev, lmt_ru, band, ntx, 2735 ch); 2736 break; 2737 case RTW89_CHANNEL_WIDTH_80: 2738 rtw89_phy_fill_txpwr_limit_ru_80m_ax(rtwdev, lmt_ru, band, ntx, 2739 ch); 2740 break; 2741 case RTW89_CHANNEL_WIDTH_160: 2742 rtw89_phy_fill_txpwr_limit_ru_160m_ax(rtwdev, lmt_ru, band, ntx, 2743 ch); 2744 break; 2745 } 2746 } 2747 2748 static void rtw89_phy_set_txpwr_byrate_ax(struct rtw89_dev *rtwdev, 2749 const struct rtw89_chan *chan, 2750 enum rtw89_phy_idx phy_idx) 2751 { 2752 u8 max_nss_num = rtwdev->chip->rf_path_num; 2753 static const u8 rs[] = { 2754 RTW89_RS_CCK, 2755 RTW89_RS_OFDM, 2756 RTW89_RS_MCS, 2757 RTW89_RS_HEDCM, 2758 }; 2759 struct rtw89_rate_desc cur = {}; 2760 u8 band = chan->band_type; 2761 u8 ch = chan->channel; 2762 u32 addr, val; 2763 s8 v[4] = {}; 2764 u8 i; 2765 2766 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 2767 "[TXPWR] set txpwr byrate with ch=%d\n", ch); 2768 2769 BUILD_BUG_ON(rtw89_rs_idx_num_ax[RTW89_RS_CCK] % 4); 2770 BUILD_BUG_ON(rtw89_rs_idx_num_ax[RTW89_RS_OFDM] % 4); 2771 BUILD_BUG_ON(rtw89_rs_idx_num_ax[RTW89_RS_MCS] % 4); 2772 BUILD_BUG_ON(rtw89_rs_idx_num_ax[RTW89_RS_HEDCM] % 4); 2773 2774 addr = R_AX_PWR_BY_RATE; 2775 for (cur.nss = 0; cur.nss < max_nss_num; cur.nss++) { 2776 for (i = 0; i < ARRAY_SIZE(rs); i++) { 2777 if (cur.nss >= rtw89_rs_nss_num_ax[rs[i]]) 2778 continue; 2779 2780 cur.rs = rs[i]; 2781 for (cur.idx = 0; cur.idx < rtw89_rs_idx_num_ax[rs[i]]; 2782 cur.idx++) { 2783 v[cur.idx % 4] = 2784 rtw89_phy_read_txpwr_byrate(rtwdev, 2785 band, 0, 2786 &cur); 2787 2788 if ((cur.idx + 1) % 4) 2789 continue; 2790 2791 val = FIELD_PREP(GENMASK(7, 0), v[0]) | 2792 FIELD_PREP(GENMASK(15, 8), v[1]) | 2793 FIELD_PREP(GENMASK(23, 16), v[2]) | 2794 FIELD_PREP(GENMASK(31, 24), v[3]); 2795 2796 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 2797 val); 2798 addr += 4; 2799 } 2800 } 2801 } 2802 } 2803 2804 static 2805 void rtw89_phy_set_txpwr_offset_ax(struct rtw89_dev *rtwdev, 2806 const struct rtw89_chan *chan, 2807 enum rtw89_phy_idx phy_idx) 2808 { 2809 struct rtw89_rate_desc desc = { 2810 .nss = RTW89_NSS_1, 2811 .rs = RTW89_RS_OFFSET, 2812 }; 2813 u8 band = chan->band_type; 2814 s8 v[RTW89_RATE_OFFSET_NUM_AX] = {}; 2815 u32 val; 2816 2817 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr offset\n"); 2818 2819 for (desc.idx = 0; desc.idx < RTW89_RATE_OFFSET_NUM_AX; desc.idx++) 2820 v[desc.idx] = rtw89_phy_read_txpwr_byrate(rtwdev, band, 0, &desc); 2821 2822 BUILD_BUG_ON(RTW89_RATE_OFFSET_NUM_AX != 5); 2823 val = FIELD_PREP(GENMASK(3, 0), v[0]) | 2824 FIELD_PREP(GENMASK(7, 4), v[1]) | 2825 FIELD_PREP(GENMASK(11, 8), v[2]) | 2826 FIELD_PREP(GENMASK(15, 12), v[3]) | 2827 FIELD_PREP(GENMASK(19, 16), v[4]); 2828 2829 rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_OFST_CTRL, 2830 GENMASK(19, 0), val); 2831 } 2832 2833 static void rtw89_phy_set_txpwr_limit_ax(struct rtw89_dev *rtwdev, 2834 const struct rtw89_chan *chan, 2835 enum rtw89_phy_idx phy_idx) 2836 { 2837 u8 max_ntx_num = rtwdev->chip->rf_path_num; 2838 struct rtw89_txpwr_limit_ax lmt; 2839 u8 ch = chan->channel; 2840 u8 bw = chan->band_width; 2841 const s8 *ptr; 2842 u32 addr, val; 2843 u8 i, j; 2844 2845 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 2846 "[TXPWR] set txpwr limit with ch=%d bw=%d\n", ch, bw); 2847 2848 BUILD_BUG_ON(sizeof(struct rtw89_txpwr_limit_ax) != 2849 RTW89_TXPWR_LMT_PAGE_SIZE_AX); 2850 2851 addr = R_AX_PWR_LMT; 2852 for (i = 0; i < max_ntx_num; i++) { 2853 rtw89_phy_fill_txpwr_limit_ax(rtwdev, chan, &lmt, i); 2854 2855 ptr = (s8 *)&lmt; 2856 for (j = 0; j < RTW89_TXPWR_LMT_PAGE_SIZE_AX; 2857 j += 4, addr += 4, ptr += 4) { 2858 val = FIELD_PREP(GENMASK(7, 0), ptr[0]) | 2859 FIELD_PREP(GENMASK(15, 8), ptr[1]) | 2860 FIELD_PREP(GENMASK(23, 16), ptr[2]) | 2861 FIELD_PREP(GENMASK(31, 24), ptr[3]); 2862 2863 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val); 2864 } 2865 } 2866 } 2867 2868 static void rtw89_phy_set_txpwr_limit_ru_ax(struct rtw89_dev *rtwdev, 2869 const struct rtw89_chan *chan, 2870 enum rtw89_phy_idx phy_idx) 2871 { 2872 u8 max_ntx_num = rtwdev->chip->rf_path_num; 2873 struct rtw89_txpwr_limit_ru_ax lmt_ru; 2874 u8 ch = chan->channel; 2875 u8 bw = chan->band_width; 2876 const s8 *ptr; 2877 u32 addr, val; 2878 u8 i, j; 2879 2880 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 2881 "[TXPWR] set txpwr limit ru with ch=%d bw=%d\n", ch, bw); 2882 2883 BUILD_BUG_ON(sizeof(struct rtw89_txpwr_limit_ru_ax) != 2884 RTW89_TXPWR_LMT_RU_PAGE_SIZE_AX); 2885 2886 addr = R_AX_PWR_RU_LMT; 2887 for (i = 0; i < max_ntx_num; i++) { 2888 rtw89_phy_fill_txpwr_limit_ru_ax(rtwdev, chan, &lmt_ru, i); 2889 2890 ptr = (s8 *)&lmt_ru; 2891 for (j = 0; j < RTW89_TXPWR_LMT_RU_PAGE_SIZE_AX; 2892 j += 4, addr += 4, ptr += 4) { 2893 val = FIELD_PREP(GENMASK(7, 0), ptr[0]) | 2894 FIELD_PREP(GENMASK(15, 8), ptr[1]) | 2895 FIELD_PREP(GENMASK(23, 16), ptr[2]) | 2896 FIELD_PREP(GENMASK(31, 24), ptr[3]); 2897 2898 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val); 2899 } 2900 } 2901 } 2902 2903 struct rtw89_phy_iter_ra_data { 2904 struct rtw89_dev *rtwdev; 2905 struct sk_buff *c2h; 2906 }; 2907 2908 static void __rtw89_phy_c2h_ra_rpt_iter(struct rtw89_sta_link *rtwsta_link, 2909 struct ieee80211_link_sta *link_sta, 2910 struct rtw89_phy_iter_ra_data *ra_data) 2911 { 2912 struct rtw89_dev *rtwdev = ra_data->rtwdev; 2913 const struct rtw89_c2h_ra_rpt *c2h = 2914 (const struct rtw89_c2h_ra_rpt *)ra_data->c2h->data; 2915 struct rtw89_ra_report *ra_report = &rtwsta_link->ra_report; 2916 const struct rtw89_chip_info *chip = rtwdev->chip; 2917 bool format_v1 = chip->chip_gen == RTW89_CHIP_BE; 2918 u8 mode, rate, bw, giltf, mac_id; 2919 u16 legacy_bitrate; 2920 bool valid; 2921 u8 mcs = 0; 2922 u8 t; 2923 2924 mac_id = le32_get_bits(c2h->w2, RTW89_C2H_RA_RPT_W2_MACID); 2925 if (mac_id != rtwsta_link->mac_id) 2926 return; 2927 2928 rate = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_MCSNSS); 2929 bw = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_BW); 2930 giltf = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_GILTF); 2931 mode = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_MD_SEL); 2932 2933 if (format_v1) { 2934 t = le32_get_bits(c2h->w2, RTW89_C2H_RA_RPT_W2_MCSNSS_B7); 2935 rate |= u8_encode_bits(t, BIT(7)); 2936 t = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_BW_B2); 2937 bw |= u8_encode_bits(t, BIT(2)); 2938 t = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_MD_SEL_B2); 2939 mode |= u8_encode_bits(t, BIT(2)); 2940 } 2941 2942 if (mode == RTW89_RA_RPT_MODE_LEGACY) { 2943 valid = rtw89_ra_report_to_bitrate(rtwdev, rate, &legacy_bitrate); 2944 if (!valid) 2945 return; 2946 } 2947 2948 memset(&ra_report->txrate, 0, sizeof(ra_report->txrate)); 2949 2950 switch (mode) { 2951 case RTW89_RA_RPT_MODE_LEGACY: 2952 ra_report->txrate.legacy = legacy_bitrate; 2953 break; 2954 case RTW89_RA_RPT_MODE_HT: 2955 ra_report->txrate.flags |= RATE_INFO_FLAGS_MCS; 2956 if (RTW89_CHK_FW_FEATURE(OLD_HT_RA_FORMAT, &rtwdev->fw)) 2957 rate = RTW89_MK_HT_RATE(FIELD_GET(RTW89_RA_RATE_MASK_NSS, rate), 2958 FIELD_GET(RTW89_RA_RATE_MASK_MCS, rate)); 2959 else 2960 rate = FIELD_GET(RTW89_RA_RATE_MASK_HT_MCS, rate); 2961 ra_report->txrate.mcs = rate; 2962 if (giltf) 2963 ra_report->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; 2964 mcs = ra_report->txrate.mcs & 0x07; 2965 break; 2966 case RTW89_RA_RPT_MODE_VHT: 2967 ra_report->txrate.flags |= RATE_INFO_FLAGS_VHT_MCS; 2968 ra_report->txrate.mcs = format_v1 ? 2969 u8_get_bits(rate, RTW89_RA_RATE_MASK_MCS_V1) : 2970 u8_get_bits(rate, RTW89_RA_RATE_MASK_MCS); 2971 ra_report->txrate.nss = format_v1 ? 2972 u8_get_bits(rate, RTW89_RA_RATE_MASK_NSS_V1) + 1 : 2973 u8_get_bits(rate, RTW89_RA_RATE_MASK_NSS) + 1; 2974 if (giltf) 2975 ra_report->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; 2976 mcs = ra_report->txrate.mcs; 2977 break; 2978 case RTW89_RA_RPT_MODE_HE: 2979 ra_report->txrate.flags |= RATE_INFO_FLAGS_HE_MCS; 2980 ra_report->txrate.mcs = format_v1 ? 2981 u8_get_bits(rate, RTW89_RA_RATE_MASK_MCS_V1) : 2982 u8_get_bits(rate, RTW89_RA_RATE_MASK_MCS); 2983 ra_report->txrate.nss = format_v1 ? 2984 u8_get_bits(rate, RTW89_RA_RATE_MASK_NSS_V1) + 1 : 2985 u8_get_bits(rate, RTW89_RA_RATE_MASK_NSS) + 1; 2986 if (giltf == RTW89_GILTF_2XHE08 || giltf == RTW89_GILTF_1XHE08) 2987 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_0_8; 2988 else if (giltf == RTW89_GILTF_2XHE16 || giltf == RTW89_GILTF_1XHE16) 2989 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_1_6; 2990 else 2991 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_3_2; 2992 mcs = ra_report->txrate.mcs; 2993 break; 2994 case RTW89_RA_RPT_MODE_EHT: 2995 ra_report->txrate.flags |= RATE_INFO_FLAGS_EHT_MCS; 2996 ra_report->txrate.mcs = u8_get_bits(rate, RTW89_RA_RATE_MASK_MCS_V1); 2997 ra_report->txrate.nss = u8_get_bits(rate, RTW89_RA_RATE_MASK_NSS_V1) + 1; 2998 if (giltf == RTW89_GILTF_2XHE08 || giltf == RTW89_GILTF_1XHE08) 2999 ra_report->txrate.eht_gi = NL80211_RATE_INFO_EHT_GI_0_8; 3000 else if (giltf == RTW89_GILTF_2XHE16 || giltf == RTW89_GILTF_1XHE16) 3001 ra_report->txrate.eht_gi = NL80211_RATE_INFO_EHT_GI_1_6; 3002 else 3003 ra_report->txrate.eht_gi = NL80211_RATE_INFO_EHT_GI_3_2; 3004 mcs = ra_report->txrate.mcs; 3005 break; 3006 } 3007 3008 ra_report->txrate.bw = rtw89_hw_to_rate_info_bw(bw); 3009 ra_report->bit_rate = cfg80211_calculate_bitrate(&ra_report->txrate); 3010 ra_report->hw_rate = format_v1 ? 3011 u16_encode_bits(mode, RTW89_HW_RATE_V1_MASK_MOD) | 3012 u16_encode_bits(rate, RTW89_HW_RATE_V1_MASK_VAL) : 3013 u16_encode_bits(mode, RTW89_HW_RATE_MASK_MOD) | 3014 u16_encode_bits(rate, RTW89_HW_RATE_MASK_VAL); 3015 ra_report->might_fallback_legacy = mcs <= 2; 3016 link_sta->agg.max_rc_amsdu_len = get_max_amsdu_len(rtwdev, ra_report); 3017 rtwsta_link->max_agg_wait = link_sta->agg.max_rc_amsdu_len / 1500 - 1; 3018 } 3019 3020 static void rtw89_phy_c2h_ra_rpt_iter(void *data, struct ieee80211_sta *sta) 3021 { 3022 struct rtw89_phy_iter_ra_data *ra_data = (struct rtw89_phy_iter_ra_data *)data; 3023 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta); 3024 struct rtw89_sta_link *rtwsta_link; 3025 struct ieee80211_link_sta *link_sta; 3026 unsigned int link_id; 3027 3028 rcu_read_lock(); 3029 3030 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) { 3031 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, false); 3032 __rtw89_phy_c2h_ra_rpt_iter(rtwsta_link, link_sta, ra_data); 3033 } 3034 3035 rcu_read_unlock(); 3036 } 3037 3038 static void 3039 rtw89_phy_c2h_ra_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 3040 { 3041 struct rtw89_phy_iter_ra_data ra_data; 3042 3043 ra_data.rtwdev = rtwdev; 3044 ra_data.c2h = c2h; 3045 ieee80211_iterate_stations_atomic(rtwdev->hw, 3046 rtw89_phy_c2h_ra_rpt_iter, 3047 &ra_data); 3048 } 3049 3050 static 3051 void (* const rtw89_phy_c2h_ra_handler[])(struct rtw89_dev *rtwdev, 3052 struct sk_buff *c2h, u32 len) = { 3053 [RTW89_PHY_C2H_FUNC_STS_RPT] = rtw89_phy_c2h_ra_rpt, 3054 [RTW89_PHY_C2H_FUNC_MU_GPTBL_RPT] = NULL, 3055 [RTW89_PHY_C2H_FUNC_TXSTS] = NULL, 3056 }; 3057 3058 static void 3059 rtw89_phy_c2h_lowrt_rty(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 3060 { 3061 } 3062 3063 static void 3064 rtw89_phy_c2h_fw_scan_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 3065 { 3066 const struct rtw89_c2h_fw_scan_rpt *c2h_rpt = 3067 (const struct rtw89_c2h_fw_scan_rpt *)c2h->data; 3068 3069 rtw89_debug(rtwdev, RTW89_DBG_DIG, 3070 "%s: band: %u, op_chan: %u, PD_low_bd(ofdm, cck): (-%d, %d), phy_idx: %u\n", 3071 __func__, c2h_rpt->band, c2h_rpt->center_ch, 3072 PD_LOWER_BOUND_BASE - (c2h_rpt->ofdm_pd_idx << 1), 3073 c2h_rpt->cck_pd_idx, c2h_rpt->phy_idx); 3074 } 3075 3076 static 3077 void (* const rtw89_phy_c2h_dm_handler[])(struct rtw89_dev *rtwdev, 3078 struct sk_buff *c2h, u32 len) = { 3079 [RTW89_PHY_C2H_DM_FUNC_FW_TEST] = NULL, 3080 [RTW89_PHY_C2H_DM_FUNC_FW_TRIG_TX_RPT] = NULL, 3081 [RTW89_PHY_C2H_DM_FUNC_SIGB] = NULL, 3082 [RTW89_PHY_C2H_DM_FUNC_LOWRT_RTY] = rtw89_phy_c2h_lowrt_rty, 3083 [RTW89_PHY_C2H_DM_FUNC_MCC_DIG] = NULL, 3084 [RTW89_PHY_C2H_DM_FUNC_FW_SCAN] = rtw89_phy_c2h_fw_scan_rpt, 3085 }; 3086 3087 static void rtw89_phy_c2h_rfk_rpt_log(struct rtw89_dev *rtwdev, 3088 enum rtw89_phy_c2h_rfk_log_func func, 3089 void *content, u16 len) 3090 { 3091 struct rtw89_c2h_rf_txgapk_rpt_log *txgapk; 3092 struct rtw89_c2h_rf_rxdck_rpt_log *rxdck; 3093 struct rtw89_c2h_rf_dack_rpt_log *dack; 3094 struct rtw89_c2h_rf_tssi_rpt_log *tssi; 3095 struct rtw89_c2h_rf_dpk_rpt_log *dpk; 3096 struct rtw89_c2h_rf_iqk_rpt_log *iqk; 3097 int i, j, k; 3098 3099 switch (func) { 3100 case RTW89_PHY_C2H_RFK_LOG_FUNC_IQK: 3101 if (len != sizeof(*iqk)) 3102 goto out; 3103 3104 iqk = content; 3105 rtw89_debug(rtwdev, RTW89_DBG_RFK, 3106 "[IQK] iqk->is_iqk_init = %x\n", iqk->is_iqk_init); 3107 rtw89_debug(rtwdev, RTW89_DBG_RFK, 3108 "[IQK] iqk->is_reload = %x\n", iqk->is_reload); 3109 rtw89_debug(rtwdev, RTW89_DBG_RFK, 3110 "[IQK] iqk->is_nbiqk = %x\n", iqk->is_nbiqk); 3111 rtw89_debug(rtwdev, RTW89_DBG_RFK, 3112 "[IQK] iqk->txiqk_en = %x\n", iqk->txiqk_en); 3113 rtw89_debug(rtwdev, RTW89_DBG_RFK, 3114 "[IQK] iqk->rxiqk_en = %x\n", iqk->rxiqk_en); 3115 rtw89_debug(rtwdev, RTW89_DBG_RFK, 3116 "[IQK] iqk->lok_en = %x\n", iqk->lok_en); 3117 rtw89_debug(rtwdev, RTW89_DBG_RFK, 3118 "[IQK] iqk->iqk_xym_en = %x\n", iqk->iqk_xym_en); 3119 rtw89_debug(rtwdev, RTW89_DBG_RFK, 3120 "[IQK] iqk->iqk_sram_en = %x\n", iqk->iqk_sram_en); 3121 rtw89_debug(rtwdev, RTW89_DBG_RFK, 3122 "[IQK] iqk->iqk_fft_en = %x\n", iqk->iqk_fft_en); 3123 rtw89_debug(rtwdev, RTW89_DBG_RFK, 3124 "[IQK] iqk->is_fw_iqk = %x\n", iqk->is_fw_iqk); 3125 rtw89_debug(rtwdev, RTW89_DBG_RFK, 3126 "[IQK] iqk->is_iqk_enable = %x\n", iqk->is_iqk_enable); 3127 rtw89_debug(rtwdev, RTW89_DBG_RFK, 3128 "[IQK] iqk->iqk_cfir_en = %x\n", iqk->iqk_cfir_en); 3129 rtw89_debug(rtwdev, RTW89_DBG_RFK, 3130 "[IQK] iqk->thermal_rek_en = %x\n", iqk->thermal_rek_en); 3131 rtw89_debug(rtwdev, RTW89_DBG_RFK, 3132 "[IQK] iqk->version = %x\n", iqk->version); 3133 rtw89_debug(rtwdev, RTW89_DBG_RFK, 3134 "[IQK] iqk->phy = %x\n", iqk->phy); 3135 rtw89_debug(rtwdev, RTW89_DBG_RFK, 3136 "[IQK] iqk->fwk_status = %x\n", iqk->fwk_status); 3137 3138 for (i = 0; i < 2; i++) { 3139 rtw89_debug(rtwdev, RTW89_DBG_RFK, 3140 "[IQK] ======== Path %x ========\n", i); 3141 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] iqk->iqk_band[%d] = %x\n", 3142 i, iqk->iqk_band[i]); 3143 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] iqk->iqk_ch[%d] = %x\n", 3144 i, iqk->iqk_ch[i]); 3145 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] iqk->iqk_bw[%d] = %x\n", 3146 i, iqk->iqk_bw[i]); 3147 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] iqk->lok_idac[%d] = %x\n", 3148 i, le32_to_cpu(iqk->lok_idac[i])); 3149 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] iqk->lok_vbuf[%d] = %x\n", 3150 i, le32_to_cpu(iqk->lok_vbuf[i])); 3151 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] iqk->iqk_tx_fail[%d] = %x\n", 3152 i, iqk->iqk_tx_fail[i]); 3153 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] iqk->iqk_rx_fail[%d] = %x\n", 3154 i, iqk->iqk_rx_fail[i]); 3155 for (j = 0; j < 4; j++) 3156 rtw89_debug(rtwdev, RTW89_DBG_RFK, 3157 "[IQK] iqk->rftxgain[%d][%d] = %x\n", 3158 i, j, le32_to_cpu(iqk->rftxgain[i][j])); 3159 for (j = 0; j < 4; j++) 3160 rtw89_debug(rtwdev, RTW89_DBG_RFK, 3161 "[IQK] iqk->tx_xym[%d][%d] = %x\n", 3162 i, j, le32_to_cpu(iqk->tx_xym[i][j])); 3163 for (j = 0; j < 4; j++) 3164 rtw89_debug(rtwdev, RTW89_DBG_RFK, 3165 "[IQK] iqk->rfrxgain[%d][%d] = %x\n", 3166 i, j, le32_to_cpu(iqk->rfrxgain[i][j])); 3167 for (j = 0; j < 4; j++) 3168 rtw89_debug(rtwdev, RTW89_DBG_RFK, 3169 "[IQK] iqk->rx_xym[%d][%d] = %x\n", 3170 i, j, le32_to_cpu(iqk->rx_xym[i][j])); 3171 } 3172 return; 3173 case RTW89_PHY_C2H_RFK_LOG_FUNC_DPK: 3174 if (len != sizeof(*dpk)) 3175 goto out; 3176 3177 dpk = content; 3178 rtw89_debug(rtwdev, RTW89_DBG_RFK, 3179 "DPK ver:%d idx:%2ph band:%2ph bw:%2ph ch:%2ph path:%2ph\n", 3180 dpk->ver, dpk->idx, dpk->band, dpk->bw, dpk->ch, dpk->path_ok); 3181 rtw89_debug(rtwdev, RTW89_DBG_RFK, 3182 "DPK txagc:%2ph ther:%2ph gs:%2ph dc_i:%4ph dc_q:%4ph\n", 3183 dpk->txagc, dpk->ther, dpk->gs, dpk->dc_i, dpk->dc_q); 3184 rtw89_debug(rtwdev, RTW89_DBG_RFK, 3185 "DPK corr_v:%2ph corr_i:%2ph to:%2ph ov:%2ph\n", 3186 dpk->corr_val, dpk->corr_idx, dpk->is_timeout, dpk->rxbb_ov); 3187 return; 3188 case RTW89_PHY_C2H_RFK_LOG_FUNC_DACK: 3189 if (len != sizeof(*dack)) 3190 goto out; 3191 3192 dack = content; 3193 3194 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]FWDACK SUMMARY!!!!!\n"); 3195 rtw89_debug(rtwdev, RTW89_DBG_RFK, 3196 "[DACK]FWDACK ver = 0x%x, FWDACK rpt_ver = 0x%x, driver rpt_ver = 0x%x\n", 3197 dack->fwdack_ver, dack->fwdack_info_ver, 0x2); 3198 3199 rtw89_debug(rtwdev, RTW89_DBG_RFK, 3200 "[DACK]timeout code = [0x%x 0x%x 0x%x 0x%x 0x%x]\n", 3201 dack->addck_timeout, dack->cdack_timeout, dack->dadck_timeout, 3202 dack->adgaink_timeout, dack->msbk_timeout); 3203 rtw89_debug(rtwdev, RTW89_DBG_RFK, 3204 "[DACK]DACK fail = 0x%x\n", dack->dack_fail); 3205 rtw89_debug(rtwdev, RTW89_DBG_RFK, 3206 "[DACK]S0 WBADCK = [0x%x]\n", dack->wbdck_d[0]); 3207 rtw89_debug(rtwdev, RTW89_DBG_RFK, 3208 "[DACK]S1 WBADCK = [0x%x]\n", dack->wbdck_d[1]); 3209 rtw89_debug(rtwdev, RTW89_DBG_RFK, 3210 "[DACK]DRCK = [0x%x]\n", dack->rck_d); 3211 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 CDACK ic = [0x%x, 0x%x]\n", 3212 dack->cdack_d[0][0][0], dack->cdack_d[0][0][1]); 3213 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 CDACK qc = [0x%x, 0x%x]\n", 3214 dack->cdack_d[0][1][0], dack->cdack_d[0][1][1]); 3215 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 CDACK ic = [0x%x, 0x%x]\n", 3216 dack->cdack_d[1][0][0], dack->cdack_d[1][0][1]); 3217 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 CDACK qc = [0x%x, 0x%x]\n", 3218 dack->cdack_d[1][1][0], dack->cdack_d[1][1][1]); 3219 3220 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 ADC_DCK ic = [0x%x, 0x%x]\n", 3221 ((u32)dack->addck2_hd[0][0][0] << 8) | dack->addck2_ld[0][0][0], 3222 ((u32)dack->addck2_hd[0][0][1] << 8) | dack->addck2_ld[0][0][1]); 3223 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 ADC_DCK qc = [0x%x, 0x%x]\n", 3224 ((u32)dack->addck2_hd[0][1][0] << 8) | dack->addck2_ld[0][1][0], 3225 ((u32)dack->addck2_hd[0][1][1] << 8) | dack->addck2_ld[0][1][1]); 3226 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 ADC_DCK ic = [0x%x, 0x%x]\n", 3227 ((u32)dack->addck2_hd[1][0][0] << 8) | dack->addck2_ld[1][0][0], 3228 ((u32)dack->addck2_hd[1][0][1] << 8) | dack->addck2_ld[1][0][1]); 3229 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 ADC_DCK qc = [0x%x, 0x%x]\n", 3230 ((u32)dack->addck2_hd[1][1][0] << 8) | dack->addck2_ld[1][1][0], 3231 ((u32)dack->addck2_hd[1][1][1] << 8) | dack->addck2_ld[1][1][1]); 3232 3233 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 ADC_GAINK ic = 0x%x, qc = 0x%x\n", 3234 dack->adgaink_d[0][0], dack->adgaink_d[0][1]); 3235 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 ADC_GAINK ic = 0x%x, qc = 0x%x\n", 3236 dack->adgaink_d[1][0], dack->adgaink_d[1][1]); 3237 3238 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 DAC_DCK ic = 0x%x, qc = 0x%x\n", 3239 dack->dadck_d[0][0], dack->dadck_d[0][1]); 3240 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 DAC_DCK ic = 0x%x, qc = 0x%x\n", 3241 dack->dadck_d[1][0], dack->dadck_d[1][1]); 3242 3243 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 biask iqc = 0x%x\n", 3244 ((u32)dack->biask_hd[0][0] << 8) | dack->biask_ld[0][0]); 3245 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 biask iqc = 0x%x\n", 3246 ((u32)dack->biask_hd[1][0] << 8) | dack->biask_ld[1][0]); 3247 3248 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 MSBK ic:\n"); 3249 for (i = 0; i < 0x10; i++) 3250 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x\n", 3251 dack->msbk_d[0][0][i]); 3252 3253 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 MSBK qc:\n"); 3254 for (i = 0; i < 0x10; i++) 3255 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x\n", 3256 dack->msbk_d[0][1][i]); 3257 3258 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 MSBK ic:\n"); 3259 for (i = 0; i < 0x10; i++) 3260 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x\n", 3261 dack->msbk_d[1][0][i]); 3262 3263 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 MSBK qc:\n"); 3264 for (i = 0; i < 0x10; i++) 3265 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x\n", 3266 dack->msbk_d[1][1][i]); 3267 return; 3268 case RTW89_PHY_C2H_RFK_LOG_FUNC_RXDCK: 3269 if (len != sizeof(*rxdck)) 3270 goto out; 3271 3272 rxdck = content; 3273 rtw89_debug(rtwdev, RTW89_DBG_RFK, 3274 "RXDCK ver:%d band:%2ph bw:%2ph ch:%2ph to:%2ph\n", 3275 rxdck->ver, rxdck->band, rxdck->bw, rxdck->ch, 3276 rxdck->timeout); 3277 return; 3278 case RTW89_PHY_C2H_RFK_LOG_FUNC_TSSI: 3279 if (len != sizeof(*tssi)) 3280 goto out; 3281 3282 tssi = content; 3283 for (i = 0; i < 2; i++) { 3284 for (j = 0; j < 2; j++) { 3285 for (k = 0; k < 4; k++) { 3286 rtw89_debug(rtwdev, RTW89_DBG_RFK, 3287 "[TSSI] alignment_power_cw_h[%d][%d][%d]=%d\n", 3288 i, j, k, tssi->alignment_power_cw_h[i][j][k]); 3289 rtw89_debug(rtwdev, RTW89_DBG_RFK, 3290 "[TSSI] alignment_power_cw_l[%d][%d][%d]=%d\n", 3291 i, j, k, tssi->alignment_power_cw_l[i][j][k]); 3292 rtw89_debug(rtwdev, RTW89_DBG_RFK, 3293 "[TSSI] alignment_power[%d][%d][%d]=%d\n", 3294 i, j, k, tssi->alignment_power[i][j][k]); 3295 rtw89_debug(rtwdev, RTW89_DBG_RFK, 3296 "[TSSI] alignment_power_cw[%d][%d][%d]=%d\n", 3297 i, j, k, 3298 (tssi->alignment_power_cw_h[i][j][k] << 8) + 3299 tssi->alignment_power_cw_l[i][j][k]); 3300 } 3301 3302 rtw89_debug(rtwdev, RTW89_DBG_RFK, 3303 "[TSSI] tssi_alimk_state[%d][%d]=%d\n", 3304 i, j, tssi->tssi_alimk_state[i][j]); 3305 rtw89_debug(rtwdev, RTW89_DBG_RFK, 3306 "[TSSI] default_txagc_offset[%d]=%d\n", 3307 j, tssi->default_txagc_offset[0][j]); 3308 } 3309 } 3310 return; 3311 case RTW89_PHY_C2H_RFK_LOG_FUNC_TXGAPK: 3312 if (len != sizeof(*txgapk)) 3313 goto out; 3314 3315 txgapk = content; 3316 rtw89_debug(rtwdev, RTW89_DBG_RFK, 3317 "[TXGAPK]rpt r0x8010[0]=0x%x, r0x8010[1]=0x%x\n", 3318 le32_to_cpu(txgapk->r0x8010[0]), 3319 le32_to_cpu(txgapk->r0x8010[1])); 3320 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt chk_id = %d\n", 3321 txgapk->chk_id); 3322 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt chk_cnt = %d\n", 3323 le32_to_cpu(txgapk->chk_cnt)); 3324 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt ver = 0x%x\n", 3325 txgapk->ver); 3326 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt rsv1 = %d\n", 3327 txgapk->rsv1); 3328 3329 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt track_d[0] = %*ph\n", 3330 (int)sizeof(txgapk->track_d[0]), txgapk->track_d[0]); 3331 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt power_d[0] = %*ph\n", 3332 (int)sizeof(txgapk->power_d[0]), txgapk->power_d[0]); 3333 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt track_d[1] = %*ph\n", 3334 (int)sizeof(txgapk->track_d[1]), txgapk->track_d[1]); 3335 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt power_d[1] = %*ph\n", 3336 (int)sizeof(txgapk->power_d[1]), txgapk->power_d[1]); 3337 return; 3338 default: 3339 break; 3340 } 3341 3342 out: 3343 rtw89_debug(rtwdev, RTW89_DBG_RFK, 3344 "unexpected RFK func %d report log with length %d\n", func, len); 3345 } 3346 3347 static bool rtw89_phy_c2h_rfk_run_log(struct rtw89_dev *rtwdev, 3348 enum rtw89_phy_c2h_rfk_log_func func, 3349 void *content, u16 len) 3350 { 3351 struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info; 3352 const struct rtw89_c2h_rf_run_log *log = content; 3353 const struct rtw89_fw_element_hdr *elm; 3354 u32 fmt_idx; 3355 u16 offset; 3356 3357 if (sizeof(*log) != len) 3358 return false; 3359 3360 if (!elm_info->rfk_log_fmt) 3361 return false; 3362 3363 elm = elm_info->rfk_log_fmt->elm[func]; 3364 fmt_idx = le32_to_cpu(log->fmt_idx); 3365 if (!elm || fmt_idx >= elm->u.rfk_log_fmt.nr) 3366 return false; 3367 3368 offset = le16_to_cpu(elm->u.rfk_log_fmt.offset[fmt_idx]); 3369 if (offset == 0) 3370 return false; 3371 3372 rtw89_debug(rtwdev, RTW89_DBG_RFK, &elm->u.common.contents[offset], 3373 le32_to_cpu(log->arg[0]), le32_to_cpu(log->arg[1]), 3374 le32_to_cpu(log->arg[2]), le32_to_cpu(log->arg[3])); 3375 3376 return true; 3377 } 3378 3379 static void rtw89_phy_c2h_rfk_log(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 3380 u32 len, enum rtw89_phy_c2h_rfk_log_func func, 3381 const char *rfk_name) 3382 { 3383 struct rtw89_c2h_hdr *c2h_hdr = (struct rtw89_c2h_hdr *)c2h->data; 3384 struct rtw89_c2h_rf_log_hdr *log_hdr; 3385 void *log_ptr = c2h_hdr; 3386 u16 content_len; 3387 u16 chunk_len; 3388 bool handled; 3389 3390 if (!rtw89_debug_is_enabled(rtwdev, RTW89_DBG_RFK)) 3391 return; 3392 3393 log_ptr += sizeof(*c2h_hdr); 3394 len -= sizeof(*c2h_hdr); 3395 3396 while (len > sizeof(*log_hdr)) { 3397 log_hdr = log_ptr; 3398 content_len = le16_to_cpu(log_hdr->len); 3399 chunk_len = content_len + sizeof(*log_hdr); 3400 3401 if (chunk_len > len) 3402 break; 3403 3404 switch (log_hdr->type) { 3405 case RTW89_RF_RUN_LOG: 3406 handled = rtw89_phy_c2h_rfk_run_log(rtwdev, func, 3407 log_hdr->content, content_len); 3408 if (handled) 3409 break; 3410 3411 rtw89_debug(rtwdev, RTW89_DBG_RFK, "%s run: %*ph\n", 3412 rfk_name, content_len, log_hdr->content); 3413 break; 3414 case RTW89_RF_RPT_LOG: 3415 rtw89_phy_c2h_rfk_rpt_log(rtwdev, func, 3416 log_hdr->content, content_len); 3417 break; 3418 default: 3419 return; 3420 } 3421 3422 log_ptr += chunk_len; 3423 len -= chunk_len; 3424 } 3425 } 3426 3427 static void 3428 rtw89_phy_c2h_rfk_log_iqk(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 3429 { 3430 rtw89_phy_c2h_rfk_log(rtwdev, c2h, len, 3431 RTW89_PHY_C2H_RFK_LOG_FUNC_IQK, "IQK"); 3432 } 3433 3434 static void 3435 rtw89_phy_c2h_rfk_log_dpk(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 3436 { 3437 rtw89_phy_c2h_rfk_log(rtwdev, c2h, len, 3438 RTW89_PHY_C2H_RFK_LOG_FUNC_DPK, "DPK"); 3439 } 3440 3441 static void 3442 rtw89_phy_c2h_rfk_log_dack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 3443 { 3444 rtw89_phy_c2h_rfk_log(rtwdev, c2h, len, 3445 RTW89_PHY_C2H_RFK_LOG_FUNC_DACK, "DACK"); 3446 } 3447 3448 static void 3449 rtw89_phy_c2h_rfk_log_rxdck(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 3450 { 3451 rtw89_phy_c2h_rfk_log(rtwdev, c2h, len, 3452 RTW89_PHY_C2H_RFK_LOG_FUNC_RXDCK, "RX_DCK"); 3453 } 3454 3455 static void 3456 rtw89_phy_c2h_rfk_log_tssi(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 3457 { 3458 rtw89_phy_c2h_rfk_log(rtwdev, c2h, len, 3459 RTW89_PHY_C2H_RFK_LOG_FUNC_TSSI, "TSSI"); 3460 } 3461 3462 static void 3463 rtw89_phy_c2h_rfk_log_txgapk(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 3464 { 3465 rtw89_phy_c2h_rfk_log(rtwdev, c2h, len, 3466 RTW89_PHY_C2H_RFK_LOG_FUNC_TXGAPK, "TXGAPK"); 3467 } 3468 3469 static 3470 void (* const rtw89_phy_c2h_rfk_log_handler[])(struct rtw89_dev *rtwdev, 3471 struct sk_buff *c2h, u32 len) = { 3472 [RTW89_PHY_C2H_RFK_LOG_FUNC_IQK] = rtw89_phy_c2h_rfk_log_iqk, 3473 [RTW89_PHY_C2H_RFK_LOG_FUNC_DPK] = rtw89_phy_c2h_rfk_log_dpk, 3474 [RTW89_PHY_C2H_RFK_LOG_FUNC_DACK] = rtw89_phy_c2h_rfk_log_dack, 3475 [RTW89_PHY_C2H_RFK_LOG_FUNC_RXDCK] = rtw89_phy_c2h_rfk_log_rxdck, 3476 [RTW89_PHY_C2H_RFK_LOG_FUNC_TSSI] = rtw89_phy_c2h_rfk_log_tssi, 3477 [RTW89_PHY_C2H_RFK_LOG_FUNC_TXGAPK] = rtw89_phy_c2h_rfk_log_txgapk, 3478 }; 3479 3480 static 3481 void rtw89_phy_rfk_report_prep(struct rtw89_dev *rtwdev) 3482 { 3483 struct rtw89_rfk_wait_info *wait = &rtwdev->rfk_wait; 3484 3485 wait->state = RTW89_RFK_STATE_START; 3486 wait->start_time = ktime_get(); 3487 reinit_completion(&wait->completion); 3488 } 3489 3490 static 3491 int rtw89_phy_rfk_report_wait(struct rtw89_dev *rtwdev, const char *rfk_name, 3492 unsigned int ms) 3493 { 3494 struct rtw89_rfk_wait_info *wait = &rtwdev->rfk_wait; 3495 unsigned long time_left; 3496 3497 /* Since we can't receive C2H event during SER, use a fixed delay. */ 3498 if (test_bit(RTW89_FLAG_SER_HANDLING, rtwdev->flags)) { 3499 fsleep(1000 * ms / 2); 3500 goto out; 3501 } 3502 3503 time_left = wait_for_completion_timeout(&wait->completion, 3504 msecs_to_jiffies(ms)); 3505 if (time_left == 0) { 3506 rtw89_warn(rtwdev, "failed to wait RF %s\n", rfk_name); 3507 return -ETIMEDOUT; 3508 } else if (wait->state != RTW89_RFK_STATE_OK) { 3509 rtw89_warn(rtwdev, "failed to do RF %s result from state %d\n", 3510 rfk_name, wait->state); 3511 return -EFAULT; 3512 } 3513 3514 out: 3515 rtw89_debug(rtwdev, RTW89_DBG_RFK, "RF %s takes %lld ms to complete\n", 3516 rfk_name, ktime_ms_delta(ktime_get(), wait->start_time)); 3517 3518 return 0; 3519 } 3520 3521 static void 3522 rtw89_phy_c2h_rfk_report_state(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 3523 { 3524 const struct rtw89_c2h_rfk_report *report = 3525 (const struct rtw89_c2h_rfk_report *)c2h->data; 3526 struct rtw89_rfk_wait_info *wait = &rtwdev->rfk_wait; 3527 3528 wait->state = report->state; 3529 wait->version = report->version; 3530 3531 complete(&wait->completion); 3532 3533 rtw89_debug(rtwdev, RTW89_DBG_RFK, 3534 "RFK report state %d with version %d (%*ph)\n", 3535 wait->state, wait->version, 3536 (int)(len - sizeof(report->hdr)), &report->state); 3537 } 3538 3539 static void 3540 rtw89_phy_c2h_rfk_log_tas_pwr(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 3541 { 3542 const struct rtw89_c2h_rf_tas_info *rf_tas = 3543 (const struct rtw89_c2h_rf_tas_info *)c2h->data; 3544 const enum rtw89_sar_sources src = rtwdev->sar.src; 3545 struct rtw89_tas_info *tas = &rtwdev->tas; 3546 u64 linear = 0; 3547 u32 i, cur_idx; 3548 s16 txpwr; 3549 3550 if (!tas->enable || src == RTW89_SAR_SOURCE_NONE) 3551 return; 3552 3553 cur_idx = le32_to_cpu(rf_tas->cur_idx); 3554 for (i = 0; i < cur_idx; i++) { 3555 txpwr = (s16)le16_to_cpu(rf_tas->txpwr_history[i]); 3556 linear += rtw89_db_quarter_to_linear(txpwr); 3557 3558 rtw89_debug(rtwdev, RTW89_DBG_SAR, 3559 "tas: index: %u, txpwr: %d\n", i, txpwr); 3560 } 3561 3562 if (cur_idx == 0) 3563 tas->instant_txpwr = rtw89_db_to_linear(0); 3564 else 3565 tas->instant_txpwr = DIV_ROUND_DOWN_ULL(linear, cur_idx); 3566 } 3567 3568 static 3569 void (* const rtw89_phy_c2h_rfk_report_handler[])(struct rtw89_dev *rtwdev, 3570 struct sk_buff *c2h, u32 len) = { 3571 [RTW89_PHY_C2H_RFK_REPORT_FUNC_STATE] = rtw89_phy_c2h_rfk_report_state, 3572 [RTW89_PHY_C2H_RFK_LOG_TAS_PWR] = rtw89_phy_c2h_rfk_log_tas_pwr, 3573 }; 3574 3575 bool rtw89_phy_c2h_chk_atomic(struct rtw89_dev *rtwdev, u8 class, u8 func) 3576 { 3577 switch (class) { 3578 case RTW89_PHY_C2H_RFK_LOG: 3579 switch (func) { 3580 case RTW89_PHY_C2H_RFK_LOG_FUNC_IQK: 3581 case RTW89_PHY_C2H_RFK_LOG_FUNC_DPK: 3582 case RTW89_PHY_C2H_RFK_LOG_FUNC_DACK: 3583 case RTW89_PHY_C2H_RFK_LOG_FUNC_RXDCK: 3584 case RTW89_PHY_C2H_RFK_LOG_FUNC_TSSI: 3585 case RTW89_PHY_C2H_RFK_LOG_FUNC_TXGAPK: 3586 return true; 3587 default: 3588 return false; 3589 } 3590 case RTW89_PHY_C2H_RFK_REPORT: 3591 switch (func) { 3592 case RTW89_PHY_C2H_RFK_REPORT_FUNC_STATE: 3593 return true; 3594 default: 3595 return false; 3596 } 3597 default: 3598 return false; 3599 } 3600 } 3601 3602 void rtw89_phy_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, 3603 u32 len, u8 class, u8 func) 3604 { 3605 void (*handler)(struct rtw89_dev *rtwdev, 3606 struct sk_buff *c2h, u32 len) = NULL; 3607 3608 switch (class) { 3609 case RTW89_PHY_C2H_CLASS_RA: 3610 if (func < RTW89_PHY_C2H_FUNC_RA_MAX) 3611 handler = rtw89_phy_c2h_ra_handler[func]; 3612 break; 3613 case RTW89_PHY_C2H_RFK_LOG: 3614 if (func < ARRAY_SIZE(rtw89_phy_c2h_rfk_log_handler)) 3615 handler = rtw89_phy_c2h_rfk_log_handler[func]; 3616 break; 3617 case RTW89_PHY_C2H_RFK_REPORT: 3618 if (func < ARRAY_SIZE(rtw89_phy_c2h_rfk_report_handler)) 3619 handler = rtw89_phy_c2h_rfk_report_handler[func]; 3620 break; 3621 case RTW89_PHY_C2H_CLASS_DM: 3622 if (func < ARRAY_SIZE(rtw89_phy_c2h_dm_handler)) 3623 handler = rtw89_phy_c2h_dm_handler[func]; 3624 break; 3625 default: 3626 rtw89_info(rtwdev, "PHY c2h class %d not support\n", class); 3627 return; 3628 } 3629 if (!handler) { 3630 rtw89_info(rtwdev, "PHY c2h class %d func %d not support\n", class, 3631 func); 3632 return; 3633 } 3634 handler(rtwdev, skb, len); 3635 } 3636 3637 int rtw89_phy_rfk_pre_ntfy_and_wait(struct rtw89_dev *rtwdev, 3638 enum rtw89_phy_idx phy_idx, 3639 unsigned int ms) 3640 { 3641 int ret; 3642 3643 rtw89_phy_rfk_report_prep(rtwdev); 3644 3645 ret = rtw89_fw_h2c_rf_pre_ntfy(rtwdev, phy_idx); 3646 if (ret) 3647 return ret; 3648 3649 return rtw89_phy_rfk_report_wait(rtwdev, "PRE_NTFY", ms); 3650 } 3651 EXPORT_SYMBOL(rtw89_phy_rfk_pre_ntfy_and_wait); 3652 3653 int rtw89_phy_rfk_tssi_and_wait(struct rtw89_dev *rtwdev, 3654 enum rtw89_phy_idx phy_idx, 3655 const struct rtw89_chan *chan, 3656 enum rtw89_tssi_mode tssi_mode, 3657 unsigned int ms) 3658 { 3659 int ret; 3660 3661 rtw89_phy_rfk_report_prep(rtwdev); 3662 3663 ret = rtw89_fw_h2c_rf_tssi(rtwdev, phy_idx, chan, tssi_mode); 3664 if (ret) 3665 return ret; 3666 3667 return rtw89_phy_rfk_report_wait(rtwdev, "TSSI", ms); 3668 } 3669 EXPORT_SYMBOL(rtw89_phy_rfk_tssi_and_wait); 3670 3671 int rtw89_phy_rfk_iqk_and_wait(struct rtw89_dev *rtwdev, 3672 enum rtw89_phy_idx phy_idx, 3673 const struct rtw89_chan *chan, 3674 unsigned int ms) 3675 { 3676 int ret; 3677 3678 rtw89_phy_rfk_report_prep(rtwdev); 3679 3680 ret = rtw89_fw_h2c_rf_iqk(rtwdev, phy_idx, chan); 3681 if (ret) 3682 return ret; 3683 3684 return rtw89_phy_rfk_report_wait(rtwdev, "IQK", ms); 3685 } 3686 EXPORT_SYMBOL(rtw89_phy_rfk_iqk_and_wait); 3687 3688 int rtw89_phy_rfk_dpk_and_wait(struct rtw89_dev *rtwdev, 3689 enum rtw89_phy_idx phy_idx, 3690 const struct rtw89_chan *chan, 3691 unsigned int ms) 3692 { 3693 int ret; 3694 3695 rtw89_phy_rfk_report_prep(rtwdev); 3696 3697 ret = rtw89_fw_h2c_rf_dpk(rtwdev, phy_idx, chan); 3698 if (ret) 3699 return ret; 3700 3701 return rtw89_phy_rfk_report_wait(rtwdev, "DPK", ms); 3702 } 3703 EXPORT_SYMBOL(rtw89_phy_rfk_dpk_and_wait); 3704 3705 int rtw89_phy_rfk_txgapk_and_wait(struct rtw89_dev *rtwdev, 3706 enum rtw89_phy_idx phy_idx, 3707 const struct rtw89_chan *chan, 3708 unsigned int ms) 3709 { 3710 int ret; 3711 3712 rtw89_phy_rfk_report_prep(rtwdev); 3713 3714 ret = rtw89_fw_h2c_rf_txgapk(rtwdev, phy_idx, chan); 3715 if (ret) 3716 return ret; 3717 3718 return rtw89_phy_rfk_report_wait(rtwdev, "TXGAPK", ms); 3719 } 3720 EXPORT_SYMBOL(rtw89_phy_rfk_txgapk_and_wait); 3721 3722 int rtw89_phy_rfk_dack_and_wait(struct rtw89_dev *rtwdev, 3723 enum rtw89_phy_idx phy_idx, 3724 const struct rtw89_chan *chan, 3725 unsigned int ms) 3726 { 3727 int ret; 3728 3729 rtw89_phy_rfk_report_prep(rtwdev); 3730 3731 ret = rtw89_fw_h2c_rf_dack(rtwdev, phy_idx, chan); 3732 if (ret) 3733 return ret; 3734 3735 return rtw89_phy_rfk_report_wait(rtwdev, "DACK", ms); 3736 } 3737 EXPORT_SYMBOL(rtw89_phy_rfk_dack_and_wait); 3738 3739 int rtw89_phy_rfk_rxdck_and_wait(struct rtw89_dev *rtwdev, 3740 enum rtw89_phy_idx phy_idx, 3741 const struct rtw89_chan *chan, 3742 bool is_chl_k, unsigned int ms) 3743 { 3744 int ret; 3745 3746 rtw89_phy_rfk_report_prep(rtwdev); 3747 3748 ret = rtw89_fw_h2c_rf_rxdck(rtwdev, phy_idx, chan, is_chl_k); 3749 if (ret) 3750 return ret; 3751 3752 return rtw89_phy_rfk_report_wait(rtwdev, "RX_DCK", ms); 3753 } 3754 EXPORT_SYMBOL(rtw89_phy_rfk_rxdck_and_wait); 3755 3756 static u32 phy_tssi_get_cck_group(u8 ch) 3757 { 3758 switch (ch) { 3759 case 1 ... 2: 3760 return 0; 3761 case 3 ... 5: 3762 return 1; 3763 case 6 ... 8: 3764 return 2; 3765 case 9 ... 11: 3766 return 3; 3767 case 12 ... 13: 3768 return 4; 3769 case 14: 3770 return 5; 3771 } 3772 3773 return 0; 3774 } 3775 3776 #define PHY_TSSI_EXTRA_GROUP_BIT BIT(31) 3777 #define PHY_TSSI_EXTRA_GROUP(idx) (PHY_TSSI_EXTRA_GROUP_BIT | (idx)) 3778 #define PHY_IS_TSSI_EXTRA_GROUP(group) ((group) & PHY_TSSI_EXTRA_GROUP_BIT) 3779 #define PHY_TSSI_EXTRA_GET_GROUP_IDX1(group) \ 3780 ((group) & ~PHY_TSSI_EXTRA_GROUP_BIT) 3781 #define PHY_TSSI_EXTRA_GET_GROUP_IDX2(group) \ 3782 (PHY_TSSI_EXTRA_GET_GROUP_IDX1(group) + 1) 3783 3784 static u32 phy_tssi_get_ofdm_group(u8 ch) 3785 { 3786 switch (ch) { 3787 case 1 ... 2: 3788 return 0; 3789 case 3 ... 5: 3790 return 1; 3791 case 6 ... 8: 3792 return 2; 3793 case 9 ... 11: 3794 return 3; 3795 case 12 ... 14: 3796 return 4; 3797 case 36 ... 40: 3798 return 5; 3799 case 41 ... 43: 3800 return PHY_TSSI_EXTRA_GROUP(5); 3801 case 44 ... 48: 3802 return 6; 3803 case 49 ... 51: 3804 return PHY_TSSI_EXTRA_GROUP(6); 3805 case 52 ... 56: 3806 return 7; 3807 case 57 ... 59: 3808 return PHY_TSSI_EXTRA_GROUP(7); 3809 case 60 ... 64: 3810 return 8; 3811 case 100 ... 104: 3812 return 9; 3813 case 105 ... 107: 3814 return PHY_TSSI_EXTRA_GROUP(9); 3815 case 108 ... 112: 3816 return 10; 3817 case 113 ... 115: 3818 return PHY_TSSI_EXTRA_GROUP(10); 3819 case 116 ... 120: 3820 return 11; 3821 case 121 ... 123: 3822 return PHY_TSSI_EXTRA_GROUP(11); 3823 case 124 ... 128: 3824 return 12; 3825 case 129 ... 131: 3826 return PHY_TSSI_EXTRA_GROUP(12); 3827 case 132 ... 136: 3828 return 13; 3829 case 137 ... 139: 3830 return PHY_TSSI_EXTRA_GROUP(13); 3831 case 140 ... 144: 3832 return 14; 3833 case 149 ... 153: 3834 return 15; 3835 case 154 ... 156: 3836 return PHY_TSSI_EXTRA_GROUP(15); 3837 case 157 ... 161: 3838 return 16; 3839 case 162 ... 164: 3840 return PHY_TSSI_EXTRA_GROUP(16); 3841 case 165 ... 169: 3842 return 17; 3843 case 170 ... 172: 3844 return PHY_TSSI_EXTRA_GROUP(17); 3845 case 173 ... 177: 3846 return 18; 3847 } 3848 3849 return 0; 3850 } 3851 3852 static u32 phy_tssi_get_6g_ofdm_group(u8 ch) 3853 { 3854 switch (ch) { 3855 case 1 ... 5: 3856 return 0; 3857 case 6 ... 8: 3858 return PHY_TSSI_EXTRA_GROUP(0); 3859 case 9 ... 13: 3860 return 1; 3861 case 14 ... 16: 3862 return PHY_TSSI_EXTRA_GROUP(1); 3863 case 17 ... 21: 3864 return 2; 3865 case 22 ... 24: 3866 return PHY_TSSI_EXTRA_GROUP(2); 3867 case 25 ... 29: 3868 return 3; 3869 case 33 ... 37: 3870 return 4; 3871 case 38 ... 40: 3872 return PHY_TSSI_EXTRA_GROUP(4); 3873 case 41 ... 45: 3874 return 5; 3875 case 46 ... 48: 3876 return PHY_TSSI_EXTRA_GROUP(5); 3877 case 49 ... 53: 3878 return 6; 3879 case 54 ... 56: 3880 return PHY_TSSI_EXTRA_GROUP(6); 3881 case 57 ... 61: 3882 return 7; 3883 case 65 ... 69: 3884 return 8; 3885 case 70 ... 72: 3886 return PHY_TSSI_EXTRA_GROUP(8); 3887 case 73 ... 77: 3888 return 9; 3889 case 78 ... 80: 3890 return PHY_TSSI_EXTRA_GROUP(9); 3891 case 81 ... 85: 3892 return 10; 3893 case 86 ... 88: 3894 return PHY_TSSI_EXTRA_GROUP(10); 3895 case 89 ... 93: 3896 return 11; 3897 case 97 ... 101: 3898 return 12; 3899 case 102 ... 104: 3900 return PHY_TSSI_EXTRA_GROUP(12); 3901 case 105 ... 109: 3902 return 13; 3903 case 110 ... 112: 3904 return PHY_TSSI_EXTRA_GROUP(13); 3905 case 113 ... 117: 3906 return 14; 3907 case 118 ... 120: 3908 return PHY_TSSI_EXTRA_GROUP(14); 3909 case 121 ... 125: 3910 return 15; 3911 case 129 ... 133: 3912 return 16; 3913 case 134 ... 136: 3914 return PHY_TSSI_EXTRA_GROUP(16); 3915 case 137 ... 141: 3916 return 17; 3917 case 142 ... 144: 3918 return PHY_TSSI_EXTRA_GROUP(17); 3919 case 145 ... 149: 3920 return 18; 3921 case 150 ... 152: 3922 return PHY_TSSI_EXTRA_GROUP(18); 3923 case 153 ... 157: 3924 return 19; 3925 case 161 ... 165: 3926 return 20; 3927 case 166 ... 168: 3928 return PHY_TSSI_EXTRA_GROUP(20); 3929 case 169 ... 173: 3930 return 21; 3931 case 174 ... 176: 3932 return PHY_TSSI_EXTRA_GROUP(21); 3933 case 177 ... 181: 3934 return 22; 3935 case 182 ... 184: 3936 return PHY_TSSI_EXTRA_GROUP(22); 3937 case 185 ... 189: 3938 return 23; 3939 case 193 ... 197: 3940 return 24; 3941 case 198 ... 200: 3942 return PHY_TSSI_EXTRA_GROUP(24); 3943 case 201 ... 205: 3944 return 25; 3945 case 206 ... 208: 3946 return PHY_TSSI_EXTRA_GROUP(25); 3947 case 209 ... 213: 3948 return 26; 3949 case 214 ... 216: 3950 return PHY_TSSI_EXTRA_GROUP(26); 3951 case 217 ... 221: 3952 return 27; 3953 case 225 ... 229: 3954 return 28; 3955 case 230 ... 232: 3956 return PHY_TSSI_EXTRA_GROUP(28); 3957 case 233 ... 237: 3958 return 29; 3959 case 238 ... 240: 3960 return PHY_TSSI_EXTRA_GROUP(29); 3961 case 241 ... 245: 3962 return 30; 3963 case 246 ... 248: 3964 return PHY_TSSI_EXTRA_GROUP(30); 3965 case 249 ... 253: 3966 return 31; 3967 } 3968 3969 return 0; 3970 } 3971 3972 static u32 phy_tssi_get_trim_group(u8 ch) 3973 { 3974 switch (ch) { 3975 case 1 ... 8: 3976 return 0; 3977 case 9 ... 14: 3978 return 1; 3979 case 36 ... 48: 3980 return 2; 3981 case 49 ... 51: 3982 return PHY_TSSI_EXTRA_GROUP(2); 3983 case 52 ... 64: 3984 return 3; 3985 case 100 ... 112: 3986 return 4; 3987 case 113 ... 115: 3988 return PHY_TSSI_EXTRA_GROUP(4); 3989 case 116 ... 128: 3990 return 5; 3991 case 132 ... 144: 3992 return 6; 3993 case 149 ... 177: 3994 return 7; 3995 } 3996 3997 return 0; 3998 } 3999 4000 static u32 phy_tssi_get_6g_trim_group(u8 ch) 4001 { 4002 switch (ch) { 4003 case 1 ... 13: 4004 return 0; 4005 case 14 ... 16: 4006 return PHY_TSSI_EXTRA_GROUP(0); 4007 case 17 ... 29: 4008 return 1; 4009 case 33 ... 45: 4010 return 2; 4011 case 46 ... 48: 4012 return PHY_TSSI_EXTRA_GROUP(2); 4013 case 49 ... 61: 4014 return 3; 4015 case 65 ... 77: 4016 return 4; 4017 case 78 ... 80: 4018 return PHY_TSSI_EXTRA_GROUP(4); 4019 case 81 ... 93: 4020 return 5; 4021 case 97 ... 109: 4022 return 6; 4023 case 110 ... 112: 4024 return PHY_TSSI_EXTRA_GROUP(6); 4025 case 113 ... 125: 4026 return 7; 4027 case 129 ... 141: 4028 return 8; 4029 case 142 ... 144: 4030 return PHY_TSSI_EXTRA_GROUP(8); 4031 case 145 ... 157: 4032 return 9; 4033 case 161 ... 173: 4034 return 10; 4035 case 174 ... 176: 4036 return PHY_TSSI_EXTRA_GROUP(10); 4037 case 177 ... 189: 4038 return 11; 4039 case 193 ... 205: 4040 return 12; 4041 case 206 ... 208: 4042 return PHY_TSSI_EXTRA_GROUP(12); 4043 case 209 ... 221: 4044 return 13; 4045 case 225 ... 237: 4046 return 14; 4047 case 238 ... 240: 4048 return PHY_TSSI_EXTRA_GROUP(14); 4049 case 241 ... 253: 4050 return 15; 4051 } 4052 4053 return 0; 4054 } 4055 4056 static s8 phy_tssi_get_ofdm_de(struct rtw89_dev *rtwdev, 4057 enum rtw89_phy_idx phy, 4058 const struct rtw89_chan *chan, 4059 enum rtw89_rf_path path) 4060 { 4061 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi; 4062 enum rtw89_band band = chan->band_type; 4063 u8 ch = chan->channel; 4064 u32 gidx_1st; 4065 u32 gidx_2nd; 4066 s8 de_1st; 4067 s8 de_2nd; 4068 u32 gidx; 4069 s8 val; 4070 4071 if (band == RTW89_BAND_6G) 4072 goto calc_6g; 4073 4074 gidx = phy_tssi_get_ofdm_group(ch); 4075 4076 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 4077 "[TSSI][TRIM]: path=%d mcs group_idx=0x%x\n", 4078 path, gidx); 4079 4080 if (PHY_IS_TSSI_EXTRA_GROUP(gidx)) { 4081 gidx_1st = PHY_TSSI_EXTRA_GET_GROUP_IDX1(gidx); 4082 gidx_2nd = PHY_TSSI_EXTRA_GET_GROUP_IDX2(gidx); 4083 de_1st = tssi_info->tssi_mcs[path][gidx_1st]; 4084 de_2nd = tssi_info->tssi_mcs[path][gidx_2nd]; 4085 val = (de_1st + de_2nd) / 2; 4086 4087 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 4088 "[TSSI][TRIM]: path=%d mcs de=%d 1st=%d 2nd=%d\n", 4089 path, val, de_1st, de_2nd); 4090 } else { 4091 val = tssi_info->tssi_mcs[path][gidx]; 4092 4093 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 4094 "[TSSI][TRIM]: path=%d mcs de=%d\n", path, val); 4095 } 4096 4097 return val; 4098 4099 calc_6g: 4100 gidx = phy_tssi_get_6g_ofdm_group(ch); 4101 4102 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 4103 "[TSSI][TRIM]: path=%d mcs group_idx=0x%x\n", 4104 path, gidx); 4105 4106 if (PHY_IS_TSSI_EXTRA_GROUP(gidx)) { 4107 gidx_1st = PHY_TSSI_EXTRA_GET_GROUP_IDX1(gidx); 4108 gidx_2nd = PHY_TSSI_EXTRA_GET_GROUP_IDX2(gidx); 4109 de_1st = tssi_info->tssi_6g_mcs[path][gidx_1st]; 4110 de_2nd = tssi_info->tssi_6g_mcs[path][gidx_2nd]; 4111 val = (de_1st + de_2nd) / 2; 4112 4113 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 4114 "[TSSI][TRIM]: path=%d mcs de=%d 1st=%d 2nd=%d\n", 4115 path, val, de_1st, de_2nd); 4116 } else { 4117 val = tssi_info->tssi_6g_mcs[path][gidx]; 4118 4119 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 4120 "[TSSI][TRIM]: path=%d mcs de=%d\n", path, val); 4121 } 4122 4123 return val; 4124 } 4125 4126 static s8 phy_tssi_get_ofdm_trim_de(struct rtw89_dev *rtwdev, 4127 enum rtw89_phy_idx phy, 4128 const struct rtw89_chan *chan, 4129 enum rtw89_rf_path path) 4130 { 4131 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi; 4132 enum rtw89_band band = chan->band_type; 4133 u8 ch = chan->channel; 4134 u32 tgidx_1st; 4135 u32 tgidx_2nd; 4136 s8 tde_1st; 4137 s8 tde_2nd; 4138 u32 tgidx; 4139 s8 val; 4140 4141 if (band == RTW89_BAND_6G) 4142 goto calc_6g; 4143 4144 tgidx = phy_tssi_get_trim_group(ch); 4145 4146 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 4147 "[TSSI][TRIM]: path=%d mcs trim_group_idx=0x%x\n", 4148 path, tgidx); 4149 4150 if (PHY_IS_TSSI_EXTRA_GROUP(tgidx)) { 4151 tgidx_1st = PHY_TSSI_EXTRA_GET_GROUP_IDX1(tgidx); 4152 tgidx_2nd = PHY_TSSI_EXTRA_GET_GROUP_IDX2(tgidx); 4153 tde_1st = tssi_info->tssi_trim[path][tgidx_1st]; 4154 tde_2nd = tssi_info->tssi_trim[path][tgidx_2nd]; 4155 val = (tde_1st + tde_2nd) / 2; 4156 4157 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 4158 "[TSSI][TRIM]: path=%d mcs trim_de=%d 1st=%d 2nd=%d\n", 4159 path, val, tde_1st, tde_2nd); 4160 } else { 4161 val = tssi_info->tssi_trim[path][tgidx]; 4162 4163 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 4164 "[TSSI][TRIM]: path=%d mcs trim_de=%d\n", 4165 path, val); 4166 } 4167 4168 return val; 4169 4170 calc_6g: 4171 tgidx = phy_tssi_get_6g_trim_group(ch); 4172 4173 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 4174 "[TSSI][TRIM]: path=%d mcs trim_group_idx=0x%x\n", 4175 path, tgidx); 4176 4177 if (PHY_IS_TSSI_EXTRA_GROUP(tgidx)) { 4178 tgidx_1st = PHY_TSSI_EXTRA_GET_GROUP_IDX1(tgidx); 4179 tgidx_2nd = PHY_TSSI_EXTRA_GET_GROUP_IDX2(tgidx); 4180 tde_1st = tssi_info->tssi_trim_6g[path][tgidx_1st]; 4181 tde_2nd = tssi_info->tssi_trim_6g[path][tgidx_2nd]; 4182 val = (tde_1st + tde_2nd) / 2; 4183 4184 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 4185 "[TSSI][TRIM]: path=%d mcs trim_de=%d 1st=%d 2nd=%d\n", 4186 path, val, tde_1st, tde_2nd); 4187 } else { 4188 val = tssi_info->tssi_trim_6g[path][tgidx]; 4189 4190 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 4191 "[TSSI][TRIM]: path=%d mcs trim_de=%d\n", 4192 path, val); 4193 } 4194 4195 return val; 4196 } 4197 4198 void rtw89_phy_rfk_tssi_fill_fwcmd_efuse_to_de(struct rtw89_dev *rtwdev, 4199 enum rtw89_phy_idx phy, 4200 const struct rtw89_chan *chan, 4201 struct rtw89_h2c_rf_tssi *h2c) 4202 { 4203 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi; 4204 u8 ch = chan->channel; 4205 s8 trim_de; 4206 s8 ofdm_de; 4207 s8 cck_de; 4208 u8 gidx; 4209 s8 val; 4210 int i; 4211 4212 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "[TSSI][TRIM]: phy=%d ch=%d\n", 4213 phy, ch); 4214 4215 for (i = RF_PATH_A; i <= RF_PATH_B; i++) { 4216 trim_de = phy_tssi_get_ofdm_trim_de(rtwdev, phy, chan, i); 4217 h2c->curr_tssi_trim_de[i] = trim_de; 4218 4219 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 4220 "[TSSI][TRIM]: path=%d trim_de=0x%x\n", i, trim_de); 4221 4222 gidx = phy_tssi_get_cck_group(ch); 4223 cck_de = tssi_info->tssi_cck[i][gidx]; 4224 val = u32_get_bits(cck_de + trim_de, 0xff); 4225 4226 h2c->curr_tssi_cck_de[i] = 0x0; 4227 h2c->curr_tssi_cck_de_20m[i] = val; 4228 h2c->curr_tssi_cck_de_40m[i] = val; 4229 h2c->curr_tssi_efuse_cck_de[i] = cck_de; 4230 4231 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 4232 "[TSSI][TRIM]: path=%d cck_de=0x%x\n", i, cck_de); 4233 4234 ofdm_de = phy_tssi_get_ofdm_de(rtwdev, phy, chan, i); 4235 val = u32_get_bits(ofdm_de + trim_de, 0xff); 4236 4237 h2c->curr_tssi_ofdm_de[i] = 0x0; 4238 h2c->curr_tssi_ofdm_de_20m[i] = val; 4239 h2c->curr_tssi_ofdm_de_40m[i] = val; 4240 h2c->curr_tssi_ofdm_de_80m[i] = val; 4241 h2c->curr_tssi_ofdm_de_160m[i] = val; 4242 h2c->curr_tssi_ofdm_de_320m[i] = val; 4243 h2c->curr_tssi_efuse_ofdm_de[i] = ofdm_de; 4244 4245 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 4246 "[TSSI][TRIM]: path=%d ofdm_de=0x%x\n", i, ofdm_de); 4247 } 4248 } 4249 4250 void rtw89_phy_rfk_tssi_fill_fwcmd_tmeter_tbl(struct rtw89_dev *rtwdev, 4251 enum rtw89_phy_idx phy, 4252 const struct rtw89_chan *chan, 4253 struct rtw89_h2c_rf_tssi *h2c) 4254 { 4255 struct rtw89_fw_txpwr_track_cfg *trk = rtwdev->fw.elm_info.txpwr_trk; 4256 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi; 4257 const s8 *thm_up[RF_PATH_B + 1] = {}; 4258 const s8 *thm_down[RF_PATH_B + 1] = {}; 4259 u8 subband = chan->subband_type; 4260 s8 thm_ofst[128] = {0}; 4261 u8 thermal; 4262 u8 path; 4263 u8 i, j; 4264 4265 switch (subband) { 4266 default: 4267 case RTW89_CH_2G: 4268 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_2GA_P][0]; 4269 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_2GA_N][0]; 4270 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_2GB_P][0]; 4271 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_2GB_N][0]; 4272 break; 4273 case RTW89_CH_5G_BAND_1: 4274 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_P][0]; 4275 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_N][0]; 4276 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_P][0]; 4277 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_N][0]; 4278 break; 4279 case RTW89_CH_5G_BAND_3: 4280 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_P][1]; 4281 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_N][1]; 4282 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_P][1]; 4283 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_N][1]; 4284 break; 4285 case RTW89_CH_5G_BAND_4: 4286 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_P][2]; 4287 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_N][2]; 4288 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_P][2]; 4289 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_N][2]; 4290 break; 4291 case RTW89_CH_6G_BAND_IDX0: 4292 case RTW89_CH_6G_BAND_IDX1: 4293 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_P][0]; 4294 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_N][0]; 4295 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_P][0]; 4296 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_N][0]; 4297 break; 4298 case RTW89_CH_6G_BAND_IDX2: 4299 case RTW89_CH_6G_BAND_IDX3: 4300 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_P][1]; 4301 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_N][1]; 4302 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_P][1]; 4303 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_N][1]; 4304 break; 4305 case RTW89_CH_6G_BAND_IDX4: 4306 case RTW89_CH_6G_BAND_IDX5: 4307 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_P][2]; 4308 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_N][2]; 4309 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_P][2]; 4310 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_N][2]; 4311 break; 4312 case RTW89_CH_6G_BAND_IDX6: 4313 case RTW89_CH_6G_BAND_IDX7: 4314 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_P][3]; 4315 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_N][3]; 4316 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_P][3]; 4317 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_N][3]; 4318 break; 4319 } 4320 4321 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 4322 "[TSSI] tmeter tbl on subband: %u\n", subband); 4323 4324 for (path = RF_PATH_A; path <= RF_PATH_B; path++) { 4325 thermal = tssi_info->thermal[path]; 4326 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 4327 "path: %u, pg thermal: 0x%x\n", path, thermal); 4328 4329 if (thermal == 0xff) { 4330 h2c->pg_thermal[path] = 0x38; 4331 memset(h2c->ftable[path], 0, sizeof(h2c->ftable[path])); 4332 continue; 4333 } 4334 4335 h2c->pg_thermal[path] = thermal; 4336 4337 i = 0; 4338 for (j = 0; j < 64; j++) 4339 thm_ofst[j] = i < DELTA_SWINGIDX_SIZE ? 4340 thm_up[path][i++] : 4341 thm_up[path][DELTA_SWINGIDX_SIZE - 1]; 4342 4343 i = 1; 4344 for (j = 127; j >= 64; j--) 4345 thm_ofst[j] = i < DELTA_SWINGIDX_SIZE ? 4346 -thm_down[path][i++] : 4347 -thm_down[path][DELTA_SWINGIDX_SIZE - 1]; 4348 4349 for (i = 0; i < 128; i += 4) { 4350 h2c->ftable[path][i + 0] = thm_ofst[i + 3]; 4351 h2c->ftable[path][i + 1] = thm_ofst[i + 2]; 4352 h2c->ftable[path][i + 2] = thm_ofst[i + 1]; 4353 h2c->ftable[path][i + 3] = thm_ofst[i + 0]; 4354 4355 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 4356 "thm ofst [%x]: %02x %02x %02x %02x\n", 4357 i, thm_ofst[i], thm_ofst[i + 1], 4358 thm_ofst[i + 2], thm_ofst[i + 3]); 4359 } 4360 } 4361 } 4362 4363 static u8 rtw89_phy_cfo_get_xcap_reg(struct rtw89_dev *rtwdev, bool sc_xo) 4364 { 4365 const struct rtw89_xtal_info *xtal = rtwdev->chip->xtal_info; 4366 u32 reg_mask; 4367 4368 if (sc_xo) 4369 reg_mask = xtal->sc_xo_mask; 4370 else 4371 reg_mask = xtal->sc_xi_mask; 4372 4373 return (u8)rtw89_read32_mask(rtwdev, xtal->xcap_reg, reg_mask); 4374 } 4375 4376 static void rtw89_phy_cfo_set_xcap_reg(struct rtw89_dev *rtwdev, bool sc_xo, 4377 u8 val) 4378 { 4379 const struct rtw89_xtal_info *xtal = rtwdev->chip->xtal_info; 4380 u32 reg_mask; 4381 4382 if (sc_xo) 4383 reg_mask = xtal->sc_xo_mask; 4384 else 4385 reg_mask = xtal->sc_xi_mask; 4386 4387 rtw89_write32_mask(rtwdev, xtal->xcap_reg, reg_mask, val); 4388 } 4389 4390 static void rtw89_phy_cfo_set_crystal_cap(struct rtw89_dev *rtwdev, 4391 u8 crystal_cap, bool force) 4392 { 4393 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 4394 const struct rtw89_chip_info *chip = rtwdev->chip; 4395 u8 sc_xi_val, sc_xo_val; 4396 4397 if (!force && cfo->crystal_cap == crystal_cap) 4398 return; 4399 if (chip->chip_id == RTL8852A || chip->chip_id == RTL8851B) { 4400 rtw89_phy_cfo_set_xcap_reg(rtwdev, true, crystal_cap); 4401 rtw89_phy_cfo_set_xcap_reg(rtwdev, false, crystal_cap); 4402 sc_xo_val = rtw89_phy_cfo_get_xcap_reg(rtwdev, true); 4403 sc_xi_val = rtw89_phy_cfo_get_xcap_reg(rtwdev, false); 4404 } else { 4405 rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XO, 4406 crystal_cap, XTAL_SC_XO_MASK); 4407 rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XI, 4408 crystal_cap, XTAL_SC_XI_MASK); 4409 rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XO, &sc_xo_val); 4410 rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XI, &sc_xi_val); 4411 } 4412 cfo->crystal_cap = sc_xi_val; 4413 cfo->x_cap_ofst = (s8)((int)cfo->crystal_cap - cfo->def_x_cap); 4414 4415 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set sc_xi=0x%x\n", sc_xi_val); 4416 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set sc_xo=0x%x\n", sc_xo_val); 4417 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Get xcap_ofst=%d\n", 4418 cfo->x_cap_ofst); 4419 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set xcap OK\n"); 4420 } 4421 4422 static void rtw89_phy_cfo_reset(struct rtw89_dev *rtwdev) 4423 { 4424 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 4425 u8 cap; 4426 4427 cfo->def_x_cap = cfo->crystal_cap_default & B_AX_XTAL_SC_MASK; 4428 cfo->is_adjust = false; 4429 if (cfo->crystal_cap == cfo->def_x_cap) 4430 return; 4431 cap = cfo->crystal_cap; 4432 cap += (cap > cfo->def_x_cap ? -1 : 1); 4433 rtw89_phy_cfo_set_crystal_cap(rtwdev, cap, false); 4434 rtw89_debug(rtwdev, RTW89_DBG_CFO, 4435 "(0x%x) approach to dflt_val=(0x%x)\n", cfo->crystal_cap, 4436 cfo->def_x_cap); 4437 } 4438 4439 static void rtw89_dcfo_comp(struct rtw89_dev *rtwdev, s32 curr_cfo) 4440 { 4441 const struct rtw89_reg_def *dcfo_comp = rtwdev->chip->dcfo_comp; 4442 bool is_linked = rtwdev->total_sta_assoc > 0; 4443 s32 cfo_avg_312; 4444 s32 dcfo_comp_val; 4445 int sign; 4446 4447 if (rtwdev->chip->chip_id == RTL8922A) 4448 return; 4449 4450 if (!is_linked) { 4451 rtw89_debug(rtwdev, RTW89_DBG_CFO, "DCFO: is_linked=%d\n", 4452 is_linked); 4453 return; 4454 } 4455 rtw89_debug(rtwdev, RTW89_DBG_CFO, "DCFO: curr_cfo=%d\n", curr_cfo); 4456 if (curr_cfo == 0) 4457 return; 4458 dcfo_comp_val = rtw89_phy_read32_mask(rtwdev, R_DCFO, B_DCFO); 4459 sign = curr_cfo > 0 ? 1 : -1; 4460 cfo_avg_312 = curr_cfo / 625 + sign * dcfo_comp_val; 4461 rtw89_debug(rtwdev, RTW89_DBG_CFO, "avg_cfo_312=%d step\n", cfo_avg_312); 4462 if (rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv == CHIP_CBV) 4463 cfo_avg_312 = -cfo_avg_312; 4464 rtw89_phy_set_phy_regs(rtwdev, dcfo_comp->addr, dcfo_comp->mask, 4465 cfo_avg_312); 4466 } 4467 4468 static void rtw89_dcfo_comp_init(struct rtw89_dev *rtwdev) 4469 { 4470 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 4471 const struct rtw89_chip_info *chip = rtwdev->chip; 4472 const struct rtw89_cfo_regs *cfo = phy->cfo; 4473 4474 rtw89_phy_set_phy_regs(rtwdev, cfo->comp_seg0, cfo->valid_0_mask, 1); 4475 rtw89_phy_set_phy_regs(rtwdev, cfo->comp, cfo->weighting_mask, 8); 4476 4477 if (chip->chip_gen == RTW89_CHIP_AX) { 4478 if (chip->cfo_hw_comp) { 4479 rtw89_write32_mask(rtwdev, R_AX_PWR_UL_CTRL2, 4480 B_AX_PWR_UL_CFO_MASK, 0x6); 4481 } else { 4482 rtw89_phy_set_phy_regs(rtwdev, R_DCFO, B_DCFO, 1); 4483 rtw89_write32_clr(rtwdev, R_AX_PWR_UL_CTRL2, 4484 B_AX_PWR_UL_CFO_MASK); 4485 } 4486 } 4487 } 4488 4489 static void rtw89_phy_cfo_init(struct rtw89_dev *rtwdev) 4490 { 4491 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 4492 struct rtw89_efuse *efuse = &rtwdev->efuse; 4493 4494 cfo->crystal_cap_default = efuse->xtal_cap & B_AX_XTAL_SC_MASK; 4495 cfo->crystal_cap = cfo->crystal_cap_default; 4496 cfo->def_x_cap = cfo->crystal_cap; 4497 cfo->x_cap_ub = min_t(int, cfo->def_x_cap + CFO_BOUND, 0x7f); 4498 cfo->x_cap_lb = max_t(int, cfo->def_x_cap - CFO_BOUND, 0x1); 4499 cfo->is_adjust = false; 4500 cfo->divergence_lock_en = false; 4501 cfo->x_cap_ofst = 0; 4502 cfo->lock_cnt = 0; 4503 cfo->rtw89_multi_cfo_mode = RTW89_TP_BASED_AVG_MODE; 4504 cfo->apply_compensation = false; 4505 cfo->residual_cfo_acc = 0; 4506 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Default xcap=%0x\n", 4507 cfo->crystal_cap_default); 4508 rtw89_phy_cfo_set_crystal_cap(rtwdev, cfo->crystal_cap_default, true); 4509 rtw89_dcfo_comp_init(rtwdev); 4510 cfo->cfo_timer_ms = 2000; 4511 cfo->cfo_trig_by_timer_en = false; 4512 cfo->phy_cfo_trk_cnt = 0; 4513 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL; 4514 cfo->cfo_ul_ofdma_acc_mode = RTW89_CFO_UL_OFDMA_ACC_ENABLE; 4515 } 4516 4517 static void rtw89_phy_cfo_crystal_cap_adjust(struct rtw89_dev *rtwdev, 4518 s32 curr_cfo) 4519 { 4520 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 4521 int crystal_cap = cfo->crystal_cap; 4522 s32 cfo_abs = abs(curr_cfo); 4523 int sign; 4524 4525 if (curr_cfo == 0) { 4526 rtw89_debug(rtwdev, RTW89_DBG_CFO, "curr_cfo=0\n"); 4527 return; 4528 } 4529 if (!cfo->is_adjust) { 4530 if (cfo_abs > CFO_TRK_ENABLE_TH) 4531 cfo->is_adjust = true; 4532 } else { 4533 if (cfo_abs <= CFO_TRK_STOP_TH) 4534 cfo->is_adjust = false; 4535 } 4536 if (!cfo->is_adjust) { 4537 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Stop CFO tracking\n"); 4538 return; 4539 } 4540 sign = curr_cfo > 0 ? 1 : -1; 4541 if (cfo_abs > CFO_TRK_STOP_TH_4) 4542 crystal_cap += 3 * sign; 4543 else if (cfo_abs > CFO_TRK_STOP_TH_3) 4544 crystal_cap += 3 * sign; 4545 else if (cfo_abs > CFO_TRK_STOP_TH_2) 4546 crystal_cap += 1 * sign; 4547 else if (cfo_abs > CFO_TRK_STOP_TH_1) 4548 crystal_cap += 1 * sign; 4549 else 4550 return; 4551 4552 crystal_cap = clamp(crystal_cap, 0, 127); 4553 rtw89_phy_cfo_set_crystal_cap(rtwdev, (u8)crystal_cap, false); 4554 rtw89_debug(rtwdev, RTW89_DBG_CFO, 4555 "X_cap{Curr,Default}={0x%x,0x%x}\n", 4556 cfo->crystal_cap, cfo->def_x_cap); 4557 } 4558 4559 static s32 rtw89_phy_average_cfo_calc(struct rtw89_dev *rtwdev) 4560 { 4561 const struct rtw89_chip_info *chip = rtwdev->chip; 4562 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 4563 s32 cfo_khz_all = 0; 4564 s32 cfo_cnt_all = 0; 4565 s32 cfo_all_avg = 0; 4566 u8 i; 4567 4568 if (rtwdev->total_sta_assoc != 1) 4569 return 0; 4570 rtw89_debug(rtwdev, RTW89_DBG_CFO, "one_entry_only\n"); 4571 for (i = 0; i < CFO_TRACK_MAX_USER; i++) { 4572 if (cfo->cfo_cnt[i] == 0) 4573 continue; 4574 cfo_khz_all += cfo->cfo_tail[i]; 4575 cfo_cnt_all += cfo->cfo_cnt[i]; 4576 cfo_all_avg = phy_div(cfo_khz_all, cfo_cnt_all); 4577 cfo->pre_cfo_avg[i] = cfo->cfo_avg[i]; 4578 cfo->dcfo_avg = phy_div(cfo_khz_all << chip->dcfo_comp_sft, 4579 cfo_cnt_all); 4580 } 4581 rtw89_debug(rtwdev, RTW89_DBG_CFO, 4582 "CFO track for macid = %d\n", i); 4583 rtw89_debug(rtwdev, RTW89_DBG_CFO, 4584 "Total cfo=%dK, pkt_cnt=%d, avg_cfo=%dK\n", 4585 cfo_khz_all, cfo_cnt_all, cfo_all_avg); 4586 return cfo_all_avg; 4587 } 4588 4589 static s32 rtw89_phy_multi_sta_cfo_calc(struct rtw89_dev *rtwdev) 4590 { 4591 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 4592 struct rtw89_traffic_stats *stats = &rtwdev->stats; 4593 s32 target_cfo = 0; 4594 s32 cfo_khz_all = 0; 4595 s32 cfo_khz_all_tp_wgt = 0; 4596 s32 cfo_avg = 0; 4597 s32 max_cfo_lb = BIT(31); 4598 s32 min_cfo_ub = GENMASK(30, 0); 4599 u16 cfo_cnt_all = 0; 4600 u8 active_entry_cnt = 0; 4601 u8 sta_cnt = 0; 4602 u32 tp_all = 0; 4603 u8 i; 4604 u8 cfo_tol = 0; 4605 4606 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Multi entry cfo_trk\n"); 4607 if (cfo->rtw89_multi_cfo_mode == RTW89_PKT_BASED_AVG_MODE) { 4608 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt based avg mode\n"); 4609 for (i = 0; i < CFO_TRACK_MAX_USER; i++) { 4610 if (cfo->cfo_cnt[i] == 0) 4611 continue; 4612 cfo_khz_all += cfo->cfo_tail[i]; 4613 cfo_cnt_all += cfo->cfo_cnt[i]; 4614 cfo_avg = phy_div(cfo_khz_all, (s32)cfo_cnt_all); 4615 rtw89_debug(rtwdev, RTW89_DBG_CFO, 4616 "Msta cfo=%d, pkt_cnt=%d, avg_cfo=%d\n", 4617 cfo_khz_all, cfo_cnt_all, cfo_avg); 4618 target_cfo = cfo_avg; 4619 } 4620 } else if (cfo->rtw89_multi_cfo_mode == RTW89_ENTRY_BASED_AVG_MODE) { 4621 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Entry based avg mode\n"); 4622 for (i = 0; i < CFO_TRACK_MAX_USER; i++) { 4623 if (cfo->cfo_cnt[i] == 0) 4624 continue; 4625 cfo->cfo_avg[i] = phy_div(cfo->cfo_tail[i], 4626 (s32)cfo->cfo_cnt[i]); 4627 cfo_khz_all += cfo->cfo_avg[i]; 4628 rtw89_debug(rtwdev, RTW89_DBG_CFO, 4629 "Macid=%d, cfo_avg=%d\n", i, 4630 cfo->cfo_avg[i]); 4631 } 4632 sta_cnt = rtwdev->total_sta_assoc; 4633 cfo_avg = phy_div(cfo_khz_all, (s32)sta_cnt); 4634 rtw89_debug(rtwdev, RTW89_DBG_CFO, 4635 "Msta cfo_acc=%d, ent_cnt=%d, avg_cfo=%d\n", 4636 cfo_khz_all, sta_cnt, cfo_avg); 4637 target_cfo = cfo_avg; 4638 } else if (cfo->rtw89_multi_cfo_mode == RTW89_TP_BASED_AVG_MODE) { 4639 rtw89_debug(rtwdev, RTW89_DBG_CFO, "TP based avg mode\n"); 4640 cfo_tol = cfo->sta_cfo_tolerance; 4641 for (i = 0; i < CFO_TRACK_MAX_USER; i++) { 4642 sta_cnt++; 4643 if (cfo->cfo_cnt[i] != 0) { 4644 cfo->cfo_avg[i] = phy_div(cfo->cfo_tail[i], 4645 (s32)cfo->cfo_cnt[i]); 4646 active_entry_cnt++; 4647 } else { 4648 cfo->cfo_avg[i] = cfo->pre_cfo_avg[i]; 4649 } 4650 max_cfo_lb = max(cfo->cfo_avg[i] - cfo_tol, max_cfo_lb); 4651 min_cfo_ub = min(cfo->cfo_avg[i] + cfo_tol, min_cfo_ub); 4652 cfo_khz_all += cfo->cfo_avg[i]; 4653 /* need tp for each entry */ 4654 rtw89_debug(rtwdev, RTW89_DBG_CFO, 4655 "[%d] cfo_avg=%d, tp=tbd\n", 4656 i, cfo->cfo_avg[i]); 4657 if (sta_cnt >= rtwdev->total_sta_assoc) 4658 break; 4659 } 4660 tp_all = stats->rx_throughput; /* need tp for each entry */ 4661 cfo_avg = phy_div(cfo_khz_all_tp_wgt, (s32)tp_all); 4662 4663 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Assoc sta cnt=%d\n", 4664 sta_cnt); 4665 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Active sta cnt=%d\n", 4666 active_entry_cnt); 4667 rtw89_debug(rtwdev, RTW89_DBG_CFO, 4668 "Msta cfo with tp_wgt=%d, avg_cfo=%d\n", 4669 cfo_khz_all_tp_wgt, cfo_avg); 4670 rtw89_debug(rtwdev, RTW89_DBG_CFO, "cfo_lb=%d,cfo_ub=%d\n", 4671 max_cfo_lb, min_cfo_ub); 4672 if (max_cfo_lb <= min_cfo_ub) { 4673 rtw89_debug(rtwdev, RTW89_DBG_CFO, 4674 "cfo win_size=%d\n", 4675 min_cfo_ub - max_cfo_lb); 4676 target_cfo = clamp(cfo_avg, max_cfo_lb, min_cfo_ub); 4677 } else { 4678 rtw89_debug(rtwdev, RTW89_DBG_CFO, 4679 "No intersection of cfo tolerance windows\n"); 4680 target_cfo = phy_div(cfo_khz_all, (s32)sta_cnt); 4681 } 4682 for (i = 0; i < CFO_TRACK_MAX_USER; i++) 4683 cfo->pre_cfo_avg[i] = cfo->cfo_avg[i]; 4684 } 4685 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Target cfo=%d\n", target_cfo); 4686 return target_cfo; 4687 } 4688 4689 static void rtw89_phy_cfo_statistics_reset(struct rtw89_dev *rtwdev) 4690 { 4691 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 4692 4693 memset(&cfo->cfo_tail, 0, sizeof(cfo->cfo_tail)); 4694 memset(&cfo->cfo_cnt, 0, sizeof(cfo->cfo_cnt)); 4695 cfo->packet_count = 0; 4696 cfo->packet_count_pre = 0; 4697 cfo->cfo_avg_pre = 0; 4698 } 4699 4700 static void rtw89_phy_cfo_dm(struct rtw89_dev *rtwdev) 4701 { 4702 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 4703 s32 new_cfo = 0; 4704 bool x_cap_update = false; 4705 u8 pre_x_cap = cfo->crystal_cap; 4706 u8 dcfo_comp_sft = rtwdev->chip->dcfo_comp_sft; 4707 4708 cfo->dcfo_avg = 0; 4709 rtw89_debug(rtwdev, RTW89_DBG_CFO, "CFO:total_sta_assoc=%d\n", 4710 rtwdev->total_sta_assoc); 4711 if (rtwdev->total_sta_assoc == 0 || rtw89_is_mlo_1_1(rtwdev)) { 4712 rtw89_phy_cfo_reset(rtwdev); 4713 return; 4714 } 4715 if (cfo->packet_count == 0) { 4716 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt cnt = 0\n"); 4717 return; 4718 } 4719 if (cfo->packet_count == cfo->packet_count_pre) { 4720 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt cnt doesn't change\n"); 4721 return; 4722 } 4723 if (rtwdev->total_sta_assoc == 1) 4724 new_cfo = rtw89_phy_average_cfo_calc(rtwdev); 4725 else 4726 new_cfo = rtw89_phy_multi_sta_cfo_calc(rtwdev); 4727 if (cfo->divergence_lock_en) { 4728 cfo->lock_cnt++; 4729 if (cfo->lock_cnt > CFO_PERIOD_CNT) { 4730 cfo->divergence_lock_en = false; 4731 cfo->lock_cnt = 0; 4732 } else { 4733 rtw89_phy_cfo_reset(rtwdev); 4734 } 4735 return; 4736 } 4737 if (cfo->crystal_cap >= cfo->x_cap_ub || 4738 cfo->crystal_cap <= cfo->x_cap_lb) { 4739 cfo->divergence_lock_en = true; 4740 rtw89_phy_cfo_reset(rtwdev); 4741 return; 4742 } 4743 4744 rtw89_phy_cfo_crystal_cap_adjust(rtwdev, new_cfo); 4745 cfo->cfo_avg_pre = new_cfo; 4746 cfo->dcfo_avg_pre = cfo->dcfo_avg; 4747 x_cap_update = cfo->crystal_cap != pre_x_cap; 4748 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Xcap_up=%d\n", x_cap_update); 4749 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Xcap: D:%x C:%x->%x, ofst=%d\n", 4750 cfo->def_x_cap, pre_x_cap, cfo->crystal_cap, 4751 cfo->x_cap_ofst); 4752 if (x_cap_update) { 4753 if (cfo->dcfo_avg > 0) 4754 cfo->dcfo_avg -= CFO_SW_COMP_FINE_TUNE << dcfo_comp_sft; 4755 else 4756 cfo->dcfo_avg += CFO_SW_COMP_FINE_TUNE << dcfo_comp_sft; 4757 } 4758 rtw89_dcfo_comp(rtwdev, cfo->dcfo_avg); 4759 rtw89_phy_cfo_statistics_reset(rtwdev); 4760 } 4761 4762 void rtw89_phy_cfo_track_work(struct wiphy *wiphy, struct wiphy_work *work) 4763 { 4764 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 4765 cfo_track_work.work); 4766 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 4767 4768 lockdep_assert_wiphy(wiphy); 4769 4770 if (!cfo->cfo_trig_by_timer_en) 4771 return; 4772 rtw89_leave_ps_mode(rtwdev); 4773 rtw89_phy_cfo_dm(rtwdev); 4774 wiphy_delayed_work_queue(wiphy, &rtwdev->cfo_track_work, 4775 msecs_to_jiffies(cfo->cfo_timer_ms)); 4776 } 4777 4778 static void rtw89_phy_cfo_start_work(struct rtw89_dev *rtwdev) 4779 { 4780 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 4781 4782 wiphy_delayed_work_queue(rtwdev->hw->wiphy, &rtwdev->cfo_track_work, 4783 msecs_to_jiffies(cfo->cfo_timer_ms)); 4784 } 4785 4786 void rtw89_phy_cfo_track(struct rtw89_dev *rtwdev) 4787 { 4788 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 4789 struct rtw89_traffic_stats *stats = &rtwdev->stats; 4790 bool is_ul_ofdma = false, ofdma_acc_en = false; 4791 4792 if (stats->rx_tf_periodic > CFO_TF_CNT_TH) 4793 is_ul_ofdma = true; 4794 if (cfo->cfo_ul_ofdma_acc_mode == RTW89_CFO_UL_OFDMA_ACC_ENABLE && 4795 is_ul_ofdma) 4796 ofdma_acc_en = true; 4797 4798 switch (cfo->phy_cfo_status) { 4799 case RTW89_PHY_DCFO_STATE_NORMAL: 4800 if (stats->tx_throughput >= CFO_TP_UPPER) { 4801 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_ENHANCE; 4802 cfo->cfo_trig_by_timer_en = true; 4803 cfo->cfo_timer_ms = CFO_COMP_PERIOD; 4804 rtw89_phy_cfo_start_work(rtwdev); 4805 } 4806 break; 4807 case RTW89_PHY_DCFO_STATE_ENHANCE: 4808 if (stats->tx_throughput <= CFO_TP_LOWER) 4809 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL; 4810 else if (ofdma_acc_en && 4811 cfo->phy_cfo_trk_cnt >= CFO_PERIOD_CNT) 4812 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_HOLD; 4813 else 4814 cfo->phy_cfo_trk_cnt++; 4815 4816 if (cfo->phy_cfo_status == RTW89_PHY_DCFO_STATE_NORMAL) { 4817 cfo->phy_cfo_trk_cnt = 0; 4818 cfo->cfo_trig_by_timer_en = false; 4819 } 4820 break; 4821 case RTW89_PHY_DCFO_STATE_HOLD: 4822 if (stats->tx_throughput <= CFO_TP_LOWER) { 4823 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL; 4824 cfo->phy_cfo_trk_cnt = 0; 4825 cfo->cfo_trig_by_timer_en = false; 4826 } else { 4827 cfo->phy_cfo_trk_cnt++; 4828 } 4829 break; 4830 default: 4831 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL; 4832 cfo->phy_cfo_trk_cnt = 0; 4833 break; 4834 } 4835 rtw89_debug(rtwdev, RTW89_DBG_CFO, 4836 "[CFO]WatchDog tp=%d,state=%d,timer_en=%d,trk_cnt=%d,thermal=%ld\n", 4837 stats->tx_throughput, cfo->phy_cfo_status, 4838 cfo->cfo_trig_by_timer_en, cfo->phy_cfo_trk_cnt, 4839 ewma_thermal_read(&rtwdev->phystat.avg_thermal[0])); 4840 if (cfo->cfo_trig_by_timer_en) 4841 return; 4842 rtw89_phy_cfo_dm(rtwdev); 4843 } 4844 4845 void rtw89_phy_cfo_parse(struct rtw89_dev *rtwdev, s16 cfo_val, 4846 struct rtw89_rx_phy_ppdu *phy_ppdu) 4847 { 4848 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 4849 u8 macid = phy_ppdu->mac_id; 4850 4851 if (macid >= CFO_TRACK_MAX_USER) { 4852 rtw89_warn(rtwdev, "mac_id %d is out of range\n", macid); 4853 return; 4854 } 4855 4856 cfo->cfo_tail[macid] += cfo_val; 4857 cfo->cfo_cnt[macid]++; 4858 cfo->packet_count++; 4859 } 4860 4861 void rtw89_phy_ul_tb_assoc(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link) 4862 { 4863 const struct rtw89_chip_info *chip = rtwdev->chip; 4864 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, 4865 rtwvif_link->chanctx_idx); 4866 struct rtw89_phy_ul_tb_info *ul_tb_info = &rtwdev->ul_tb_info; 4867 4868 if (!chip->ul_tb_waveform_ctrl) 4869 return; 4870 4871 rtwvif_link->def_tri_idx = 4872 rtw89_phy_read32_mask(rtwdev, R_DCFO_OPT, B_TXSHAPE_TRIANGULAR_CFG); 4873 4874 if (chip->chip_id == RTL8852B && rtwdev->hal.cv > CHIP_CBV) 4875 rtwvif_link->dyn_tb_bedge_en = false; 4876 else if (chan->band_type >= RTW89_BAND_5G && 4877 chan->band_width >= RTW89_CHANNEL_WIDTH_40) 4878 rtwvif_link->dyn_tb_bedge_en = true; 4879 else 4880 rtwvif_link->dyn_tb_bedge_en = false; 4881 4882 rtw89_debug(rtwdev, RTW89_DBG_UL_TB, 4883 "[ULTB] def_if_bandedge=%d, def_tri_idx=%d\n", 4884 ul_tb_info->def_if_bandedge, rtwvif_link->def_tri_idx); 4885 rtw89_debug(rtwdev, RTW89_DBG_UL_TB, 4886 "[ULTB] dyn_tb_begde_en=%d, dyn_tb_tri_en=%d\n", 4887 rtwvif_link->dyn_tb_bedge_en, ul_tb_info->dyn_tb_tri_en); 4888 } 4889 4890 struct rtw89_phy_ul_tb_check_data { 4891 bool valid; 4892 bool high_tf_client; 4893 bool low_tf_client; 4894 bool dyn_tb_bedge_en; 4895 u8 def_tri_idx; 4896 }; 4897 4898 struct rtw89_phy_power_diff { 4899 u32 q_00; 4900 u32 q_11; 4901 u32 q_matrix_en; 4902 u32 ultb_1t_norm_160; 4903 u32 ultb_2t_norm_160; 4904 u32 com1_norm_1sts; 4905 u32 com2_resp_1sts_path; 4906 }; 4907 4908 static void rtw89_phy_ofdma_power_diff(struct rtw89_dev *rtwdev, 4909 struct rtw89_vif_link *rtwvif_link) 4910 { 4911 static const struct rtw89_phy_power_diff table[2] = { 4912 {0x0, 0x0, 0x0, 0x0, 0xf4, 0x3, 0x3}, 4913 {0xb50, 0xb50, 0x1, 0xc, 0x0, 0x1, 0x1}, 4914 }; 4915 const struct rtw89_phy_power_diff *param; 4916 u32 reg; 4917 4918 if (!rtwdev->chip->ul_tb_pwr_diff) 4919 return; 4920 4921 if (rtwvif_link->pwr_diff_en == rtwvif_link->pre_pwr_diff_en) { 4922 rtwvif_link->pwr_diff_en = false; 4923 return; 4924 } 4925 4926 rtwvif_link->pre_pwr_diff_en = rtwvif_link->pwr_diff_en; 4927 param = &table[rtwvif_link->pwr_diff_en]; 4928 4929 rtw89_phy_write32_mask(rtwdev, R_Q_MATRIX_00, B_Q_MATRIX_00_REAL, 4930 param->q_00); 4931 rtw89_phy_write32_mask(rtwdev, R_Q_MATRIX_11, B_Q_MATRIX_11_REAL, 4932 param->q_11); 4933 rtw89_phy_write32_mask(rtwdev, R_CUSTOMIZE_Q_MATRIX, 4934 B_CUSTOMIZE_Q_MATRIX_EN, param->q_matrix_en); 4935 4936 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_1T, rtwvif_link->mac_idx); 4937 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_1T_NORM_BW160, 4938 param->ultb_1t_norm_160); 4939 4940 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_2T, rtwvif_link->mac_idx); 4941 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_2T_NORM_BW160, 4942 param->ultb_2t_norm_160); 4943 4944 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PATH_COM1, rtwvif_link->mac_idx); 4945 rtw89_write32_mask(rtwdev, reg, B_AX_PATH_COM1_NORM_1STS, 4946 param->com1_norm_1sts); 4947 4948 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PATH_COM2, rtwvif_link->mac_idx); 4949 rtw89_write32_mask(rtwdev, reg, B_AX_PATH_COM2_RESP_1STS_PATH, 4950 param->com2_resp_1sts_path); 4951 } 4952 4953 static 4954 void rtw89_phy_ul_tb_ctrl_check(struct rtw89_dev *rtwdev, 4955 struct rtw89_vif_link *rtwvif_link, 4956 struct rtw89_phy_ul_tb_check_data *ul_tb_data) 4957 { 4958 struct rtw89_traffic_stats *stats = &rtwdev->stats; 4959 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 4960 4961 if (rtwvif_link->wifi_role != RTW89_WIFI_ROLE_STATION) 4962 return; 4963 4964 if (!vif->cfg.assoc) 4965 return; 4966 4967 if (rtwdev->chip->ul_tb_waveform_ctrl) { 4968 if (stats->rx_tf_periodic > UL_TB_TF_CNT_L2H_TH) 4969 ul_tb_data->high_tf_client = true; 4970 else if (stats->rx_tf_periodic < UL_TB_TF_CNT_H2L_TH) 4971 ul_tb_data->low_tf_client = true; 4972 4973 ul_tb_data->valid = true; 4974 ul_tb_data->def_tri_idx = rtwvif_link->def_tri_idx; 4975 ul_tb_data->dyn_tb_bedge_en = rtwvif_link->dyn_tb_bedge_en; 4976 } 4977 4978 rtw89_phy_ofdma_power_diff(rtwdev, rtwvif_link); 4979 } 4980 4981 static void rtw89_phy_ul_tb_waveform_ctrl(struct rtw89_dev *rtwdev, 4982 struct rtw89_phy_ul_tb_check_data *ul_tb_data) 4983 { 4984 struct rtw89_phy_ul_tb_info *ul_tb_info = &rtwdev->ul_tb_info; 4985 4986 if (!rtwdev->chip->ul_tb_waveform_ctrl) 4987 return; 4988 4989 if (ul_tb_data->dyn_tb_bedge_en) { 4990 if (ul_tb_data->high_tf_client) { 4991 rtw89_phy_write32_mask(rtwdev, R_BANDEDGE, B_BANDEDGE_EN, 0); 4992 rtw89_debug(rtwdev, RTW89_DBG_UL_TB, 4993 "[ULTB] Turn off if_bandedge\n"); 4994 } else if (ul_tb_data->low_tf_client) { 4995 rtw89_phy_write32_mask(rtwdev, R_BANDEDGE, B_BANDEDGE_EN, 4996 ul_tb_info->def_if_bandedge); 4997 rtw89_debug(rtwdev, RTW89_DBG_UL_TB, 4998 "[ULTB] Set to default if_bandedge = %d\n", 4999 ul_tb_info->def_if_bandedge); 5000 } 5001 } 5002 5003 if (ul_tb_info->dyn_tb_tri_en) { 5004 if (ul_tb_data->high_tf_client) { 5005 rtw89_phy_write32_mask(rtwdev, R_DCFO_OPT, 5006 B_TXSHAPE_TRIANGULAR_CFG, 0); 5007 rtw89_debug(rtwdev, RTW89_DBG_UL_TB, 5008 "[ULTB] Turn off Tx triangle\n"); 5009 } else if (ul_tb_data->low_tf_client) { 5010 rtw89_phy_write32_mask(rtwdev, R_DCFO_OPT, 5011 B_TXSHAPE_TRIANGULAR_CFG, 5012 ul_tb_data->def_tri_idx); 5013 rtw89_debug(rtwdev, RTW89_DBG_UL_TB, 5014 "[ULTB] Set to default tx_shap_idx = %d\n", 5015 ul_tb_data->def_tri_idx); 5016 } 5017 } 5018 } 5019 5020 void rtw89_phy_ul_tb_ctrl_track(struct rtw89_dev *rtwdev) 5021 { 5022 const struct rtw89_chip_info *chip = rtwdev->chip; 5023 struct rtw89_phy_ul_tb_check_data ul_tb_data = {}; 5024 struct rtw89_vif_link *rtwvif_link; 5025 struct rtw89_vif *rtwvif; 5026 unsigned int link_id; 5027 5028 if (!chip->ul_tb_waveform_ctrl && !chip->ul_tb_pwr_diff) 5029 return; 5030 5031 if (rtwdev->total_sta_assoc != 1) 5032 return; 5033 5034 rtw89_for_each_rtwvif(rtwdev, rtwvif) 5035 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) 5036 rtw89_phy_ul_tb_ctrl_check(rtwdev, rtwvif_link, &ul_tb_data); 5037 5038 if (!ul_tb_data.valid) 5039 return; 5040 5041 rtw89_phy_ul_tb_waveform_ctrl(rtwdev, &ul_tb_data); 5042 } 5043 5044 static void rtw89_phy_ul_tb_info_init(struct rtw89_dev *rtwdev) 5045 { 5046 const struct rtw89_chip_info *chip = rtwdev->chip; 5047 struct rtw89_phy_ul_tb_info *ul_tb_info = &rtwdev->ul_tb_info; 5048 5049 if (!chip->ul_tb_waveform_ctrl) 5050 return; 5051 5052 ul_tb_info->dyn_tb_tri_en = true; 5053 ul_tb_info->def_if_bandedge = 5054 rtw89_phy_read32_mask(rtwdev, R_BANDEDGE, B_BANDEDGE_EN); 5055 } 5056 5057 static 5058 void rtw89_phy_antdiv_sts_instance_reset(struct rtw89_antdiv_stats *antdiv_sts) 5059 { 5060 ewma_rssi_init(&antdiv_sts->cck_rssi_avg); 5061 ewma_rssi_init(&antdiv_sts->ofdm_rssi_avg); 5062 ewma_rssi_init(&antdiv_sts->non_legacy_rssi_avg); 5063 antdiv_sts->pkt_cnt_cck = 0; 5064 antdiv_sts->pkt_cnt_ofdm = 0; 5065 antdiv_sts->pkt_cnt_non_legacy = 0; 5066 antdiv_sts->evm = 0; 5067 } 5068 5069 static void rtw89_phy_antdiv_sts_instance_add(struct rtw89_dev *rtwdev, 5070 struct rtw89_rx_phy_ppdu *phy_ppdu, 5071 struct rtw89_antdiv_stats *stats) 5072 { 5073 if (rtw89_get_data_rate_mode(rtwdev, phy_ppdu->rate) == DATA_RATE_MODE_NON_HT) { 5074 if (phy_ppdu->rate < RTW89_HW_RATE_OFDM6) { 5075 ewma_rssi_add(&stats->cck_rssi_avg, phy_ppdu->rssi_avg); 5076 stats->pkt_cnt_cck++; 5077 } else { 5078 ewma_rssi_add(&stats->ofdm_rssi_avg, phy_ppdu->rssi_avg); 5079 stats->pkt_cnt_ofdm++; 5080 stats->evm += phy_ppdu->ofdm.evm_min; 5081 } 5082 } else { 5083 ewma_rssi_add(&stats->non_legacy_rssi_avg, phy_ppdu->rssi_avg); 5084 stats->pkt_cnt_non_legacy++; 5085 stats->evm += phy_ppdu->ofdm.evm_min; 5086 } 5087 } 5088 5089 static u8 rtw89_phy_antdiv_sts_instance_get_rssi(struct rtw89_antdiv_stats *stats) 5090 { 5091 if (stats->pkt_cnt_non_legacy >= stats->pkt_cnt_cck && 5092 stats->pkt_cnt_non_legacy >= stats->pkt_cnt_ofdm) 5093 return ewma_rssi_read(&stats->non_legacy_rssi_avg); 5094 else if (stats->pkt_cnt_ofdm >= stats->pkt_cnt_cck && 5095 stats->pkt_cnt_ofdm >= stats->pkt_cnt_non_legacy) 5096 return ewma_rssi_read(&stats->ofdm_rssi_avg); 5097 else 5098 return ewma_rssi_read(&stats->cck_rssi_avg); 5099 } 5100 5101 static u8 rtw89_phy_antdiv_sts_instance_get_evm(struct rtw89_antdiv_stats *stats) 5102 { 5103 return phy_div(stats->evm, stats->pkt_cnt_non_legacy + stats->pkt_cnt_ofdm); 5104 } 5105 5106 void rtw89_phy_antdiv_parse(struct rtw89_dev *rtwdev, 5107 struct rtw89_rx_phy_ppdu *phy_ppdu) 5108 { 5109 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv; 5110 struct rtw89_hal *hal = &rtwdev->hal; 5111 5112 if (!hal->ant_diversity || hal->ant_diversity_fixed) 5113 return; 5114 5115 rtw89_phy_antdiv_sts_instance_add(rtwdev, phy_ppdu, &antdiv->target_stats); 5116 5117 if (!antdiv->get_stats) 5118 return; 5119 5120 if (hal->antenna_rx == RF_A) 5121 rtw89_phy_antdiv_sts_instance_add(rtwdev, phy_ppdu, &antdiv->main_stats); 5122 else if (hal->antenna_rx == RF_B) 5123 rtw89_phy_antdiv_sts_instance_add(rtwdev, phy_ppdu, &antdiv->aux_stats); 5124 } 5125 5126 static void rtw89_phy_antdiv_reg_init(struct rtw89_dev *rtwdev) 5127 { 5128 rtw89_phy_write32_idx(rtwdev, R_P0_TRSW, B_P0_ANT_TRAIN_EN, 5129 0x0, RTW89_PHY_0); 5130 rtw89_phy_write32_idx(rtwdev, R_P0_TRSW, B_P0_TX_ANT_SEL, 5131 0x0, RTW89_PHY_0); 5132 5133 rtw89_phy_write32_idx(rtwdev, R_P0_ANT_SW, B_P0_TRSW_TX_EXTEND, 5134 0x0, RTW89_PHY_0); 5135 rtw89_phy_write32_idx(rtwdev, R_P0_ANT_SW, B_P0_HW_ANTSW_DIS_BY_GNT_BT, 5136 0x0, RTW89_PHY_0); 5137 5138 rtw89_phy_write32_idx(rtwdev, R_P0_TRSW, B_P0_BT_FORCE_ANTIDX_EN, 5139 0x0, RTW89_PHY_0); 5140 5141 rtw89_phy_write32_idx(rtwdev, R_RFSW_CTRL_ANT0_BASE, B_RFSW_CTRL_ANT_MAPPING, 5142 0x0100, RTW89_PHY_0); 5143 5144 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_BTG_TRX, 5145 0x1, RTW89_PHY_0); 5146 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_HW_CTRL, 5147 0x0, RTW89_PHY_0); 5148 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_SW_2G, 5149 0x0, RTW89_PHY_0); 5150 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_SW_5G, 5151 0x0, RTW89_PHY_0); 5152 } 5153 5154 static void rtw89_phy_antdiv_sts_reset(struct rtw89_dev *rtwdev) 5155 { 5156 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv; 5157 5158 rtw89_phy_antdiv_sts_instance_reset(&antdiv->target_stats); 5159 rtw89_phy_antdiv_sts_instance_reset(&antdiv->main_stats); 5160 rtw89_phy_antdiv_sts_instance_reset(&antdiv->aux_stats); 5161 } 5162 5163 static void rtw89_phy_antdiv_init(struct rtw89_dev *rtwdev) 5164 { 5165 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv; 5166 struct rtw89_hal *hal = &rtwdev->hal; 5167 5168 if (!hal->ant_diversity) 5169 return; 5170 5171 antdiv->get_stats = false; 5172 antdiv->rssi_pre = 0; 5173 rtw89_phy_antdiv_sts_reset(rtwdev); 5174 rtw89_phy_antdiv_reg_init(rtwdev); 5175 } 5176 5177 static void rtw89_phy_thermal_protect(struct rtw89_dev *rtwdev) 5178 { 5179 struct rtw89_phy_stat *phystat = &rtwdev->phystat; 5180 struct rtw89_hal *hal = &rtwdev->hal; 5181 u8 th_max = phystat->last_thermal_max; 5182 u8 lv = hal->thermal_prot_lv; 5183 5184 if (!hal->thermal_prot_th || 5185 (hal->disabled_dm_bitmap & BIT(RTW89_DM_THERMAL_PROTECT))) 5186 return; 5187 5188 if (th_max > hal->thermal_prot_th && lv < RTW89_THERMAL_PROT_LV_MAX) 5189 lv++; 5190 else if (th_max < hal->thermal_prot_th - 2 && lv > 0) 5191 lv--; 5192 else 5193 return; 5194 5195 hal->thermal_prot_lv = lv; 5196 5197 rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK, "thermal protection lv=%d\n", lv); 5198 5199 rtw89_fw_h2c_tx_duty(rtwdev, hal->thermal_prot_lv); 5200 } 5201 5202 static void rtw89_phy_stat_thermal_update(struct rtw89_dev *rtwdev) 5203 { 5204 struct rtw89_phy_stat *phystat = &rtwdev->phystat; 5205 u8 th, th_max = 0; 5206 int i; 5207 5208 for (i = 0; i < rtwdev->chip->rf_path_num; i++) { 5209 th = rtw89_chip_get_thermal(rtwdev, i); 5210 if (th) 5211 ewma_thermal_add(&phystat->avg_thermal[i], th); 5212 5213 rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK, 5214 "path(%d) thermal cur=%u avg=%ld", i, th, 5215 ewma_thermal_read(&phystat->avg_thermal[i])); 5216 5217 th_max = max(th_max, th); 5218 } 5219 5220 phystat->last_thermal_max = th_max; 5221 } 5222 5223 struct rtw89_phy_iter_rssi_data { 5224 struct rtw89_dev *rtwdev; 5225 bool rssi_changed; 5226 }; 5227 5228 static 5229 void __rtw89_phy_stat_rssi_update_iter(struct rtw89_sta_link *rtwsta_link, 5230 struct rtw89_phy_iter_rssi_data *rssi_data) 5231 { 5232 struct rtw89_vif_link *rtwvif_link = rtwsta_link->rtwvif_link; 5233 struct rtw89_dev *rtwdev = rssi_data->rtwdev; 5234 struct rtw89_phy_ch_info *ch_info; 5235 struct rtw89_bb_ctx *bb; 5236 unsigned long rssi_curr; 5237 5238 rssi_curr = ewma_rssi_read(&rtwsta_link->avg_rssi); 5239 bb = rtw89_get_bb_ctx(rtwdev, rtwvif_link->phy_idx); 5240 ch_info = &bb->ch_info; 5241 5242 if (rssi_curr < ch_info->rssi_min) { 5243 ch_info->rssi_min = rssi_curr; 5244 ch_info->rssi_min_macid = rtwsta_link->mac_id; 5245 } 5246 5247 if (rtwsta_link->prev_rssi == 0) { 5248 rtwsta_link->prev_rssi = rssi_curr; 5249 } else if (abs((int)rtwsta_link->prev_rssi - (int)rssi_curr) > 5250 (3 << RSSI_FACTOR)) { 5251 rtwsta_link->prev_rssi = rssi_curr; 5252 rssi_data->rssi_changed = true; 5253 } 5254 } 5255 5256 static void rtw89_phy_stat_rssi_update_iter(void *data, 5257 struct ieee80211_sta *sta) 5258 { 5259 struct rtw89_phy_iter_rssi_data *rssi_data = 5260 (struct rtw89_phy_iter_rssi_data *)data; 5261 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta); 5262 struct rtw89_sta_link *rtwsta_link; 5263 unsigned int link_id; 5264 5265 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) 5266 __rtw89_phy_stat_rssi_update_iter(rtwsta_link, rssi_data); 5267 } 5268 5269 static void rtw89_phy_stat_rssi_update(struct rtw89_dev *rtwdev) 5270 { 5271 struct rtw89_phy_iter_rssi_data rssi_data = {}; 5272 struct rtw89_bb_ctx *bb; 5273 5274 rssi_data.rtwdev = rtwdev; 5275 rtw89_for_each_active_bb(rtwdev, bb) 5276 bb->ch_info.rssi_min = U8_MAX; 5277 5278 ieee80211_iterate_stations_atomic(rtwdev->hw, 5279 rtw89_phy_stat_rssi_update_iter, 5280 &rssi_data); 5281 if (rssi_data.rssi_changed) 5282 rtw89_btc_ntfy_wl_sta(rtwdev); 5283 } 5284 5285 static void rtw89_phy_stat_init(struct rtw89_dev *rtwdev) 5286 { 5287 struct rtw89_phy_stat *phystat = &rtwdev->phystat; 5288 int i; 5289 5290 for (i = 0; i < rtwdev->chip->rf_path_num; i++) 5291 ewma_thermal_init(&phystat->avg_thermal[i]); 5292 5293 rtw89_phy_stat_thermal_update(rtwdev); 5294 5295 memset(&phystat->cur_pkt_stat, 0, sizeof(phystat->cur_pkt_stat)); 5296 memset(&phystat->last_pkt_stat, 0, sizeof(phystat->last_pkt_stat)); 5297 5298 ewma_rssi_init(&phystat->bcn_rssi); 5299 5300 rtwdev->hal.thermal_prot_lv = 0; 5301 } 5302 5303 void rtw89_phy_stat_track(struct rtw89_dev *rtwdev) 5304 { 5305 struct rtw89_phy_stat *phystat = &rtwdev->phystat; 5306 5307 rtw89_phy_stat_thermal_update(rtwdev); 5308 rtw89_phy_thermal_protect(rtwdev); 5309 rtw89_phy_stat_rssi_update(rtwdev); 5310 5311 phystat->last_pkt_stat = phystat->cur_pkt_stat; 5312 memset(&phystat->cur_pkt_stat, 0, sizeof(phystat->cur_pkt_stat)); 5313 } 5314 5315 static u16 rtw89_phy_ccx_us_to_idx(struct rtw89_dev *rtwdev, 5316 struct rtw89_bb_ctx *bb, u32 time_us) 5317 { 5318 struct rtw89_env_monitor_info *env = &bb->env_monitor; 5319 5320 return time_us >> (ilog2(CCX_US_BASE_RATIO) + env->ccx_unit_idx); 5321 } 5322 5323 static u32 rtw89_phy_ccx_idx_to_us(struct rtw89_dev *rtwdev, 5324 struct rtw89_bb_ctx *bb, u16 idx) 5325 { 5326 struct rtw89_env_monitor_info *env = &bb->env_monitor; 5327 5328 return idx << (ilog2(CCX_US_BASE_RATIO) + env->ccx_unit_idx); 5329 } 5330 5331 static void rtw89_phy_ccx_top_setting_init(struct rtw89_dev *rtwdev, 5332 struct rtw89_bb_ctx *bb) 5333 { 5334 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 5335 struct rtw89_env_monitor_info *env = &bb->env_monitor; 5336 const struct rtw89_ccx_regs *ccx = phy->ccx; 5337 5338 env->ccx_manual_ctrl = false; 5339 env->ccx_ongoing = false; 5340 env->ccx_rac_lv = RTW89_RAC_RELEASE; 5341 env->ccx_period = 0; 5342 env->ccx_unit_idx = RTW89_CCX_32_US; 5343 5344 rtw89_phy_write32_idx(rtwdev, ccx->setting_addr, ccx->en_mask, 1, bb->phy_idx); 5345 rtw89_phy_write32_idx(rtwdev, ccx->setting_addr, ccx->trig_opt_mask, 1, 5346 bb->phy_idx); 5347 rtw89_phy_write32_idx(rtwdev, ccx->setting_addr, ccx->measurement_trig_mask, 1, 5348 bb->phy_idx); 5349 rtw89_phy_write32_idx(rtwdev, ccx->setting_addr, ccx->edcca_opt_mask, 5350 RTW89_CCX_EDCCA_BW20_0, bb->phy_idx); 5351 } 5352 5353 static u16 rtw89_phy_ccx_get_report(struct rtw89_dev *rtwdev, 5354 struct rtw89_bb_ctx *bb, 5355 u16 report, u16 score) 5356 { 5357 struct rtw89_env_monitor_info *env = &bb->env_monitor; 5358 u32 numer = 0; 5359 u16 ret = 0; 5360 5361 numer = report * score + (env->ccx_period >> 1); 5362 if (env->ccx_period) 5363 ret = numer / env->ccx_period; 5364 5365 return ret >= score ? score - 1 : ret; 5366 } 5367 5368 static void rtw89_phy_ccx_ms_to_period_unit(struct rtw89_dev *rtwdev, 5369 u16 time_ms, u32 *period, 5370 u32 *unit_idx) 5371 { 5372 u32 idx; 5373 u8 quotient; 5374 5375 if (time_ms >= CCX_MAX_PERIOD) 5376 time_ms = CCX_MAX_PERIOD; 5377 5378 quotient = CCX_MAX_PERIOD_UNIT * time_ms / CCX_MAX_PERIOD; 5379 5380 if (quotient < 4) 5381 idx = RTW89_CCX_4_US; 5382 else if (quotient < 8) 5383 idx = RTW89_CCX_8_US; 5384 else if (quotient < 16) 5385 idx = RTW89_CCX_16_US; 5386 else 5387 idx = RTW89_CCX_32_US; 5388 5389 *unit_idx = idx; 5390 *period = (time_ms * MS_TO_4US_RATIO) >> idx; 5391 5392 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 5393 "[Trigger Time] period:%d, unit_idx:%d\n", 5394 *period, *unit_idx); 5395 } 5396 5397 static void rtw89_phy_ccx_racing_release(struct rtw89_dev *rtwdev, 5398 struct rtw89_bb_ctx *bb) 5399 { 5400 struct rtw89_env_monitor_info *env = &bb->env_monitor; 5401 5402 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 5403 "lv:(%d)->(0)\n", env->ccx_rac_lv); 5404 5405 env->ccx_ongoing = false; 5406 env->ccx_rac_lv = RTW89_RAC_RELEASE; 5407 env->ifs_clm_app = RTW89_IFS_CLM_BACKGROUND; 5408 } 5409 5410 static bool rtw89_phy_ifs_clm_th_update_check(struct rtw89_dev *rtwdev, 5411 struct rtw89_bb_ctx *bb, 5412 struct rtw89_ccx_para_info *para) 5413 { 5414 struct rtw89_env_monitor_info *env = &bb->env_monitor; 5415 bool is_update = env->ifs_clm_app != para->ifs_clm_app; 5416 u8 i = 0; 5417 u16 *ifs_th_l = env->ifs_clm_th_l; 5418 u16 *ifs_th_h = env->ifs_clm_th_h; 5419 u32 ifs_th0_us = 0, ifs_th_times = 0; 5420 u32 ifs_th_h_us[RTW89_IFS_CLM_NUM] = {0}; 5421 5422 if (!is_update) 5423 goto ifs_update_finished; 5424 5425 switch (para->ifs_clm_app) { 5426 case RTW89_IFS_CLM_INIT: 5427 case RTW89_IFS_CLM_BACKGROUND: 5428 case RTW89_IFS_CLM_ACS: 5429 case RTW89_IFS_CLM_DBG: 5430 case RTW89_IFS_CLM_DIG: 5431 case RTW89_IFS_CLM_TDMA_DIG: 5432 ifs_th0_us = IFS_CLM_TH0_UPPER; 5433 ifs_th_times = IFS_CLM_TH_MUL; 5434 break; 5435 case RTW89_IFS_CLM_DBG_MANUAL: 5436 ifs_th0_us = para->ifs_clm_manual_th0; 5437 ifs_th_times = para->ifs_clm_manual_th_times; 5438 break; 5439 default: 5440 break; 5441 } 5442 5443 /* Set sampling threshold for 4 different regions, unit in idx_cnt. 5444 * low[i] = high[i-1] + 1 5445 * high[i] = high[i-1] * ifs_th_times 5446 */ 5447 ifs_th_l[IFS_CLM_TH_START_IDX] = 0; 5448 ifs_th_h_us[IFS_CLM_TH_START_IDX] = ifs_th0_us; 5449 ifs_th_h[IFS_CLM_TH_START_IDX] = rtw89_phy_ccx_us_to_idx(rtwdev, bb, 5450 ifs_th0_us); 5451 for (i = 1; i < RTW89_IFS_CLM_NUM; i++) { 5452 ifs_th_l[i] = ifs_th_h[i - 1] + 1; 5453 ifs_th_h_us[i] = ifs_th_h_us[i - 1] * ifs_th_times; 5454 ifs_th_h[i] = rtw89_phy_ccx_us_to_idx(rtwdev, bb, ifs_th_h_us[i]); 5455 } 5456 5457 ifs_update_finished: 5458 if (!is_update) 5459 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 5460 "No need to update IFS_TH\n"); 5461 5462 return is_update; 5463 } 5464 5465 static void rtw89_phy_ifs_clm_set_th_reg(struct rtw89_dev *rtwdev, 5466 struct rtw89_bb_ctx *bb) 5467 { 5468 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 5469 struct rtw89_env_monitor_info *env = &bb->env_monitor; 5470 const struct rtw89_ccx_regs *ccx = phy->ccx; 5471 u8 i = 0; 5472 5473 rtw89_phy_write32_idx(rtwdev, ccx->ifs_t1_addr, ccx->ifs_t1_th_l_mask, 5474 env->ifs_clm_th_l[0], bb->phy_idx); 5475 rtw89_phy_write32_idx(rtwdev, ccx->ifs_t2_addr, ccx->ifs_t2_th_l_mask, 5476 env->ifs_clm_th_l[1], bb->phy_idx); 5477 rtw89_phy_write32_idx(rtwdev, ccx->ifs_t3_addr, ccx->ifs_t3_th_l_mask, 5478 env->ifs_clm_th_l[2], bb->phy_idx); 5479 rtw89_phy_write32_idx(rtwdev, ccx->ifs_t4_addr, ccx->ifs_t4_th_l_mask, 5480 env->ifs_clm_th_l[3], bb->phy_idx); 5481 5482 rtw89_phy_write32_idx(rtwdev, ccx->ifs_t1_addr, ccx->ifs_t1_th_h_mask, 5483 env->ifs_clm_th_h[0], bb->phy_idx); 5484 rtw89_phy_write32_idx(rtwdev, ccx->ifs_t2_addr, ccx->ifs_t2_th_h_mask, 5485 env->ifs_clm_th_h[1], bb->phy_idx); 5486 rtw89_phy_write32_idx(rtwdev, ccx->ifs_t3_addr, ccx->ifs_t3_th_h_mask, 5487 env->ifs_clm_th_h[2], bb->phy_idx); 5488 rtw89_phy_write32_idx(rtwdev, ccx->ifs_t4_addr, ccx->ifs_t4_th_h_mask, 5489 env->ifs_clm_th_h[3], bb->phy_idx); 5490 5491 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) 5492 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 5493 "Update IFS_T%d_th{low, high} : {%d, %d}\n", 5494 i + 1, env->ifs_clm_th_l[i], env->ifs_clm_th_h[i]); 5495 } 5496 5497 static void rtw89_phy_ifs_clm_setting_init(struct rtw89_dev *rtwdev, 5498 struct rtw89_bb_ctx *bb) 5499 { 5500 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 5501 struct rtw89_env_monitor_info *env = &bb->env_monitor; 5502 const struct rtw89_ccx_regs *ccx = phy->ccx; 5503 struct rtw89_ccx_para_info para = {}; 5504 5505 env->ifs_clm_app = RTW89_IFS_CLM_BACKGROUND; 5506 env->ifs_clm_mntr_time = 0; 5507 5508 para.ifs_clm_app = RTW89_IFS_CLM_INIT; 5509 if (rtw89_phy_ifs_clm_th_update_check(rtwdev, bb, ¶)) 5510 rtw89_phy_ifs_clm_set_th_reg(rtwdev, bb); 5511 5512 rtw89_phy_write32_idx(rtwdev, ccx->ifs_cnt_addr, ccx->ifs_collect_en_mask, true, 5513 bb->phy_idx); 5514 rtw89_phy_write32_idx(rtwdev, ccx->ifs_t1_addr, ccx->ifs_t1_en_mask, true, 5515 bb->phy_idx); 5516 rtw89_phy_write32_idx(rtwdev, ccx->ifs_t2_addr, ccx->ifs_t2_en_mask, true, 5517 bb->phy_idx); 5518 rtw89_phy_write32_idx(rtwdev, ccx->ifs_t3_addr, ccx->ifs_t3_en_mask, true, 5519 bb->phy_idx); 5520 rtw89_phy_write32_idx(rtwdev, ccx->ifs_t4_addr, ccx->ifs_t4_en_mask, true, 5521 bb->phy_idx); 5522 } 5523 5524 static int rtw89_phy_ccx_racing_ctrl(struct rtw89_dev *rtwdev, 5525 struct rtw89_bb_ctx *bb, 5526 enum rtw89_env_racing_lv level) 5527 { 5528 struct rtw89_env_monitor_info *env = &bb->env_monitor; 5529 int ret = 0; 5530 5531 if (level >= RTW89_RAC_MAX_NUM) { 5532 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 5533 "[WARNING] Wrong LV=%d\n", level); 5534 return -EINVAL; 5535 } 5536 5537 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 5538 "ccx_ongoing=%d, level:(%d)->(%d)\n", env->ccx_ongoing, 5539 env->ccx_rac_lv, level); 5540 5541 if (env->ccx_ongoing) { 5542 if (level <= env->ccx_rac_lv) 5543 ret = -EINVAL; 5544 else 5545 env->ccx_ongoing = false; 5546 } 5547 5548 if (ret == 0) 5549 env->ccx_rac_lv = level; 5550 5551 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "ccx racing success=%d\n", 5552 !ret); 5553 5554 return ret; 5555 } 5556 5557 static void rtw89_phy_ccx_trigger(struct rtw89_dev *rtwdev, 5558 struct rtw89_bb_ctx *bb) 5559 { 5560 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 5561 struct rtw89_env_monitor_info *env = &bb->env_monitor; 5562 const struct rtw89_ccx_regs *ccx = phy->ccx; 5563 5564 rtw89_phy_write32_idx(rtwdev, ccx->ifs_cnt_addr, ccx->ifs_clm_cnt_clear_mask, 0, 5565 bb->phy_idx); 5566 rtw89_phy_write32_idx(rtwdev, ccx->setting_addr, ccx->measurement_trig_mask, 0, 5567 bb->phy_idx); 5568 rtw89_phy_write32_idx(rtwdev, ccx->ifs_cnt_addr, ccx->ifs_clm_cnt_clear_mask, 1, 5569 bb->phy_idx); 5570 rtw89_phy_write32_idx(rtwdev, ccx->setting_addr, ccx->measurement_trig_mask, 1, 5571 bb->phy_idx); 5572 5573 env->ccx_ongoing = true; 5574 } 5575 5576 static void rtw89_phy_ifs_clm_get_utility(struct rtw89_dev *rtwdev, 5577 struct rtw89_bb_ctx *bb) 5578 { 5579 struct rtw89_env_monitor_info *env = &bb->env_monitor; 5580 u8 i = 0; 5581 u32 res = 0; 5582 5583 env->ifs_clm_tx_ratio = 5584 rtw89_phy_ccx_get_report(rtwdev, bb, env->ifs_clm_tx, PERCENT); 5585 env->ifs_clm_edcca_excl_cca_ratio = 5586 rtw89_phy_ccx_get_report(rtwdev, bb, env->ifs_clm_edcca_excl_cca, 5587 PERCENT); 5588 env->ifs_clm_cck_fa_ratio = 5589 rtw89_phy_ccx_get_report(rtwdev, bb, env->ifs_clm_cckfa, PERCENT); 5590 env->ifs_clm_ofdm_fa_ratio = 5591 rtw89_phy_ccx_get_report(rtwdev, bb, env->ifs_clm_ofdmfa, PERCENT); 5592 env->ifs_clm_cck_cca_excl_fa_ratio = 5593 rtw89_phy_ccx_get_report(rtwdev, bb, env->ifs_clm_cckcca_excl_fa, 5594 PERCENT); 5595 env->ifs_clm_ofdm_cca_excl_fa_ratio = 5596 rtw89_phy_ccx_get_report(rtwdev, bb, env->ifs_clm_ofdmcca_excl_fa, 5597 PERCENT); 5598 env->ifs_clm_cck_fa_permil = 5599 rtw89_phy_ccx_get_report(rtwdev, bb, env->ifs_clm_cckfa, PERMIL); 5600 env->ifs_clm_ofdm_fa_permil = 5601 rtw89_phy_ccx_get_report(rtwdev, bb, env->ifs_clm_ofdmfa, PERMIL); 5602 5603 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) { 5604 if (env->ifs_clm_his[i] > ENV_MNTR_IFSCLM_HIS_MAX) { 5605 env->ifs_clm_ifs_avg[i] = ENV_MNTR_FAIL_DWORD; 5606 } else { 5607 env->ifs_clm_ifs_avg[i] = 5608 rtw89_phy_ccx_idx_to_us(rtwdev, bb, 5609 env->ifs_clm_avg[i]); 5610 } 5611 5612 res = rtw89_phy_ccx_idx_to_us(rtwdev, bb, env->ifs_clm_cca[i]); 5613 res += env->ifs_clm_his[i] >> 1; 5614 if (env->ifs_clm_his[i]) 5615 res /= env->ifs_clm_his[i]; 5616 else 5617 res = 0; 5618 env->ifs_clm_cca_avg[i] = res; 5619 } 5620 5621 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 5622 "IFS-CLM ratio {Tx, EDCCA_exclu_cca} = {%d, %d}\n", 5623 env->ifs_clm_tx_ratio, env->ifs_clm_edcca_excl_cca_ratio); 5624 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 5625 "IFS-CLM FA ratio {CCK, OFDM} = {%d, %d}\n", 5626 env->ifs_clm_cck_fa_ratio, env->ifs_clm_ofdm_fa_ratio); 5627 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 5628 "IFS-CLM FA permil {CCK, OFDM} = {%d, %d}\n", 5629 env->ifs_clm_cck_fa_permil, env->ifs_clm_ofdm_fa_permil); 5630 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 5631 "IFS-CLM CCA_exclu_FA ratio {CCK, OFDM} = {%d, %d}\n", 5632 env->ifs_clm_cck_cca_excl_fa_ratio, 5633 env->ifs_clm_ofdm_cca_excl_fa_ratio); 5634 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 5635 "Time:[his, ifs_avg(us), cca_avg(us)]\n"); 5636 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) 5637 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "T%d:[%d, %d, %d]\n", 5638 i + 1, env->ifs_clm_his[i], env->ifs_clm_ifs_avg[i], 5639 env->ifs_clm_cca_avg[i]); 5640 } 5641 5642 static bool rtw89_phy_ifs_clm_get_result(struct rtw89_dev *rtwdev, 5643 struct rtw89_bb_ctx *bb) 5644 { 5645 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 5646 struct rtw89_env_monitor_info *env = &bb->env_monitor; 5647 const struct rtw89_ccx_regs *ccx = phy->ccx; 5648 u8 i = 0; 5649 5650 if (rtw89_phy_read32_idx(rtwdev, ccx->ifs_total_addr, 5651 ccx->ifs_cnt_done_mask, bb->phy_idx) == 0) { 5652 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 5653 "Get IFS_CLM report Fail\n"); 5654 return false; 5655 } 5656 5657 env->ifs_clm_tx = 5658 rtw89_phy_read32_idx(rtwdev, ccx->ifs_clm_tx_cnt_addr, 5659 ccx->ifs_clm_tx_cnt_msk, bb->phy_idx); 5660 env->ifs_clm_edcca_excl_cca = 5661 rtw89_phy_read32_idx(rtwdev, ccx->ifs_clm_tx_cnt_addr, 5662 ccx->ifs_clm_edcca_excl_cca_fa_mask, bb->phy_idx); 5663 env->ifs_clm_cckcca_excl_fa = 5664 rtw89_phy_read32_idx(rtwdev, ccx->ifs_clm_cca_addr, 5665 ccx->ifs_clm_cckcca_excl_fa_mask, bb->phy_idx); 5666 env->ifs_clm_ofdmcca_excl_fa = 5667 rtw89_phy_read32_idx(rtwdev, ccx->ifs_clm_cca_addr, 5668 ccx->ifs_clm_ofdmcca_excl_fa_mask, bb->phy_idx); 5669 env->ifs_clm_cckfa = 5670 rtw89_phy_read32_idx(rtwdev, ccx->ifs_clm_fa_addr, 5671 ccx->ifs_clm_cck_fa_mask, bb->phy_idx); 5672 env->ifs_clm_ofdmfa = 5673 rtw89_phy_read32_idx(rtwdev, ccx->ifs_clm_fa_addr, 5674 ccx->ifs_clm_ofdm_fa_mask, bb->phy_idx); 5675 5676 env->ifs_clm_his[0] = 5677 rtw89_phy_read32_idx(rtwdev, ccx->ifs_his_addr, 5678 ccx->ifs_t1_his_mask, bb->phy_idx); 5679 env->ifs_clm_his[1] = 5680 rtw89_phy_read32_idx(rtwdev, ccx->ifs_his_addr, 5681 ccx->ifs_t2_his_mask, bb->phy_idx); 5682 env->ifs_clm_his[2] = 5683 rtw89_phy_read32_idx(rtwdev, ccx->ifs_his_addr, 5684 ccx->ifs_t3_his_mask, bb->phy_idx); 5685 env->ifs_clm_his[3] = 5686 rtw89_phy_read32_idx(rtwdev, ccx->ifs_his_addr, 5687 ccx->ifs_t4_his_mask, bb->phy_idx); 5688 5689 env->ifs_clm_avg[0] = 5690 rtw89_phy_read32_idx(rtwdev, ccx->ifs_avg_l_addr, 5691 ccx->ifs_t1_avg_mask, bb->phy_idx); 5692 env->ifs_clm_avg[1] = 5693 rtw89_phy_read32_idx(rtwdev, ccx->ifs_avg_l_addr, 5694 ccx->ifs_t2_avg_mask, bb->phy_idx); 5695 env->ifs_clm_avg[2] = 5696 rtw89_phy_read32_idx(rtwdev, ccx->ifs_avg_h_addr, 5697 ccx->ifs_t3_avg_mask, bb->phy_idx); 5698 env->ifs_clm_avg[3] = 5699 rtw89_phy_read32_idx(rtwdev, ccx->ifs_avg_h_addr, 5700 ccx->ifs_t4_avg_mask, bb->phy_idx); 5701 5702 env->ifs_clm_cca[0] = 5703 rtw89_phy_read32_idx(rtwdev, ccx->ifs_cca_l_addr, 5704 ccx->ifs_t1_cca_mask, bb->phy_idx); 5705 env->ifs_clm_cca[1] = 5706 rtw89_phy_read32_idx(rtwdev, ccx->ifs_cca_l_addr, 5707 ccx->ifs_t2_cca_mask, bb->phy_idx); 5708 env->ifs_clm_cca[2] = 5709 rtw89_phy_read32_idx(rtwdev, ccx->ifs_cca_h_addr, 5710 ccx->ifs_t3_cca_mask, bb->phy_idx); 5711 env->ifs_clm_cca[3] = 5712 rtw89_phy_read32_idx(rtwdev, ccx->ifs_cca_h_addr, 5713 ccx->ifs_t4_cca_mask, bb->phy_idx); 5714 5715 env->ifs_clm_total_ifs = 5716 rtw89_phy_read32_idx(rtwdev, ccx->ifs_total_addr, 5717 ccx->ifs_total_mask, bb->phy_idx); 5718 5719 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "IFS-CLM total_ifs = %d\n", 5720 env->ifs_clm_total_ifs); 5721 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 5722 "{Tx, EDCCA_exclu_cca} = {%d, %d}\n", 5723 env->ifs_clm_tx, env->ifs_clm_edcca_excl_cca); 5724 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 5725 "IFS-CLM FA{CCK, OFDM} = {%d, %d}\n", 5726 env->ifs_clm_cckfa, env->ifs_clm_ofdmfa); 5727 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 5728 "IFS-CLM CCA_exclu_FA{CCK, OFDM} = {%d, %d}\n", 5729 env->ifs_clm_cckcca_excl_fa, env->ifs_clm_ofdmcca_excl_fa); 5730 5731 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "Time:[his, avg, cca]\n"); 5732 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) 5733 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 5734 "T%d:[%d, %d, %d]\n", i + 1, env->ifs_clm_his[i], 5735 env->ifs_clm_avg[i], env->ifs_clm_cca[i]); 5736 5737 rtw89_phy_ifs_clm_get_utility(rtwdev, bb); 5738 5739 return true; 5740 } 5741 5742 static int rtw89_phy_ifs_clm_set(struct rtw89_dev *rtwdev, 5743 struct rtw89_bb_ctx *bb, 5744 struct rtw89_ccx_para_info *para) 5745 { 5746 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 5747 struct rtw89_env_monitor_info *env = &bb->env_monitor; 5748 const struct rtw89_ccx_regs *ccx = phy->ccx; 5749 u32 period = 0; 5750 u32 unit_idx = 0; 5751 5752 if (para->mntr_time == 0) { 5753 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 5754 "[WARN] MNTR_TIME is 0\n"); 5755 return -EINVAL; 5756 } 5757 5758 if (rtw89_phy_ccx_racing_ctrl(rtwdev, bb, para->rac_lv)) 5759 return -EINVAL; 5760 5761 if (para->mntr_time != env->ifs_clm_mntr_time) { 5762 rtw89_phy_ccx_ms_to_period_unit(rtwdev, para->mntr_time, 5763 &period, &unit_idx); 5764 rtw89_phy_write32_idx(rtwdev, ccx->ifs_cnt_addr, 5765 ccx->ifs_clm_period_mask, period, bb->phy_idx); 5766 rtw89_phy_write32_idx(rtwdev, ccx->ifs_cnt_addr, 5767 ccx->ifs_clm_cnt_unit_mask, 5768 unit_idx, bb->phy_idx); 5769 5770 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 5771 "Update IFS-CLM time ((%d)) -> ((%d))\n", 5772 env->ifs_clm_mntr_time, para->mntr_time); 5773 5774 env->ifs_clm_mntr_time = para->mntr_time; 5775 env->ccx_period = (u16)period; 5776 env->ccx_unit_idx = (u8)unit_idx; 5777 } 5778 5779 if (rtw89_phy_ifs_clm_th_update_check(rtwdev, bb, para)) { 5780 env->ifs_clm_app = para->ifs_clm_app; 5781 rtw89_phy_ifs_clm_set_th_reg(rtwdev, bb); 5782 } 5783 5784 return 0; 5785 } 5786 5787 static void __rtw89_phy_env_monitor_track(struct rtw89_dev *rtwdev, 5788 struct rtw89_bb_ctx *bb) 5789 { 5790 struct rtw89_env_monitor_info *env = &bb->env_monitor; 5791 struct rtw89_ccx_para_info para = {}; 5792 u8 chk_result = RTW89_PHY_ENV_MON_CCX_FAIL; 5793 5794 env->ccx_watchdog_result = RTW89_PHY_ENV_MON_CCX_FAIL; 5795 if (env->ccx_manual_ctrl) { 5796 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 5797 "CCX in manual ctrl\n"); 5798 return; 5799 } 5800 5801 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 5802 "BB-%d env_monitor track\n", bb->phy_idx); 5803 5804 /* only ifs_clm for now */ 5805 if (rtw89_phy_ifs_clm_get_result(rtwdev, bb)) 5806 env->ccx_watchdog_result |= RTW89_PHY_ENV_MON_IFS_CLM; 5807 5808 rtw89_phy_ccx_racing_release(rtwdev, bb); 5809 para.mntr_time = 1900; 5810 para.rac_lv = RTW89_RAC_LV_1; 5811 para.ifs_clm_app = RTW89_IFS_CLM_BACKGROUND; 5812 5813 if (rtw89_phy_ifs_clm_set(rtwdev, bb, ¶) == 0) 5814 chk_result |= RTW89_PHY_ENV_MON_IFS_CLM; 5815 if (chk_result) 5816 rtw89_phy_ccx_trigger(rtwdev, bb); 5817 5818 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 5819 "get_result=0x%x, chk_result:0x%x\n", 5820 env->ccx_watchdog_result, chk_result); 5821 } 5822 5823 void rtw89_phy_env_monitor_track(struct rtw89_dev *rtwdev) 5824 { 5825 struct rtw89_bb_ctx *bb; 5826 5827 rtw89_for_each_active_bb(rtwdev, bb) 5828 __rtw89_phy_env_monitor_track(rtwdev, bb); 5829 } 5830 5831 static bool rtw89_physts_ie_page_valid(enum rtw89_phy_status_bitmap *ie_page) 5832 { 5833 if (*ie_page >= RTW89_PHYSTS_BITMAP_NUM || 5834 *ie_page == RTW89_RSVD_9) 5835 return false; 5836 else if (*ie_page > RTW89_RSVD_9) 5837 *ie_page -= 1; 5838 5839 return true; 5840 } 5841 5842 static u32 rtw89_phy_get_ie_bitmap_addr(enum rtw89_phy_status_bitmap ie_page) 5843 { 5844 static const u8 ie_page_shift = 2; 5845 5846 return R_PHY_STS_BITMAP_ADDR_START + (ie_page << ie_page_shift); 5847 } 5848 5849 static u32 rtw89_physts_get_ie_bitmap(struct rtw89_dev *rtwdev, 5850 enum rtw89_phy_status_bitmap ie_page, 5851 enum rtw89_phy_idx phy_idx) 5852 { 5853 u32 addr; 5854 5855 if (!rtw89_physts_ie_page_valid(&ie_page)) 5856 return 0; 5857 5858 addr = rtw89_phy_get_ie_bitmap_addr(ie_page); 5859 5860 return rtw89_phy_read32_idx(rtwdev, addr, MASKDWORD, phy_idx); 5861 } 5862 5863 static void rtw89_physts_set_ie_bitmap(struct rtw89_dev *rtwdev, 5864 enum rtw89_phy_status_bitmap ie_page, 5865 u32 val, enum rtw89_phy_idx phy_idx) 5866 { 5867 const struct rtw89_chip_info *chip = rtwdev->chip; 5868 u32 addr; 5869 5870 if (!rtw89_physts_ie_page_valid(&ie_page)) 5871 return; 5872 5873 if (chip->chip_id == RTL8852A) 5874 val &= B_PHY_STS_BITMAP_MSK_52A; 5875 5876 addr = rtw89_phy_get_ie_bitmap_addr(ie_page); 5877 rtw89_phy_write32_idx(rtwdev, addr, MASKDWORD, val, phy_idx); 5878 } 5879 5880 static void rtw89_physts_enable_ie_bitmap(struct rtw89_dev *rtwdev, 5881 enum rtw89_phy_status_bitmap bitmap, 5882 enum rtw89_phy_status_ie_type ie, 5883 bool enable, enum rtw89_phy_idx phy_idx) 5884 { 5885 u32 val = rtw89_physts_get_ie_bitmap(rtwdev, bitmap, phy_idx); 5886 5887 if (enable) 5888 val |= BIT(ie); 5889 else 5890 val &= ~BIT(ie); 5891 5892 rtw89_physts_set_ie_bitmap(rtwdev, bitmap, val, phy_idx); 5893 } 5894 5895 static void rtw89_physts_enable_fail_report(struct rtw89_dev *rtwdev, 5896 bool enable, 5897 enum rtw89_phy_idx phy_idx) 5898 { 5899 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 5900 const struct rtw89_physts_regs *physts = phy->physts; 5901 5902 if (enable) { 5903 rtw89_phy_write32_idx_clr(rtwdev, physts->setting_addr, 5904 physts->dis_trigger_fail_mask, phy_idx); 5905 rtw89_phy_write32_idx_clr(rtwdev, physts->setting_addr, 5906 physts->dis_trigger_brk_mask, phy_idx); 5907 } else { 5908 rtw89_phy_write32_idx_set(rtwdev, physts->setting_addr, 5909 physts->dis_trigger_fail_mask, phy_idx); 5910 rtw89_phy_write32_idx_set(rtwdev, physts->setting_addr, 5911 physts->dis_trigger_brk_mask, phy_idx); 5912 } 5913 } 5914 5915 static void __rtw89_physts_parsing_init(struct rtw89_dev *rtwdev, 5916 enum rtw89_phy_idx phy_idx) 5917 { 5918 u8 i; 5919 5920 rtw89_physts_enable_fail_report(rtwdev, false, phy_idx); 5921 5922 for (i = 0; i < RTW89_PHYSTS_BITMAP_NUM; i++) { 5923 if (i >= RTW89_CCK_PKT) 5924 rtw89_physts_enable_ie_bitmap(rtwdev, i, 5925 RTW89_PHYSTS_IE09_FTR_0, 5926 true, phy_idx); 5927 if ((i >= RTW89_CCK_BRK && i <= RTW89_VHT_MU) || 5928 (i >= RTW89_RSVD_9 && i <= RTW89_CCK_PKT)) 5929 continue; 5930 rtw89_physts_enable_ie_bitmap(rtwdev, i, 5931 RTW89_PHYSTS_IE24_OFDM_TD_PATH_A, 5932 true, phy_idx); 5933 } 5934 rtw89_physts_enable_ie_bitmap(rtwdev, RTW89_VHT_PKT, 5935 RTW89_PHYSTS_IE13_DL_MU_DEF, true, phy_idx); 5936 rtw89_physts_enable_ie_bitmap(rtwdev, RTW89_HE_PKT, 5937 RTW89_PHYSTS_IE13_DL_MU_DEF, true, phy_idx); 5938 5939 /* force IE01 for channel index, only channel field is valid */ 5940 rtw89_physts_enable_ie_bitmap(rtwdev, RTW89_CCK_PKT, 5941 RTW89_PHYSTS_IE01_CMN_OFDM, true, phy_idx); 5942 } 5943 5944 static void rtw89_physts_parsing_init(struct rtw89_dev *rtwdev) 5945 { 5946 __rtw89_physts_parsing_init(rtwdev, RTW89_PHY_0); 5947 if (rtwdev->dbcc_en) 5948 __rtw89_physts_parsing_init(rtwdev, RTW89_PHY_1); 5949 } 5950 5951 static void rtw89_phy_dig_read_gain_table(struct rtw89_dev *rtwdev, 5952 struct rtw89_bb_ctx *bb, int type) 5953 { 5954 const struct rtw89_chip_info *chip = rtwdev->chip; 5955 const struct rtw89_phy_dig_gain_cfg *cfg; 5956 struct rtw89_dig_info *dig = &bb->dig; 5957 const char *msg; 5958 u8 i; 5959 s8 gain_base; 5960 s8 *gain_arr; 5961 u32 tmp; 5962 5963 switch (type) { 5964 case RTW89_DIG_GAIN_LNA_G: 5965 gain_arr = dig->lna_gain_g; 5966 gain_base = LNA0_GAIN; 5967 cfg = chip->dig_table->cfg_lna_g; 5968 msg = "lna_gain_g"; 5969 break; 5970 case RTW89_DIG_GAIN_TIA_G: 5971 gain_arr = dig->tia_gain_g; 5972 gain_base = TIA0_GAIN_G; 5973 cfg = chip->dig_table->cfg_tia_g; 5974 msg = "tia_gain_g"; 5975 break; 5976 case RTW89_DIG_GAIN_LNA_A: 5977 gain_arr = dig->lna_gain_a; 5978 gain_base = LNA0_GAIN; 5979 cfg = chip->dig_table->cfg_lna_a; 5980 msg = "lna_gain_a"; 5981 break; 5982 case RTW89_DIG_GAIN_TIA_A: 5983 gain_arr = dig->tia_gain_a; 5984 gain_base = TIA0_GAIN_A; 5985 cfg = chip->dig_table->cfg_tia_a; 5986 msg = "tia_gain_a"; 5987 break; 5988 default: 5989 return; 5990 } 5991 5992 for (i = 0; i < cfg->size; i++) { 5993 tmp = rtw89_phy_read32_idx(rtwdev, cfg->table[i].addr, 5994 cfg->table[i].mask, bb->phy_idx); 5995 tmp >>= DIG_GAIN_SHIFT; 5996 gain_arr[i] = sign_extend32(tmp, U4_MAX_BIT) + gain_base; 5997 gain_base += DIG_GAIN; 5998 5999 rtw89_debug(rtwdev, RTW89_DBG_DIG, "%s[%d]=%d\n", 6000 msg, i, gain_arr[i]); 6001 } 6002 } 6003 6004 static void rtw89_phy_dig_update_gain_para(struct rtw89_dev *rtwdev, 6005 struct rtw89_bb_ctx *bb) 6006 { 6007 struct rtw89_dig_info *dig = &bb->dig; 6008 u32 tmp; 6009 u8 i; 6010 6011 if (!rtwdev->hal.support_igi) 6012 return; 6013 6014 tmp = rtw89_phy_read32_idx(rtwdev, R_PATH0_IB_PKPW, 6015 B_PATH0_IB_PKPW_MSK, bb->phy_idx); 6016 dig->ib_pkpwr = sign_extend32(tmp >> DIG_GAIN_SHIFT, U8_MAX_BIT); 6017 dig->ib_pbk = rtw89_phy_read32_idx(rtwdev, R_PATH0_IB_PBK, 6018 B_PATH0_IB_PBK_MSK, bb->phy_idx); 6019 rtw89_debug(rtwdev, RTW89_DBG_DIG, "ib_pkpwr=%d, ib_pbk=%d\n", 6020 dig->ib_pkpwr, dig->ib_pbk); 6021 6022 for (i = RTW89_DIG_GAIN_LNA_G; i < RTW89_DIG_GAIN_MAX; i++) 6023 rtw89_phy_dig_read_gain_table(rtwdev, bb, i); 6024 } 6025 6026 static const u8 rssi_nolink = 22; 6027 static const u8 igi_rssi_th[IGI_RSSI_TH_NUM] = {68, 84, 90, 98, 104}; 6028 static const u16 fa_th_2g[FA_TH_NUM] = {22, 44, 66, 88}; 6029 static const u16 fa_th_5g[FA_TH_NUM] = {4, 8, 12, 16}; 6030 static const u16 fa_th_nolink[FA_TH_NUM] = {196, 352, 440, 528}; 6031 6032 static void rtw89_phy_dig_update_rssi_info(struct rtw89_dev *rtwdev, 6033 struct rtw89_bb_ctx *bb) 6034 { 6035 struct rtw89_phy_ch_info *ch_info = &bb->ch_info; 6036 struct rtw89_dig_info *dig = &bb->dig; 6037 bool is_linked = rtwdev->total_sta_assoc > 0; 6038 6039 if (is_linked) { 6040 dig->igi_rssi = ch_info->rssi_min >> 1; 6041 } else { 6042 rtw89_debug(rtwdev, RTW89_DBG_DIG, "RSSI update : NO Link\n"); 6043 dig->igi_rssi = rssi_nolink; 6044 } 6045 } 6046 6047 static void rtw89_phy_dig_update_para(struct rtw89_dev *rtwdev, 6048 struct rtw89_bb_ctx *bb) 6049 { 6050 const struct rtw89_chan *chan = rtw89_mgnt_chan_get(rtwdev, bb->phy_idx); 6051 struct rtw89_dig_info *dig = &bb->dig; 6052 bool is_linked = rtwdev->total_sta_assoc > 0; 6053 const u16 *fa_th_src = NULL; 6054 6055 switch (chan->band_type) { 6056 case RTW89_BAND_2G: 6057 dig->lna_gain = dig->lna_gain_g; 6058 dig->tia_gain = dig->tia_gain_g; 6059 fa_th_src = is_linked ? fa_th_2g : fa_th_nolink; 6060 dig->force_gaincode_idx_en = false; 6061 dig->dyn_pd_th_en = true; 6062 break; 6063 case RTW89_BAND_5G: 6064 default: 6065 dig->lna_gain = dig->lna_gain_a; 6066 dig->tia_gain = dig->tia_gain_a; 6067 fa_th_src = is_linked ? fa_th_5g : fa_th_nolink; 6068 dig->force_gaincode_idx_en = true; 6069 dig->dyn_pd_th_en = true; 6070 break; 6071 } 6072 memcpy(dig->fa_th, fa_th_src, sizeof(dig->fa_th)); 6073 memcpy(dig->igi_rssi_th, igi_rssi_th, sizeof(dig->igi_rssi_th)); 6074 } 6075 6076 static const u8 pd_low_th_offset = 16, dynamic_igi_min = 0x20; 6077 static const u8 igi_max_performance_mode = 0x5a; 6078 static const u8 dynamic_pd_threshold_max; 6079 6080 static void rtw89_phy_dig_para_reset(struct rtw89_dev *rtwdev, 6081 struct rtw89_bb_ctx *bb) 6082 { 6083 struct rtw89_dig_info *dig = &bb->dig; 6084 6085 dig->cur_gaincode.lna_idx = LNA_IDX_MAX; 6086 dig->cur_gaincode.tia_idx = TIA_IDX_MAX; 6087 dig->cur_gaincode.rxb_idx = RXB_IDX_MAX; 6088 dig->force_gaincode.lna_idx = LNA_IDX_MAX; 6089 dig->force_gaincode.tia_idx = TIA_IDX_MAX; 6090 dig->force_gaincode.rxb_idx = RXB_IDX_MAX; 6091 6092 dig->dyn_igi_max = igi_max_performance_mode; 6093 dig->dyn_igi_min = dynamic_igi_min; 6094 dig->dyn_pd_th_max = dynamic_pd_threshold_max; 6095 dig->pd_low_th_ofst = pd_low_th_offset; 6096 dig->is_linked_pre = false; 6097 } 6098 6099 static void __rtw89_phy_dig_init(struct rtw89_dev *rtwdev, 6100 struct rtw89_bb_ctx *bb) 6101 { 6102 rtw89_debug(rtwdev, RTW89_DBG_DIG, "BB-%d dig_init\n", bb->phy_idx); 6103 6104 rtw89_phy_dig_update_gain_para(rtwdev, bb); 6105 rtw89_phy_dig_reset(rtwdev, bb); 6106 } 6107 6108 static void rtw89_phy_dig_init(struct rtw89_dev *rtwdev) 6109 { 6110 struct rtw89_bb_ctx *bb; 6111 6112 rtw89_for_each_capab_bb(rtwdev, bb) 6113 __rtw89_phy_dig_init(rtwdev, bb); 6114 } 6115 6116 static u8 rtw89_phy_dig_lna_idx_by_rssi(struct rtw89_dev *rtwdev, 6117 struct rtw89_bb_ctx *bb, u8 rssi) 6118 { 6119 struct rtw89_dig_info *dig = &bb->dig; 6120 u8 lna_idx; 6121 6122 if (rssi < dig->igi_rssi_th[0]) 6123 lna_idx = RTW89_DIG_GAIN_LNA_IDX6; 6124 else if (rssi < dig->igi_rssi_th[1]) 6125 lna_idx = RTW89_DIG_GAIN_LNA_IDX5; 6126 else if (rssi < dig->igi_rssi_th[2]) 6127 lna_idx = RTW89_DIG_GAIN_LNA_IDX4; 6128 else if (rssi < dig->igi_rssi_th[3]) 6129 lna_idx = RTW89_DIG_GAIN_LNA_IDX3; 6130 else if (rssi < dig->igi_rssi_th[4]) 6131 lna_idx = RTW89_DIG_GAIN_LNA_IDX2; 6132 else 6133 lna_idx = RTW89_DIG_GAIN_LNA_IDX1; 6134 6135 return lna_idx; 6136 } 6137 6138 static u8 rtw89_phy_dig_tia_idx_by_rssi(struct rtw89_dev *rtwdev, 6139 struct rtw89_bb_ctx *bb, u8 rssi) 6140 { 6141 struct rtw89_dig_info *dig = &bb->dig; 6142 u8 tia_idx; 6143 6144 if (rssi < dig->igi_rssi_th[0]) 6145 tia_idx = RTW89_DIG_GAIN_TIA_IDX1; 6146 else 6147 tia_idx = RTW89_DIG_GAIN_TIA_IDX0; 6148 6149 return tia_idx; 6150 } 6151 6152 #define IB_PBK_BASE 110 6153 #define WB_RSSI_BASE 10 6154 static u8 rtw89_phy_dig_rxb_idx_by_rssi(struct rtw89_dev *rtwdev, 6155 struct rtw89_bb_ctx *bb, u8 rssi, 6156 struct rtw89_agc_gaincode_set *set) 6157 { 6158 struct rtw89_dig_info *dig = &bb->dig; 6159 s8 lna_gain = dig->lna_gain[set->lna_idx]; 6160 s8 tia_gain = dig->tia_gain[set->tia_idx]; 6161 s32 wb_rssi = rssi + lna_gain + tia_gain; 6162 s32 rxb_idx_tmp = IB_PBK_BASE + WB_RSSI_BASE; 6163 u8 rxb_idx; 6164 6165 rxb_idx_tmp += dig->ib_pkpwr - dig->ib_pbk - wb_rssi; 6166 rxb_idx = clamp_t(s32, rxb_idx_tmp, RXB_IDX_MIN, RXB_IDX_MAX); 6167 6168 rtw89_debug(rtwdev, RTW89_DBG_DIG, "wb_rssi=%03d, rxb_idx_tmp=%03d\n", 6169 wb_rssi, rxb_idx_tmp); 6170 6171 return rxb_idx; 6172 } 6173 6174 static void rtw89_phy_dig_gaincode_by_rssi(struct rtw89_dev *rtwdev, 6175 struct rtw89_bb_ctx *bb, u8 rssi, 6176 struct rtw89_agc_gaincode_set *set) 6177 { 6178 set->lna_idx = rtw89_phy_dig_lna_idx_by_rssi(rtwdev, bb, rssi); 6179 set->tia_idx = rtw89_phy_dig_tia_idx_by_rssi(rtwdev, bb, rssi); 6180 set->rxb_idx = rtw89_phy_dig_rxb_idx_by_rssi(rtwdev, bb, rssi, set); 6181 6182 rtw89_debug(rtwdev, RTW89_DBG_DIG, 6183 "final_rssi=%03d, (lna,tia,rab)=(%d,%d,%02d)\n", 6184 rssi, set->lna_idx, set->tia_idx, set->rxb_idx); 6185 } 6186 6187 #define IGI_OFFSET_MAX 25 6188 #define IGI_OFFSET_MUL 2 6189 static void rtw89_phy_dig_igi_offset_by_env(struct rtw89_dev *rtwdev, 6190 struct rtw89_bb_ctx *bb) 6191 { 6192 struct rtw89_dig_info *dig = &bb->dig; 6193 struct rtw89_env_monitor_info *env = &bb->env_monitor; 6194 enum rtw89_dig_noisy_level noisy_lv; 6195 u8 igi_offset = dig->fa_rssi_ofst; 6196 u16 fa_ratio = 0; 6197 6198 fa_ratio = env->ifs_clm_cck_fa_permil + env->ifs_clm_ofdm_fa_permil; 6199 6200 if (fa_ratio < dig->fa_th[0]) 6201 noisy_lv = RTW89_DIG_NOISY_LEVEL0; 6202 else if (fa_ratio < dig->fa_th[1]) 6203 noisy_lv = RTW89_DIG_NOISY_LEVEL1; 6204 else if (fa_ratio < dig->fa_th[2]) 6205 noisy_lv = RTW89_DIG_NOISY_LEVEL2; 6206 else if (fa_ratio < dig->fa_th[3]) 6207 noisy_lv = RTW89_DIG_NOISY_LEVEL3; 6208 else 6209 noisy_lv = RTW89_DIG_NOISY_LEVEL_MAX; 6210 6211 if (noisy_lv == RTW89_DIG_NOISY_LEVEL0 && igi_offset < 2) 6212 igi_offset = 0; 6213 else 6214 igi_offset += noisy_lv * IGI_OFFSET_MUL; 6215 6216 igi_offset = min_t(u8, igi_offset, IGI_OFFSET_MAX); 6217 dig->fa_rssi_ofst = igi_offset; 6218 6219 rtw89_debug(rtwdev, RTW89_DBG_DIG, 6220 "fa_th: [+6 (%d) +4 (%d) +2 (%d) 0 (%d) -2 ]\n", 6221 dig->fa_th[3], dig->fa_th[2], dig->fa_th[1], dig->fa_th[0]); 6222 6223 rtw89_debug(rtwdev, RTW89_DBG_DIG, 6224 "fa(CCK,OFDM,ALL)=(%d,%d,%d)%%, noisy_lv=%d, ofst=%d\n", 6225 env->ifs_clm_cck_fa_permil, env->ifs_clm_ofdm_fa_permil, 6226 env->ifs_clm_cck_fa_permil + env->ifs_clm_ofdm_fa_permil, 6227 noisy_lv, igi_offset); 6228 } 6229 6230 static void rtw89_phy_dig_set_lna_idx(struct rtw89_dev *rtwdev, 6231 struct rtw89_bb_ctx *bb, u8 lna_idx) 6232 { 6233 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs; 6234 6235 rtw89_phy_write32_idx(rtwdev, dig_regs->p0_lna_init.addr, 6236 dig_regs->p0_lna_init.mask, lna_idx, bb->phy_idx); 6237 rtw89_phy_write32_idx(rtwdev, dig_regs->p1_lna_init.addr, 6238 dig_regs->p1_lna_init.mask, lna_idx, bb->phy_idx); 6239 } 6240 6241 static void rtw89_phy_dig_set_tia_idx(struct rtw89_dev *rtwdev, 6242 struct rtw89_bb_ctx *bb, u8 tia_idx) 6243 { 6244 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs; 6245 6246 rtw89_phy_write32_idx(rtwdev, dig_regs->p0_tia_init.addr, 6247 dig_regs->p0_tia_init.mask, tia_idx, bb->phy_idx); 6248 rtw89_phy_write32_idx(rtwdev, dig_regs->p1_tia_init.addr, 6249 dig_regs->p1_tia_init.mask, tia_idx, bb->phy_idx); 6250 } 6251 6252 static void rtw89_phy_dig_set_rxb_idx(struct rtw89_dev *rtwdev, 6253 struct rtw89_bb_ctx *bb, u8 rxb_idx) 6254 { 6255 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs; 6256 6257 rtw89_phy_write32_idx(rtwdev, dig_regs->p0_rxb_init.addr, 6258 dig_regs->p0_rxb_init.mask, rxb_idx, bb->phy_idx); 6259 rtw89_phy_write32_idx(rtwdev, dig_regs->p1_rxb_init.addr, 6260 dig_regs->p1_rxb_init.mask, rxb_idx, bb->phy_idx); 6261 } 6262 6263 static void rtw89_phy_dig_set_igi_cr(struct rtw89_dev *rtwdev, 6264 struct rtw89_bb_ctx *bb, 6265 const struct rtw89_agc_gaincode_set set) 6266 { 6267 if (!rtwdev->hal.support_igi) 6268 return; 6269 6270 rtw89_phy_dig_set_lna_idx(rtwdev, bb, set.lna_idx); 6271 rtw89_phy_dig_set_tia_idx(rtwdev, bb, set.tia_idx); 6272 rtw89_phy_dig_set_rxb_idx(rtwdev, bb, set.rxb_idx); 6273 6274 rtw89_debug(rtwdev, RTW89_DBG_DIG, "Set (lna,tia,rxb)=((%d,%d,%02d))\n", 6275 set.lna_idx, set.tia_idx, set.rxb_idx); 6276 } 6277 6278 static void rtw89_phy_dig_sdagc_follow_pagc_config(struct rtw89_dev *rtwdev, 6279 struct rtw89_bb_ctx *bb, 6280 bool enable) 6281 { 6282 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs; 6283 6284 rtw89_phy_write32_idx(rtwdev, dig_regs->p0_p20_pagcugc_en.addr, 6285 dig_regs->p0_p20_pagcugc_en.mask, enable, bb->phy_idx); 6286 rtw89_phy_write32_idx(rtwdev, dig_regs->p0_s20_pagcugc_en.addr, 6287 dig_regs->p0_s20_pagcugc_en.mask, enable, bb->phy_idx); 6288 rtw89_phy_write32_idx(rtwdev, dig_regs->p1_p20_pagcugc_en.addr, 6289 dig_regs->p1_p20_pagcugc_en.mask, enable, bb->phy_idx); 6290 rtw89_phy_write32_idx(rtwdev, dig_regs->p1_s20_pagcugc_en.addr, 6291 dig_regs->p1_s20_pagcugc_en.mask, enable, bb->phy_idx); 6292 6293 rtw89_debug(rtwdev, RTW89_DBG_DIG, "sdagc_follow_pagc=%d\n", enable); 6294 } 6295 6296 static void rtw89_phy_dig_config_igi(struct rtw89_dev *rtwdev, 6297 struct rtw89_bb_ctx *bb) 6298 { 6299 struct rtw89_dig_info *dig = &bb->dig; 6300 6301 if (!rtwdev->hal.support_igi) 6302 return; 6303 6304 if (dig->force_gaincode_idx_en) { 6305 rtw89_phy_dig_set_igi_cr(rtwdev, bb, dig->force_gaincode); 6306 rtw89_debug(rtwdev, RTW89_DBG_DIG, 6307 "Force gaincode index enabled.\n"); 6308 } else { 6309 rtw89_phy_dig_gaincode_by_rssi(rtwdev, bb, dig->igi_fa_rssi, 6310 &dig->cur_gaincode); 6311 rtw89_phy_dig_set_igi_cr(rtwdev, bb, dig->cur_gaincode); 6312 } 6313 } 6314 6315 static void rtw89_phy_dig_dyn_pd_th(struct rtw89_dev *rtwdev, 6316 struct rtw89_bb_ctx *bb, 6317 u8 rssi, bool enable) 6318 { 6319 const struct rtw89_chan *chan = rtw89_mgnt_chan_get(rtwdev, bb->phy_idx); 6320 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs; 6321 enum rtw89_bandwidth cbw = chan->band_width; 6322 struct rtw89_dig_info *dig = &bb->dig; 6323 u8 final_rssi = 0, under_region = dig->pd_low_th_ofst; 6324 u8 ofdm_cca_th; 6325 s8 cck_cca_th; 6326 u32 pd_val = 0; 6327 6328 if (rtwdev->chip->chip_gen == RTW89_CHIP_AX) 6329 under_region += PD_TH_SB_FLTR_CMP_VAL; 6330 6331 switch (cbw) { 6332 case RTW89_CHANNEL_WIDTH_40: 6333 under_region += PD_TH_BW40_CMP_VAL; 6334 break; 6335 case RTW89_CHANNEL_WIDTH_80: 6336 under_region += PD_TH_BW80_CMP_VAL; 6337 break; 6338 case RTW89_CHANNEL_WIDTH_160: 6339 under_region += PD_TH_BW160_CMP_VAL; 6340 break; 6341 case RTW89_CHANNEL_WIDTH_20: 6342 fallthrough; 6343 default: 6344 under_region += PD_TH_BW20_CMP_VAL; 6345 break; 6346 } 6347 6348 dig->dyn_pd_th_max = dig->igi_rssi; 6349 6350 final_rssi = min_t(u8, rssi, dig->igi_rssi); 6351 ofdm_cca_th = clamp_t(u8, final_rssi, PD_TH_MIN_RSSI + under_region, 6352 PD_TH_MAX_RSSI + under_region); 6353 6354 if (enable) { 6355 pd_val = (ofdm_cca_th - under_region - PD_TH_MIN_RSSI) >> 1; 6356 rtw89_debug(rtwdev, RTW89_DBG_DIG, 6357 "igi=%d, ofdm_ccaTH=%d, backoff=%d, PD_low=%d\n", 6358 final_rssi, ofdm_cca_th, under_region, pd_val); 6359 } else { 6360 rtw89_debug(rtwdev, RTW89_DBG_DIG, 6361 "Dynamic PD th disabled, Set PD_low_bd=0\n"); 6362 } 6363 6364 rtw89_phy_write32_idx(rtwdev, dig_regs->seg0_pd_reg, 6365 dig_regs->pd_lower_bound_mask, pd_val, bb->phy_idx); 6366 rtw89_phy_write32_idx(rtwdev, dig_regs->seg0_pd_reg, 6367 dig_regs->pd_spatial_reuse_en, enable, bb->phy_idx); 6368 6369 if (!rtwdev->hal.support_cckpd) 6370 return; 6371 6372 cck_cca_th = max_t(s8, final_rssi - under_region, CCKPD_TH_MIN_RSSI); 6373 pd_val = (u32)(cck_cca_th - IGI_RSSI_MAX); 6374 6375 rtw89_debug(rtwdev, RTW89_DBG_DIG, 6376 "igi=%d, cck_ccaTH=%d, backoff=%d, cck_PD_low=((%d))dB\n", 6377 final_rssi, cck_cca_th, under_region, pd_val); 6378 6379 rtw89_phy_write32_idx(rtwdev, dig_regs->bmode_pd_reg, 6380 dig_regs->bmode_cca_rssi_limit_en, enable, bb->phy_idx); 6381 rtw89_phy_write32_idx(rtwdev, dig_regs->bmode_pd_lower_bound_reg, 6382 dig_regs->bmode_rssi_nocca_low_th_mask, pd_val, bb->phy_idx); 6383 } 6384 6385 void rtw89_phy_dig_reset(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *bb) 6386 { 6387 struct rtw89_dig_info *dig = &bb->dig; 6388 6389 dig->bypass_dig = false; 6390 rtw89_phy_dig_para_reset(rtwdev, bb); 6391 rtw89_phy_dig_set_igi_cr(rtwdev, bb, dig->force_gaincode); 6392 rtw89_phy_dig_dyn_pd_th(rtwdev, bb, rssi_nolink, false); 6393 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, bb, false); 6394 rtw89_phy_dig_update_para(rtwdev, bb); 6395 } 6396 6397 #define IGI_RSSI_MIN 10 6398 #define ABS_IGI_MIN 0xc 6399 static void __rtw89_phy_dig(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *bb) 6400 { 6401 struct rtw89_dig_info *dig = &bb->dig; 6402 bool is_linked = rtwdev->total_sta_assoc > 0; 6403 u8 igi_min; 6404 6405 if (unlikely(dig->bypass_dig)) { 6406 dig->bypass_dig = false; 6407 return; 6408 } 6409 6410 rtw89_debug(rtwdev, RTW89_DBG_DIG, "BB-%d dig track\n", bb->phy_idx); 6411 6412 rtw89_phy_dig_update_rssi_info(rtwdev, bb); 6413 6414 if (!dig->is_linked_pre && is_linked) { 6415 rtw89_debug(rtwdev, RTW89_DBG_DIG, "First connected\n"); 6416 rtw89_phy_dig_update_para(rtwdev, bb); 6417 dig->igi_fa_rssi = dig->igi_rssi; 6418 } else if (dig->is_linked_pre && !is_linked) { 6419 rtw89_debug(rtwdev, RTW89_DBG_DIG, "First disconnected\n"); 6420 rtw89_phy_dig_update_para(rtwdev, bb); 6421 dig->igi_fa_rssi = dig->igi_rssi; 6422 } 6423 dig->is_linked_pre = is_linked; 6424 6425 rtw89_phy_dig_igi_offset_by_env(rtwdev, bb); 6426 6427 igi_min = max_t(int, dig->igi_rssi - IGI_RSSI_MIN, 0); 6428 dig->dyn_igi_max = min(igi_min + IGI_OFFSET_MAX, igi_max_performance_mode); 6429 dig->dyn_igi_min = max(igi_min, ABS_IGI_MIN); 6430 6431 if (dig->dyn_igi_max >= dig->dyn_igi_min) { 6432 dig->igi_fa_rssi += dig->fa_rssi_ofst; 6433 dig->igi_fa_rssi = clamp(dig->igi_fa_rssi, dig->dyn_igi_min, 6434 dig->dyn_igi_max); 6435 } else { 6436 dig->igi_fa_rssi = dig->dyn_igi_max; 6437 } 6438 6439 rtw89_debug(rtwdev, RTW89_DBG_DIG, 6440 "rssi=%03d, dyn_joint(max,min)=(%d,%d), final_rssi=%d\n", 6441 dig->igi_rssi, dig->dyn_igi_max, dig->dyn_igi_min, 6442 dig->igi_fa_rssi); 6443 6444 rtw89_phy_dig_config_igi(rtwdev, bb); 6445 6446 rtw89_phy_dig_dyn_pd_th(rtwdev, bb, dig->igi_fa_rssi, dig->dyn_pd_th_en); 6447 6448 if (dig->dyn_pd_th_en && dig->igi_fa_rssi > dig->dyn_pd_th_max) 6449 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, bb, true); 6450 else 6451 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, bb, false); 6452 } 6453 6454 void rtw89_phy_dig(struct rtw89_dev *rtwdev) 6455 { 6456 struct rtw89_bb_ctx *bb; 6457 6458 rtw89_for_each_active_bb(rtwdev, bb) 6459 __rtw89_phy_dig(rtwdev, bb); 6460 } 6461 6462 static void __rtw89_phy_tx_path_div_sta_iter(struct rtw89_dev *rtwdev, 6463 struct rtw89_sta_link *rtwsta_link) 6464 { 6465 struct rtw89_hal *hal = &rtwdev->hal; 6466 u8 rssi_a, rssi_b; 6467 u32 candidate; 6468 6469 rssi_a = ewma_rssi_read(&rtwsta_link->rssi[RF_PATH_A]); 6470 rssi_b = ewma_rssi_read(&rtwsta_link->rssi[RF_PATH_B]); 6471 6472 if (rssi_a > rssi_b + RTW89_TX_DIV_RSSI_RAW_TH) 6473 candidate = RF_A; 6474 else if (rssi_b > rssi_a + RTW89_TX_DIV_RSSI_RAW_TH) 6475 candidate = RF_B; 6476 else 6477 return; 6478 6479 if (hal->antenna_tx == candidate) 6480 return; 6481 6482 hal->antenna_tx = candidate; 6483 rtw89_fw_h2c_txpath_cmac_tbl(rtwdev, rtwsta_link); 6484 6485 if (hal->antenna_tx == RF_A) { 6486 rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE, B_P0_RFMODE_MUX, 0x12); 6487 rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE, B_P1_RFMODE_MUX, 0x11); 6488 } else if (hal->antenna_tx == RF_B) { 6489 rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE, B_P0_RFMODE_MUX, 0x11); 6490 rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE, B_P1_RFMODE_MUX, 0x12); 6491 } 6492 } 6493 6494 static void rtw89_phy_tx_path_div_sta_iter(void *data, struct ieee80211_sta *sta) 6495 { 6496 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta); 6497 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 6498 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 6499 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 6500 struct rtw89_vif_link *rtwvif_link; 6501 struct rtw89_sta_link *rtwsta_link; 6502 unsigned int link_id; 6503 bool *done = data; 6504 6505 if (WARN(ieee80211_vif_is_mld(vif), "MLD mix path_div\n")) 6506 return; 6507 6508 if (sta->tdls) 6509 return; 6510 6511 if (*done) 6512 return; 6513 6514 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) { 6515 rtwvif_link = rtwsta_link->rtwvif_link; 6516 if (rtwvif_link->wifi_role != RTW89_WIFI_ROLE_STATION) 6517 continue; 6518 6519 *done = true; 6520 __rtw89_phy_tx_path_div_sta_iter(rtwdev, rtwsta_link); 6521 return; 6522 } 6523 } 6524 6525 void rtw89_phy_tx_path_div_track(struct rtw89_dev *rtwdev) 6526 { 6527 struct rtw89_hal *hal = &rtwdev->hal; 6528 bool done = false; 6529 6530 if (!hal->tx_path_diversity) 6531 return; 6532 6533 ieee80211_iterate_stations_atomic(rtwdev->hw, 6534 rtw89_phy_tx_path_div_sta_iter, 6535 &done); 6536 } 6537 6538 #define ANTDIV_MAIN 0 6539 #define ANTDIV_AUX 1 6540 6541 static void rtw89_phy_antdiv_set_ant(struct rtw89_dev *rtwdev) 6542 { 6543 struct rtw89_hal *hal = &rtwdev->hal; 6544 u8 default_ant, optional_ant; 6545 6546 if (!hal->ant_diversity || hal->antenna_tx == 0) 6547 return; 6548 6549 if (hal->antenna_tx == RF_B) { 6550 default_ant = ANTDIV_AUX; 6551 optional_ant = ANTDIV_MAIN; 6552 } else { 6553 default_ant = ANTDIV_MAIN; 6554 optional_ant = ANTDIV_AUX; 6555 } 6556 6557 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_CGCS_CTRL, 6558 default_ant, RTW89_PHY_0); 6559 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_RX_ORI, 6560 default_ant, RTW89_PHY_0); 6561 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_RX_ALT, 6562 optional_ant, RTW89_PHY_0); 6563 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_TX_ORI, 6564 default_ant, RTW89_PHY_0); 6565 } 6566 6567 static void rtw89_phy_swap_hal_antenna(struct rtw89_dev *rtwdev) 6568 { 6569 struct rtw89_hal *hal = &rtwdev->hal; 6570 6571 hal->antenna_rx = hal->antenna_rx == RF_A ? RF_B : RF_A; 6572 hal->antenna_tx = hal->antenna_rx; 6573 } 6574 6575 static void rtw89_phy_antdiv_decision_state(struct rtw89_dev *rtwdev) 6576 { 6577 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv; 6578 struct rtw89_hal *hal = &rtwdev->hal; 6579 bool no_change = false; 6580 u8 main_rssi, aux_rssi; 6581 u8 main_evm, aux_evm; 6582 u32 candidate; 6583 6584 antdiv->get_stats = false; 6585 antdiv->training_count = 0; 6586 6587 main_rssi = rtw89_phy_antdiv_sts_instance_get_rssi(&antdiv->main_stats); 6588 main_evm = rtw89_phy_antdiv_sts_instance_get_evm(&antdiv->main_stats); 6589 aux_rssi = rtw89_phy_antdiv_sts_instance_get_rssi(&antdiv->aux_stats); 6590 aux_evm = rtw89_phy_antdiv_sts_instance_get_evm(&antdiv->aux_stats); 6591 6592 if (main_evm > aux_evm + ANTDIV_EVM_DIFF_TH) 6593 candidate = RF_A; 6594 else if (aux_evm > main_evm + ANTDIV_EVM_DIFF_TH) 6595 candidate = RF_B; 6596 else if (main_rssi > aux_rssi + RTW89_TX_DIV_RSSI_RAW_TH) 6597 candidate = RF_A; 6598 else if (aux_rssi > main_rssi + RTW89_TX_DIV_RSSI_RAW_TH) 6599 candidate = RF_B; 6600 else 6601 no_change = true; 6602 6603 if (no_change) { 6604 /* swap back from training antenna to original */ 6605 rtw89_phy_swap_hal_antenna(rtwdev); 6606 return; 6607 } 6608 6609 hal->antenna_tx = candidate; 6610 hal->antenna_rx = candidate; 6611 } 6612 6613 static void rtw89_phy_antdiv_training_state(struct rtw89_dev *rtwdev) 6614 { 6615 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv; 6616 u64 state_period; 6617 6618 if (antdiv->training_count % 2 == 0) { 6619 if (antdiv->training_count == 0) 6620 rtw89_phy_antdiv_sts_reset(rtwdev); 6621 6622 antdiv->get_stats = true; 6623 state_period = msecs_to_jiffies(ANTDIV_TRAINNING_INTVL); 6624 } else { 6625 antdiv->get_stats = false; 6626 state_period = msecs_to_jiffies(ANTDIV_DELAY); 6627 6628 rtw89_phy_swap_hal_antenna(rtwdev); 6629 rtw89_phy_antdiv_set_ant(rtwdev); 6630 } 6631 6632 antdiv->training_count++; 6633 wiphy_delayed_work_queue(rtwdev->hw->wiphy, &rtwdev->antdiv_work, 6634 state_period); 6635 } 6636 6637 void rtw89_phy_antdiv_work(struct wiphy *wiphy, struct wiphy_work *work) 6638 { 6639 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 6640 antdiv_work.work); 6641 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv; 6642 6643 lockdep_assert_wiphy(wiphy); 6644 6645 if (antdiv->training_count <= ANTDIV_TRAINNING_CNT) { 6646 rtw89_phy_antdiv_training_state(rtwdev); 6647 } else { 6648 rtw89_phy_antdiv_decision_state(rtwdev); 6649 rtw89_phy_antdiv_set_ant(rtwdev); 6650 } 6651 } 6652 6653 void rtw89_phy_antdiv_track(struct rtw89_dev *rtwdev) 6654 { 6655 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv; 6656 struct rtw89_hal *hal = &rtwdev->hal; 6657 u8 rssi, rssi_pre; 6658 6659 if (!hal->ant_diversity || hal->ant_diversity_fixed) 6660 return; 6661 6662 rssi = rtw89_phy_antdiv_sts_instance_get_rssi(&antdiv->target_stats); 6663 rssi_pre = antdiv->rssi_pre; 6664 antdiv->rssi_pre = rssi; 6665 rtw89_phy_antdiv_sts_instance_reset(&antdiv->target_stats); 6666 6667 if (abs((int)rssi - (int)rssi_pre) < ANTDIV_RSSI_DIFF_TH) 6668 return; 6669 6670 antdiv->training_count = 0; 6671 wiphy_delayed_work_queue(rtwdev->hw->wiphy, &rtwdev->antdiv_work, 0); 6672 } 6673 6674 static void __rtw89_phy_env_monitor_init(struct rtw89_dev *rtwdev, 6675 struct rtw89_bb_ctx *bb) 6676 { 6677 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 6678 "BB-%d env_monitor init\n", bb->phy_idx); 6679 6680 rtw89_phy_ccx_top_setting_init(rtwdev, bb); 6681 rtw89_phy_ifs_clm_setting_init(rtwdev, bb); 6682 } 6683 6684 static void rtw89_phy_env_monitor_init(struct rtw89_dev *rtwdev) 6685 { 6686 struct rtw89_bb_ctx *bb; 6687 6688 rtw89_for_each_capab_bb(rtwdev, bb) 6689 __rtw89_phy_env_monitor_init(rtwdev, bb); 6690 } 6691 6692 static void __rtw89_phy_edcca_init(struct rtw89_dev *rtwdev, 6693 struct rtw89_bb_ctx *bb) 6694 { 6695 const struct rtw89_edcca_regs *edcca_regs = rtwdev->chip->edcca_regs; 6696 struct rtw89_edcca_bak *edcca_bak = &bb->edcca_bak; 6697 6698 rtw89_debug(rtwdev, RTW89_DBG_EDCCA, "BB-%d edcca init\n", bb->phy_idx); 6699 6700 memset(edcca_bak, 0, sizeof(*edcca_bak)); 6701 6702 if (rtwdev->chip->chip_id == RTL8922A && rtwdev->hal.cv == CHIP_CAV) { 6703 rtw89_phy_set_phy_regs(rtwdev, R_TXGATING, B_TXGATING_EN, 0); 6704 rtw89_phy_set_phy_regs(rtwdev, R_CTLTOP, B_CTLTOP_VAL, 2); 6705 rtw89_phy_set_phy_regs(rtwdev, R_CTLTOP, B_CTLTOP_ON, 1); 6706 rtw89_phy_set_phy_regs(rtwdev, R_SPOOF_CG, B_SPOOF_CG_EN, 0); 6707 rtw89_phy_set_phy_regs(rtwdev, R_DFS_FFT_CG, B_DFS_CG_EN, 0); 6708 rtw89_phy_set_phy_regs(rtwdev, R_DFS_FFT_CG, B_DFS_FFT_EN, 0); 6709 rtw89_phy_set_phy_regs(rtwdev, R_SEGSND, B_SEGSND_EN, 0); 6710 rtw89_phy_set_phy_regs(rtwdev, R_SEGSND, B_SEGSND_EN, 1); 6711 rtw89_phy_set_phy_regs(rtwdev, R_DFS_FFT_CG, B_DFS_FFT_EN, 1); 6712 } 6713 6714 rtw89_phy_write32_idx(rtwdev, edcca_regs->tx_collision_t2r_st, 6715 edcca_regs->tx_collision_t2r_st_mask, 0x29, bb->phy_idx); 6716 } 6717 6718 static void rtw89_phy_edcca_init(struct rtw89_dev *rtwdev) 6719 { 6720 struct rtw89_bb_ctx *bb; 6721 6722 rtw89_for_each_capab_bb(rtwdev, bb) 6723 __rtw89_phy_edcca_init(rtwdev, bb); 6724 } 6725 6726 void rtw89_phy_dm_init(struct rtw89_dev *rtwdev) 6727 { 6728 rtw89_phy_stat_init(rtwdev); 6729 6730 rtw89_chip_bb_sethw(rtwdev); 6731 6732 rtw89_phy_env_monitor_init(rtwdev); 6733 rtw89_physts_parsing_init(rtwdev); 6734 rtw89_phy_dig_init(rtwdev); 6735 rtw89_phy_cfo_init(rtwdev); 6736 rtw89_phy_bb_wrap_init(rtwdev); 6737 rtw89_phy_edcca_init(rtwdev); 6738 rtw89_phy_ch_info_init(rtwdev); 6739 rtw89_phy_ul_tb_info_init(rtwdev); 6740 rtw89_phy_antdiv_init(rtwdev); 6741 rtw89_chip_rfe_gpio(rtwdev); 6742 rtw89_phy_antdiv_set_ant(rtwdev); 6743 6744 rtw89_chip_rfk_hw_init(rtwdev); 6745 rtw89_phy_init_rf_nctl(rtwdev); 6746 rtw89_chip_rfk_init(rtwdev); 6747 rtw89_chip_set_txpwr_ctrl(rtwdev); 6748 rtw89_chip_power_trim(rtwdev); 6749 rtw89_chip_cfg_txrx_path(rtwdev); 6750 } 6751 6752 void rtw89_phy_dm_reinit(struct rtw89_dev *rtwdev) 6753 { 6754 rtw89_phy_env_monitor_init(rtwdev); 6755 rtw89_physts_parsing_init(rtwdev); 6756 } 6757 6758 void rtw89_phy_set_bss_color(struct rtw89_dev *rtwdev, 6759 struct rtw89_vif_link *rtwvif_link) 6760 { 6761 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 6762 const struct rtw89_chip_info *chip = rtwdev->chip; 6763 const struct rtw89_reg_def *bss_clr_vld = &chip->bss_clr_vld; 6764 enum rtw89_phy_idx phy_idx = rtwvif_link->phy_idx; 6765 struct ieee80211_bss_conf *bss_conf; 6766 u8 bss_color; 6767 6768 rcu_read_lock(); 6769 6770 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true); 6771 if (!bss_conf->he_support || !vif->cfg.assoc) { 6772 rcu_read_unlock(); 6773 return; 6774 } 6775 6776 bss_color = bss_conf->he_bss_color.color; 6777 6778 rcu_read_unlock(); 6779 6780 rtw89_phy_write32_idx(rtwdev, bss_clr_vld->addr, bss_clr_vld->mask, 0x1, 6781 phy_idx); 6782 rtw89_phy_write32_idx(rtwdev, chip->bss_clr_map_reg, B_BSS_CLR_MAP_TGT, 6783 bss_color, phy_idx); 6784 rtw89_phy_write32_idx(rtwdev, chip->bss_clr_map_reg, B_BSS_CLR_MAP_STAID, 6785 vif->cfg.aid, phy_idx); 6786 } 6787 6788 static bool rfk_chan_validate_desc(const struct rtw89_rfk_chan_desc *desc) 6789 { 6790 return desc->ch != 0; 6791 } 6792 6793 static bool rfk_chan_is_equivalent(const struct rtw89_rfk_chan_desc *desc, 6794 const struct rtw89_chan *chan) 6795 { 6796 if (!rfk_chan_validate_desc(desc)) 6797 return false; 6798 6799 if (desc->ch != chan->channel) 6800 return false; 6801 6802 if (desc->has_band && desc->band != chan->band_type) 6803 return false; 6804 6805 if (desc->has_bw && desc->bw != chan->band_width) 6806 return false; 6807 6808 return true; 6809 } 6810 6811 struct rfk_chan_iter_data { 6812 const struct rtw89_rfk_chan_desc desc; 6813 unsigned int found; 6814 }; 6815 6816 static int rfk_chan_iter_search(const struct rtw89_chan *chan, void *data) 6817 { 6818 struct rfk_chan_iter_data *iter_data = data; 6819 6820 if (rfk_chan_is_equivalent(&iter_data->desc, chan)) 6821 iter_data->found++; 6822 6823 return 0; 6824 } 6825 6826 u8 rtw89_rfk_chan_lookup(struct rtw89_dev *rtwdev, 6827 const struct rtw89_rfk_chan_desc *desc, u8 desc_nr, 6828 const struct rtw89_chan *target_chan) 6829 { 6830 int sel = -1; 6831 u8 i; 6832 6833 for (i = 0; i < desc_nr; i++) { 6834 struct rfk_chan_iter_data iter_data = { 6835 .desc = desc[i], 6836 }; 6837 6838 if (rfk_chan_is_equivalent(&desc[i], target_chan)) 6839 return i; 6840 6841 rtw89_iterate_entity_chan(rtwdev, rfk_chan_iter_search, &iter_data); 6842 if (!iter_data.found && sel == -1) 6843 sel = i; 6844 } 6845 6846 if (sel == -1) { 6847 rtw89_debug(rtwdev, RTW89_DBG_RFK, 6848 "no idle rfk entry; force replace the first\n"); 6849 sel = 0; 6850 } 6851 6852 return sel; 6853 } 6854 EXPORT_SYMBOL(rtw89_rfk_chan_lookup); 6855 6856 static void 6857 _rfk_write_rf(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 6858 { 6859 rtw89_write_rf(rtwdev, def->path, def->addr, def->mask, def->data); 6860 } 6861 6862 static void 6863 _rfk_write32_mask(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 6864 { 6865 rtw89_phy_write32_mask(rtwdev, def->addr, def->mask, def->data); 6866 } 6867 6868 static void 6869 _rfk_write32_set(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 6870 { 6871 rtw89_phy_write32_set(rtwdev, def->addr, def->mask); 6872 } 6873 6874 static void 6875 _rfk_write32_clr(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 6876 { 6877 rtw89_phy_write32_clr(rtwdev, def->addr, def->mask); 6878 } 6879 6880 static void 6881 _rfk_delay(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 6882 { 6883 udelay(def->data); 6884 } 6885 6886 static void 6887 (*_rfk_handler[])(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) = { 6888 [RTW89_RFK_F_WRF] = _rfk_write_rf, 6889 [RTW89_RFK_F_WM] = _rfk_write32_mask, 6890 [RTW89_RFK_F_WS] = _rfk_write32_set, 6891 [RTW89_RFK_F_WC] = _rfk_write32_clr, 6892 [RTW89_RFK_F_DELAY] = _rfk_delay, 6893 }; 6894 6895 static_assert(ARRAY_SIZE(_rfk_handler) == RTW89_RFK_F_NUM); 6896 6897 void 6898 rtw89_rfk_parser(struct rtw89_dev *rtwdev, const struct rtw89_rfk_tbl *tbl) 6899 { 6900 const struct rtw89_reg5_def *p = tbl->defs; 6901 const struct rtw89_reg5_def *end = tbl->defs + tbl->size; 6902 6903 for (; p < end; p++) 6904 _rfk_handler[p->flag](rtwdev, p); 6905 } 6906 EXPORT_SYMBOL(rtw89_rfk_parser); 6907 6908 #define RTW89_TSSI_FAST_MODE_NUM 4 6909 6910 static const struct rtw89_reg_def rtw89_tssi_fastmode_regs_flat[RTW89_TSSI_FAST_MODE_NUM] = { 6911 {0xD934, 0xff0000}, 6912 {0xD934, 0xff000000}, 6913 {0xD938, 0xff}, 6914 {0xD934, 0xff00}, 6915 }; 6916 6917 static const struct rtw89_reg_def rtw89_tssi_fastmode_regs_level[RTW89_TSSI_FAST_MODE_NUM] = { 6918 {0xD930, 0xff0000}, 6919 {0xD930, 0xff000000}, 6920 {0xD934, 0xff}, 6921 {0xD930, 0xff00}, 6922 }; 6923 6924 static 6925 void rtw89_phy_tssi_ctrl_set_fast_mode_cfg(struct rtw89_dev *rtwdev, 6926 enum rtw89_mac_idx mac_idx, 6927 enum rtw89_tssi_bandedge_cfg bandedge_cfg, 6928 u32 val) 6929 { 6930 const struct rtw89_reg_def *regs; 6931 u32 reg; 6932 int i; 6933 6934 if (bandedge_cfg == RTW89_TSSI_BANDEDGE_FLAT) 6935 regs = rtw89_tssi_fastmode_regs_flat; 6936 else 6937 regs = rtw89_tssi_fastmode_regs_level; 6938 6939 for (i = 0; i < RTW89_TSSI_FAST_MODE_NUM; i++) { 6940 reg = rtw89_mac_reg_by_idx(rtwdev, regs[i].addr, mac_idx); 6941 rtw89_write32_mask(rtwdev, reg, regs[i].mask, val); 6942 } 6943 } 6944 6945 static const struct rtw89_reg_def rtw89_tssi_bandedge_regs_flat[RTW89_TSSI_SBW_NUM] = { 6946 {0xD91C, 0xff000000}, 6947 {0xD920, 0xff}, 6948 {0xD920, 0xff00}, 6949 {0xD920, 0xff0000}, 6950 {0xD920, 0xff000000}, 6951 {0xD924, 0xff}, 6952 {0xD924, 0xff00}, 6953 {0xD914, 0xff000000}, 6954 {0xD918, 0xff}, 6955 {0xD918, 0xff00}, 6956 {0xD918, 0xff0000}, 6957 {0xD918, 0xff000000}, 6958 {0xD91C, 0xff}, 6959 {0xD91C, 0xff00}, 6960 {0xD91C, 0xff0000}, 6961 }; 6962 6963 static const struct rtw89_reg_def rtw89_tssi_bandedge_regs_level[RTW89_TSSI_SBW_NUM] = { 6964 {0xD910, 0xff}, 6965 {0xD910, 0xff00}, 6966 {0xD910, 0xff0000}, 6967 {0xD910, 0xff000000}, 6968 {0xD914, 0xff}, 6969 {0xD914, 0xff00}, 6970 {0xD914, 0xff0000}, 6971 {0xD908, 0xff}, 6972 {0xD908, 0xff00}, 6973 {0xD908, 0xff0000}, 6974 {0xD908, 0xff000000}, 6975 {0xD90C, 0xff}, 6976 {0xD90C, 0xff00}, 6977 {0xD90C, 0xff0000}, 6978 {0xD90C, 0xff000000}, 6979 }; 6980 6981 void rtw89_phy_tssi_ctrl_set_bandedge_cfg(struct rtw89_dev *rtwdev, 6982 enum rtw89_mac_idx mac_idx, 6983 enum rtw89_tssi_bandedge_cfg bandedge_cfg) 6984 { 6985 const struct rtw89_chip_info *chip = rtwdev->chip; 6986 const struct rtw89_reg_def *regs; 6987 const u32 *data; 6988 u32 reg; 6989 int i; 6990 6991 if (bandedge_cfg >= RTW89_TSSI_CFG_NUM) 6992 return; 6993 6994 if (bandedge_cfg == RTW89_TSSI_BANDEDGE_FLAT) 6995 regs = rtw89_tssi_bandedge_regs_flat; 6996 else 6997 regs = rtw89_tssi_bandedge_regs_level; 6998 6999 data = chip->tssi_dbw_table->data[bandedge_cfg]; 7000 7001 for (i = 0; i < RTW89_TSSI_SBW_NUM; i++) { 7002 reg = rtw89_mac_reg_by_idx(rtwdev, regs[i].addr, mac_idx); 7003 rtw89_write32_mask(rtwdev, reg, regs[i].mask, data[i]); 7004 } 7005 7006 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BANDEDGE_CFG, mac_idx); 7007 rtw89_write32_mask(rtwdev, reg, B_AX_BANDEDGE_CFG_IDX_MASK, bandedge_cfg); 7008 7009 rtw89_phy_tssi_ctrl_set_fast_mode_cfg(rtwdev, mac_idx, bandedge_cfg, 7010 data[RTW89_TSSI_SBW20]); 7011 } 7012 EXPORT_SYMBOL(rtw89_phy_tssi_ctrl_set_bandedge_cfg); 7013 7014 static 7015 const u8 rtw89_ch_base_table[16] = {1, 0xff, 7016 36, 100, 132, 149, 0xff, 7017 1, 33, 65, 97, 129, 161, 193, 225, 0xff}; 7018 #define RTW89_CH_BASE_IDX_2G 0 7019 #define RTW89_CH_BASE_IDX_5G_FIRST 2 7020 #define RTW89_CH_BASE_IDX_5G_LAST 5 7021 #define RTW89_CH_BASE_IDX_6G_FIRST 7 7022 #define RTW89_CH_BASE_IDX_6G_LAST 14 7023 7024 #define RTW89_CH_BASE_IDX_MASK GENMASK(7, 4) 7025 #define RTW89_CH_OFFSET_MASK GENMASK(3, 0) 7026 7027 u8 rtw89_encode_chan_idx(struct rtw89_dev *rtwdev, u8 central_ch, u8 band) 7028 { 7029 u8 chan_idx; 7030 u8 last, first; 7031 u8 idx; 7032 7033 switch (band) { 7034 case RTW89_BAND_2G: 7035 chan_idx = FIELD_PREP(RTW89_CH_BASE_IDX_MASK, RTW89_CH_BASE_IDX_2G) | 7036 FIELD_PREP(RTW89_CH_OFFSET_MASK, central_ch); 7037 return chan_idx; 7038 case RTW89_BAND_5G: 7039 first = RTW89_CH_BASE_IDX_5G_FIRST; 7040 last = RTW89_CH_BASE_IDX_5G_LAST; 7041 break; 7042 case RTW89_BAND_6G: 7043 first = RTW89_CH_BASE_IDX_6G_FIRST; 7044 last = RTW89_CH_BASE_IDX_6G_LAST; 7045 break; 7046 default: 7047 rtw89_warn(rtwdev, "Unsupported band %d\n", band); 7048 return 0; 7049 } 7050 7051 for (idx = last; idx >= first; idx--) 7052 if (central_ch >= rtw89_ch_base_table[idx]) 7053 break; 7054 7055 if (idx < first) { 7056 rtw89_warn(rtwdev, "Unknown band %d channel %d\n", band, central_ch); 7057 return 0; 7058 } 7059 7060 chan_idx = FIELD_PREP(RTW89_CH_BASE_IDX_MASK, idx) | 7061 FIELD_PREP(RTW89_CH_OFFSET_MASK, 7062 (central_ch - rtw89_ch_base_table[idx]) >> 1); 7063 return chan_idx; 7064 } 7065 EXPORT_SYMBOL(rtw89_encode_chan_idx); 7066 7067 void rtw89_decode_chan_idx(struct rtw89_dev *rtwdev, u8 chan_idx, 7068 u8 *ch, enum nl80211_band *band) 7069 { 7070 u8 idx, offset; 7071 7072 idx = FIELD_GET(RTW89_CH_BASE_IDX_MASK, chan_idx); 7073 offset = FIELD_GET(RTW89_CH_OFFSET_MASK, chan_idx); 7074 7075 if (idx == RTW89_CH_BASE_IDX_2G) { 7076 *band = NL80211_BAND_2GHZ; 7077 *ch = offset; 7078 return; 7079 } 7080 7081 *band = idx <= RTW89_CH_BASE_IDX_5G_LAST ? NL80211_BAND_5GHZ : NL80211_BAND_6GHZ; 7082 *ch = rtw89_ch_base_table[idx] + (offset << 1); 7083 } 7084 EXPORT_SYMBOL(rtw89_decode_chan_idx); 7085 7086 void rtw89_phy_config_edcca(struct rtw89_dev *rtwdev, 7087 struct rtw89_bb_ctx *bb, bool scan) 7088 { 7089 const struct rtw89_edcca_regs *edcca_regs = rtwdev->chip->edcca_regs; 7090 struct rtw89_edcca_bak *edcca_bak = &bb->edcca_bak; 7091 7092 if (scan) { 7093 edcca_bak->a = 7094 rtw89_phy_read32_idx(rtwdev, edcca_regs->edcca_level, 7095 edcca_regs->edcca_mask, bb->phy_idx); 7096 edcca_bak->p = 7097 rtw89_phy_read32_idx(rtwdev, edcca_regs->edcca_level, 7098 edcca_regs->edcca_p_mask, bb->phy_idx); 7099 edcca_bak->ppdu = 7100 rtw89_phy_read32_idx(rtwdev, edcca_regs->ppdu_level, 7101 edcca_regs->ppdu_mask, bb->phy_idx); 7102 7103 rtw89_phy_write32_idx(rtwdev, edcca_regs->edcca_level, 7104 edcca_regs->edcca_mask, EDCCA_MAX, bb->phy_idx); 7105 rtw89_phy_write32_idx(rtwdev, edcca_regs->edcca_level, 7106 edcca_regs->edcca_p_mask, EDCCA_MAX, bb->phy_idx); 7107 rtw89_phy_write32_idx(rtwdev, edcca_regs->ppdu_level, 7108 edcca_regs->ppdu_mask, EDCCA_MAX, bb->phy_idx); 7109 } else { 7110 rtw89_phy_write32_idx(rtwdev, edcca_regs->edcca_level, 7111 edcca_regs->edcca_mask, 7112 edcca_bak->a, bb->phy_idx); 7113 rtw89_phy_write32_idx(rtwdev, edcca_regs->edcca_level, 7114 edcca_regs->edcca_p_mask, 7115 edcca_bak->p, bb->phy_idx); 7116 rtw89_phy_write32_idx(rtwdev, edcca_regs->ppdu_level, 7117 edcca_regs->ppdu_mask, 7118 edcca_bak->ppdu, bb->phy_idx); 7119 } 7120 } 7121 7122 static void rtw89_phy_edcca_log(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *bb) 7123 { 7124 const struct rtw89_edcca_regs *edcca_regs = rtwdev->chip->edcca_regs; 7125 const struct rtw89_edcca_p_regs *edcca_p_regs; 7126 bool flag_fb, flag_p20, flag_s20, flag_s40, flag_s80; 7127 s8 pwdb_fb, pwdb_p20, pwdb_s20, pwdb_s40, pwdb_s80; 7128 u8 path, per20_bitmap; 7129 u8 pwdb[8]; 7130 u32 tmp; 7131 7132 if (!rtw89_debug_is_enabled(rtwdev, RTW89_DBG_EDCCA)) 7133 return; 7134 7135 if (bb->phy_idx == RTW89_PHY_1) 7136 edcca_p_regs = &edcca_regs->p[RTW89_PHY_1]; 7137 else 7138 edcca_p_regs = &edcca_regs->p[RTW89_PHY_0]; 7139 7140 if (rtwdev->chip->chip_id == RTL8922A) 7141 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel_be, 7142 edcca_regs->rpt_sel_be_mask, 0); 7143 7144 rtw89_phy_write32_mask(rtwdev, edcca_p_regs->rpt_sel, 7145 edcca_p_regs->rpt_sel_mask, 0); 7146 tmp = rtw89_phy_read32(rtwdev, edcca_p_regs->rpt_b); 7147 path = u32_get_bits(tmp, B_EDCCA_RPT_B_PATH_MASK); 7148 flag_s80 = u32_get_bits(tmp, B_EDCCA_RPT_B_S80); 7149 flag_s40 = u32_get_bits(tmp, B_EDCCA_RPT_B_S40); 7150 flag_s20 = u32_get_bits(tmp, B_EDCCA_RPT_B_S20); 7151 flag_p20 = u32_get_bits(tmp, B_EDCCA_RPT_B_P20); 7152 flag_fb = u32_get_bits(tmp, B_EDCCA_RPT_B_FB); 7153 pwdb_s20 = u32_get_bits(tmp, MASKBYTE1); 7154 pwdb_p20 = u32_get_bits(tmp, MASKBYTE2); 7155 pwdb_fb = u32_get_bits(tmp, MASKBYTE3); 7156 7157 rtw89_phy_write32_mask(rtwdev, edcca_p_regs->rpt_sel, 7158 edcca_p_regs->rpt_sel_mask, 4); 7159 tmp = rtw89_phy_read32(rtwdev, edcca_p_regs->rpt_b); 7160 pwdb_s80 = u32_get_bits(tmp, MASKBYTE1); 7161 pwdb_s40 = u32_get_bits(tmp, MASKBYTE2); 7162 7163 per20_bitmap = rtw89_phy_read32_mask(rtwdev, edcca_p_regs->rpt_a, 7164 MASKBYTE0); 7165 7166 if (rtwdev->chip->chip_id == RTL8922A) { 7167 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel_be, 7168 edcca_regs->rpt_sel_be_mask, 4); 7169 tmp = rtw89_phy_read32(rtwdev, edcca_p_regs->rpt_b); 7170 pwdb[0] = u32_get_bits(tmp, MASKBYTE3); 7171 pwdb[1] = u32_get_bits(tmp, MASKBYTE2); 7172 pwdb[2] = u32_get_bits(tmp, MASKBYTE1); 7173 pwdb[3] = u32_get_bits(tmp, MASKBYTE0); 7174 7175 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel_be, 7176 edcca_regs->rpt_sel_be_mask, 5); 7177 tmp = rtw89_phy_read32(rtwdev, edcca_p_regs->rpt_b); 7178 pwdb[4] = u32_get_bits(tmp, MASKBYTE3); 7179 pwdb[5] = u32_get_bits(tmp, MASKBYTE2); 7180 pwdb[6] = u32_get_bits(tmp, MASKBYTE1); 7181 pwdb[7] = u32_get_bits(tmp, MASKBYTE0); 7182 } else { 7183 rtw89_phy_write32_mask(rtwdev, edcca_p_regs->rpt_sel, 7184 edcca_p_regs->rpt_sel_mask, 0); 7185 tmp = rtw89_phy_read32(rtwdev, edcca_p_regs->rpt_a); 7186 pwdb[0] = u32_get_bits(tmp, MASKBYTE3); 7187 pwdb[1] = u32_get_bits(tmp, MASKBYTE2); 7188 7189 rtw89_phy_write32_mask(rtwdev, edcca_p_regs->rpt_sel, 7190 edcca_p_regs->rpt_sel_mask, 1); 7191 tmp = rtw89_phy_read32(rtwdev, edcca_p_regs->rpt_a); 7192 pwdb[2] = u32_get_bits(tmp, MASKBYTE3); 7193 pwdb[3] = u32_get_bits(tmp, MASKBYTE2); 7194 7195 rtw89_phy_write32_mask(rtwdev, edcca_p_regs->rpt_sel, 7196 edcca_p_regs->rpt_sel_mask, 2); 7197 tmp = rtw89_phy_read32(rtwdev, edcca_p_regs->rpt_a); 7198 pwdb[4] = u32_get_bits(tmp, MASKBYTE3); 7199 pwdb[5] = u32_get_bits(tmp, MASKBYTE2); 7200 7201 rtw89_phy_write32_mask(rtwdev, edcca_p_regs->rpt_sel, 7202 edcca_p_regs->rpt_sel_mask, 3); 7203 tmp = rtw89_phy_read32(rtwdev, edcca_p_regs->rpt_a); 7204 pwdb[6] = u32_get_bits(tmp, MASKBYTE3); 7205 pwdb[7] = u32_get_bits(tmp, MASKBYTE2); 7206 } 7207 7208 rtw89_debug(rtwdev, RTW89_DBG_EDCCA, 7209 "[EDCCA]: edcca_bitmap = %04x\n", per20_bitmap); 7210 7211 rtw89_debug(rtwdev, RTW89_DBG_EDCCA, 7212 "[EDCCA]: pwdb per20{0,1,2,3,4,5,6,7} = {%d,%d,%d,%d,%d,%d,%d,%d}(dBm)\n", 7213 pwdb[0], pwdb[1], pwdb[2], pwdb[3], pwdb[4], pwdb[5], 7214 pwdb[6], pwdb[7]); 7215 7216 rtw89_debug(rtwdev, RTW89_DBG_EDCCA, 7217 "[EDCCA]: path=%d, flag {FB,p20,s20,s40,s80} = {%d,%d,%d,%d,%d}\n", 7218 path, flag_fb, flag_p20, flag_s20, flag_s40, flag_s80); 7219 7220 rtw89_debug(rtwdev, RTW89_DBG_EDCCA, 7221 "[EDCCA]: pwdb {FB,p20,s20,s40,s80} = {%d,%d,%d,%d,%d}(dBm)\n", 7222 pwdb_fb, pwdb_p20, pwdb_s20, pwdb_s40, pwdb_s80); 7223 } 7224 7225 static u8 rtw89_phy_edcca_get_thre_by_rssi(struct rtw89_dev *rtwdev, 7226 struct rtw89_bb_ctx *bb) 7227 { 7228 struct rtw89_phy_ch_info *ch_info = &bb->ch_info; 7229 bool is_linked = rtwdev->total_sta_assoc > 0; 7230 u8 rssi_min = ch_info->rssi_min >> 1; 7231 u8 edcca_thre; 7232 7233 if (!is_linked) { 7234 edcca_thre = EDCCA_MAX; 7235 } else { 7236 edcca_thre = rssi_min - RSSI_UNIT_CONVER + EDCCA_UNIT_CONVER - 7237 EDCCA_TH_REF; 7238 edcca_thre = max_t(u8, edcca_thre, EDCCA_TH_L2H_LB); 7239 } 7240 7241 return edcca_thre; 7242 } 7243 7244 void rtw89_phy_edcca_thre_calc(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *bb) 7245 { 7246 const struct rtw89_edcca_regs *edcca_regs = rtwdev->chip->edcca_regs; 7247 struct rtw89_edcca_bak *edcca_bak = &bb->edcca_bak; 7248 u8 th; 7249 7250 th = rtw89_phy_edcca_get_thre_by_rssi(rtwdev, bb); 7251 if (th == edcca_bak->th_old) 7252 return; 7253 7254 edcca_bak->th_old = th; 7255 7256 rtw89_debug(rtwdev, RTW89_DBG_EDCCA, 7257 "[EDCCA]: Normal Mode, EDCCA_th = %d\n", th); 7258 7259 rtw89_phy_write32_idx(rtwdev, edcca_regs->edcca_level, 7260 edcca_regs->edcca_mask, th, bb->phy_idx); 7261 rtw89_phy_write32_idx(rtwdev, edcca_regs->edcca_level, 7262 edcca_regs->edcca_p_mask, th, bb->phy_idx); 7263 rtw89_phy_write32_idx(rtwdev, edcca_regs->ppdu_level, 7264 edcca_regs->ppdu_mask, th, bb->phy_idx); 7265 } 7266 7267 static 7268 void __rtw89_phy_edcca_track(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *bb) 7269 { 7270 rtw89_debug(rtwdev, RTW89_DBG_EDCCA, "BB-%d edcca track\n", bb->phy_idx); 7271 7272 rtw89_phy_edcca_thre_calc(rtwdev, bb); 7273 rtw89_phy_edcca_log(rtwdev, bb); 7274 } 7275 7276 void rtw89_phy_edcca_track(struct rtw89_dev *rtwdev) 7277 { 7278 struct rtw89_hal *hal = &rtwdev->hal; 7279 struct rtw89_bb_ctx *bb; 7280 7281 if (hal->disabled_dm_bitmap & BIT(RTW89_DM_DYNAMIC_EDCCA)) 7282 return; 7283 7284 rtw89_for_each_active_bb(rtwdev, bb) 7285 __rtw89_phy_edcca_track(rtwdev, bb); 7286 } 7287 7288 enum rtw89_rf_path_bit rtw89_phy_get_kpath(struct rtw89_dev *rtwdev, 7289 enum rtw89_phy_idx phy_idx) 7290 { 7291 rtw89_debug(rtwdev, RTW89_DBG_RFK, 7292 "[RFK] kpath dbcc_en: 0x%x, mode=0x%x, PHY%d\n", 7293 rtwdev->dbcc_en, rtwdev->mlo_dbcc_mode, phy_idx); 7294 7295 switch (rtwdev->mlo_dbcc_mode) { 7296 case MLO_1_PLUS_1_1RF: 7297 if (phy_idx == RTW89_PHY_0) 7298 return RF_A; 7299 else 7300 return RF_B; 7301 case MLO_1_PLUS_1_2RF: 7302 if (phy_idx == RTW89_PHY_0) 7303 return RF_A; 7304 else 7305 return RF_D; 7306 case MLO_0_PLUS_2_1RF: 7307 case MLO_2_PLUS_0_1RF: 7308 /* for both PHY 0/1 */ 7309 return RF_AB; 7310 case MLO_0_PLUS_2_2RF: 7311 case MLO_2_PLUS_0_2RF: 7312 case MLO_2_PLUS_2_2RF: 7313 default: 7314 if (phy_idx == RTW89_PHY_0) 7315 return RF_AB; 7316 else 7317 return RF_CD; 7318 } 7319 } 7320 EXPORT_SYMBOL(rtw89_phy_get_kpath); 7321 7322 enum rtw89_rf_path rtw89_phy_get_syn_sel(struct rtw89_dev *rtwdev, 7323 enum rtw89_phy_idx phy_idx) 7324 { 7325 rtw89_debug(rtwdev, RTW89_DBG_RFK, 7326 "[RFK] kpath dbcc_en: 0x%x, mode=0x%x, PHY%d\n", 7327 rtwdev->dbcc_en, rtwdev->mlo_dbcc_mode, phy_idx); 7328 7329 switch (rtwdev->mlo_dbcc_mode) { 7330 case MLO_1_PLUS_1_1RF: 7331 if (phy_idx == RTW89_PHY_0) 7332 return RF_PATH_A; 7333 else 7334 return RF_PATH_B; 7335 case MLO_1_PLUS_1_2RF: 7336 if (phy_idx == RTW89_PHY_0) 7337 return RF_PATH_A; 7338 else 7339 return RF_PATH_D; 7340 case MLO_0_PLUS_2_1RF: 7341 case MLO_2_PLUS_0_1RF: 7342 if (phy_idx == RTW89_PHY_0) 7343 return RF_PATH_A; 7344 else 7345 return RF_PATH_B; 7346 case MLO_0_PLUS_2_2RF: 7347 case MLO_2_PLUS_0_2RF: 7348 case MLO_2_PLUS_2_2RF: 7349 default: 7350 if (phy_idx == RTW89_PHY_0) 7351 return RF_PATH_A; 7352 else 7353 return RF_PATH_C; 7354 } 7355 } 7356 EXPORT_SYMBOL(rtw89_phy_get_syn_sel); 7357 7358 static const struct rtw89_ccx_regs rtw89_ccx_regs_ax = { 7359 .setting_addr = R_CCX, 7360 .edcca_opt_mask = B_CCX_EDCCA_OPT_MSK, 7361 .measurement_trig_mask = B_MEASUREMENT_TRIG_MSK, 7362 .trig_opt_mask = B_CCX_TRIG_OPT_MSK, 7363 .en_mask = B_CCX_EN_MSK, 7364 .ifs_cnt_addr = R_IFS_COUNTER, 7365 .ifs_clm_period_mask = B_IFS_CLM_PERIOD_MSK, 7366 .ifs_clm_cnt_unit_mask = B_IFS_CLM_COUNTER_UNIT_MSK, 7367 .ifs_clm_cnt_clear_mask = B_IFS_COUNTER_CLR_MSK, 7368 .ifs_collect_en_mask = B_IFS_COLLECT_EN, 7369 .ifs_t1_addr = R_IFS_T1, 7370 .ifs_t1_th_h_mask = B_IFS_T1_TH_HIGH_MSK, 7371 .ifs_t1_en_mask = B_IFS_T1_EN_MSK, 7372 .ifs_t1_th_l_mask = B_IFS_T1_TH_LOW_MSK, 7373 .ifs_t2_addr = R_IFS_T2, 7374 .ifs_t2_th_h_mask = B_IFS_T2_TH_HIGH_MSK, 7375 .ifs_t2_en_mask = B_IFS_T2_EN_MSK, 7376 .ifs_t2_th_l_mask = B_IFS_T2_TH_LOW_MSK, 7377 .ifs_t3_addr = R_IFS_T3, 7378 .ifs_t3_th_h_mask = B_IFS_T3_TH_HIGH_MSK, 7379 .ifs_t3_en_mask = B_IFS_T3_EN_MSK, 7380 .ifs_t3_th_l_mask = B_IFS_T3_TH_LOW_MSK, 7381 .ifs_t4_addr = R_IFS_T4, 7382 .ifs_t4_th_h_mask = B_IFS_T4_TH_HIGH_MSK, 7383 .ifs_t4_en_mask = B_IFS_T4_EN_MSK, 7384 .ifs_t4_th_l_mask = B_IFS_T4_TH_LOW_MSK, 7385 .ifs_clm_tx_cnt_addr = R_IFS_CLM_TX_CNT, 7386 .ifs_clm_edcca_excl_cca_fa_mask = B_IFS_CLM_EDCCA_EXCLUDE_CCA_FA_MSK, 7387 .ifs_clm_tx_cnt_msk = B_IFS_CLM_TX_CNT_MSK, 7388 .ifs_clm_cca_addr = R_IFS_CLM_CCA, 7389 .ifs_clm_ofdmcca_excl_fa_mask = B_IFS_CLM_OFDMCCA_EXCLUDE_FA_MSK, 7390 .ifs_clm_cckcca_excl_fa_mask = B_IFS_CLM_CCKCCA_EXCLUDE_FA_MSK, 7391 .ifs_clm_fa_addr = R_IFS_CLM_FA, 7392 .ifs_clm_ofdm_fa_mask = B_IFS_CLM_OFDM_FA_MSK, 7393 .ifs_clm_cck_fa_mask = B_IFS_CLM_CCK_FA_MSK, 7394 .ifs_his_addr = R_IFS_HIS, 7395 .ifs_t4_his_mask = B_IFS_T4_HIS_MSK, 7396 .ifs_t3_his_mask = B_IFS_T3_HIS_MSK, 7397 .ifs_t2_his_mask = B_IFS_T2_HIS_MSK, 7398 .ifs_t1_his_mask = B_IFS_T1_HIS_MSK, 7399 .ifs_avg_l_addr = R_IFS_AVG_L, 7400 .ifs_t2_avg_mask = B_IFS_T2_AVG_MSK, 7401 .ifs_t1_avg_mask = B_IFS_T1_AVG_MSK, 7402 .ifs_avg_h_addr = R_IFS_AVG_H, 7403 .ifs_t4_avg_mask = B_IFS_T4_AVG_MSK, 7404 .ifs_t3_avg_mask = B_IFS_T3_AVG_MSK, 7405 .ifs_cca_l_addr = R_IFS_CCA_L, 7406 .ifs_t2_cca_mask = B_IFS_T2_CCA_MSK, 7407 .ifs_t1_cca_mask = B_IFS_T1_CCA_MSK, 7408 .ifs_cca_h_addr = R_IFS_CCA_H, 7409 .ifs_t4_cca_mask = B_IFS_T4_CCA_MSK, 7410 .ifs_t3_cca_mask = B_IFS_T3_CCA_MSK, 7411 .ifs_total_addr = R_IFSCNT, 7412 .ifs_cnt_done_mask = B_IFSCNT_DONE_MSK, 7413 .ifs_total_mask = B_IFSCNT_TOTAL_CNT_MSK, 7414 }; 7415 7416 static const struct rtw89_physts_regs rtw89_physts_regs_ax = { 7417 .setting_addr = R_PLCP_HISTOGRAM, 7418 .dis_trigger_fail_mask = B_STS_DIS_TRIG_BY_FAIL, 7419 .dis_trigger_brk_mask = B_STS_DIS_TRIG_BY_BRK, 7420 }; 7421 7422 static const struct rtw89_cfo_regs rtw89_cfo_regs_ax = { 7423 .comp = R_DCFO_WEIGHT, 7424 .weighting_mask = B_DCFO_WEIGHT_MSK, 7425 .comp_seg0 = R_DCFO_OPT, 7426 .valid_0_mask = B_DCFO_OPT_EN, 7427 }; 7428 7429 const struct rtw89_phy_gen_def rtw89_phy_gen_ax = { 7430 .cr_base = 0x10000, 7431 .ccx = &rtw89_ccx_regs_ax, 7432 .physts = &rtw89_physts_regs_ax, 7433 .cfo = &rtw89_cfo_regs_ax, 7434 .phy0_phy1_offset = rtw89_phy0_phy1_offset_ax, 7435 .config_bb_gain = rtw89_phy_config_bb_gain_ax, 7436 .preinit_rf_nctl = rtw89_phy_preinit_rf_nctl_ax, 7437 .bb_wrap_init = NULL, 7438 .ch_info_init = NULL, 7439 7440 .set_txpwr_byrate = rtw89_phy_set_txpwr_byrate_ax, 7441 .set_txpwr_offset = rtw89_phy_set_txpwr_offset_ax, 7442 .set_txpwr_limit = rtw89_phy_set_txpwr_limit_ax, 7443 .set_txpwr_limit_ru = rtw89_phy_set_txpwr_limit_ru_ax, 7444 }; 7445 EXPORT_SYMBOL(rtw89_phy_gen_ax); 7446