1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 #include <linux/ip.h> 5 #include <linux/udp.h> 6 7 #include "cam.h" 8 #include "chan.h" 9 #include "coex.h" 10 #include "core.h" 11 #include "efuse.h" 12 #include "fw.h" 13 #include "mac.h" 14 #include "phy.h" 15 #include "ps.h" 16 #include "reg.h" 17 #include "sar.h" 18 #include "ser.h" 19 #include "txrx.h" 20 #include "util.h" 21 #include "wow.h" 22 23 static bool rtw89_disable_ps_mode; 24 module_param_named(disable_ps_mode, rtw89_disable_ps_mode, bool, 0644); 25 MODULE_PARM_DESC(disable_ps_mode, "Set Y to disable low power mode"); 26 27 #define RTW89_DEF_CHAN(_freq, _hw_val, _flags, _band) \ 28 { .center_freq = _freq, .hw_value = _hw_val, .flags = _flags, .band = _band, } 29 #define RTW89_DEF_CHAN_2G(_freq, _hw_val) \ 30 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_2GHZ) 31 #define RTW89_DEF_CHAN_5G(_freq, _hw_val) \ 32 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_5GHZ) 33 #define RTW89_DEF_CHAN_5G_NO_HT40MINUS(_freq, _hw_val) \ 34 RTW89_DEF_CHAN(_freq, _hw_val, IEEE80211_CHAN_NO_HT40MINUS, NL80211_BAND_5GHZ) 35 #define RTW89_DEF_CHAN_6G(_freq, _hw_val) \ 36 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_6GHZ) 37 38 static struct ieee80211_channel rtw89_channels_2ghz[] = { 39 RTW89_DEF_CHAN_2G(2412, 1), 40 RTW89_DEF_CHAN_2G(2417, 2), 41 RTW89_DEF_CHAN_2G(2422, 3), 42 RTW89_DEF_CHAN_2G(2427, 4), 43 RTW89_DEF_CHAN_2G(2432, 5), 44 RTW89_DEF_CHAN_2G(2437, 6), 45 RTW89_DEF_CHAN_2G(2442, 7), 46 RTW89_DEF_CHAN_2G(2447, 8), 47 RTW89_DEF_CHAN_2G(2452, 9), 48 RTW89_DEF_CHAN_2G(2457, 10), 49 RTW89_DEF_CHAN_2G(2462, 11), 50 RTW89_DEF_CHAN_2G(2467, 12), 51 RTW89_DEF_CHAN_2G(2472, 13), 52 RTW89_DEF_CHAN_2G(2484, 14), 53 }; 54 55 static struct ieee80211_channel rtw89_channels_5ghz[] = { 56 RTW89_DEF_CHAN_5G(5180, 36), 57 RTW89_DEF_CHAN_5G(5200, 40), 58 RTW89_DEF_CHAN_5G(5220, 44), 59 RTW89_DEF_CHAN_5G(5240, 48), 60 RTW89_DEF_CHAN_5G(5260, 52), 61 RTW89_DEF_CHAN_5G(5280, 56), 62 RTW89_DEF_CHAN_5G(5300, 60), 63 RTW89_DEF_CHAN_5G(5320, 64), 64 RTW89_DEF_CHAN_5G(5500, 100), 65 RTW89_DEF_CHAN_5G(5520, 104), 66 RTW89_DEF_CHAN_5G(5540, 108), 67 RTW89_DEF_CHAN_5G(5560, 112), 68 RTW89_DEF_CHAN_5G(5580, 116), 69 RTW89_DEF_CHAN_5G(5600, 120), 70 RTW89_DEF_CHAN_5G(5620, 124), 71 RTW89_DEF_CHAN_5G(5640, 128), 72 RTW89_DEF_CHAN_5G(5660, 132), 73 RTW89_DEF_CHAN_5G(5680, 136), 74 RTW89_DEF_CHAN_5G(5700, 140), 75 RTW89_DEF_CHAN_5G(5720, 144), 76 RTW89_DEF_CHAN_5G(5745, 149), 77 RTW89_DEF_CHAN_5G(5765, 153), 78 RTW89_DEF_CHAN_5G(5785, 157), 79 RTW89_DEF_CHAN_5G(5805, 161), 80 RTW89_DEF_CHAN_5G_NO_HT40MINUS(5825, 165), 81 RTW89_DEF_CHAN_5G(5845, 169), 82 RTW89_DEF_CHAN_5G(5865, 173), 83 RTW89_DEF_CHAN_5G(5885, 177), 84 }; 85 86 static_assert(RTW89_5GHZ_UNII4_START_INDEX + RTW89_5GHZ_UNII4_CHANNEL_NUM == 87 ARRAY_SIZE(rtw89_channels_5ghz)); 88 89 static struct ieee80211_channel rtw89_channels_6ghz[] = { 90 RTW89_DEF_CHAN_6G(5955, 1), 91 RTW89_DEF_CHAN_6G(5975, 5), 92 RTW89_DEF_CHAN_6G(5995, 9), 93 RTW89_DEF_CHAN_6G(6015, 13), 94 RTW89_DEF_CHAN_6G(6035, 17), 95 RTW89_DEF_CHAN_6G(6055, 21), 96 RTW89_DEF_CHAN_6G(6075, 25), 97 RTW89_DEF_CHAN_6G(6095, 29), 98 RTW89_DEF_CHAN_6G(6115, 33), 99 RTW89_DEF_CHAN_6G(6135, 37), 100 RTW89_DEF_CHAN_6G(6155, 41), 101 RTW89_DEF_CHAN_6G(6175, 45), 102 RTW89_DEF_CHAN_6G(6195, 49), 103 RTW89_DEF_CHAN_6G(6215, 53), 104 RTW89_DEF_CHAN_6G(6235, 57), 105 RTW89_DEF_CHAN_6G(6255, 61), 106 RTW89_DEF_CHAN_6G(6275, 65), 107 RTW89_DEF_CHAN_6G(6295, 69), 108 RTW89_DEF_CHAN_6G(6315, 73), 109 RTW89_DEF_CHAN_6G(6335, 77), 110 RTW89_DEF_CHAN_6G(6355, 81), 111 RTW89_DEF_CHAN_6G(6375, 85), 112 RTW89_DEF_CHAN_6G(6395, 89), 113 RTW89_DEF_CHAN_6G(6415, 93), 114 RTW89_DEF_CHAN_6G(6435, 97), 115 RTW89_DEF_CHAN_6G(6455, 101), 116 RTW89_DEF_CHAN_6G(6475, 105), 117 RTW89_DEF_CHAN_6G(6495, 109), 118 RTW89_DEF_CHAN_6G(6515, 113), 119 RTW89_DEF_CHAN_6G(6535, 117), 120 RTW89_DEF_CHAN_6G(6555, 121), 121 RTW89_DEF_CHAN_6G(6575, 125), 122 RTW89_DEF_CHAN_6G(6595, 129), 123 RTW89_DEF_CHAN_6G(6615, 133), 124 RTW89_DEF_CHAN_6G(6635, 137), 125 RTW89_DEF_CHAN_6G(6655, 141), 126 RTW89_DEF_CHAN_6G(6675, 145), 127 RTW89_DEF_CHAN_6G(6695, 149), 128 RTW89_DEF_CHAN_6G(6715, 153), 129 RTW89_DEF_CHAN_6G(6735, 157), 130 RTW89_DEF_CHAN_6G(6755, 161), 131 RTW89_DEF_CHAN_6G(6775, 165), 132 RTW89_DEF_CHAN_6G(6795, 169), 133 RTW89_DEF_CHAN_6G(6815, 173), 134 RTW89_DEF_CHAN_6G(6835, 177), 135 RTW89_DEF_CHAN_6G(6855, 181), 136 RTW89_DEF_CHAN_6G(6875, 185), 137 RTW89_DEF_CHAN_6G(6895, 189), 138 RTW89_DEF_CHAN_6G(6915, 193), 139 RTW89_DEF_CHAN_6G(6935, 197), 140 RTW89_DEF_CHAN_6G(6955, 201), 141 RTW89_DEF_CHAN_6G(6975, 205), 142 RTW89_DEF_CHAN_6G(6995, 209), 143 RTW89_DEF_CHAN_6G(7015, 213), 144 RTW89_DEF_CHAN_6G(7035, 217), 145 RTW89_DEF_CHAN_6G(7055, 221), 146 RTW89_DEF_CHAN_6G(7075, 225), 147 RTW89_DEF_CHAN_6G(7095, 229), 148 RTW89_DEF_CHAN_6G(7115, 233), 149 }; 150 151 static struct ieee80211_rate rtw89_bitrates[] = { 152 { .bitrate = 10, .hw_value = 0x00, }, 153 { .bitrate = 20, .hw_value = 0x01, }, 154 { .bitrate = 55, .hw_value = 0x02, }, 155 { .bitrate = 110, .hw_value = 0x03, }, 156 { .bitrate = 60, .hw_value = 0x04, }, 157 { .bitrate = 90, .hw_value = 0x05, }, 158 { .bitrate = 120, .hw_value = 0x06, }, 159 { .bitrate = 180, .hw_value = 0x07, }, 160 { .bitrate = 240, .hw_value = 0x08, }, 161 { .bitrate = 360, .hw_value = 0x09, }, 162 { .bitrate = 480, .hw_value = 0x0a, }, 163 { .bitrate = 540, .hw_value = 0x0b, }, 164 }; 165 166 static const struct ieee80211_iface_limit rtw89_iface_limits[] = { 167 { 168 .max = 1, 169 .types = BIT(NL80211_IFTYPE_STATION), 170 }, 171 { 172 .max = 1, 173 .types = BIT(NL80211_IFTYPE_P2P_CLIENT) | 174 BIT(NL80211_IFTYPE_P2P_GO) | 175 BIT(NL80211_IFTYPE_AP), 176 }, 177 }; 178 179 static const struct ieee80211_iface_limit rtw89_iface_limits_mcc[] = { 180 { 181 .max = 1, 182 .types = BIT(NL80211_IFTYPE_STATION), 183 }, 184 { 185 .max = 1, 186 .types = BIT(NL80211_IFTYPE_P2P_CLIENT) | 187 BIT(NL80211_IFTYPE_P2P_GO), 188 }, 189 }; 190 191 static const struct ieee80211_iface_combination rtw89_iface_combs[] = { 192 { 193 .limits = rtw89_iface_limits, 194 .n_limits = ARRAY_SIZE(rtw89_iface_limits), 195 .max_interfaces = RTW89_MAX_INTERFACE_NUM, 196 .num_different_channels = 1, 197 }, 198 { 199 .limits = rtw89_iface_limits_mcc, 200 .n_limits = ARRAY_SIZE(rtw89_iface_limits_mcc), 201 .max_interfaces = RTW89_MAX_INTERFACE_NUM, 202 .num_different_channels = 2, 203 }, 204 }; 205 206 static const u8 rtw89_ext_capa_sta[] = { 207 [2] = WLAN_EXT_CAPA3_MULTI_BSSID_SUPPORT, 208 [7] = WLAN_EXT_CAPA8_OPMODE_NOTIF, 209 }; 210 211 static const struct wiphy_iftype_ext_capab rtw89_iftypes_ext_capa[] = { 212 { 213 .iftype = NL80211_IFTYPE_STATION, 214 .extended_capabilities = rtw89_ext_capa_sta, 215 .extended_capabilities_mask = rtw89_ext_capa_sta, 216 .extended_capabilities_len = sizeof(rtw89_ext_capa_sta), 217 /* relevant only if EHT is supported */ 218 .eml_capabilities = 0, 219 .mld_capa_and_ops = 0, 220 }, 221 }; 222 223 #define RTW89_6GHZ_SPAN_HEAD 6145 224 #define RTW89_6GHZ_SPAN_IDX(center_freq) \ 225 ((((int)(center_freq) - RTW89_6GHZ_SPAN_HEAD) / 5) / 2) 226 227 #define RTW89_DECL_6GHZ_SPAN(center_freq, subband_l, subband_h) \ 228 [RTW89_6GHZ_SPAN_IDX(center_freq)] = { \ 229 .sar_subband_low = RTW89_SAR_6GHZ_ ## subband_l, \ 230 .sar_subband_high = RTW89_SAR_6GHZ_ ## subband_h, \ 231 .acpi_sar_subband_low = RTW89_ACPI_SAR_6GHZ_ ## subband_l, \ 232 .acpi_sar_subband_high = RTW89_ACPI_SAR_6GHZ_ ## subband_h, \ 233 .ant_gain_subband_low = RTW89_ANT_GAIN_6GHZ_ ## subband_l, \ 234 .ant_gain_subband_high = RTW89_ANT_GAIN_6GHZ_ ## subband_h, \ 235 } 236 237 /* Since 6GHz subbands are not edge aligned, some cases span two subbands. 238 * In the following, we describe each of them with rtw89_6ghz_span. 239 */ 240 static const struct rtw89_6ghz_span rtw89_overlapping_6ghz[] = { 241 RTW89_DECL_6GHZ_SPAN(6145, SUBBAND_5_L, SUBBAND_5_H), 242 RTW89_DECL_6GHZ_SPAN(6165, SUBBAND_5_L, SUBBAND_5_H), 243 RTW89_DECL_6GHZ_SPAN(6185, SUBBAND_5_L, SUBBAND_5_H), 244 RTW89_DECL_6GHZ_SPAN(6505, SUBBAND_6, SUBBAND_7_L), 245 RTW89_DECL_6GHZ_SPAN(6525, SUBBAND_6, SUBBAND_7_L), 246 RTW89_DECL_6GHZ_SPAN(6545, SUBBAND_6, SUBBAND_7_L), 247 RTW89_DECL_6GHZ_SPAN(6665, SUBBAND_7_L, SUBBAND_7_H), 248 RTW89_DECL_6GHZ_SPAN(6705, SUBBAND_7_L, SUBBAND_7_H), 249 RTW89_DECL_6GHZ_SPAN(6825, SUBBAND_7_H, SUBBAND_8), 250 RTW89_DECL_6GHZ_SPAN(6865, SUBBAND_7_H, SUBBAND_8), 251 RTW89_DECL_6GHZ_SPAN(6875, SUBBAND_7_H, SUBBAND_8), 252 RTW89_DECL_6GHZ_SPAN(6885, SUBBAND_7_H, SUBBAND_8), 253 }; 254 255 const struct rtw89_6ghz_span * 256 rtw89_get_6ghz_span(struct rtw89_dev *rtwdev, u32 center_freq) 257 { 258 int idx; 259 260 if (center_freq >= RTW89_6GHZ_SPAN_HEAD) { 261 idx = RTW89_6GHZ_SPAN_IDX(center_freq); 262 /* To decrease size of rtw89_overlapping_6ghz[], 263 * RTW89_6GHZ_SPAN_IDX() truncates the leading NULLs 264 * to make first span as index 0 of the table. So, if center 265 * frequency is less than the first one, it will get netative. 266 */ 267 if (idx >= 0 && idx < ARRAY_SIZE(rtw89_overlapping_6ghz)) 268 return &rtw89_overlapping_6ghz[idx]; 269 } 270 271 return NULL; 272 } 273 274 bool rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate, u16 *bitrate) 275 { 276 struct ieee80211_rate rate; 277 278 if (unlikely(rpt_rate >= ARRAY_SIZE(rtw89_bitrates))) { 279 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, "invalid rpt rate %d\n", rpt_rate); 280 return false; 281 } 282 283 rate = rtw89_bitrates[rpt_rate]; 284 *bitrate = rate.bitrate; 285 286 return true; 287 } 288 289 static const struct ieee80211_supported_band rtw89_sband_2ghz = { 290 .band = NL80211_BAND_2GHZ, 291 .channels = rtw89_channels_2ghz, 292 .n_channels = ARRAY_SIZE(rtw89_channels_2ghz), 293 .bitrates = rtw89_bitrates, 294 .n_bitrates = ARRAY_SIZE(rtw89_bitrates), 295 .ht_cap = {0}, 296 .vht_cap = {0}, 297 }; 298 299 static const struct ieee80211_supported_band rtw89_sband_5ghz = { 300 .band = NL80211_BAND_5GHZ, 301 .channels = rtw89_channels_5ghz, 302 .n_channels = ARRAY_SIZE(rtw89_channels_5ghz), 303 304 /* 5G has no CCK rates, 1M/2M/5.5M/11M */ 305 .bitrates = rtw89_bitrates + 4, 306 .n_bitrates = ARRAY_SIZE(rtw89_bitrates) - 4, 307 .ht_cap = {0}, 308 .vht_cap = {0}, 309 }; 310 311 static const struct ieee80211_supported_band rtw89_sband_6ghz = { 312 .band = NL80211_BAND_6GHZ, 313 .channels = rtw89_channels_6ghz, 314 .n_channels = ARRAY_SIZE(rtw89_channels_6ghz), 315 316 /* 6G has no CCK rates, 1M/2M/5.5M/11M */ 317 .bitrates = rtw89_bitrates + 4, 318 .n_bitrates = ARRAY_SIZE(rtw89_bitrates) - 4, 319 }; 320 321 static void rtw89_traffic_stats_accu(struct rtw89_dev *rtwdev, 322 struct rtw89_traffic_stats *stats, 323 struct sk_buff *skb, bool tx) 324 { 325 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 326 327 if (tx && ieee80211_is_assoc_req(hdr->frame_control)) 328 rtw89_wow_parse_akm(rtwdev, skb); 329 330 if (!ieee80211_is_data(hdr->frame_control)) 331 return; 332 333 if (is_broadcast_ether_addr(hdr->addr1) || 334 is_multicast_ether_addr(hdr->addr1)) 335 return; 336 337 if (tx) { 338 stats->tx_cnt++; 339 stats->tx_unicast += skb->len; 340 } else { 341 stats->rx_cnt++; 342 stats->rx_unicast += skb->len; 343 } 344 } 345 346 void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef) 347 { 348 cfg80211_chandef_create(chandef, &rtw89_channels_2ghz[0], 349 NL80211_CHAN_NO_HT); 350 } 351 352 void rtw89_get_channel_params(const struct cfg80211_chan_def *chandef, 353 struct rtw89_chan *chan) 354 { 355 struct ieee80211_channel *channel = chandef->chan; 356 enum nl80211_chan_width width = chandef->width; 357 u32 primary_freq, center_freq; 358 u8 center_chan; 359 u8 bandwidth = RTW89_CHANNEL_WIDTH_20; 360 u32 offset; 361 u8 band; 362 363 center_chan = channel->hw_value; 364 primary_freq = channel->center_freq; 365 center_freq = chandef->center_freq1; 366 367 switch (width) { 368 case NL80211_CHAN_WIDTH_20_NOHT: 369 case NL80211_CHAN_WIDTH_20: 370 bandwidth = RTW89_CHANNEL_WIDTH_20; 371 break; 372 case NL80211_CHAN_WIDTH_40: 373 bandwidth = RTW89_CHANNEL_WIDTH_40; 374 if (primary_freq > center_freq) { 375 center_chan -= 2; 376 } else { 377 center_chan += 2; 378 } 379 break; 380 case NL80211_CHAN_WIDTH_80: 381 case NL80211_CHAN_WIDTH_160: 382 bandwidth = nl_to_rtw89_bandwidth(width); 383 if (primary_freq > center_freq) { 384 offset = (primary_freq - center_freq - 10) / 20; 385 center_chan -= 2 + offset * 4; 386 } else { 387 offset = (center_freq - primary_freq - 10) / 20; 388 center_chan += 2 + offset * 4; 389 } 390 break; 391 default: 392 center_chan = 0; 393 break; 394 } 395 396 switch (channel->band) { 397 default: 398 case NL80211_BAND_2GHZ: 399 band = RTW89_BAND_2G; 400 break; 401 case NL80211_BAND_5GHZ: 402 band = RTW89_BAND_5G; 403 break; 404 case NL80211_BAND_6GHZ: 405 band = RTW89_BAND_6G; 406 break; 407 } 408 409 rtw89_chan_create(chan, center_chan, channel->hw_value, band, bandwidth); 410 } 411 412 static void __rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev, 413 const struct rtw89_chan *chan, 414 enum rtw89_phy_idx phy_idx) 415 { 416 const struct rtw89_chip_info *chip = rtwdev->chip; 417 bool entity_active; 418 419 entity_active = rtw89_get_entity_state(rtwdev, phy_idx); 420 if (!entity_active) 421 return; 422 423 chip->ops->set_txpwr(rtwdev, chan, phy_idx); 424 } 425 426 void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev) 427 { 428 const struct rtw89_chan *chan; 429 430 chan = rtw89_mgnt_chan_get(rtwdev, 0); 431 __rtw89_core_set_chip_txpwr(rtwdev, chan, RTW89_PHY_0); 432 433 if (!rtwdev->support_mlo) 434 return; 435 436 chan = rtw89_mgnt_chan_get(rtwdev, 1); 437 __rtw89_core_set_chip_txpwr(rtwdev, chan, RTW89_PHY_1); 438 } 439 440 static void __rtw89_set_channel(struct rtw89_dev *rtwdev, 441 const struct rtw89_chan *chan, 442 enum rtw89_mac_idx mac_idx, 443 enum rtw89_phy_idx phy_idx) 444 { 445 const struct rtw89_chip_info *chip = rtwdev->chip; 446 const struct rtw89_chan_rcd *chan_rcd; 447 struct rtw89_channel_help_params bak; 448 bool entity_active; 449 450 entity_active = rtw89_get_entity_state(rtwdev, phy_idx); 451 452 chan_rcd = rtw89_chan_rcd_get_by_chan(chan); 453 454 rtw89_chip_set_channel_prepare(rtwdev, &bak, chan, mac_idx, phy_idx); 455 456 chip->ops->set_channel(rtwdev, chan, mac_idx, phy_idx); 457 458 chip->ops->set_txpwr(rtwdev, chan, phy_idx); 459 460 rtw89_chip_set_channel_done(rtwdev, &bak, chan, mac_idx, phy_idx); 461 462 if (!entity_active || chan_rcd->band_changed) { 463 rtw89_btc_ntfy_switch_band(rtwdev, phy_idx, chan->band_type); 464 rtw89_chip_rfk_band_changed(rtwdev, phy_idx, chan); 465 } 466 467 rtw89_set_entity_state(rtwdev, phy_idx, true); 468 } 469 470 int rtw89_set_channel(struct rtw89_dev *rtwdev) 471 { 472 const struct rtw89_chan *chan; 473 enum rtw89_entity_mode mode; 474 475 mode = rtw89_entity_recalc(rtwdev); 476 if (mode < 0 || mode >= NUM_OF_RTW89_ENTITY_MODE) { 477 WARN(1, "Invalid ent mode: %d\n", mode); 478 return -EINVAL; 479 } 480 481 chan = rtw89_mgnt_chan_get(rtwdev, 0); 482 __rtw89_set_channel(rtwdev, chan, RTW89_MAC_0, RTW89_PHY_0); 483 484 if (!rtwdev->support_mlo) 485 return 0; 486 487 chan = rtw89_mgnt_chan_get(rtwdev, 1); 488 __rtw89_set_channel(rtwdev, chan, RTW89_MAC_1, RTW89_PHY_1); 489 490 return 0; 491 } 492 493 static enum rtw89_core_tx_type 494 rtw89_core_get_tx_type(struct rtw89_dev *rtwdev, 495 struct sk_buff *skb) 496 { 497 struct ieee80211_hdr *hdr = (void *)skb->data; 498 __le16 fc = hdr->frame_control; 499 500 if (ieee80211_is_mgmt(fc) || ieee80211_is_nullfunc(fc)) 501 return RTW89_CORE_TX_TYPE_MGMT; 502 503 return RTW89_CORE_TX_TYPE_DATA; 504 } 505 506 static void 507 rtw89_core_tx_update_ampdu_info(struct rtw89_dev *rtwdev, 508 struct rtw89_core_tx_request *tx_req, 509 enum btc_pkt_type pkt_type) 510 { 511 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link; 512 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 513 struct ieee80211_link_sta *link_sta; 514 struct sk_buff *skb = tx_req->skb; 515 struct rtw89_sta *rtwsta; 516 u8 ampdu_num; 517 u8 tid; 518 519 if (pkt_type == PACKET_EAPOL) { 520 desc_info->bk = true; 521 return; 522 } 523 524 if (!(IEEE80211_SKB_CB(skb)->flags & IEEE80211_TX_CTL_AMPDU)) 525 return; 526 527 if (!rtwsta_link) { 528 rtw89_warn(rtwdev, "cannot set ampdu info without sta\n"); 529 return; 530 } 531 532 tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK; 533 rtwsta = rtwsta_link->rtwsta; 534 535 rcu_read_lock(); 536 537 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, false); 538 ampdu_num = (u8)((rtwsta->ampdu_params[tid].agg_num ? 539 rtwsta->ampdu_params[tid].agg_num : 540 4 << link_sta->ht_cap.ampdu_factor) - 1); 541 542 desc_info->agg_en = true; 543 desc_info->ampdu_density = link_sta->ht_cap.ampdu_density; 544 desc_info->ampdu_num = ampdu_num; 545 546 rcu_read_unlock(); 547 } 548 549 static void 550 rtw89_core_tx_update_sec_key(struct rtw89_dev *rtwdev, 551 struct rtw89_core_tx_request *tx_req) 552 { 553 struct rtw89_cam_info *cam_info = &rtwdev->cam_info; 554 const struct rtw89_chip_info *chip = rtwdev->chip; 555 const struct rtw89_sec_cam_entry *sec_cam; 556 struct ieee80211_tx_info *info; 557 struct ieee80211_key_conf *key; 558 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 559 struct sk_buff *skb = tx_req->skb; 560 u8 sec_type = RTW89_SEC_KEY_TYPE_NONE; 561 u8 sec_cam_idx; 562 u64 pn64; 563 564 info = IEEE80211_SKB_CB(skb); 565 key = info->control.hw_key; 566 sec_cam_idx = key->hw_key_idx; 567 sec_cam = cam_info->sec_entries[sec_cam_idx]; 568 if (!sec_cam) { 569 rtw89_warn(rtwdev, "sec cam entry is empty\n"); 570 return; 571 } 572 573 switch (key->cipher) { 574 case WLAN_CIPHER_SUITE_WEP40: 575 sec_type = RTW89_SEC_KEY_TYPE_WEP40; 576 break; 577 case WLAN_CIPHER_SUITE_WEP104: 578 sec_type = RTW89_SEC_KEY_TYPE_WEP104; 579 break; 580 case WLAN_CIPHER_SUITE_TKIP: 581 sec_type = RTW89_SEC_KEY_TYPE_TKIP; 582 break; 583 case WLAN_CIPHER_SUITE_CCMP: 584 sec_type = RTW89_SEC_KEY_TYPE_CCMP128; 585 break; 586 case WLAN_CIPHER_SUITE_CCMP_256: 587 sec_type = RTW89_SEC_KEY_TYPE_CCMP256; 588 break; 589 case WLAN_CIPHER_SUITE_GCMP: 590 sec_type = RTW89_SEC_KEY_TYPE_GCMP128; 591 break; 592 case WLAN_CIPHER_SUITE_GCMP_256: 593 sec_type = RTW89_SEC_KEY_TYPE_GCMP256; 594 break; 595 default: 596 rtw89_warn(rtwdev, "key cipher not supported %d\n", key->cipher); 597 return; 598 } 599 600 desc_info->sec_en = true; 601 desc_info->sec_keyid = key->keyidx; 602 desc_info->sec_type = sec_type; 603 desc_info->sec_cam_idx = sec_cam->sec_cam_idx; 604 605 if (!chip->hw_sec_hdr) 606 return; 607 608 pn64 = atomic64_inc_return(&key->tx_pn); 609 desc_info->sec_seq[0] = pn64; 610 desc_info->sec_seq[1] = pn64 >> 8; 611 desc_info->sec_seq[2] = pn64 >> 16; 612 desc_info->sec_seq[3] = pn64 >> 24; 613 desc_info->sec_seq[4] = pn64 >> 32; 614 desc_info->sec_seq[5] = pn64 >> 40; 615 desc_info->wp_offset = 1; /* in unit of 8 bytes for security header */ 616 } 617 618 static u16 rtw89_core_get_mgmt_rate(struct rtw89_dev *rtwdev, 619 struct rtw89_core_tx_request *tx_req, 620 const struct rtw89_chan *chan) 621 { 622 struct sk_buff *skb = tx_req->skb; 623 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link; 624 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link; 625 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 626 struct ieee80211_vif *vif = tx_info->control.vif; 627 struct ieee80211_bss_conf *bss_conf; 628 u16 lowest_rate; 629 u16 rate; 630 631 if (tx_info->flags & IEEE80211_TX_CTL_NO_CCK_RATE || 632 (vif && vif->p2p)) 633 lowest_rate = RTW89_HW_RATE_OFDM6; 634 else if (chan->band_type == RTW89_BAND_2G) 635 lowest_rate = RTW89_HW_RATE_CCK1; 636 else 637 lowest_rate = RTW89_HW_RATE_OFDM6; 638 639 if (!rtwvif_link) 640 return lowest_rate; 641 642 rcu_read_lock(); 643 644 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, false); 645 if (!bss_conf->basic_rates || !rtwsta_link) { 646 rate = lowest_rate; 647 goto out; 648 } 649 650 rate = __ffs(bss_conf->basic_rates) + lowest_rate; 651 652 out: 653 rcu_read_unlock(); 654 655 return rate; 656 } 657 658 static u8 rtw89_core_tx_get_mac_id(struct rtw89_dev *rtwdev, 659 struct rtw89_core_tx_request *tx_req) 660 { 661 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 662 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link; 663 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link; 664 665 if (desc_info->mlo && !desc_info->sw_mld) { 666 if (rtwsta_link) 667 return rtw89_sta_get_main_macid(rtwsta_link->rtwsta); 668 else 669 return rtw89_vif_get_main_macid(rtwvif_link->rtwvif); 670 } 671 672 if (!rtwsta_link) 673 return rtwvif_link->mac_id; 674 675 return rtwsta_link->mac_id; 676 } 677 678 static void rtw89_core_tx_update_llc_hdr(struct rtw89_dev *rtwdev, 679 struct rtw89_tx_desc_info *desc_info, 680 struct sk_buff *skb) 681 { 682 struct ieee80211_hdr *hdr = (void *)skb->data; 683 __le16 fc = hdr->frame_control; 684 685 desc_info->hdr_llc_len = ieee80211_hdrlen(fc); 686 desc_info->hdr_llc_len >>= 1; /* in unit of 2 bytes */ 687 } 688 689 static void 690 rtw89_core_tx_update_mgmt_info(struct rtw89_dev *rtwdev, 691 struct rtw89_core_tx_request *tx_req) 692 { 693 const struct rtw89_chip_info *chip = rtwdev->chip; 694 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link; 695 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 696 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, 697 rtwvif_link->chanctx_idx); 698 struct sk_buff *skb = tx_req->skb; 699 u8 qsel, ch_dma; 700 701 qsel = rtw89_core_get_qsel_mgmt(rtwdev, tx_req); 702 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); 703 704 desc_info->qsel = qsel; 705 desc_info->ch_dma = ch_dma; 706 desc_info->port = desc_info->hiq ? rtwvif_link->port : 0; 707 desc_info->mac_id = rtw89_core_tx_get_mac_id(rtwdev, tx_req); 708 desc_info->hw_ssn_sel = RTW89_MGMT_HW_SSN_SEL; 709 desc_info->hw_seq_mode = RTW89_MGMT_HW_SEQ_MODE; 710 711 /* fixed data rate for mgmt frames */ 712 desc_info->en_wd_info = true; 713 desc_info->use_rate = true; 714 desc_info->dis_data_fb = true; 715 desc_info->data_rate = rtw89_core_get_mgmt_rate(rtwdev, tx_req, chan); 716 717 if (chip->hw_mgmt_tx_encrypt && IEEE80211_SKB_CB(skb)->control.hw_key) { 718 rtw89_core_tx_update_sec_key(rtwdev, tx_req); 719 rtw89_core_tx_update_llc_hdr(rtwdev, desc_info, skb); 720 } 721 722 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 723 "tx mgmt frame with rate 0x%x on channel %d (band %d, bw %d)\n", 724 desc_info->data_rate, chan->channel, chan->band_type, 725 chan->band_width); 726 } 727 728 static void 729 rtw89_core_tx_update_h2c_info(struct rtw89_dev *rtwdev, 730 struct rtw89_core_tx_request *tx_req) 731 { 732 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 733 734 desc_info->is_bmc = false; 735 desc_info->wd_page = false; 736 desc_info->ch_dma = RTW89_DMA_H2C; 737 } 738 739 static void rtw89_core_get_no_ul_ofdma_htc(struct rtw89_dev *rtwdev, __le32 *htc, 740 const struct rtw89_chan *chan) 741 { 742 static const u8 rtw89_bandwidth_to_om[] = { 743 [RTW89_CHANNEL_WIDTH_20] = HTC_OM_CHANNEL_WIDTH_20, 744 [RTW89_CHANNEL_WIDTH_40] = HTC_OM_CHANNEL_WIDTH_40, 745 [RTW89_CHANNEL_WIDTH_80] = HTC_OM_CHANNEL_WIDTH_80, 746 [RTW89_CHANNEL_WIDTH_160] = HTC_OM_CHANNEL_WIDTH_160_OR_80_80, 747 [RTW89_CHANNEL_WIDTH_80_80] = HTC_OM_CHANNEL_WIDTH_160_OR_80_80, 748 }; 749 const struct rtw89_chip_info *chip = rtwdev->chip; 750 struct rtw89_hal *hal = &rtwdev->hal; 751 u8 om_bandwidth; 752 753 if (!chip->dis_2g_40m_ul_ofdma || 754 chan->band_type != RTW89_BAND_2G || 755 chan->band_width != RTW89_CHANNEL_WIDTH_40) 756 return; 757 758 om_bandwidth = chan->band_width < ARRAY_SIZE(rtw89_bandwidth_to_om) ? 759 rtw89_bandwidth_to_om[chan->band_width] : 0; 760 *htc = le32_encode_bits(RTW89_HTC_VARIANT_HE, RTW89_HTC_MASK_VARIANT) | 761 le32_encode_bits(RTW89_HTC_VARIANT_HE_CID_OM, RTW89_HTC_MASK_CTL_ID) | 762 le32_encode_bits(hal->rx_nss - 1, RTW89_HTC_MASK_HTC_OM_RX_NSS) | 763 le32_encode_bits(om_bandwidth, RTW89_HTC_MASK_HTC_OM_CH_WIDTH) | 764 le32_encode_bits(1, RTW89_HTC_MASK_HTC_OM_UL_MU_DIS) | 765 le32_encode_bits(hal->tx_nss - 1, RTW89_HTC_MASK_HTC_OM_TX_NSTS) | 766 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_ER_SU_DIS) | 767 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR) | 768 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS); 769 } 770 771 static bool 772 __rtw89_core_tx_check_he_qos_htc(struct rtw89_dev *rtwdev, 773 struct rtw89_core_tx_request *tx_req, 774 enum btc_pkt_type pkt_type) 775 { 776 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link; 777 struct sk_buff *skb = tx_req->skb; 778 struct ieee80211_hdr *hdr = (void *)skb->data; 779 struct ieee80211_link_sta *link_sta; 780 __le16 fc = hdr->frame_control; 781 782 /* AP IOT issue with EAPoL, ARP and DHCP */ 783 if (pkt_type < PACKET_MAX) 784 return false; 785 786 if (!rtwsta_link) 787 return false; 788 789 rcu_read_lock(); 790 791 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, false); 792 if (!link_sta->he_cap.has_he) { 793 rcu_read_unlock(); 794 return false; 795 } 796 797 rcu_read_unlock(); 798 799 if (!ieee80211_is_data_qos(fc)) 800 return false; 801 802 if (skb_headroom(skb) < IEEE80211_HT_CTL_LEN) 803 return false; 804 805 if (rtwsta_link && rtwsta_link->ra_report.might_fallback_legacy) 806 return false; 807 808 return true; 809 } 810 811 static void 812 __rtw89_core_tx_adjust_he_qos_htc(struct rtw89_dev *rtwdev, 813 struct rtw89_core_tx_request *tx_req) 814 { 815 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link; 816 struct sk_buff *skb = tx_req->skb; 817 struct ieee80211_hdr *hdr = (void *)skb->data; 818 __le16 fc = hdr->frame_control; 819 void *data; 820 __le32 *htc; 821 u8 *qc; 822 int hdr_len; 823 824 hdr_len = ieee80211_has_a4(fc) ? 32 : 26; 825 data = skb_push(skb, IEEE80211_HT_CTL_LEN); 826 memmove(data, data + IEEE80211_HT_CTL_LEN, hdr_len); 827 828 hdr = data; 829 htc = data + hdr_len; 830 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_ORDER); 831 *htc = rtwsta_link->htc_template ? rtwsta_link->htc_template : 832 le32_encode_bits(RTW89_HTC_VARIANT_HE, RTW89_HTC_MASK_VARIANT) | 833 le32_encode_bits(RTW89_HTC_VARIANT_HE_CID_CAS, RTW89_HTC_MASK_CTL_ID); 834 835 qc = data + hdr_len - IEEE80211_QOS_CTL_LEN; 836 qc[0] |= IEEE80211_QOS_CTL_EOSP; 837 } 838 839 static void 840 rtw89_core_tx_update_he_qos_htc(struct rtw89_dev *rtwdev, 841 struct rtw89_core_tx_request *tx_req, 842 enum btc_pkt_type pkt_type) 843 { 844 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 845 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link; 846 847 if (!__rtw89_core_tx_check_he_qos_htc(rtwdev, tx_req, pkt_type)) 848 goto desc_bk; 849 850 __rtw89_core_tx_adjust_he_qos_htc(rtwdev, tx_req); 851 852 desc_info->pkt_size += IEEE80211_HT_CTL_LEN; 853 desc_info->a_ctrl_bsr = true; 854 855 desc_bk: 856 if (!rtwvif_link || rtwvif_link->last_a_ctrl == desc_info->a_ctrl_bsr) 857 return; 858 859 rtwvif_link->last_a_ctrl = desc_info->a_ctrl_bsr; 860 desc_info->bk = true; 861 } 862 863 static u16 rtw89_core_get_data_rate(struct rtw89_dev *rtwdev, 864 struct rtw89_core_tx_request *tx_req) 865 { 866 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link; 867 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link; 868 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 869 struct rtw89_phy_rate_pattern *rate_pattern = &rtwvif_link->rate_pattern; 870 enum rtw89_chanctx_idx idx = rtwvif_link->chanctx_idx; 871 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, idx); 872 struct ieee80211_link_sta *link_sta; 873 u16 lowest_rate; 874 u16 rate; 875 876 if (rate_pattern->enable) 877 return rate_pattern->rate; 878 879 if (vif->p2p) 880 lowest_rate = RTW89_HW_RATE_OFDM6; 881 else if (chan->band_type == RTW89_BAND_2G) 882 lowest_rate = RTW89_HW_RATE_CCK1; 883 else 884 lowest_rate = RTW89_HW_RATE_OFDM6; 885 886 if (!rtwsta_link) 887 return lowest_rate; 888 889 rcu_read_lock(); 890 891 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, false); 892 if (!link_sta->supp_rates[chan->band_type]) { 893 rate = lowest_rate; 894 goto out; 895 } 896 897 rate = __ffs(link_sta->supp_rates[chan->band_type]) + lowest_rate; 898 899 out: 900 rcu_read_unlock(); 901 902 return rate; 903 } 904 905 static void 906 rtw89_core_tx_update_data_info(struct rtw89_dev *rtwdev, 907 struct rtw89_core_tx_request *tx_req) 908 { 909 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link; 910 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link; 911 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 912 struct sk_buff *skb = tx_req->skb; 913 u8 tid, tid_indicate; 914 u8 qsel, ch_dma; 915 916 tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK; 917 tid_indicate = rtw89_core_get_tid_indicate(rtwdev, tid); 918 qsel = desc_info->hiq ? RTW89_TX_QSEL_B0_HI : rtw89_core_get_qsel(rtwdev, tid); 919 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); 920 921 desc_info->ch_dma = ch_dma; 922 desc_info->tid_indicate = tid_indicate; 923 desc_info->qsel = qsel; 924 desc_info->mac_id = rtw89_core_tx_get_mac_id(rtwdev, tx_req); 925 desc_info->port = desc_info->hiq ? rtwvif_link->port : 0; 926 desc_info->er_cap = rtwsta_link ? rtwsta_link->er_cap : false; 927 desc_info->stbc = rtwsta_link ? rtwsta_link->ra.stbc_cap : false; 928 desc_info->ldpc = rtwsta_link ? rtwsta_link->ra.ldpc_cap : false; 929 930 /* enable wd_info for AMPDU */ 931 desc_info->en_wd_info = true; 932 933 if (IEEE80211_SKB_CB(skb)->control.hw_key) 934 rtw89_core_tx_update_sec_key(rtwdev, tx_req); 935 936 desc_info->data_retry_lowest_rate = rtw89_core_get_data_rate(rtwdev, tx_req); 937 } 938 939 static enum btc_pkt_type 940 rtw89_core_tx_btc_spec_pkt_notify(struct rtw89_dev *rtwdev, 941 struct rtw89_core_tx_request *tx_req) 942 { 943 struct wiphy *wiphy = rtwdev->hw->wiphy; 944 struct sk_buff *skb = tx_req->skb; 945 struct udphdr *udphdr; 946 947 if (IEEE80211_SKB_CB(skb)->control.flags & IEEE80211_TX_CTRL_PORT_CTRL_PROTO) { 948 wiphy_work_queue(wiphy, &rtwdev->btc.eapol_notify_work); 949 return PACKET_EAPOL; 950 } 951 952 if (skb->protocol == htons(ETH_P_ARP)) { 953 wiphy_work_queue(wiphy, &rtwdev->btc.arp_notify_work); 954 return PACKET_ARP; 955 } 956 957 if (skb->protocol == htons(ETH_P_IP) && 958 ip_hdr(skb)->protocol == IPPROTO_UDP) { 959 udphdr = udp_hdr(skb); 960 if (((udphdr->source == htons(67) && udphdr->dest == htons(68)) || 961 (udphdr->source == htons(68) && udphdr->dest == htons(67))) && 962 skb->len > 282) { 963 wiphy_work_queue(wiphy, &rtwdev->btc.dhcp_notify_work); 964 return PACKET_DHCP; 965 } 966 } 967 968 if (skb->protocol == htons(ETH_P_IP) && 969 ip_hdr(skb)->protocol == IPPROTO_ICMP) { 970 wiphy_work_queue(wiphy, &rtwdev->btc.icmp_notify_work); 971 return PACKET_ICMP; 972 } 973 974 return PACKET_MAX; 975 } 976 977 static void 978 rtw89_core_tx_wake(struct rtw89_dev *rtwdev, 979 struct rtw89_core_tx_request *tx_req) 980 { 981 const struct rtw89_chip_info *chip = rtwdev->chip; 982 983 if (!RTW89_CHK_FW_FEATURE(TX_WAKE, &rtwdev->fw)) 984 return; 985 986 if (!test_bit(RTW89_FLAG_LOW_POWER_MODE, rtwdev->flags)) 987 return; 988 989 if (chip->chip_id != RTL8852C && 990 tx_req->tx_type != RTW89_CORE_TX_TYPE_MGMT) 991 return; 992 993 rtw89_mac_notify_wake(rtwdev); 994 } 995 996 static void 997 rtw89_core_tx_update_desc_info(struct rtw89_dev *rtwdev, 998 struct rtw89_core_tx_request *tx_req) 999 { 1000 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 1001 struct sk_buff *skb = tx_req->skb; 1002 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1003 struct ieee80211_hdr *hdr = (void *)skb->data; 1004 struct rtw89_addr_cam_entry *addr_cam; 1005 enum rtw89_core_tx_type tx_type; 1006 enum btc_pkt_type pkt_type; 1007 bool upd_wlan_hdr = false; 1008 bool is_bmc; 1009 u16 seq; 1010 1011 if (tx_req->sta) 1012 desc_info->mlo = tx_req->sta->mlo; 1013 else if (tx_req->vif) 1014 desc_info->mlo = ieee80211_vif_is_mld(tx_req->vif); 1015 1016 seq = (le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_SEQ) >> 4; 1017 if (tx_req->tx_type != RTW89_CORE_TX_TYPE_FWCMD) { 1018 tx_type = rtw89_core_get_tx_type(rtwdev, skb); 1019 tx_req->tx_type = tx_type; 1020 1021 addr_cam = rtw89_get_addr_cam_of(tx_req->rtwvif_link, 1022 tx_req->rtwsta_link); 1023 if (addr_cam->valid && desc_info->mlo) 1024 upd_wlan_hdr = true; 1025 } 1026 is_bmc = (is_broadcast_ether_addr(hdr->addr1) || 1027 is_multicast_ether_addr(hdr->addr1)); 1028 1029 desc_info->seq = seq; 1030 desc_info->pkt_size = skb->len; 1031 desc_info->is_bmc = is_bmc; 1032 desc_info->wd_page = true; 1033 desc_info->hiq = info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM; 1034 desc_info->upd_wlan_hdr = upd_wlan_hdr; 1035 1036 switch (tx_req->tx_type) { 1037 case RTW89_CORE_TX_TYPE_MGMT: 1038 rtw89_core_tx_update_mgmt_info(rtwdev, tx_req); 1039 break; 1040 case RTW89_CORE_TX_TYPE_DATA: 1041 rtw89_core_tx_update_data_info(rtwdev, tx_req); 1042 pkt_type = rtw89_core_tx_btc_spec_pkt_notify(rtwdev, tx_req); 1043 rtw89_core_tx_update_he_qos_htc(rtwdev, tx_req, pkt_type); 1044 rtw89_core_tx_update_ampdu_info(rtwdev, tx_req, pkt_type); 1045 rtw89_core_tx_update_llc_hdr(rtwdev, desc_info, skb); 1046 break; 1047 case RTW89_CORE_TX_TYPE_FWCMD: 1048 rtw89_core_tx_update_h2c_info(rtwdev, tx_req); 1049 break; 1050 } 1051 } 1052 1053 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel) 1054 { 1055 u8 ch_dma; 1056 1057 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); 1058 1059 rtw89_hci_tx_kick_off(rtwdev, ch_dma); 1060 } 1061 1062 int rtw89_core_tx_kick_off_and_wait(struct rtw89_dev *rtwdev, struct sk_buff *skb, 1063 int qsel, unsigned int timeout) 1064 { 1065 struct rtw89_tx_skb_data *skb_data = RTW89_TX_SKB_CB(skb); 1066 struct rtw89_tx_wait_info *wait; 1067 unsigned long time_left; 1068 int ret = 0; 1069 1070 wait = kzalloc(sizeof(*wait), GFP_KERNEL); 1071 if (!wait) { 1072 rtw89_core_tx_kick_off(rtwdev, qsel); 1073 return 0; 1074 } 1075 1076 init_completion(&wait->completion); 1077 rcu_assign_pointer(skb_data->wait, wait); 1078 1079 rtw89_core_tx_kick_off(rtwdev, qsel); 1080 time_left = wait_for_completion_timeout(&wait->completion, 1081 msecs_to_jiffies(timeout)); 1082 if (time_left == 0) 1083 ret = -ETIMEDOUT; 1084 else if (!wait->tx_done) 1085 ret = -EAGAIN; 1086 1087 rcu_assign_pointer(skb_data->wait, NULL); 1088 kfree_rcu(wait, rcu_head); 1089 1090 return ret; 1091 } 1092 1093 int rtw89_h2c_tx(struct rtw89_dev *rtwdev, 1094 struct sk_buff *skb, bool fwdl) 1095 { 1096 struct rtw89_core_tx_request tx_req = {0}; 1097 u32 cnt; 1098 int ret; 1099 1100 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) { 1101 rtw89_debug(rtwdev, RTW89_DBG_FW, 1102 "ignore h2c due to power is off with firmware state=%d\n", 1103 test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)); 1104 dev_kfree_skb(skb); 1105 return 0; 1106 } 1107 1108 tx_req.skb = skb; 1109 tx_req.tx_type = RTW89_CORE_TX_TYPE_FWCMD; 1110 if (fwdl) 1111 tx_req.desc_info.fw_dl = true; 1112 1113 rtw89_core_tx_update_desc_info(rtwdev, &tx_req); 1114 1115 if (!fwdl) 1116 rtw89_hex_dump(rtwdev, RTW89_DBG_FW, "H2C: ", skb->data, skb->len); 1117 1118 cnt = rtw89_hci_check_and_reclaim_tx_resource(rtwdev, RTW89_TXCH_CH12); 1119 if (cnt == 0) { 1120 rtw89_err(rtwdev, "no tx fwcmd resource\n"); 1121 return -ENOSPC; 1122 } 1123 1124 ret = rtw89_hci_tx_write(rtwdev, &tx_req); 1125 if (ret) { 1126 rtw89_err(rtwdev, "failed to transmit skb to HCI\n"); 1127 return ret; 1128 } 1129 rtw89_hci_tx_kick_off(rtwdev, RTW89_TXCH_CH12); 1130 1131 return 0; 1132 } 1133 1134 static int rtw89_core_tx_write_link(struct rtw89_dev *rtwdev, 1135 struct rtw89_vif_link *rtwvif_link, 1136 struct rtw89_sta_link *rtwsta_link, 1137 struct sk_buff *skb, int *qsel, bool sw_mld) 1138 { 1139 struct ieee80211_sta *sta = rtwsta_link_to_sta_safe(rtwsta_link); 1140 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 1141 struct rtw89_vif *rtwvif = rtwvif_link->rtwvif; 1142 struct rtw89_core_tx_request tx_req = {}; 1143 int ret; 1144 1145 tx_req.skb = skb; 1146 tx_req.vif = vif; 1147 tx_req.sta = sta; 1148 tx_req.rtwvif_link = rtwvif_link; 1149 tx_req.rtwsta_link = rtwsta_link; 1150 tx_req.desc_info.sw_mld = sw_mld; 1151 1152 rtw89_traffic_stats_accu(rtwdev, &rtwdev->stats, skb, true); 1153 rtw89_traffic_stats_accu(rtwdev, &rtwvif->stats, skb, true); 1154 rtw89_core_tx_update_desc_info(rtwdev, &tx_req); 1155 rtw89_core_tx_wake(rtwdev, &tx_req); 1156 1157 ret = rtw89_hci_tx_write(rtwdev, &tx_req); 1158 if (ret) { 1159 rtw89_err(rtwdev, "failed to transmit skb to HCI\n"); 1160 return ret; 1161 } 1162 1163 if (qsel) 1164 *qsel = tx_req.desc_info.qsel; 1165 1166 return 0; 1167 } 1168 1169 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 1170 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel) 1171 { 1172 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta); 1173 struct rtw89_vif *rtwvif = vif_to_rtwvif(vif); 1174 struct rtw89_sta_link *rtwsta_link = NULL; 1175 struct rtw89_vif_link *rtwvif_link; 1176 1177 if (rtwsta) { 1178 rtwsta_link = rtw89_get_designated_link(rtwsta); 1179 if (unlikely(!rtwsta_link)) { 1180 rtw89_err(rtwdev, "tx: find no sta designated link\n"); 1181 return -ENOLINK; 1182 } 1183 1184 rtwvif_link = rtwsta_link->rtwvif_link; 1185 } else { 1186 rtwvif_link = rtw89_get_designated_link(rtwvif); 1187 if (unlikely(!rtwvif_link)) { 1188 rtw89_err(rtwdev, "tx: find no vif designated link\n"); 1189 return -ENOLINK; 1190 } 1191 } 1192 1193 return rtw89_core_tx_write_link(rtwdev, rtwvif_link, rtwsta_link, skb, qsel, false); 1194 } 1195 1196 static __le32 rtw89_build_txwd_body0(struct rtw89_tx_desc_info *desc_info) 1197 { 1198 u32 dword = FIELD_PREP(RTW89_TXWD_BODY0_WP_OFFSET, desc_info->wp_offset) | 1199 FIELD_PREP(RTW89_TXWD_BODY0_WD_INFO_EN, desc_info->en_wd_info) | 1200 FIELD_PREP(RTW89_TXWD_BODY0_CHANNEL_DMA, desc_info->ch_dma) | 1201 FIELD_PREP(RTW89_TXWD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) | 1202 FIELD_PREP(RTW89_TXWD_BODY0_WD_PAGE, desc_info->wd_page) | 1203 FIELD_PREP(RTW89_TXWD_BODY0_FW_DL, desc_info->fw_dl) | 1204 FIELD_PREP(RTW89_TXWD_BODY0_HW_SSN_SEL, desc_info->hw_ssn_sel) | 1205 FIELD_PREP(RTW89_TXWD_BODY0_HW_SSN_MODE, desc_info->hw_seq_mode); 1206 1207 return cpu_to_le32(dword); 1208 } 1209 1210 static __le32 rtw89_build_txwd_body0_v1(struct rtw89_tx_desc_info *desc_info) 1211 { 1212 u32 dword = FIELD_PREP(RTW89_TXWD_BODY0_WP_OFFSET_V1, desc_info->wp_offset) | 1213 FIELD_PREP(RTW89_TXWD_BODY0_WD_INFO_EN, desc_info->en_wd_info) | 1214 FIELD_PREP(RTW89_TXWD_BODY0_CHANNEL_DMA, desc_info->ch_dma) | 1215 FIELD_PREP(RTW89_TXWD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) | 1216 FIELD_PREP(RTW89_TXWD_BODY0_WD_PAGE, desc_info->wd_page) | 1217 FIELD_PREP(RTW89_TXWD_BODY0_FW_DL, desc_info->fw_dl); 1218 1219 return cpu_to_le32(dword); 1220 } 1221 1222 static __le32 rtw89_build_txwd_body1_v1(struct rtw89_tx_desc_info *desc_info) 1223 { 1224 u32 dword = FIELD_PREP(RTW89_TXWD_BODY1_ADDR_INFO_NUM, desc_info->addr_info_nr) | 1225 FIELD_PREP(RTW89_TXWD_BODY1_SEC_KEYID, desc_info->sec_keyid) | 1226 FIELD_PREP(RTW89_TXWD_BODY1_SEC_TYPE, desc_info->sec_type); 1227 1228 return cpu_to_le32(dword); 1229 } 1230 1231 static __le32 rtw89_build_txwd_body2(struct rtw89_tx_desc_info *desc_info) 1232 { 1233 u32 dword = FIELD_PREP(RTW89_TXWD_BODY2_TID_INDICATE, desc_info->tid_indicate) | 1234 FIELD_PREP(RTW89_TXWD_BODY2_QSEL, desc_info->qsel) | 1235 FIELD_PREP(RTW89_TXWD_BODY2_TXPKT_SIZE, desc_info->pkt_size) | 1236 FIELD_PREP(RTW89_TXWD_BODY2_MACID, desc_info->mac_id); 1237 1238 return cpu_to_le32(dword); 1239 } 1240 1241 static __le32 rtw89_build_txwd_body3(struct rtw89_tx_desc_info *desc_info) 1242 { 1243 u32 dword = FIELD_PREP(RTW89_TXWD_BODY3_SW_SEQ, desc_info->seq) | 1244 FIELD_PREP(RTW89_TXWD_BODY3_AGG_EN, desc_info->agg_en) | 1245 FIELD_PREP(RTW89_TXWD_BODY3_BK, desc_info->bk); 1246 1247 return cpu_to_le32(dword); 1248 } 1249 1250 static __le32 rtw89_build_txwd_body4(struct rtw89_tx_desc_info *desc_info) 1251 { 1252 u32 dword = FIELD_PREP(RTW89_TXWD_BODY4_SEC_IV_L0, desc_info->sec_seq[0]) | 1253 FIELD_PREP(RTW89_TXWD_BODY4_SEC_IV_L1, desc_info->sec_seq[1]); 1254 1255 return cpu_to_le32(dword); 1256 } 1257 1258 static __le32 rtw89_build_txwd_body5(struct rtw89_tx_desc_info *desc_info) 1259 { 1260 u32 dword = FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H2, desc_info->sec_seq[2]) | 1261 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H3, desc_info->sec_seq[3]) | 1262 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H4, desc_info->sec_seq[4]) | 1263 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H5, desc_info->sec_seq[5]); 1264 1265 return cpu_to_le32(dword); 1266 } 1267 1268 static __le32 rtw89_build_txwd_body7_v1(struct rtw89_tx_desc_info *desc_info) 1269 { 1270 u32 dword = FIELD_PREP(RTW89_TXWD_BODY7_USE_RATE_V1, desc_info->use_rate) | 1271 FIELD_PREP(RTW89_TXWD_BODY7_DATA_RATE, desc_info->data_rate); 1272 1273 return cpu_to_le32(dword); 1274 } 1275 1276 static __le32 rtw89_build_txwd_info0(struct rtw89_tx_desc_info *desc_info) 1277 { 1278 u32 dword = FIELD_PREP(RTW89_TXWD_INFO0_USE_RATE, desc_info->use_rate) | 1279 FIELD_PREP(RTW89_TXWD_INFO0_DATA_RATE, desc_info->data_rate) | 1280 FIELD_PREP(RTW89_TXWD_INFO0_DATA_STBC, desc_info->stbc) | 1281 FIELD_PREP(RTW89_TXWD_INFO0_DATA_LDPC, desc_info->ldpc) | 1282 FIELD_PREP(RTW89_TXWD_INFO0_DISDATAFB, desc_info->dis_data_fb) | 1283 FIELD_PREP(RTW89_TXWD_INFO0_MULTIPORT_ID, desc_info->port); 1284 1285 return cpu_to_le32(dword); 1286 } 1287 1288 static __le32 rtw89_build_txwd_info0_v1(struct rtw89_tx_desc_info *desc_info) 1289 { 1290 u32 dword = FIELD_PREP(RTW89_TXWD_INFO0_DATA_STBC, desc_info->stbc) | 1291 FIELD_PREP(RTW89_TXWD_INFO0_DATA_LDPC, desc_info->ldpc) | 1292 FIELD_PREP(RTW89_TXWD_INFO0_DISDATAFB, desc_info->dis_data_fb) | 1293 FIELD_PREP(RTW89_TXWD_INFO0_MULTIPORT_ID, desc_info->port) | 1294 FIELD_PREP(RTW89_TXWD_INFO0_DATA_ER, desc_info->er_cap) | 1295 FIELD_PREP(RTW89_TXWD_INFO0_DATA_BW_ER, 0); 1296 1297 return cpu_to_le32(dword); 1298 } 1299 1300 static __le32 rtw89_build_txwd_info1(struct rtw89_tx_desc_info *desc_info) 1301 { 1302 u32 dword = FIELD_PREP(RTW89_TXWD_INFO1_MAX_AGGNUM, desc_info->ampdu_num) | 1303 FIELD_PREP(RTW89_TXWD_INFO1_A_CTRL_BSR, desc_info->a_ctrl_bsr) | 1304 FIELD_PREP(RTW89_TXWD_INFO1_DATA_RTY_LOWEST_RATE, 1305 desc_info->data_retry_lowest_rate); 1306 1307 return cpu_to_le32(dword); 1308 } 1309 1310 static __le32 rtw89_build_txwd_info2(struct rtw89_tx_desc_info *desc_info) 1311 { 1312 u32 dword = FIELD_PREP(RTW89_TXWD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) | 1313 FIELD_PREP(RTW89_TXWD_INFO2_SEC_TYPE, desc_info->sec_type) | 1314 FIELD_PREP(RTW89_TXWD_INFO2_SEC_HW_ENC, desc_info->sec_en) | 1315 FIELD_PREP(RTW89_TXWD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx); 1316 1317 return cpu_to_le32(dword); 1318 } 1319 1320 static __le32 rtw89_build_txwd_info2_v1(struct rtw89_tx_desc_info *desc_info) 1321 { 1322 u32 dword = FIELD_PREP(RTW89_TXWD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) | 1323 FIELD_PREP(RTW89_TXWD_INFO2_FORCE_KEY_EN, desc_info->sec_en) | 1324 FIELD_PREP(RTW89_TXWD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx); 1325 1326 return cpu_to_le32(dword); 1327 } 1328 1329 static __le32 rtw89_build_txwd_info4(struct rtw89_tx_desc_info *desc_info) 1330 { 1331 bool rts_en = !desc_info->is_bmc; 1332 u32 dword = FIELD_PREP(RTW89_TXWD_INFO4_RTS_EN, rts_en) | 1333 FIELD_PREP(RTW89_TXWD_INFO4_HW_RTS_EN, 1); 1334 1335 return cpu_to_le32(dword); 1336 } 1337 1338 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev, 1339 struct rtw89_tx_desc_info *desc_info, 1340 void *txdesc) 1341 { 1342 struct rtw89_txwd_body *txwd_body = (struct rtw89_txwd_body *)txdesc; 1343 struct rtw89_txwd_info *txwd_info; 1344 1345 txwd_body->dword0 = rtw89_build_txwd_body0(desc_info); 1346 txwd_body->dword2 = rtw89_build_txwd_body2(desc_info); 1347 txwd_body->dword3 = rtw89_build_txwd_body3(desc_info); 1348 1349 if (!desc_info->en_wd_info) 1350 return; 1351 1352 txwd_info = (struct rtw89_txwd_info *)(txwd_body + 1); 1353 txwd_info->dword0 = rtw89_build_txwd_info0(desc_info); 1354 txwd_info->dword1 = rtw89_build_txwd_info1(desc_info); 1355 txwd_info->dword2 = rtw89_build_txwd_info2(desc_info); 1356 txwd_info->dword4 = rtw89_build_txwd_info4(desc_info); 1357 1358 } 1359 EXPORT_SYMBOL(rtw89_core_fill_txdesc); 1360 1361 void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev, 1362 struct rtw89_tx_desc_info *desc_info, 1363 void *txdesc) 1364 { 1365 struct rtw89_txwd_body_v1 *txwd_body = (struct rtw89_txwd_body_v1 *)txdesc; 1366 struct rtw89_txwd_info *txwd_info; 1367 1368 txwd_body->dword0 = rtw89_build_txwd_body0_v1(desc_info); 1369 txwd_body->dword1 = rtw89_build_txwd_body1_v1(desc_info); 1370 txwd_body->dword2 = rtw89_build_txwd_body2(desc_info); 1371 txwd_body->dword3 = rtw89_build_txwd_body3(desc_info); 1372 if (desc_info->sec_en) { 1373 txwd_body->dword4 = rtw89_build_txwd_body4(desc_info); 1374 txwd_body->dword5 = rtw89_build_txwd_body5(desc_info); 1375 } 1376 txwd_body->dword7 = rtw89_build_txwd_body7_v1(desc_info); 1377 1378 if (!desc_info->en_wd_info) 1379 return; 1380 1381 txwd_info = (struct rtw89_txwd_info *)(txwd_body + 1); 1382 txwd_info->dword0 = rtw89_build_txwd_info0_v1(desc_info); 1383 txwd_info->dword1 = rtw89_build_txwd_info1(desc_info); 1384 txwd_info->dword2 = rtw89_build_txwd_info2_v1(desc_info); 1385 txwd_info->dword4 = rtw89_build_txwd_info4(desc_info); 1386 } 1387 EXPORT_SYMBOL(rtw89_core_fill_txdesc_v1); 1388 1389 static __le32 rtw89_build_txwd_body0_v2(struct rtw89_tx_desc_info *desc_info) 1390 { 1391 u32 dword = FIELD_PREP(BE_TXD_BODY0_WP_OFFSET_V1, desc_info->wp_offset) | 1392 FIELD_PREP(BE_TXD_BODY0_WDINFO_EN, desc_info->en_wd_info) | 1393 FIELD_PREP(BE_TXD_BODY0_CH_DMA, desc_info->ch_dma) | 1394 FIELD_PREP(BE_TXD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) | 1395 FIELD_PREP(BE_TXD_BODY0_WD_PAGE, desc_info->wd_page); 1396 1397 return cpu_to_le32(dword); 1398 } 1399 1400 static __le32 rtw89_build_txwd_body1_v2(struct rtw89_tx_desc_info *desc_info) 1401 { 1402 u32 dword = FIELD_PREP(BE_TXD_BODY1_ADDR_INFO_NUM, desc_info->addr_info_nr) | 1403 FIELD_PREP(BE_TXD_BODY1_SEC_KEYID, desc_info->sec_keyid) | 1404 FIELD_PREP(BE_TXD_BODY1_SEC_TYPE, desc_info->sec_type); 1405 1406 return cpu_to_le32(dword); 1407 } 1408 1409 static __le32 rtw89_build_txwd_body2_v2(struct rtw89_tx_desc_info *desc_info) 1410 { 1411 u32 dword = FIELD_PREP(BE_TXD_BODY2_TID_IND, desc_info->tid_indicate) | 1412 FIELD_PREP(BE_TXD_BODY2_QSEL, desc_info->qsel) | 1413 FIELD_PREP(BE_TXD_BODY2_TXPKTSIZE, desc_info->pkt_size) | 1414 FIELD_PREP(BE_TXD_BODY2_AGG_EN, desc_info->agg_en) | 1415 FIELD_PREP(BE_TXD_BODY2_BK, desc_info->bk) | 1416 FIELD_PREP(BE_TXD_BODY2_MACID, desc_info->mac_id); 1417 1418 return cpu_to_le32(dword); 1419 } 1420 1421 static __le32 rtw89_build_txwd_body3_v2(struct rtw89_tx_desc_info *desc_info) 1422 { 1423 u32 dword = FIELD_PREP(BE_TXD_BODY3_WIFI_SEQ, desc_info->seq) | 1424 FIELD_PREP(BE_TXD_BODY3_MLO_FLAG, desc_info->mlo) | 1425 FIELD_PREP(BE_TXD_BODY3_IS_MLD_SW_EN, desc_info->sw_mld); 1426 1427 return cpu_to_le32(dword); 1428 } 1429 1430 static __le32 rtw89_build_txwd_body4_v2(struct rtw89_tx_desc_info *desc_info) 1431 { 1432 u32 dword = FIELD_PREP(BE_TXD_BODY4_SEC_IV_L0, desc_info->sec_seq[0]) | 1433 FIELD_PREP(BE_TXD_BODY4_SEC_IV_L1, desc_info->sec_seq[1]); 1434 1435 return cpu_to_le32(dword); 1436 } 1437 1438 static __le32 rtw89_build_txwd_body5_v2(struct rtw89_tx_desc_info *desc_info) 1439 { 1440 u32 dword = FIELD_PREP(BE_TXD_BODY5_SEC_IV_H2, desc_info->sec_seq[2]) | 1441 FIELD_PREP(BE_TXD_BODY5_SEC_IV_H3, desc_info->sec_seq[3]) | 1442 FIELD_PREP(BE_TXD_BODY5_SEC_IV_H4, desc_info->sec_seq[4]) | 1443 FIELD_PREP(BE_TXD_BODY5_SEC_IV_H5, desc_info->sec_seq[5]); 1444 1445 return cpu_to_le32(dword); 1446 } 1447 1448 static __le32 rtw89_build_txwd_body6_v2(struct rtw89_tx_desc_info *desc_info) 1449 { 1450 u32 dword = FIELD_PREP(BE_TXD_BODY6_UPD_WLAN_HDR, desc_info->upd_wlan_hdr); 1451 1452 return cpu_to_le32(dword); 1453 } 1454 1455 static __le32 rtw89_build_txwd_body7_v2(struct rtw89_tx_desc_info *desc_info) 1456 { 1457 u32 dword = FIELD_PREP(BE_TXD_BODY7_USERATE_SEL, desc_info->use_rate) | 1458 FIELD_PREP(BE_TXD_BODY7_DATA_ER, desc_info->er_cap) | 1459 FIELD_PREP(BE_TXD_BODY7_DATA_BW_ER, 0) | 1460 FIELD_PREP(BE_TXD_BODY7_DATARATE, desc_info->data_rate); 1461 1462 return cpu_to_le32(dword); 1463 } 1464 1465 static __le32 rtw89_build_txwd_info0_v2(struct rtw89_tx_desc_info *desc_info) 1466 { 1467 u32 dword = FIELD_PREP(BE_TXD_INFO0_DATA_STBC, desc_info->stbc) | 1468 FIELD_PREP(BE_TXD_INFO0_DATA_LDPC, desc_info->ldpc) | 1469 FIELD_PREP(BE_TXD_INFO0_DISDATAFB, desc_info->dis_data_fb) | 1470 FIELD_PREP(BE_TXD_INFO0_MULTIPORT_ID, desc_info->port); 1471 1472 return cpu_to_le32(dword); 1473 } 1474 1475 static __le32 rtw89_build_txwd_info1_v2(struct rtw89_tx_desc_info *desc_info) 1476 { 1477 u32 dword = FIELD_PREP(BE_TXD_INFO1_MAX_AGG_NUM, desc_info->ampdu_num) | 1478 FIELD_PREP(BE_TXD_INFO1_A_CTRL_BSR, desc_info->a_ctrl_bsr) | 1479 FIELD_PREP(BE_TXD_INFO1_DATA_RTY_LOWEST_RATE, 1480 desc_info->data_retry_lowest_rate); 1481 1482 return cpu_to_le32(dword); 1483 } 1484 1485 static __le32 rtw89_build_txwd_info2_v2(struct rtw89_tx_desc_info *desc_info) 1486 { 1487 u32 dword = FIELD_PREP(BE_TXD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) | 1488 FIELD_PREP(BE_TXD_INFO2_FORCE_KEY_EN, desc_info->sec_en) | 1489 FIELD_PREP(BE_TXD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx); 1490 1491 return cpu_to_le32(dword); 1492 } 1493 1494 static __le32 rtw89_build_txwd_info4_v2(struct rtw89_tx_desc_info *desc_info) 1495 { 1496 bool rts_en = !desc_info->is_bmc; 1497 u32 dword = FIELD_PREP(BE_TXD_INFO4_RTS_EN, rts_en) | 1498 FIELD_PREP(BE_TXD_INFO4_HW_RTS_EN, 1); 1499 1500 return cpu_to_le32(dword); 1501 } 1502 1503 void rtw89_core_fill_txdesc_v2(struct rtw89_dev *rtwdev, 1504 struct rtw89_tx_desc_info *desc_info, 1505 void *txdesc) 1506 { 1507 struct rtw89_txwd_body_v2 *txwd_body = txdesc; 1508 struct rtw89_txwd_info_v2 *txwd_info; 1509 1510 txwd_body->dword0 = rtw89_build_txwd_body0_v2(desc_info); 1511 txwd_body->dword1 = rtw89_build_txwd_body1_v2(desc_info); 1512 txwd_body->dword2 = rtw89_build_txwd_body2_v2(desc_info); 1513 txwd_body->dword3 = rtw89_build_txwd_body3_v2(desc_info); 1514 if (desc_info->sec_en) { 1515 txwd_body->dword4 = rtw89_build_txwd_body4_v2(desc_info); 1516 txwd_body->dword5 = rtw89_build_txwd_body5_v2(desc_info); 1517 } 1518 txwd_body->dword6 = rtw89_build_txwd_body6_v2(desc_info); 1519 txwd_body->dword7 = rtw89_build_txwd_body7_v2(desc_info); 1520 1521 if (!desc_info->en_wd_info) 1522 return; 1523 1524 txwd_info = (struct rtw89_txwd_info_v2 *)(txwd_body + 1); 1525 txwd_info->dword0 = rtw89_build_txwd_info0_v2(desc_info); 1526 txwd_info->dword1 = rtw89_build_txwd_info1_v2(desc_info); 1527 txwd_info->dword2 = rtw89_build_txwd_info2_v2(desc_info); 1528 txwd_info->dword4 = rtw89_build_txwd_info4_v2(desc_info); 1529 } 1530 EXPORT_SYMBOL(rtw89_core_fill_txdesc_v2); 1531 1532 static __le32 rtw89_build_txwd_fwcmd0_v1(struct rtw89_tx_desc_info *desc_info) 1533 { 1534 u32 dword = FIELD_PREP(AX_RXD_RPKT_LEN_MASK, desc_info->pkt_size) | 1535 FIELD_PREP(AX_RXD_RPKT_TYPE_MASK, desc_info->fw_dl ? 1536 RTW89_CORE_RX_TYPE_FWDL : 1537 RTW89_CORE_RX_TYPE_H2C); 1538 1539 return cpu_to_le32(dword); 1540 } 1541 1542 void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev, 1543 struct rtw89_tx_desc_info *desc_info, 1544 void *txdesc) 1545 { 1546 struct rtw89_rxdesc_short *txwd_v1 = (struct rtw89_rxdesc_short *)txdesc; 1547 1548 txwd_v1->dword0 = rtw89_build_txwd_fwcmd0_v1(desc_info); 1549 } 1550 EXPORT_SYMBOL(rtw89_core_fill_txdesc_fwcmd_v1); 1551 1552 static __le32 rtw89_build_txwd_fwcmd0_v2(struct rtw89_tx_desc_info *desc_info) 1553 { 1554 u32 dword = FIELD_PREP(BE_RXD_RPKT_LEN_MASK, desc_info->pkt_size) | 1555 FIELD_PREP(BE_RXD_RPKT_TYPE_MASK, desc_info->fw_dl ? 1556 RTW89_CORE_RX_TYPE_FWDL : 1557 RTW89_CORE_RX_TYPE_H2C); 1558 1559 return cpu_to_le32(dword); 1560 } 1561 1562 void rtw89_core_fill_txdesc_fwcmd_v2(struct rtw89_dev *rtwdev, 1563 struct rtw89_tx_desc_info *desc_info, 1564 void *txdesc) 1565 { 1566 struct rtw89_rxdesc_short_v2 *txwd_v2 = (struct rtw89_rxdesc_short_v2 *)txdesc; 1567 1568 txwd_v2->dword0 = rtw89_build_txwd_fwcmd0_v2(desc_info); 1569 } 1570 EXPORT_SYMBOL(rtw89_core_fill_txdesc_fwcmd_v2); 1571 1572 static int rtw89_core_rx_process_mac_ppdu(struct rtw89_dev *rtwdev, 1573 struct sk_buff *skb, 1574 struct rtw89_rx_phy_ppdu *phy_ppdu) 1575 { 1576 const struct rtw89_chip_info *chip = rtwdev->chip; 1577 const struct rtw89_rxinfo *rxinfo = (const struct rtw89_rxinfo *)skb->data; 1578 const struct rtw89_rxinfo_user *user; 1579 enum rtw89_chip_gen chip_gen = rtwdev->chip->chip_gen; 1580 int rx_cnt_size = RTW89_PPDU_MAC_RX_CNT_SIZE; 1581 bool rx_cnt_valid = false; 1582 bool invalid = false; 1583 u8 plcp_size = 0; 1584 u8 *phy_sts; 1585 u8 usr_num; 1586 int i; 1587 1588 if (chip_gen == RTW89_CHIP_BE) { 1589 invalid = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_INVALID_V1); 1590 rx_cnt_size = RTW89_PPDU_MAC_RX_CNT_SIZE_V1; 1591 } 1592 1593 if (invalid) 1594 return -EINVAL; 1595 1596 rx_cnt_valid = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_RX_CNT_VLD); 1597 if (chip_gen == RTW89_CHIP_BE) { 1598 plcp_size = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_PLCP_LEN_V1) << 3; 1599 usr_num = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_USR_NUM_V1); 1600 } else { 1601 plcp_size = le32_get_bits(rxinfo->w1, RTW89_RXINFO_W1_PLCP_LEN) << 3; 1602 usr_num = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_USR_NUM); 1603 } 1604 if (usr_num > chip->ppdu_max_usr) { 1605 rtw89_warn(rtwdev, "Invalid user number (%d) in mac info\n", 1606 usr_num); 1607 return -EINVAL; 1608 } 1609 1610 for (i = 0; i < usr_num; i++) { 1611 user = &rxinfo->user[i]; 1612 if (!le32_get_bits(user->w0, RTW89_RXINFO_USER_MAC_ID_VALID)) 1613 continue; 1614 /* For WiFi 7 chips, RXWD.mac_id of PPDU status is not set 1615 * by hardware, so update mac_id by rxinfo_user[].mac_id. 1616 */ 1617 if (chip_gen == RTW89_CHIP_BE) 1618 phy_ppdu->mac_id = 1619 le32_get_bits(user->w0, RTW89_RXINFO_USER_MACID); 1620 phy_ppdu->has_data = 1621 le32_get_bits(user->w0, RTW89_RXINFO_USER_DATA); 1622 phy_ppdu->has_bcn = 1623 le32_get_bits(user->w0, RTW89_RXINFO_USER_BCN); 1624 break; 1625 } 1626 1627 phy_sts = skb->data + RTW89_PPDU_MAC_INFO_SIZE; 1628 phy_sts += usr_num * RTW89_PPDU_MAC_INFO_USR_SIZE; 1629 /* 8-byte alignment */ 1630 if (usr_num & BIT(0)) 1631 phy_sts += RTW89_PPDU_MAC_INFO_USR_SIZE; 1632 if (rx_cnt_valid) 1633 phy_sts += rx_cnt_size; 1634 phy_sts += plcp_size; 1635 1636 if (phy_sts > skb->data + skb->len) 1637 return -EINVAL; 1638 1639 phy_ppdu->buf = phy_sts; 1640 phy_ppdu->len = skb->data + skb->len - phy_sts; 1641 1642 return 0; 1643 } 1644 1645 static u8 rtw89_get_data_rate_nss(struct rtw89_dev *rtwdev, u16 data_rate) 1646 { 1647 u8 data_rate_mode; 1648 1649 data_rate_mode = rtw89_get_data_rate_mode(rtwdev, data_rate); 1650 switch (data_rate_mode) { 1651 case DATA_RATE_MODE_NON_HT: 1652 return 1; 1653 case DATA_RATE_MODE_HT: 1654 return rtw89_get_data_ht_nss(rtwdev, data_rate) + 1; 1655 case DATA_RATE_MODE_VHT: 1656 case DATA_RATE_MODE_HE: 1657 case DATA_RATE_MODE_EHT: 1658 return rtw89_get_data_nss(rtwdev, data_rate) + 1; 1659 default: 1660 rtw89_warn(rtwdev, "invalid RX rate mode %d\n", data_rate_mode); 1661 return 0; 1662 } 1663 } 1664 1665 static void rtw89_core_rx_process_phy_ppdu_iter(void *data, 1666 struct ieee80211_sta *sta) 1667 { 1668 struct rtw89_rx_phy_ppdu *phy_ppdu = (struct rtw89_rx_phy_ppdu *)data; 1669 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta); 1670 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 1671 struct rtw89_hal *hal = &rtwdev->hal; 1672 struct rtw89_sta_link *rtwsta_link; 1673 u8 ant_num = hal->ant_diversity ? 2 : rtwdev->chip->rf_path_num; 1674 u8 ant_pos = U8_MAX; 1675 u8 evm_pos = 0; 1676 int i; 1677 1678 rtwsta_link = rtw89_sta_get_link_inst(rtwsta, phy_ppdu->phy_idx); 1679 if (unlikely(!rtwsta_link)) 1680 return; 1681 1682 if (rtwsta_link->mac_id != phy_ppdu->mac_id || !phy_ppdu->to_self) 1683 return; 1684 1685 if (hal->ant_diversity && hal->antenna_rx) { 1686 ant_pos = __ffs(hal->antenna_rx); 1687 evm_pos = ant_pos; 1688 } 1689 1690 ewma_rssi_add(&rtwsta_link->avg_rssi, phy_ppdu->rssi_avg); 1691 1692 if (ant_pos < ant_num) { 1693 ewma_rssi_add(&rtwsta_link->rssi[ant_pos], phy_ppdu->rssi[0]); 1694 } else { 1695 for (i = 0; i < rtwdev->chip->rf_path_num; i++) 1696 ewma_rssi_add(&rtwsta_link->rssi[i], phy_ppdu->rssi[i]); 1697 } 1698 1699 if (phy_ppdu->ofdm.has && (phy_ppdu->has_data || phy_ppdu->has_bcn)) { 1700 ewma_snr_add(&rtwsta_link->avg_snr, phy_ppdu->ofdm.avg_snr); 1701 if (rtw89_get_data_rate_nss(rtwdev, phy_ppdu->rate) == 1) { 1702 ewma_evm_add(&rtwsta_link->evm_1ss, phy_ppdu->ofdm.evm_min); 1703 } else { 1704 ewma_evm_add(&rtwsta_link->evm_min[evm_pos], 1705 phy_ppdu->ofdm.evm_min); 1706 ewma_evm_add(&rtwsta_link->evm_max[evm_pos], 1707 phy_ppdu->ofdm.evm_max); 1708 } 1709 } 1710 } 1711 1712 #define VAR_LEN 0xff 1713 #define VAR_LEN_UNIT 8 1714 static u16 rtw89_core_get_phy_status_ie_len(struct rtw89_dev *rtwdev, 1715 const struct rtw89_phy_sts_iehdr *iehdr) 1716 { 1717 static const u8 physts_ie_len_tabs[RTW89_CHIP_GEN_NUM][32] = { 1718 [RTW89_CHIP_AX] = { 1719 16, 32, 24, 24, 8, 8, 8, 8, VAR_LEN, 8, VAR_LEN, 176, VAR_LEN, 1720 VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, 16, 24, VAR_LEN, 1721 VAR_LEN, VAR_LEN, 0, 24, 24, 24, 24, 32, 32, 32, 32 1722 }, 1723 [RTW89_CHIP_BE] = { 1724 32, 40, 24, 24, 8, 8, 8, 8, VAR_LEN, 8, VAR_LEN, 176, VAR_LEN, 1725 VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, 16, 24, VAR_LEN, 1726 VAR_LEN, VAR_LEN, 0, 24, 24, 24, 24, 32, 32, 32, 32 1727 }, 1728 }; 1729 const u8 *physts_ie_len_tab; 1730 u16 ie_len; 1731 u8 ie; 1732 1733 physts_ie_len_tab = physts_ie_len_tabs[rtwdev->chip->chip_gen]; 1734 1735 ie = le32_get_bits(iehdr->w0, RTW89_PHY_STS_IEHDR_TYPE); 1736 if (physts_ie_len_tab[ie] != VAR_LEN) 1737 ie_len = physts_ie_len_tab[ie]; 1738 else 1739 ie_len = le32_get_bits(iehdr->w0, RTW89_PHY_STS_IEHDR_LEN) * VAR_LEN_UNIT; 1740 1741 return ie_len; 1742 } 1743 1744 static void rtw89_core_parse_phy_status_ie01_v2(struct rtw89_dev *rtwdev, 1745 const struct rtw89_phy_sts_iehdr *iehdr, 1746 struct rtw89_rx_phy_ppdu *phy_ppdu) 1747 { 1748 const struct rtw89_phy_sts_ie01_v2 *ie; 1749 u8 *rpl_fd = phy_ppdu->rpl_fd; 1750 1751 ie = (const struct rtw89_phy_sts_ie01_v2 *)iehdr; 1752 rpl_fd[RF_PATH_A] = le32_get_bits(ie->w8, RTW89_PHY_STS_IE01_V2_W8_RPL_FD_A); 1753 rpl_fd[RF_PATH_B] = le32_get_bits(ie->w8, RTW89_PHY_STS_IE01_V2_W8_RPL_FD_B); 1754 rpl_fd[RF_PATH_C] = le32_get_bits(ie->w9, RTW89_PHY_STS_IE01_V2_W9_RPL_FD_C); 1755 rpl_fd[RF_PATH_D] = le32_get_bits(ie->w9, RTW89_PHY_STS_IE01_V2_W9_RPL_FD_D); 1756 1757 phy_ppdu->bw_idx = le32_get_bits(ie->w5, RTW89_PHY_STS_IE01_V2_W5_BW_IDX); 1758 } 1759 1760 static void rtw89_core_parse_phy_status_ie01(struct rtw89_dev *rtwdev, 1761 const struct rtw89_phy_sts_iehdr *iehdr, 1762 struct rtw89_rx_phy_ppdu *phy_ppdu) 1763 { 1764 const struct rtw89_phy_sts_ie01 *ie = (const struct rtw89_phy_sts_ie01 *)iehdr; 1765 s16 cfo; 1766 u32 t; 1767 1768 phy_ppdu->chan_idx = le32_get_bits(ie->w0, RTW89_PHY_STS_IE01_W0_CH_IDX); 1769 1770 if (rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR) { 1771 phy_ppdu->ldpc = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_LDPC); 1772 phy_ppdu->stbc = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_STBC); 1773 } 1774 1775 if (!phy_ppdu->hdr_2_en) 1776 phy_ppdu->rx_path_en = 1777 le32_get_bits(ie->w0, RTW89_PHY_STS_IE01_W0_RX_PATH_EN); 1778 1779 if (phy_ppdu->rate < RTW89_HW_RATE_OFDM6) 1780 return; 1781 1782 if (!phy_ppdu->to_self) 1783 return; 1784 1785 phy_ppdu->rpl_avg = le32_get_bits(ie->w0, RTW89_PHY_STS_IE01_W0_RSSI_AVG_FD); 1786 phy_ppdu->ofdm.avg_snr = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_AVG_SNR); 1787 phy_ppdu->ofdm.evm_max = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_EVM_MAX); 1788 phy_ppdu->ofdm.evm_min = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_EVM_MIN); 1789 phy_ppdu->ofdm.has = true; 1790 1791 /* sign conversion for S(12,2) */ 1792 if (rtwdev->chip->cfo_src_fd) { 1793 t = le32_get_bits(ie->w1, RTW89_PHY_STS_IE01_W1_FD_CFO); 1794 cfo = sign_extend32(t, 11); 1795 } else { 1796 t = le32_get_bits(ie->w1, RTW89_PHY_STS_IE01_W1_PREMB_CFO); 1797 cfo = sign_extend32(t, 11); 1798 } 1799 1800 rtw89_phy_cfo_parse(rtwdev, cfo, phy_ppdu); 1801 1802 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) 1803 rtw89_core_parse_phy_status_ie01_v2(rtwdev, iehdr, phy_ppdu); 1804 } 1805 1806 static void rtw89_core_parse_phy_status_ie00(struct rtw89_dev *rtwdev, 1807 const struct rtw89_phy_sts_iehdr *iehdr, 1808 struct rtw89_rx_phy_ppdu *phy_ppdu) 1809 { 1810 const struct rtw89_phy_sts_ie00 *ie = (const struct rtw89_phy_sts_ie00 *)iehdr; 1811 u16 tmp_rpl; 1812 1813 tmp_rpl = le32_get_bits(ie->w0, RTW89_PHY_STS_IE00_W0_RPL); 1814 phy_ppdu->rpl_avg = tmp_rpl >> 1; 1815 } 1816 1817 static void rtw89_core_parse_phy_status_ie00_v2(struct rtw89_dev *rtwdev, 1818 const struct rtw89_phy_sts_iehdr *iehdr, 1819 struct rtw89_rx_phy_ppdu *phy_ppdu) 1820 { 1821 const struct rtw89_phy_sts_ie00_v2 *ie; 1822 u8 *rpl_path = phy_ppdu->rpl_path; 1823 u16 tmp_rpl[RF_PATH_MAX]; 1824 u8 i; 1825 1826 ie = (const struct rtw89_phy_sts_ie00_v2 *)iehdr; 1827 tmp_rpl[RF_PATH_A] = le32_get_bits(ie->w4, RTW89_PHY_STS_IE00_V2_W4_RPL_TD_A); 1828 tmp_rpl[RF_PATH_B] = le32_get_bits(ie->w4, RTW89_PHY_STS_IE00_V2_W4_RPL_TD_B); 1829 tmp_rpl[RF_PATH_C] = le32_get_bits(ie->w4, RTW89_PHY_STS_IE00_V2_W4_RPL_TD_C); 1830 tmp_rpl[RF_PATH_D] = le32_get_bits(ie->w5, RTW89_PHY_STS_IE00_V2_W5_RPL_TD_D); 1831 1832 for (i = 0; i < RF_PATH_MAX; i++) 1833 rpl_path[i] = tmp_rpl[i] >> 1; 1834 } 1835 1836 static int rtw89_core_process_phy_status_ie(struct rtw89_dev *rtwdev, 1837 const struct rtw89_phy_sts_iehdr *iehdr, 1838 struct rtw89_rx_phy_ppdu *phy_ppdu) 1839 { 1840 u8 ie; 1841 1842 ie = le32_get_bits(iehdr->w0, RTW89_PHY_STS_IEHDR_TYPE); 1843 1844 switch (ie) { 1845 case RTW89_PHYSTS_IE00_CMN_CCK: 1846 rtw89_core_parse_phy_status_ie00(rtwdev, iehdr, phy_ppdu); 1847 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) 1848 rtw89_core_parse_phy_status_ie00_v2(rtwdev, iehdr, phy_ppdu); 1849 break; 1850 case RTW89_PHYSTS_IE01_CMN_OFDM: 1851 rtw89_core_parse_phy_status_ie01(rtwdev, iehdr, phy_ppdu); 1852 break; 1853 default: 1854 break; 1855 } 1856 1857 return 0; 1858 } 1859 1860 static void rtw89_core_update_phy_ppdu_hdr_v2(struct rtw89_rx_phy_ppdu *phy_ppdu) 1861 { 1862 const struct rtw89_phy_sts_hdr_v2 *hdr = phy_ppdu->buf + PHY_STS_HDR_LEN; 1863 1864 phy_ppdu->rx_path_en = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_V2_W0_PATH_EN); 1865 } 1866 1867 static void rtw89_core_update_phy_ppdu(struct rtw89_rx_phy_ppdu *phy_ppdu) 1868 { 1869 const struct rtw89_phy_sts_hdr *hdr = phy_ppdu->buf; 1870 u8 *rssi = phy_ppdu->rssi; 1871 1872 phy_ppdu->ie = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_IE_MAP); 1873 phy_ppdu->rssi_avg = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_RSSI_AVG); 1874 rssi[RF_PATH_A] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_A); 1875 rssi[RF_PATH_B] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_B); 1876 rssi[RF_PATH_C] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_C); 1877 rssi[RF_PATH_D] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_D); 1878 1879 phy_ppdu->hdr_2_en = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_HDR_2_EN); 1880 if (phy_ppdu->hdr_2_en) 1881 rtw89_core_update_phy_ppdu_hdr_v2(phy_ppdu); 1882 } 1883 1884 static int rtw89_core_rx_process_phy_ppdu(struct rtw89_dev *rtwdev, 1885 struct rtw89_rx_phy_ppdu *phy_ppdu) 1886 { 1887 const struct rtw89_phy_sts_hdr *hdr = phy_ppdu->buf; 1888 u32 len_from_header; 1889 bool physts_valid; 1890 1891 physts_valid = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_VALID); 1892 if (!physts_valid) 1893 return -EINVAL; 1894 1895 len_from_header = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_LEN) << 3; 1896 1897 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) 1898 len_from_header += PHY_STS_HDR_LEN; 1899 1900 if (len_from_header != phy_ppdu->len) { 1901 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, "phy ppdu len mismatch\n"); 1902 return -EINVAL; 1903 } 1904 rtw89_core_update_phy_ppdu(phy_ppdu); 1905 1906 return 0; 1907 } 1908 1909 static int rtw89_core_rx_parse_phy_sts(struct rtw89_dev *rtwdev, 1910 struct rtw89_rx_phy_ppdu *phy_ppdu) 1911 { 1912 u16 ie_len; 1913 void *pos, *end; 1914 1915 /* mark invalid reports and bypass them */ 1916 if (phy_ppdu->ie < RTW89_CCK_PKT) 1917 return -EINVAL; 1918 1919 pos = phy_ppdu->buf + PHY_STS_HDR_LEN; 1920 end = phy_ppdu->buf + phy_ppdu->len; 1921 while (pos < end) { 1922 const struct rtw89_phy_sts_iehdr *iehdr = pos; 1923 1924 ie_len = rtw89_core_get_phy_status_ie_len(rtwdev, iehdr); 1925 rtw89_core_process_phy_status_ie(rtwdev, iehdr, phy_ppdu); 1926 pos += ie_len; 1927 if (pos > end || ie_len == 0) { 1928 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 1929 "phy status parse failed\n"); 1930 return -EINVAL; 1931 } 1932 } 1933 1934 rtw89_chip_convert_rpl_to_rssi(rtwdev, phy_ppdu); 1935 rtw89_phy_antdiv_parse(rtwdev, phy_ppdu); 1936 1937 return 0; 1938 } 1939 1940 static void rtw89_core_rx_process_phy_sts(struct rtw89_dev *rtwdev, 1941 struct rtw89_rx_phy_ppdu *phy_ppdu) 1942 { 1943 int ret; 1944 1945 ret = rtw89_core_rx_parse_phy_sts(rtwdev, phy_ppdu); 1946 if (ret) 1947 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "parse phy sts failed\n"); 1948 else 1949 phy_ppdu->valid = true; 1950 1951 ieee80211_iterate_stations_atomic(rtwdev->hw, 1952 rtw89_core_rx_process_phy_ppdu_iter, 1953 phy_ppdu); 1954 } 1955 1956 static u8 rtw89_rxdesc_to_nl_he_gi(struct rtw89_dev *rtwdev, 1957 u8 desc_info_gi, 1958 bool rx_status) 1959 { 1960 switch (desc_info_gi) { 1961 case RTW89_GILTF_SGI_4XHE08: 1962 case RTW89_GILTF_2XHE08: 1963 case RTW89_GILTF_1XHE08: 1964 return NL80211_RATE_INFO_HE_GI_0_8; 1965 case RTW89_GILTF_2XHE16: 1966 case RTW89_GILTF_1XHE16: 1967 return NL80211_RATE_INFO_HE_GI_1_6; 1968 case RTW89_GILTF_LGI_4XHE32: 1969 return NL80211_RATE_INFO_HE_GI_3_2; 1970 default: 1971 rtw89_warn(rtwdev, "invalid gi_ltf=%d", desc_info_gi); 1972 if (rx_status) 1973 return NL80211_RATE_INFO_HE_GI_3_2; 1974 return U8_MAX; 1975 } 1976 } 1977 1978 static u8 rtw89_rxdesc_to_nl_eht_gi(struct rtw89_dev *rtwdev, 1979 u8 desc_info_gi, 1980 bool rx_status) 1981 { 1982 switch (desc_info_gi) { 1983 case RTW89_GILTF_SGI_4XHE08: 1984 case RTW89_GILTF_2XHE08: 1985 case RTW89_GILTF_1XHE08: 1986 return NL80211_RATE_INFO_EHT_GI_0_8; 1987 case RTW89_GILTF_2XHE16: 1988 case RTW89_GILTF_1XHE16: 1989 return NL80211_RATE_INFO_EHT_GI_1_6; 1990 case RTW89_GILTF_LGI_4XHE32: 1991 return NL80211_RATE_INFO_EHT_GI_3_2; 1992 default: 1993 rtw89_warn(rtwdev, "invalid gi_ltf=%d", desc_info_gi); 1994 if (rx_status) 1995 return NL80211_RATE_INFO_EHT_GI_3_2; 1996 return U8_MAX; 1997 } 1998 } 1999 2000 static u8 rtw89_rxdesc_to_nl_he_eht_gi(struct rtw89_dev *rtwdev, 2001 u8 desc_info_gi, 2002 bool rx_status, bool eht) 2003 { 2004 return eht ? rtw89_rxdesc_to_nl_eht_gi(rtwdev, desc_info_gi, rx_status) : 2005 rtw89_rxdesc_to_nl_he_gi(rtwdev, desc_info_gi, rx_status); 2006 } 2007 2008 static 2009 bool rtw89_check_rx_statu_gi_match(struct ieee80211_rx_status *status, u8 gi_ltf, 2010 bool eht) 2011 { 2012 if (eht) 2013 return status->eht.gi == gi_ltf; 2014 2015 return status->he_gi == gi_ltf; 2016 } 2017 2018 static bool rtw89_core_rx_ppdu_match(struct rtw89_dev *rtwdev, 2019 struct rtw89_rx_desc_info *desc_info, 2020 struct ieee80211_rx_status *status) 2021 { 2022 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 2023 u8 data_rate_mode, bw, rate_idx = MASKBYTE0, gi_ltf; 2024 bool eht = false; 2025 u16 data_rate; 2026 bool ret; 2027 2028 data_rate = desc_info->data_rate; 2029 data_rate_mode = rtw89_get_data_rate_mode(rtwdev, data_rate); 2030 if (data_rate_mode == DATA_RATE_MODE_NON_HT) { 2031 rate_idx = rtw89_get_data_not_ht_idx(rtwdev, data_rate); 2032 /* rate_idx is still hardware value here */ 2033 } else if (data_rate_mode == DATA_RATE_MODE_HT) { 2034 rate_idx = rtw89_get_data_ht_mcs(rtwdev, data_rate); 2035 } else if (data_rate_mode == DATA_RATE_MODE_VHT || 2036 data_rate_mode == DATA_RATE_MODE_HE || 2037 data_rate_mode == DATA_RATE_MODE_EHT) { 2038 rate_idx = rtw89_get_data_mcs(rtwdev, data_rate); 2039 } else { 2040 rtw89_warn(rtwdev, "invalid RX rate mode %d\n", data_rate_mode); 2041 } 2042 2043 eht = data_rate_mode == DATA_RATE_MODE_EHT; 2044 bw = rtw89_hw_to_rate_info_bw(desc_info->bw); 2045 gi_ltf = rtw89_rxdesc_to_nl_he_eht_gi(rtwdev, desc_info->gi_ltf, false, eht); 2046 ret = rtwdev->ppdu_sts.curr_rx_ppdu_cnt[band] == desc_info->ppdu_cnt && 2047 status->rate_idx == rate_idx && 2048 rtw89_check_rx_statu_gi_match(status, gi_ltf, eht) && 2049 status->bw == bw; 2050 2051 return ret; 2052 } 2053 2054 struct rtw89_vif_rx_stats_iter_data { 2055 struct rtw89_dev *rtwdev; 2056 struct rtw89_rx_phy_ppdu *phy_ppdu; 2057 struct rtw89_rx_desc_info *desc_info; 2058 struct sk_buff *skb; 2059 const u8 *bssid; 2060 }; 2061 2062 static void rtw89_stats_trigger_frame(struct rtw89_dev *rtwdev, 2063 struct rtw89_vif_link *rtwvif_link, 2064 struct ieee80211_bss_conf *bss_conf, 2065 struct sk_buff *skb) 2066 { 2067 struct ieee80211_trigger *tf = (struct ieee80211_trigger *)skb->data; 2068 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 2069 struct rtw89_vif *rtwvif = rtwvif_link->rtwvif; 2070 u8 *pos, *end, type, tf_bw; 2071 u16 aid, tf_rua; 2072 2073 if (!ether_addr_equal(bss_conf->bssid, tf->ta) || 2074 rtwvif_link->wifi_role != RTW89_WIFI_ROLE_STATION || 2075 rtwvif_link->net_type == RTW89_NET_TYPE_NO_LINK) 2076 return; 2077 2078 type = le64_get_bits(tf->common_info, IEEE80211_TRIGGER_TYPE_MASK); 2079 if (type != IEEE80211_TRIGGER_TYPE_BASIC && type != IEEE80211_TRIGGER_TYPE_MU_BAR) 2080 return; 2081 2082 end = (u8 *)tf + skb->len; 2083 pos = tf->variable; 2084 2085 while (end - pos >= RTW89_TF_BASIC_USER_INFO_SZ) { 2086 aid = RTW89_GET_TF_USER_INFO_AID12(pos); 2087 tf_rua = RTW89_GET_TF_USER_INFO_RUA(pos); 2088 tf_bw = le64_get_bits(tf->common_info, IEEE80211_TRIGGER_ULBW_MASK); 2089 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 2090 "[TF] aid: %d, ul_mcs: %d, rua: %d, bw: %d\n", 2091 aid, RTW89_GET_TF_USER_INFO_UL_MCS(pos), 2092 tf_rua, tf_bw); 2093 2094 if (aid == RTW89_TF_PAD) 2095 break; 2096 2097 if (aid == vif->cfg.aid) { 2098 enum nl80211_he_ru_alloc rua; 2099 2100 rtwvif->stats.rx_tf_acc++; 2101 rtwdev->stats.rx_tf_acc++; 2102 2103 /* The following only required for HE trigger frame, but we 2104 * cannot use UL HE-SIG-A2 reserved subfield to identify it 2105 * since some 11ax APs will fill it with all 0s, which will 2106 * be misunderstood as EHT trigger frame. 2107 */ 2108 if (bss_conf->eht_support) 2109 break; 2110 2111 rua = rtw89_he_rua_to_ru_alloc(tf_rua >> 1); 2112 2113 if (tf_bw == IEEE80211_TRIGGER_ULBW_160_80P80MHZ && 2114 rua <= NL80211_RATE_INFO_HE_RU_ALLOC_106) 2115 rtwvif_link->pwr_diff_en = true; 2116 break; 2117 } 2118 2119 pos += RTW89_TF_BASIC_USER_INFO_SZ; 2120 } 2121 } 2122 2123 static void rtw89_cancel_6ghz_probe_work(struct wiphy *wiphy, struct wiphy_work *work) 2124 { 2125 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 2126 cancel_6ghz_probe_work); 2127 struct list_head *pkt_list = rtwdev->scan_info.pkt_list; 2128 struct rtw89_pktofld_info *info; 2129 2130 lockdep_assert_wiphy(wiphy); 2131 2132 if (!rtwdev->scanning) 2133 return; 2134 2135 list_for_each_entry(info, &pkt_list[NL80211_BAND_6GHZ], list) { 2136 if (!info->cancel || !test_bit(info->id, rtwdev->pkt_offload)) 2137 continue; 2138 2139 rtw89_fw_h2c_del_pkt_offload(rtwdev, info->id); 2140 2141 /* Don't delete/free info from pkt_list at this moment. Let it 2142 * be deleted/freed in rtw89_release_pkt_list() after scanning, 2143 * since if during scanning, pkt_list is accessed in bottom half. 2144 */ 2145 } 2146 } 2147 2148 static void rtw89_core_cancel_6ghz_probe_tx(struct rtw89_dev *rtwdev, 2149 struct sk_buff *skb) 2150 { 2151 struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb); 2152 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data; 2153 struct list_head *pkt_list = rtwdev->scan_info.pkt_list; 2154 struct rtw89_pktofld_info *info; 2155 const u8 *ies = mgmt->u.beacon.variable, *ssid_ie; 2156 bool queue_work = false; 2157 2158 if (rx_status->band != NL80211_BAND_6GHZ) 2159 return; 2160 2161 ssid_ie = cfg80211_find_ie(WLAN_EID_SSID, ies, skb->len); 2162 2163 list_for_each_entry(info, &pkt_list[NL80211_BAND_6GHZ], list) { 2164 if (ether_addr_equal(info->bssid, mgmt->bssid)) { 2165 info->cancel = true; 2166 queue_work = true; 2167 continue; 2168 } 2169 2170 if (!ssid_ie || ssid_ie[1] != info->ssid_len || info->ssid_len == 0) 2171 continue; 2172 2173 if (memcmp(&ssid_ie[2], info->ssid, info->ssid_len) == 0) { 2174 info->cancel = true; 2175 queue_work = true; 2176 } 2177 } 2178 2179 if (queue_work) 2180 wiphy_work_queue(rtwdev->hw->wiphy, &rtwdev->cancel_6ghz_probe_work); 2181 } 2182 2183 static void rtw89_vif_sync_bcn_tsf(struct rtw89_vif_link *rtwvif_link, 2184 struct ieee80211_hdr *hdr, size_t len) 2185 { 2186 struct ieee80211_mgmt *mgmt = (typeof(mgmt))hdr; 2187 2188 if (len < offsetof(typeof(*mgmt), u.beacon.variable)) 2189 return; 2190 2191 WRITE_ONCE(rtwvif_link->sync_bcn_tsf, le64_to_cpu(mgmt->u.beacon.timestamp)); 2192 } 2193 2194 static void rtw89_vif_rx_stats_iter(void *data, u8 *mac, 2195 struct ieee80211_vif *vif) 2196 { 2197 struct rtw89_vif_rx_stats_iter_data *iter_data = data; 2198 struct rtw89_dev *rtwdev = iter_data->rtwdev; 2199 struct rtw89_vif *rtwvif = vif_to_rtwvif(vif); 2200 struct rtw89_pkt_stat *pkt_stat = &rtwdev->phystat.cur_pkt_stat; 2201 struct rtw89_rx_desc_info *desc_info = iter_data->desc_info; 2202 struct sk_buff *skb = iter_data->skb; 2203 struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb); 2204 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 2205 struct rtw89_rx_phy_ppdu *phy_ppdu = iter_data->phy_ppdu; 2206 bool is_mld = ieee80211_vif_is_mld(vif); 2207 struct ieee80211_bss_conf *bss_conf; 2208 struct rtw89_vif_link *rtwvif_link; 2209 const u8 *bssid = iter_data->bssid; 2210 2211 if (rtwdev->scanning && 2212 (ieee80211_is_beacon(hdr->frame_control) || 2213 ieee80211_is_probe_resp(hdr->frame_control))) 2214 rtw89_core_cancel_6ghz_probe_tx(rtwdev, skb); 2215 2216 rcu_read_lock(); 2217 2218 rtwvif_link = rtw89_vif_get_link_inst(rtwvif, desc_info->bb_sel); 2219 if (unlikely(!rtwvif_link)) 2220 goto out; 2221 2222 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, false); 2223 if (!bss_conf->bssid) 2224 goto out; 2225 2226 if (ieee80211_is_trigger(hdr->frame_control)) { 2227 rtw89_stats_trigger_frame(rtwdev, rtwvif_link, bss_conf, skb); 2228 goto out; 2229 } 2230 2231 if (!ether_addr_equal(bss_conf->bssid, bssid)) 2232 goto out; 2233 2234 if (is_mld) { 2235 rx_status->link_valid = true; 2236 rx_status->link_id = rtwvif_link->link_id; 2237 } 2238 2239 if (ieee80211_is_beacon(hdr->frame_control)) { 2240 if (vif->type == NL80211_IFTYPE_STATION && 2241 !test_bit(RTW89_FLAG_WOWLAN, rtwdev->flags)) { 2242 rtw89_vif_sync_bcn_tsf(rtwvif_link, hdr, skb->len); 2243 rtw89_fw_h2c_rssi_offload(rtwdev, phy_ppdu); 2244 } 2245 pkt_stat->beacon_nr++; 2246 2247 if (phy_ppdu) { 2248 ewma_rssi_add(&rtwdev->phystat.bcn_rssi, phy_ppdu->rssi_avg); 2249 if (!test_bit(RTW89_FLAG_LOW_POWER_MODE, rtwdev->flags)) 2250 rtwvif_link->bcn_bw_idx = phy_ppdu->bw_idx; 2251 } 2252 2253 pkt_stat->beacon_rate = desc_info->data_rate; 2254 } 2255 2256 if (!ether_addr_equal(bss_conf->addr, hdr->addr1)) 2257 goto out; 2258 2259 if (desc_info->data_rate < RTW89_HW_RATE_NR) 2260 pkt_stat->rx_rate_cnt[desc_info->data_rate]++; 2261 2262 rtw89_traffic_stats_accu(rtwdev, &rtwvif->stats, skb, false); 2263 2264 out: 2265 rcu_read_unlock(); 2266 } 2267 2268 static void rtw89_core_rx_stats(struct rtw89_dev *rtwdev, 2269 struct rtw89_rx_phy_ppdu *phy_ppdu, 2270 struct rtw89_rx_desc_info *desc_info, 2271 struct sk_buff *skb) 2272 { 2273 struct rtw89_vif_rx_stats_iter_data iter_data; 2274 2275 rtw89_traffic_stats_accu(rtwdev, &rtwdev->stats, skb, false); 2276 2277 iter_data.rtwdev = rtwdev; 2278 iter_data.phy_ppdu = phy_ppdu; 2279 iter_data.desc_info = desc_info; 2280 iter_data.skb = skb; 2281 iter_data.bssid = get_hdr_bssid((struct ieee80211_hdr *)skb->data); 2282 rtw89_iterate_vifs_bh(rtwdev, rtw89_vif_rx_stats_iter, &iter_data); 2283 } 2284 2285 static void rtw89_correct_cck_chan(struct rtw89_dev *rtwdev, 2286 struct ieee80211_rx_status *status) 2287 { 2288 const struct rtw89_chan_rcd *rcd = 2289 rtw89_chan_rcd_get(rtwdev, RTW89_CHANCTX_0); 2290 u16 chan = rcd->prev_primary_channel; 2291 u8 band = rtw89_hw_to_nl80211_band(rcd->prev_band_type); 2292 2293 if (status->band != NL80211_BAND_2GHZ && 2294 status->encoding == RX_ENC_LEGACY && 2295 status->rate_idx < RTW89_HW_RATE_OFDM6) { 2296 status->freq = ieee80211_channel_to_frequency(chan, band); 2297 status->band = band; 2298 } 2299 } 2300 2301 static void rtw89_core_hw_to_sband_rate(struct ieee80211_rx_status *rx_status) 2302 { 2303 if (rx_status->band == NL80211_BAND_2GHZ || 2304 rx_status->encoding != RX_ENC_LEGACY) 2305 return; 2306 2307 /* Some control frames' freq(ACKs in this case) are reported wrong due 2308 * to FW notify timing, set to lowest rate to prevent overflow. 2309 */ 2310 if (rx_status->rate_idx < RTW89_HW_RATE_OFDM6) { 2311 rx_status->rate_idx = 0; 2312 return; 2313 } 2314 2315 /* No 4 CCK rates for non-2G */ 2316 rx_status->rate_idx -= 4; 2317 } 2318 2319 static 2320 void rtw89_core_update_rx_status_by_ppdu(struct rtw89_dev *rtwdev, 2321 struct ieee80211_rx_status *rx_status, 2322 struct rtw89_rx_phy_ppdu *phy_ppdu) 2323 { 2324 if (!(rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR)) 2325 return; 2326 2327 if (!phy_ppdu) 2328 return; 2329 2330 if (phy_ppdu->ldpc) 2331 rx_status->enc_flags |= RX_ENC_FLAG_LDPC; 2332 if (phy_ppdu->stbc) 2333 rx_status->enc_flags |= u8_encode_bits(1, RX_ENC_FLAG_STBC_MASK); 2334 } 2335 2336 static const u8 rx_status_bw_to_radiotap_eht_usig[] = { 2337 [RATE_INFO_BW_20] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_20MHZ, 2338 [RATE_INFO_BW_5] = U8_MAX, 2339 [RATE_INFO_BW_10] = U8_MAX, 2340 [RATE_INFO_BW_40] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_40MHZ, 2341 [RATE_INFO_BW_80] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_80MHZ, 2342 [RATE_INFO_BW_160] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_160MHZ, 2343 [RATE_INFO_BW_HE_RU] = U8_MAX, 2344 [RATE_INFO_BW_320] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_320MHZ_1, 2345 [RATE_INFO_BW_EHT_RU] = U8_MAX, 2346 }; 2347 2348 static void rtw89_core_update_radiotap_eht(struct rtw89_dev *rtwdev, 2349 struct sk_buff *skb, 2350 struct ieee80211_rx_status *rx_status) 2351 { 2352 struct ieee80211_radiotap_eht_usig *usig; 2353 struct ieee80211_radiotap_eht *eht; 2354 struct ieee80211_radiotap_tlv *tlv; 2355 int eht_len = struct_size(eht, user_info, 1); 2356 int usig_len = sizeof(*usig); 2357 int len; 2358 u8 bw; 2359 2360 len = sizeof(*tlv) + ALIGN(eht_len, 4) + 2361 sizeof(*tlv) + ALIGN(usig_len, 4); 2362 2363 rx_status->flag |= RX_FLAG_RADIOTAP_TLV_AT_END; 2364 skb_reset_mac_header(skb); 2365 2366 /* EHT */ 2367 tlv = skb_push(skb, len); 2368 memset(tlv, 0, len); 2369 tlv->type = cpu_to_le16(IEEE80211_RADIOTAP_EHT); 2370 tlv->len = cpu_to_le16(eht_len); 2371 2372 eht = (struct ieee80211_radiotap_eht *)tlv->data; 2373 eht->known = cpu_to_le32(IEEE80211_RADIOTAP_EHT_KNOWN_GI); 2374 eht->data[0] = 2375 le32_encode_bits(rx_status->eht.gi, IEEE80211_RADIOTAP_EHT_DATA0_GI); 2376 2377 eht->user_info[0] = 2378 cpu_to_le32(IEEE80211_RADIOTAP_EHT_USER_INFO_MCS_KNOWN | 2379 IEEE80211_RADIOTAP_EHT_USER_INFO_NSS_KNOWN_O | 2380 IEEE80211_RADIOTAP_EHT_USER_INFO_CODING_KNOWN); 2381 eht->user_info[0] |= 2382 le32_encode_bits(rx_status->rate_idx, IEEE80211_RADIOTAP_EHT_USER_INFO_MCS) | 2383 le32_encode_bits(rx_status->nss, IEEE80211_RADIOTAP_EHT_USER_INFO_NSS_O); 2384 if (rx_status->enc_flags & RX_ENC_FLAG_LDPC) 2385 eht->user_info[0] |= 2386 cpu_to_le32(IEEE80211_RADIOTAP_EHT_USER_INFO_CODING); 2387 2388 /* U-SIG */ 2389 tlv = (void *)tlv + sizeof(*tlv) + ALIGN(eht_len, 4); 2390 tlv->type = cpu_to_le16(IEEE80211_RADIOTAP_EHT_USIG); 2391 tlv->len = cpu_to_le16(usig_len); 2392 2393 if (rx_status->bw >= ARRAY_SIZE(rx_status_bw_to_radiotap_eht_usig)) 2394 return; 2395 2396 bw = rx_status_bw_to_radiotap_eht_usig[rx_status->bw]; 2397 if (bw == U8_MAX) 2398 return; 2399 2400 usig = (struct ieee80211_radiotap_eht_usig *)tlv->data; 2401 usig->common = 2402 le32_encode_bits(1, IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_KNOWN) | 2403 le32_encode_bits(bw, IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW); 2404 } 2405 2406 static void rtw89_core_update_radiotap(struct rtw89_dev *rtwdev, 2407 struct sk_buff *skb, 2408 struct ieee80211_rx_status *rx_status) 2409 { 2410 static const struct ieee80211_radiotap_he known_he = { 2411 .data1 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN | 2412 IEEE80211_RADIOTAP_HE_DATA1_CODING_KNOWN | 2413 IEEE80211_RADIOTAP_HE_DATA1_STBC_KNOWN | 2414 IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN), 2415 .data2 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN), 2416 }; 2417 struct ieee80211_radiotap_he *he; 2418 2419 if (!(rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR)) 2420 return; 2421 2422 if (rx_status->encoding == RX_ENC_HE) { 2423 rx_status->flag |= RX_FLAG_RADIOTAP_HE; 2424 he = skb_push(skb, sizeof(*he)); 2425 *he = known_he; 2426 } else if (rx_status->encoding == RX_ENC_EHT) { 2427 rtw89_core_update_radiotap_eht(rtwdev, skb, rx_status); 2428 } 2429 } 2430 2431 static void rtw89_core_validate_rx_signal(struct ieee80211_rx_status *rx_status) 2432 { 2433 if (!rx_status->signal) 2434 rx_status->flag |= RX_FLAG_NO_SIGNAL_VAL; 2435 } 2436 2437 static void rtw89_core_update_rx_freq_from_ie(struct rtw89_dev *rtwdev, 2438 struct sk_buff *skb, 2439 struct ieee80211_rx_status *rx_status) 2440 { 2441 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data; 2442 size_t hdr_len, ielen; 2443 u8 *variable; 2444 int chan; 2445 2446 if (!rtwdev->chip->rx_freq_frome_ie) 2447 return; 2448 2449 if (!rtwdev->scanning) 2450 return; 2451 2452 if (ieee80211_is_beacon(mgmt->frame_control)) { 2453 variable = mgmt->u.beacon.variable; 2454 hdr_len = offsetof(struct ieee80211_mgmt, 2455 u.beacon.variable); 2456 } else if (ieee80211_is_probe_resp(mgmt->frame_control)) { 2457 variable = mgmt->u.probe_resp.variable; 2458 hdr_len = offsetof(struct ieee80211_mgmt, 2459 u.probe_resp.variable); 2460 } else { 2461 return; 2462 } 2463 2464 if (skb->len > hdr_len) 2465 ielen = skb->len - hdr_len; 2466 else 2467 return; 2468 2469 /* The parsing code for both 2GHz and 5GHz bands is the same in this 2470 * function. 2471 */ 2472 chan = cfg80211_get_ies_channel_number(variable, ielen, NL80211_BAND_2GHZ); 2473 if (chan == -1) 2474 return; 2475 2476 rx_status->band = chan > 14 ? RTW89_BAND_5G : RTW89_BAND_2G; 2477 rx_status->freq = ieee80211_channel_to_frequency(chan, rx_status->band); 2478 } 2479 2480 static void rtw89_core_rx_to_mac80211(struct rtw89_dev *rtwdev, 2481 struct rtw89_rx_phy_ppdu *phy_ppdu, 2482 struct rtw89_rx_desc_info *desc_info, 2483 struct sk_buff *skb_ppdu, 2484 struct ieee80211_rx_status *rx_status) 2485 { 2486 struct napi_struct *napi = &rtwdev->napi; 2487 2488 /* In low power mode, napi isn't scheduled. Receive it to netif. */ 2489 if (unlikely(!napi_is_scheduled(napi))) 2490 napi = NULL; 2491 2492 rtw89_core_hw_to_sband_rate(rx_status); 2493 rtw89_core_rx_stats(rtwdev, phy_ppdu, desc_info, skb_ppdu); 2494 rtw89_core_update_rx_status_by_ppdu(rtwdev, rx_status, phy_ppdu); 2495 rtw89_core_update_radiotap(rtwdev, skb_ppdu, rx_status); 2496 rtw89_core_validate_rx_signal(rx_status); 2497 rtw89_core_update_rx_freq_from_ie(rtwdev, skb_ppdu, rx_status); 2498 2499 /* In low power mode, it does RX in thread context. */ 2500 local_bh_disable(); 2501 ieee80211_rx_napi(rtwdev->hw, NULL, skb_ppdu, napi); 2502 local_bh_enable(); 2503 rtwdev->napi_budget_countdown--; 2504 } 2505 2506 static void rtw89_core_rx_pending_skb(struct rtw89_dev *rtwdev, 2507 struct rtw89_rx_phy_ppdu *phy_ppdu, 2508 struct rtw89_rx_desc_info *desc_info, 2509 struct sk_buff *skb) 2510 { 2511 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 2512 int curr = rtwdev->ppdu_sts.curr_rx_ppdu_cnt[band]; 2513 struct sk_buff *skb_ppdu = NULL, *tmp; 2514 struct ieee80211_rx_status *rx_status; 2515 2516 if (curr > RTW89_MAX_PPDU_CNT) 2517 return; 2518 2519 skb_queue_walk_safe(&rtwdev->ppdu_sts.rx_queue[band], skb_ppdu, tmp) { 2520 skb_unlink(skb_ppdu, &rtwdev->ppdu_sts.rx_queue[band]); 2521 rx_status = IEEE80211_SKB_RXCB(skb_ppdu); 2522 if (rtw89_core_rx_ppdu_match(rtwdev, desc_info, rx_status)) 2523 rtw89_chip_query_ppdu(rtwdev, phy_ppdu, rx_status); 2524 rtw89_correct_cck_chan(rtwdev, rx_status); 2525 rtw89_core_rx_to_mac80211(rtwdev, phy_ppdu, desc_info, skb_ppdu, rx_status); 2526 } 2527 } 2528 2529 static void rtw89_core_rx_process_ppdu_sts(struct rtw89_dev *rtwdev, 2530 struct rtw89_rx_desc_info *desc_info, 2531 struct sk_buff *skb) 2532 { 2533 struct rtw89_rx_phy_ppdu phy_ppdu = {.buf = skb->data, .valid = false, 2534 .len = skb->len, 2535 .to_self = desc_info->addr1_match, 2536 .rate = desc_info->data_rate, 2537 .mac_id = desc_info->mac_id, 2538 .phy_idx = desc_info->bb_sel}; 2539 int ret; 2540 2541 if (desc_info->mac_info_valid) { 2542 ret = rtw89_core_rx_process_mac_ppdu(rtwdev, skb, &phy_ppdu); 2543 if (ret) 2544 goto out; 2545 } 2546 2547 ret = rtw89_core_rx_process_phy_ppdu(rtwdev, &phy_ppdu); 2548 if (ret) 2549 goto out; 2550 2551 rtw89_core_rx_process_phy_sts(rtwdev, &phy_ppdu); 2552 2553 out: 2554 rtw89_core_rx_pending_skb(rtwdev, &phy_ppdu, desc_info, skb); 2555 dev_kfree_skb_any(skb); 2556 } 2557 2558 static void rtw89_core_rx_process_report(struct rtw89_dev *rtwdev, 2559 struct rtw89_rx_desc_info *desc_info, 2560 struct sk_buff *skb) 2561 { 2562 switch (desc_info->pkt_type) { 2563 case RTW89_CORE_RX_TYPE_C2H: 2564 rtw89_fw_c2h_irqsafe(rtwdev, skb); 2565 break; 2566 case RTW89_CORE_RX_TYPE_PPDU_STAT: 2567 rtw89_core_rx_process_ppdu_sts(rtwdev, desc_info, skb); 2568 break; 2569 default: 2570 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "unhandled pkt_type=%d\n", 2571 desc_info->pkt_type); 2572 dev_kfree_skb_any(skb); 2573 break; 2574 } 2575 } 2576 2577 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev, 2578 struct rtw89_rx_desc_info *desc_info, 2579 u8 *data, u32 data_offset) 2580 { 2581 const struct rtw89_chip_info *chip = rtwdev->chip; 2582 struct rtw89_rxdesc_short *rxd_s; 2583 struct rtw89_rxdesc_long *rxd_l; 2584 u8 shift_len, drv_info_len; 2585 2586 rxd_s = (struct rtw89_rxdesc_short *)(data + data_offset); 2587 desc_info->pkt_size = le32_get_bits(rxd_s->dword0, AX_RXD_RPKT_LEN_MASK); 2588 desc_info->drv_info_size = le32_get_bits(rxd_s->dword0, AX_RXD_DRV_INFO_SIZE_MASK); 2589 desc_info->long_rxdesc = le32_get_bits(rxd_s->dword0, AX_RXD_LONG_RXD); 2590 desc_info->pkt_type = le32_get_bits(rxd_s->dword0, AX_RXD_RPKT_TYPE_MASK); 2591 desc_info->mac_info_valid = le32_get_bits(rxd_s->dword0, AX_RXD_MAC_INFO_VLD); 2592 if (chip->chip_id == RTL8852C) 2593 desc_info->bw = le32_get_bits(rxd_s->dword1, AX_RXD_BW_v1_MASK); 2594 else 2595 desc_info->bw = le32_get_bits(rxd_s->dword1, AX_RXD_BW_MASK); 2596 desc_info->data_rate = le32_get_bits(rxd_s->dword1, AX_RXD_RX_DATARATE_MASK); 2597 desc_info->gi_ltf = le32_get_bits(rxd_s->dword1, AX_RXD_RX_GI_LTF_MASK); 2598 desc_info->user_id = le32_get_bits(rxd_s->dword1, AX_RXD_USER_ID_MASK); 2599 desc_info->sr_en = le32_get_bits(rxd_s->dword1, AX_RXD_SR_EN); 2600 desc_info->ppdu_cnt = le32_get_bits(rxd_s->dword1, AX_RXD_PPDU_CNT_MASK); 2601 desc_info->ppdu_type = le32_get_bits(rxd_s->dword1, AX_RXD_PPDU_TYPE_MASK); 2602 desc_info->free_run_cnt = le32_get_bits(rxd_s->dword2, AX_RXD_FREERUN_CNT_MASK); 2603 desc_info->icv_err = le32_get_bits(rxd_s->dword3, AX_RXD_ICV_ERR); 2604 desc_info->crc32_err = le32_get_bits(rxd_s->dword3, AX_RXD_CRC32_ERR); 2605 desc_info->hw_dec = le32_get_bits(rxd_s->dword3, AX_RXD_HW_DEC); 2606 desc_info->sw_dec = le32_get_bits(rxd_s->dword3, AX_RXD_SW_DEC); 2607 desc_info->addr1_match = le32_get_bits(rxd_s->dword3, AX_RXD_A1_MATCH); 2608 2609 shift_len = desc_info->shift << 1; /* 2-byte unit */ 2610 drv_info_len = desc_info->drv_info_size << 3; /* 8-byte unit */ 2611 desc_info->offset = data_offset + shift_len + drv_info_len; 2612 if (desc_info->long_rxdesc) 2613 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_long); 2614 else 2615 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_short); 2616 desc_info->ready = true; 2617 2618 if (!desc_info->long_rxdesc) 2619 return; 2620 2621 rxd_l = (struct rtw89_rxdesc_long *)(data + data_offset); 2622 desc_info->frame_type = le32_get_bits(rxd_l->dword4, AX_RXD_TYPE_MASK); 2623 desc_info->addr_cam_valid = le32_get_bits(rxd_l->dword5, AX_RXD_ADDR_CAM_VLD); 2624 desc_info->addr_cam_id = le32_get_bits(rxd_l->dword5, AX_RXD_ADDR_CAM_MASK); 2625 desc_info->sec_cam_id = le32_get_bits(rxd_l->dword5, AX_RXD_SEC_CAM_IDX_MASK); 2626 desc_info->mac_id = le32_get_bits(rxd_l->dword5, AX_RXD_MAC_ID_MASK); 2627 desc_info->rx_pl_id = le32_get_bits(rxd_l->dword5, AX_RXD_RX_PL_ID_MASK); 2628 } 2629 EXPORT_SYMBOL(rtw89_core_query_rxdesc); 2630 2631 void rtw89_core_query_rxdesc_v2(struct rtw89_dev *rtwdev, 2632 struct rtw89_rx_desc_info *desc_info, 2633 u8 *data, u32 data_offset) 2634 { 2635 struct rtw89_rxdesc_phy_rpt_v2 *rxd_rpt; 2636 struct rtw89_rxdesc_short_v2 *rxd_s; 2637 struct rtw89_rxdesc_long_v2 *rxd_l; 2638 u16 shift_len, drv_info_len, phy_rtp_len, hdr_cnv_len; 2639 2640 rxd_s = (struct rtw89_rxdesc_short_v2 *)(data + data_offset); 2641 2642 desc_info->pkt_size = le32_get_bits(rxd_s->dword0, BE_RXD_RPKT_LEN_MASK); 2643 desc_info->drv_info_size = le32_get_bits(rxd_s->dword0, BE_RXD_DRV_INFO_SZ_MASK); 2644 desc_info->phy_rpt_size = le32_get_bits(rxd_s->dword0, BE_RXD_PHY_RPT_SZ_MASK); 2645 desc_info->hdr_cnv_size = le32_get_bits(rxd_s->dword0, BE_RXD_HDR_CNV_SZ_MASK); 2646 desc_info->shift = le32_get_bits(rxd_s->dword0, BE_RXD_SHIFT_MASK); 2647 desc_info->long_rxdesc = le32_get_bits(rxd_s->dword0, BE_RXD_LONG_RXD); 2648 desc_info->pkt_type = le32_get_bits(rxd_s->dword0, BE_RXD_RPKT_TYPE_MASK); 2649 desc_info->bb_sel = le32_get_bits(rxd_s->dword0, BE_RXD_BB_SEL); 2650 if (desc_info->pkt_type == RTW89_CORE_RX_TYPE_PPDU_STAT) 2651 desc_info->mac_info_valid = true; 2652 2653 desc_info->frame_type = le32_get_bits(rxd_s->dword2, BE_RXD_TYPE_MASK); 2654 desc_info->mac_id = le32_get_bits(rxd_s->dword2, BE_RXD_MAC_ID_MASK); 2655 desc_info->addr_cam_valid = le32_get_bits(rxd_s->dword2, BE_RXD_ADDR_CAM_VLD); 2656 2657 desc_info->icv_err = le32_get_bits(rxd_s->dword3, BE_RXD_ICV_ERR); 2658 desc_info->crc32_err = le32_get_bits(rxd_s->dword3, BE_RXD_CRC32_ERR); 2659 desc_info->hw_dec = le32_get_bits(rxd_s->dword3, BE_RXD_HW_DEC); 2660 desc_info->sw_dec = le32_get_bits(rxd_s->dword3, BE_RXD_SW_DEC); 2661 desc_info->addr1_match = le32_get_bits(rxd_s->dword3, BE_RXD_A1_MATCH); 2662 2663 desc_info->bw = le32_get_bits(rxd_s->dword4, BE_RXD_BW_MASK); 2664 desc_info->data_rate = le32_get_bits(rxd_s->dword4, BE_RXD_RX_DATARATE_MASK); 2665 desc_info->gi_ltf = le32_get_bits(rxd_s->dword4, BE_RXD_RX_GI_LTF_MASK); 2666 desc_info->ppdu_cnt = le32_get_bits(rxd_s->dword4, BE_RXD_PPDU_CNT_MASK); 2667 desc_info->ppdu_type = le32_get_bits(rxd_s->dword4, BE_RXD_PPDU_TYPE_MASK); 2668 2669 desc_info->free_run_cnt = le32_to_cpu(rxd_s->dword5); 2670 2671 shift_len = desc_info->shift << 1; /* 2-byte unit */ 2672 drv_info_len = desc_info->drv_info_size << 3; /* 8-byte unit */ 2673 phy_rtp_len = desc_info->phy_rpt_size << 3; /* 8-byte unit */ 2674 hdr_cnv_len = desc_info->hdr_cnv_size << 4; /* 16-byte unit */ 2675 desc_info->offset = data_offset + shift_len + drv_info_len + 2676 phy_rtp_len + hdr_cnv_len; 2677 2678 if (desc_info->long_rxdesc) 2679 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_long_v2); 2680 else 2681 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_short_v2); 2682 desc_info->ready = true; 2683 2684 if (phy_rtp_len == sizeof(*rxd_rpt)) { 2685 rxd_rpt = (struct rtw89_rxdesc_phy_rpt_v2 *)(data + data_offset + 2686 desc_info->rxd_len); 2687 desc_info->rssi = le32_get_bits(rxd_rpt->dword0, BE_RXD_PHY_RSSI); 2688 } 2689 2690 if (!desc_info->long_rxdesc) 2691 return; 2692 2693 rxd_l = (struct rtw89_rxdesc_long_v2 *)(data + data_offset); 2694 2695 desc_info->sr_en = le32_get_bits(rxd_l->dword6, BE_RXD_SR_EN); 2696 desc_info->user_id = le32_get_bits(rxd_l->dword6, BE_RXD_USER_ID_MASK); 2697 desc_info->addr_cam_id = le32_get_bits(rxd_l->dword6, BE_RXD_ADDR_CAM_MASK); 2698 desc_info->sec_cam_id = le32_get_bits(rxd_l->dword6, BE_RXD_SEC_CAM_IDX_MASK); 2699 2700 desc_info->rx_pl_id = le32_get_bits(rxd_l->dword7, BE_RXD_RX_PL_ID_MASK); 2701 } 2702 EXPORT_SYMBOL(rtw89_core_query_rxdesc_v2); 2703 2704 struct rtw89_core_iter_rx_status { 2705 struct rtw89_dev *rtwdev; 2706 struct ieee80211_rx_status *rx_status; 2707 struct rtw89_rx_desc_info *desc_info; 2708 u8 mac_id; 2709 }; 2710 2711 static 2712 void rtw89_core_stats_sta_rx_status_iter(void *data, struct ieee80211_sta *sta) 2713 { 2714 struct rtw89_core_iter_rx_status *iter_data = 2715 (struct rtw89_core_iter_rx_status *)data; 2716 struct ieee80211_rx_status *rx_status = iter_data->rx_status; 2717 struct rtw89_rx_desc_info *desc_info = iter_data->desc_info; 2718 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta); 2719 struct rtw89_sta_link *rtwsta_link; 2720 u8 mac_id = iter_data->mac_id; 2721 2722 rtwsta_link = rtw89_sta_get_link_inst(rtwsta, desc_info->bb_sel); 2723 if (unlikely(!rtwsta_link)) 2724 return; 2725 2726 if (mac_id != rtwsta_link->mac_id) 2727 return; 2728 2729 rtwsta_link->rx_status = *rx_status; 2730 rtwsta_link->rx_hw_rate = desc_info->data_rate; 2731 } 2732 2733 static void rtw89_core_stats_sta_rx_status(struct rtw89_dev *rtwdev, 2734 struct rtw89_rx_desc_info *desc_info, 2735 struct ieee80211_rx_status *rx_status) 2736 { 2737 struct rtw89_core_iter_rx_status iter_data; 2738 2739 if (!desc_info->addr1_match || !desc_info->long_rxdesc) 2740 return; 2741 2742 if (desc_info->frame_type != RTW89_RX_TYPE_DATA) 2743 return; 2744 2745 iter_data.rtwdev = rtwdev; 2746 iter_data.rx_status = rx_status; 2747 iter_data.desc_info = desc_info; 2748 iter_data.mac_id = desc_info->mac_id; 2749 ieee80211_iterate_stations_atomic(rtwdev->hw, 2750 rtw89_core_stats_sta_rx_status_iter, 2751 &iter_data); 2752 } 2753 2754 static void rtw89_core_update_rx_status(struct rtw89_dev *rtwdev, 2755 struct rtw89_rx_desc_info *desc_info, 2756 struct ieee80211_rx_status *rx_status) 2757 { 2758 const struct cfg80211_chan_def *chandef = 2759 rtw89_chandef_get(rtwdev, RTW89_CHANCTX_0); 2760 u16 data_rate; 2761 u8 data_rate_mode; 2762 bool eht = false; 2763 u8 gi; 2764 2765 /* currently using single PHY */ 2766 rx_status->freq = chandef->chan->center_freq; 2767 rx_status->band = chandef->chan->band; 2768 2769 if (rtwdev->scanning && 2770 RTW89_CHK_FW_FEATURE(SCAN_OFFLOAD, &rtwdev->fw)) { 2771 const struct rtw89_chan *cur = rtw89_scan_chan_get(rtwdev); 2772 u8 chan = cur->primary_channel; 2773 u8 band = cur->band_type; 2774 enum nl80211_band nl_band; 2775 2776 nl_band = rtw89_hw_to_nl80211_band(band); 2777 rx_status->freq = ieee80211_channel_to_frequency(chan, nl_band); 2778 rx_status->band = nl_band; 2779 } 2780 2781 if (desc_info->icv_err || desc_info->crc32_err) 2782 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; 2783 2784 if (desc_info->hw_dec && 2785 !(desc_info->sw_dec || desc_info->icv_err)) 2786 rx_status->flag |= RX_FLAG_DECRYPTED; 2787 2788 rx_status->bw = rtw89_hw_to_rate_info_bw(desc_info->bw); 2789 2790 data_rate = desc_info->data_rate; 2791 data_rate_mode = rtw89_get_data_rate_mode(rtwdev, data_rate); 2792 if (data_rate_mode == DATA_RATE_MODE_NON_HT) { 2793 rx_status->encoding = RX_ENC_LEGACY; 2794 rx_status->rate_idx = rtw89_get_data_not_ht_idx(rtwdev, data_rate); 2795 /* convert rate_idx after we get the correct band */ 2796 } else if (data_rate_mode == DATA_RATE_MODE_HT) { 2797 rx_status->encoding = RX_ENC_HT; 2798 rx_status->rate_idx = rtw89_get_data_ht_mcs(rtwdev, data_rate); 2799 if (desc_info->gi_ltf) 2800 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 2801 } else if (data_rate_mode == DATA_RATE_MODE_VHT) { 2802 rx_status->encoding = RX_ENC_VHT; 2803 rx_status->rate_idx = rtw89_get_data_mcs(rtwdev, data_rate); 2804 rx_status->nss = rtw89_get_data_nss(rtwdev, data_rate) + 1; 2805 if (desc_info->gi_ltf) 2806 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 2807 } else if (data_rate_mode == DATA_RATE_MODE_HE) { 2808 rx_status->encoding = RX_ENC_HE; 2809 rx_status->rate_idx = rtw89_get_data_mcs(rtwdev, data_rate); 2810 rx_status->nss = rtw89_get_data_nss(rtwdev, data_rate) + 1; 2811 } else if (data_rate_mode == DATA_RATE_MODE_EHT) { 2812 rx_status->encoding = RX_ENC_EHT; 2813 rx_status->rate_idx = rtw89_get_data_mcs(rtwdev, data_rate); 2814 rx_status->nss = rtw89_get_data_nss(rtwdev, data_rate) + 1; 2815 eht = true; 2816 } else { 2817 rtw89_warn(rtwdev, "invalid RX rate mode %d\n", data_rate_mode); 2818 } 2819 2820 /* he_gi is used to match ppdu, so we always fill it. */ 2821 gi = rtw89_rxdesc_to_nl_he_eht_gi(rtwdev, desc_info->gi_ltf, true, eht); 2822 if (eht) 2823 rx_status->eht.gi = gi; 2824 else 2825 rx_status->he_gi = gi; 2826 rx_status->flag |= RX_FLAG_MACTIME_START; 2827 rx_status->mactime = desc_info->free_run_cnt; 2828 2829 rtw89_chip_phy_rpt_to_rssi(rtwdev, desc_info, rx_status); 2830 rtw89_core_stats_sta_rx_status(rtwdev, desc_info, rx_status); 2831 } 2832 2833 static enum rtw89_ps_mode rtw89_update_ps_mode(struct rtw89_dev *rtwdev) 2834 { 2835 const struct rtw89_chip_info *chip = rtwdev->chip; 2836 2837 if (rtw89_disable_ps_mode || !chip->ps_mode_supported || 2838 RTW89_CHK_FW_FEATURE(NO_DEEP_PS, &rtwdev->fw)) 2839 return RTW89_PS_MODE_NONE; 2840 2841 if ((chip->ps_mode_supported & BIT(RTW89_PS_MODE_PWR_GATED)) && 2842 !RTW89_CHK_FW_FEATURE(NO_LPS_PG, &rtwdev->fw)) 2843 return RTW89_PS_MODE_PWR_GATED; 2844 2845 if (chip->ps_mode_supported & BIT(RTW89_PS_MODE_CLK_GATED)) 2846 return RTW89_PS_MODE_CLK_GATED; 2847 2848 if (chip->ps_mode_supported & BIT(RTW89_PS_MODE_RFOFF)) 2849 return RTW89_PS_MODE_RFOFF; 2850 2851 return RTW89_PS_MODE_NONE; 2852 } 2853 2854 static void rtw89_core_flush_ppdu_rx_queue(struct rtw89_dev *rtwdev, 2855 struct rtw89_rx_desc_info *desc_info) 2856 { 2857 struct rtw89_ppdu_sts_info *ppdu_sts = &rtwdev->ppdu_sts; 2858 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 2859 struct ieee80211_rx_status *rx_status; 2860 struct sk_buff *skb_ppdu, *tmp; 2861 2862 skb_queue_walk_safe(&ppdu_sts->rx_queue[band], skb_ppdu, tmp) { 2863 skb_unlink(skb_ppdu, &ppdu_sts->rx_queue[band]); 2864 rx_status = IEEE80211_SKB_RXCB(skb_ppdu); 2865 rtw89_core_rx_to_mac80211(rtwdev, NULL, desc_info, skb_ppdu, rx_status); 2866 } 2867 } 2868 2869 static 2870 void rtw89_core_rx_pkt_hdl(struct rtw89_dev *rtwdev, const struct sk_buff *skb, 2871 const struct rtw89_rx_desc_info *desc) 2872 { 2873 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 2874 struct rtw89_sta_link *rtwsta_link; 2875 struct ieee80211_sta *sta; 2876 struct rtw89_sta *rtwsta; 2877 u8 macid = desc->mac_id; 2878 2879 if (!refcount_read(&rtwdev->refcount_ap_info)) 2880 return; 2881 2882 rcu_read_lock(); 2883 2884 rtwsta_link = rtw89_assoc_link_rcu_dereference(rtwdev, macid); 2885 if (!rtwsta_link) 2886 goto out; 2887 2888 rtwsta = rtwsta_link->rtwsta; 2889 if (!test_bit(RTW89_REMOTE_STA_IN_PS, rtwsta->flags)) 2890 goto out; 2891 2892 sta = rtwsta_to_sta(rtwsta); 2893 if (ieee80211_is_pspoll(hdr->frame_control)) 2894 ieee80211_sta_pspoll(sta); 2895 else if (ieee80211_has_pm(hdr->frame_control) && 2896 (ieee80211_is_data_qos(hdr->frame_control) || 2897 ieee80211_is_qos_nullfunc(hdr->frame_control))) 2898 ieee80211_sta_uapsd_trigger(sta, ieee80211_get_tid(hdr)); 2899 2900 out: 2901 rcu_read_unlock(); 2902 } 2903 2904 void rtw89_core_rx(struct rtw89_dev *rtwdev, 2905 struct rtw89_rx_desc_info *desc_info, 2906 struct sk_buff *skb) 2907 { 2908 struct ieee80211_rx_status *rx_status; 2909 struct rtw89_ppdu_sts_info *ppdu_sts = &rtwdev->ppdu_sts; 2910 u8 ppdu_cnt = desc_info->ppdu_cnt; 2911 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 2912 2913 if (desc_info->pkt_type != RTW89_CORE_RX_TYPE_WIFI) { 2914 rtw89_core_rx_process_report(rtwdev, desc_info, skb); 2915 return; 2916 } 2917 2918 if (ppdu_sts->curr_rx_ppdu_cnt[band] != ppdu_cnt) { 2919 rtw89_core_flush_ppdu_rx_queue(rtwdev, desc_info); 2920 ppdu_sts->curr_rx_ppdu_cnt[band] = ppdu_cnt; 2921 } 2922 2923 rx_status = IEEE80211_SKB_RXCB(skb); 2924 memset(rx_status, 0, sizeof(*rx_status)); 2925 rtw89_core_update_rx_status(rtwdev, desc_info, rx_status); 2926 rtw89_core_rx_pkt_hdl(rtwdev, skb, desc_info); 2927 if (desc_info->long_rxdesc && 2928 BIT(desc_info->frame_type) & PPDU_FILTER_BITMAP) 2929 skb_queue_tail(&ppdu_sts->rx_queue[band], skb); 2930 else 2931 rtw89_core_rx_to_mac80211(rtwdev, NULL, desc_info, skb, rx_status); 2932 } 2933 EXPORT_SYMBOL(rtw89_core_rx); 2934 2935 void rtw89_core_napi_start(struct rtw89_dev *rtwdev) 2936 { 2937 if (test_and_set_bit(RTW89_FLAG_NAPI_RUNNING, rtwdev->flags)) 2938 return; 2939 2940 napi_enable(&rtwdev->napi); 2941 } 2942 EXPORT_SYMBOL(rtw89_core_napi_start); 2943 2944 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev) 2945 { 2946 if (!test_and_clear_bit(RTW89_FLAG_NAPI_RUNNING, rtwdev->flags)) 2947 return; 2948 2949 napi_synchronize(&rtwdev->napi); 2950 napi_disable(&rtwdev->napi); 2951 } 2952 EXPORT_SYMBOL(rtw89_core_napi_stop); 2953 2954 int rtw89_core_napi_init(struct rtw89_dev *rtwdev) 2955 { 2956 rtwdev->netdev = alloc_netdev_dummy(0); 2957 if (!rtwdev->netdev) 2958 return -ENOMEM; 2959 2960 netif_napi_add(rtwdev->netdev, &rtwdev->napi, 2961 rtwdev->hci.ops->napi_poll); 2962 return 0; 2963 } 2964 EXPORT_SYMBOL(rtw89_core_napi_init); 2965 2966 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev) 2967 { 2968 rtw89_core_napi_stop(rtwdev); 2969 netif_napi_del(&rtwdev->napi); 2970 free_netdev(rtwdev->netdev); 2971 } 2972 EXPORT_SYMBOL(rtw89_core_napi_deinit); 2973 2974 static void rtw89_core_ba_work(struct work_struct *work) 2975 { 2976 struct rtw89_dev *rtwdev = 2977 container_of(work, struct rtw89_dev, ba_work); 2978 struct rtw89_txq *rtwtxq, *tmp; 2979 int ret; 2980 2981 spin_lock_bh(&rtwdev->ba_lock); 2982 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->ba_list, list) { 2983 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 2984 struct ieee80211_sta *sta = txq->sta; 2985 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta); 2986 u8 tid = txq->tid; 2987 2988 if (!sta) { 2989 rtw89_warn(rtwdev, "cannot start BA without sta\n"); 2990 goto skip_ba_work; 2991 } 2992 2993 if (rtwsta->disassoc) { 2994 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 2995 "cannot start BA with disassoc sta\n"); 2996 goto skip_ba_work; 2997 } 2998 2999 ret = ieee80211_start_tx_ba_session(sta, tid, 0); 3000 if (ret) { 3001 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 3002 "failed to setup BA session for %pM:%2d: %d\n", 3003 sta->addr, tid, ret); 3004 if (ret == -EINVAL) 3005 set_bit(RTW89_TXQ_F_BLOCK_BA, &rtwtxq->flags); 3006 } 3007 skip_ba_work: 3008 list_del_init(&rtwtxq->list); 3009 } 3010 spin_unlock_bh(&rtwdev->ba_lock); 3011 } 3012 3013 void rtw89_core_free_sta_pending_ba(struct rtw89_dev *rtwdev, 3014 struct ieee80211_sta *sta) 3015 { 3016 struct rtw89_txq *rtwtxq, *tmp; 3017 3018 spin_lock_bh(&rtwdev->ba_lock); 3019 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->ba_list, list) { 3020 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 3021 3022 if (sta == txq->sta) 3023 list_del_init(&rtwtxq->list); 3024 } 3025 spin_unlock_bh(&rtwdev->ba_lock); 3026 } 3027 3028 void rtw89_core_free_sta_pending_forbid_ba(struct rtw89_dev *rtwdev, 3029 struct ieee80211_sta *sta) 3030 { 3031 struct rtw89_txq *rtwtxq, *tmp; 3032 3033 spin_lock_bh(&rtwdev->ba_lock); 3034 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->forbid_ba_list, list) { 3035 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 3036 3037 if (sta == txq->sta) { 3038 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags); 3039 list_del_init(&rtwtxq->list); 3040 } 3041 } 3042 spin_unlock_bh(&rtwdev->ba_lock); 3043 } 3044 3045 void rtw89_core_free_sta_pending_roc_tx(struct rtw89_dev *rtwdev, 3046 struct ieee80211_sta *sta) 3047 { 3048 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta); 3049 struct sk_buff *skb, *tmp; 3050 3051 skb_queue_walk_safe(&rtwsta->roc_queue, skb, tmp) { 3052 skb_unlink(skb, &rtwsta->roc_queue); 3053 dev_kfree_skb_any(skb); 3054 } 3055 } 3056 3057 static void rtw89_core_stop_tx_ba_session(struct rtw89_dev *rtwdev, 3058 struct rtw89_txq *rtwtxq) 3059 { 3060 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 3061 struct ieee80211_sta *sta = txq->sta; 3062 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta); 3063 3064 if (unlikely(!rtwsta) || unlikely(rtwsta->disassoc)) 3065 return; 3066 3067 if (!test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags) || 3068 test_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags)) 3069 return; 3070 3071 spin_lock_bh(&rtwdev->ba_lock); 3072 if (!test_and_set_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags)) 3073 list_add_tail(&rtwtxq->list, &rtwdev->forbid_ba_list); 3074 spin_unlock_bh(&rtwdev->ba_lock); 3075 3076 ieee80211_stop_tx_ba_session(sta, txq->tid); 3077 cancel_delayed_work(&rtwdev->forbid_ba_work); 3078 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->forbid_ba_work, 3079 RTW89_FORBID_BA_TIMER); 3080 } 3081 3082 static void rtw89_core_txq_check_agg(struct rtw89_dev *rtwdev, 3083 struct rtw89_txq *rtwtxq, 3084 struct sk_buff *skb) 3085 { 3086 struct ieee80211_hw *hw = rtwdev->hw; 3087 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 3088 struct ieee80211_sta *sta = txq->sta; 3089 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta); 3090 3091 if (test_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags)) 3092 return; 3093 3094 if (unlikely(skb->protocol == cpu_to_be16(ETH_P_PAE))) { 3095 rtw89_core_stop_tx_ba_session(rtwdev, rtwtxq); 3096 return; 3097 } 3098 3099 if (unlikely(!sta)) 3100 return; 3101 3102 if (unlikely(test_bit(RTW89_TXQ_F_BLOCK_BA, &rtwtxq->flags))) 3103 return; 3104 3105 if (test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags)) { 3106 IEEE80211_SKB_CB(skb)->flags |= IEEE80211_TX_CTL_AMPDU; 3107 return; 3108 } 3109 3110 spin_lock_bh(&rtwdev->ba_lock); 3111 if (!rtwsta->disassoc && list_empty(&rtwtxq->list)) { 3112 list_add_tail(&rtwtxq->list, &rtwdev->ba_list); 3113 ieee80211_queue_work(hw, &rtwdev->ba_work); 3114 } 3115 spin_unlock_bh(&rtwdev->ba_lock); 3116 } 3117 3118 static void rtw89_core_txq_push(struct rtw89_dev *rtwdev, 3119 struct rtw89_txq *rtwtxq, 3120 unsigned long frame_cnt, 3121 unsigned long byte_cnt) 3122 { 3123 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 3124 struct ieee80211_vif *vif = txq->vif; 3125 struct ieee80211_sta *sta = txq->sta; 3126 struct sk_buff *skb; 3127 unsigned long i; 3128 int ret; 3129 3130 rcu_read_lock(); 3131 for (i = 0; i < frame_cnt; i++) { 3132 skb = ieee80211_tx_dequeue_ni(rtwdev->hw, txq); 3133 if (!skb) { 3134 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "dequeue a NULL skb\n"); 3135 goto out; 3136 } 3137 rtw89_core_txq_check_agg(rtwdev, rtwtxq, skb); 3138 ret = rtw89_core_tx_write(rtwdev, vif, sta, skb, NULL); 3139 if (ret) { 3140 rtw89_err(rtwdev, "failed to push txq: %d\n", ret); 3141 ieee80211_free_txskb(rtwdev->hw, skb); 3142 break; 3143 } 3144 } 3145 out: 3146 rcu_read_unlock(); 3147 } 3148 3149 static u32 rtw89_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 tid) 3150 { 3151 u8 qsel, ch_dma; 3152 3153 qsel = rtw89_core_get_qsel(rtwdev, tid); 3154 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); 3155 3156 return rtw89_hci_check_and_reclaim_tx_resource(rtwdev, ch_dma); 3157 } 3158 3159 static bool rtw89_core_txq_agg_wait(struct rtw89_dev *rtwdev, 3160 struct ieee80211_txq *txq, 3161 unsigned long *frame_cnt, 3162 bool *sched_txq, bool *reinvoke) 3163 { 3164 struct rtw89_txq *rtwtxq = (struct rtw89_txq *)txq->drv_priv; 3165 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(txq->sta); 3166 struct rtw89_sta_link *rtwsta_link; 3167 3168 if (!rtwsta) 3169 return false; 3170 3171 rtwsta_link = rtw89_get_designated_link(rtwsta); 3172 if (unlikely(!rtwsta_link)) { 3173 rtw89_err(rtwdev, "agg wait: find no designated link\n"); 3174 return false; 3175 } 3176 3177 if (rtwsta_link->max_agg_wait <= 0) 3178 return false; 3179 3180 if (rtwdev->stats.tx_tfc_lv <= RTW89_TFC_MID) 3181 return false; 3182 3183 if (*frame_cnt > 1) { 3184 *frame_cnt -= 1; 3185 *sched_txq = true; 3186 *reinvoke = true; 3187 rtwtxq->wait_cnt = 1; 3188 return false; 3189 } 3190 3191 if (*frame_cnt == 1 && rtwtxq->wait_cnt < rtwsta_link->max_agg_wait) { 3192 *reinvoke = true; 3193 rtwtxq->wait_cnt++; 3194 return true; 3195 } 3196 3197 rtwtxq->wait_cnt = 0; 3198 return false; 3199 } 3200 3201 static void rtw89_core_txq_schedule(struct rtw89_dev *rtwdev, u8 ac, bool *reinvoke) 3202 { 3203 struct ieee80211_hw *hw = rtwdev->hw; 3204 struct ieee80211_txq *txq; 3205 struct rtw89_vif *rtwvif; 3206 struct rtw89_txq *rtwtxq; 3207 unsigned long frame_cnt; 3208 unsigned long byte_cnt; 3209 u32 tx_resource; 3210 bool sched_txq; 3211 3212 ieee80211_txq_schedule_start(hw, ac); 3213 while ((txq = ieee80211_next_txq(hw, ac))) { 3214 rtwtxq = (struct rtw89_txq *)txq->drv_priv; 3215 rtwvif = vif_to_rtwvif(txq->vif); 3216 3217 if (rtwvif->offchan) { 3218 ieee80211_return_txq(hw, txq, true); 3219 continue; 3220 } 3221 tx_resource = rtw89_check_and_reclaim_tx_resource(rtwdev, txq->tid); 3222 sched_txq = false; 3223 3224 ieee80211_txq_get_depth(txq, &frame_cnt, &byte_cnt); 3225 if (rtw89_core_txq_agg_wait(rtwdev, txq, &frame_cnt, &sched_txq, reinvoke)) { 3226 ieee80211_return_txq(hw, txq, true); 3227 continue; 3228 } 3229 frame_cnt = min_t(unsigned long, frame_cnt, tx_resource); 3230 rtw89_core_txq_push(rtwdev, rtwtxq, frame_cnt, byte_cnt); 3231 ieee80211_return_txq(hw, txq, sched_txq); 3232 if (frame_cnt != 0) 3233 rtw89_core_tx_kick_off(rtwdev, rtw89_core_get_qsel(rtwdev, txq->tid)); 3234 3235 /* bound of tx_resource could get stuck due to burst traffic */ 3236 if (frame_cnt == tx_resource) 3237 *reinvoke = true; 3238 } 3239 ieee80211_txq_schedule_end(hw, ac); 3240 } 3241 3242 static void rtw89_ips_work(struct wiphy *wiphy, struct wiphy_work *work) 3243 { 3244 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 3245 ips_work); 3246 3247 lockdep_assert_wiphy(wiphy); 3248 3249 rtw89_enter_ips_by_hwflags(rtwdev); 3250 } 3251 3252 static void rtw89_core_txq_work(struct work_struct *w) 3253 { 3254 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev, txq_work); 3255 bool reinvoke = false; 3256 u8 ac; 3257 3258 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++) 3259 rtw89_core_txq_schedule(rtwdev, ac, &reinvoke); 3260 3261 if (reinvoke) { 3262 /* reinvoke to process the last frame */ 3263 mod_delayed_work(rtwdev->txq_wq, &rtwdev->txq_reinvoke_work, 1); 3264 } 3265 } 3266 3267 static void rtw89_core_txq_reinvoke_work(struct work_struct *w) 3268 { 3269 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev, 3270 txq_reinvoke_work.work); 3271 3272 queue_work(rtwdev->txq_wq, &rtwdev->txq_work); 3273 } 3274 3275 static void rtw89_forbid_ba_work(struct work_struct *w) 3276 { 3277 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev, 3278 forbid_ba_work.work); 3279 struct rtw89_txq *rtwtxq, *tmp; 3280 3281 spin_lock_bh(&rtwdev->ba_lock); 3282 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->forbid_ba_list, list) { 3283 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags); 3284 list_del_init(&rtwtxq->list); 3285 } 3286 spin_unlock_bh(&rtwdev->ba_lock); 3287 } 3288 3289 static void rtw89_core_sta_pending_tx_iter(void *data, 3290 struct ieee80211_sta *sta) 3291 { 3292 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta); 3293 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 3294 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 3295 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 3296 struct rtw89_vif_link *target = data; 3297 struct rtw89_vif_link *rtwvif_link; 3298 struct sk_buff *skb, *tmp; 3299 unsigned int link_id; 3300 int qsel, ret; 3301 3302 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) 3303 if (rtwvif_link->chanctx_idx == target->chanctx_idx) 3304 goto bottom; 3305 3306 return; 3307 3308 bottom: 3309 if (skb_queue_len(&rtwsta->roc_queue) == 0) 3310 return; 3311 3312 skb_queue_walk_safe(&rtwsta->roc_queue, skb, tmp) { 3313 skb_unlink(skb, &rtwsta->roc_queue); 3314 3315 ret = rtw89_core_tx_write(rtwdev, vif, sta, skb, &qsel); 3316 if (ret) { 3317 rtw89_warn(rtwdev, "pending tx failed with %d\n", ret); 3318 dev_kfree_skb_any(skb); 3319 } else { 3320 rtw89_core_tx_kick_off(rtwdev, qsel); 3321 } 3322 } 3323 } 3324 3325 static void rtw89_core_handle_sta_pending_tx(struct rtw89_dev *rtwdev, 3326 struct rtw89_vif_link *rtwvif_link) 3327 { 3328 ieee80211_iterate_stations_atomic(rtwdev->hw, 3329 rtw89_core_sta_pending_tx_iter, 3330 rtwvif_link); 3331 } 3332 3333 static int rtw89_core_send_nullfunc(struct rtw89_dev *rtwdev, 3334 struct rtw89_vif_link *rtwvif_link, bool qos, bool ps) 3335 { 3336 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 3337 int link_id = ieee80211_vif_is_mld(vif) ? rtwvif_link->link_id : -1; 3338 struct rtw89_sta_link *rtwsta_link; 3339 struct ieee80211_sta *sta; 3340 struct ieee80211_hdr *hdr; 3341 struct rtw89_sta *rtwsta; 3342 struct sk_buff *skb; 3343 int ret, qsel; 3344 3345 if (vif->type != NL80211_IFTYPE_STATION || !vif->cfg.assoc) 3346 return 0; 3347 3348 rcu_read_lock(); 3349 sta = ieee80211_find_sta(vif, vif->cfg.ap_addr); 3350 if (!sta) { 3351 ret = -EINVAL; 3352 goto out; 3353 } 3354 rtwsta = sta_to_rtwsta(sta); 3355 3356 skb = ieee80211_nullfunc_get(rtwdev->hw, vif, link_id, qos); 3357 if (!skb) { 3358 ret = -ENOMEM; 3359 goto out; 3360 } 3361 3362 hdr = (struct ieee80211_hdr *)skb->data; 3363 if (ps) 3364 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); 3365 3366 rtwsta_link = rtwsta->links[rtwvif_link->link_id]; 3367 if (unlikely(!rtwsta_link)) { 3368 ret = -ENOLINK; 3369 goto out; 3370 } 3371 3372 ret = rtw89_core_tx_write_link(rtwdev, rtwvif_link, rtwsta_link, skb, &qsel, true); 3373 if (ret) { 3374 rtw89_warn(rtwdev, "nullfunc transmit failed: %d\n", ret); 3375 dev_kfree_skb_any(skb); 3376 goto out; 3377 } 3378 3379 rcu_read_unlock(); 3380 3381 return rtw89_core_tx_kick_off_and_wait(rtwdev, skb, qsel, 3382 RTW89_ROC_TX_TIMEOUT); 3383 out: 3384 rcu_read_unlock(); 3385 3386 return ret; 3387 } 3388 3389 void rtw89_roc_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 3390 { 3391 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3392 struct rtw89_chanctx_pause_parm pause_parm = { 3393 .rsn = RTW89_CHANCTX_PAUSE_REASON_ROC, 3394 }; 3395 struct ieee80211_hw *hw = rtwdev->hw; 3396 struct rtw89_roc *roc = &rtwvif->roc; 3397 struct rtw89_vif_link *rtwvif_link; 3398 struct cfg80211_chan_def roc_chan; 3399 struct rtw89_vif *tmp_vif; 3400 u32 reg; 3401 int ret; 3402 3403 lockdep_assert_wiphy(hw->wiphy); 3404 3405 rtw89_leave_ips_by_hwflags(rtwdev); 3406 rtw89_leave_lps(rtwdev); 3407 3408 rtwvif_link = rtw89_get_designated_link(rtwvif); 3409 if (unlikely(!rtwvif_link)) { 3410 rtw89_err(rtwdev, "roc start: find no designated link\n"); 3411 return; 3412 } 3413 3414 roc->link_id = rtwvif_link->link_id; 3415 3416 pause_parm.trigger = rtwvif_link; 3417 rtw89_chanctx_pause(rtwdev, &pause_parm); 3418 3419 ret = rtw89_core_send_nullfunc(rtwdev, rtwvif_link, true, true); 3420 if (ret) 3421 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 3422 "roc send null-1 failed: %d\n", ret); 3423 3424 rtw89_for_each_rtwvif(rtwdev, tmp_vif) { 3425 struct rtw89_vif_link *tmp_link; 3426 unsigned int link_id; 3427 3428 rtw89_vif_for_each_link(tmp_vif, tmp_link, link_id) { 3429 if (tmp_link->chanctx_idx == rtwvif_link->chanctx_idx) { 3430 tmp_vif->offchan = true; 3431 break; 3432 } 3433 } 3434 } 3435 3436 cfg80211_chandef_create(&roc_chan, &roc->chan, NL80211_CHAN_NO_HT); 3437 rtw89_config_roc_chandef(rtwdev, rtwvif_link, &roc_chan); 3438 rtw89_set_channel(rtwdev); 3439 3440 reg = rtw89_mac_reg_by_idx(rtwdev, mac->rx_fltr, rtwvif_link->mac_idx); 3441 rtw89_write32_clr(rtwdev, reg, B_AX_A_UC_CAM_MATCH | B_AX_A_BC_CAM_MATCH); 3442 3443 ieee80211_ready_on_channel(hw); 3444 wiphy_delayed_work_cancel(hw->wiphy, &rtwvif->roc.roc_work); 3445 wiphy_delayed_work_queue(hw->wiphy, &rtwvif->roc.roc_work, 3446 msecs_to_jiffies(rtwvif->roc.duration)); 3447 } 3448 3449 void rtw89_roc_end(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 3450 { 3451 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3452 struct ieee80211_hw *hw = rtwdev->hw; 3453 struct rtw89_roc *roc = &rtwvif->roc; 3454 struct rtw89_vif_link *rtwvif_link; 3455 struct rtw89_vif *tmp_vif; 3456 u32 reg; 3457 int ret; 3458 3459 lockdep_assert_wiphy(hw->wiphy); 3460 3461 ieee80211_remain_on_channel_expired(hw); 3462 3463 rtw89_leave_ips_by_hwflags(rtwdev); 3464 rtw89_leave_lps(rtwdev); 3465 3466 rtwvif_link = rtwvif->links[roc->link_id]; 3467 if (unlikely(!rtwvif_link)) { 3468 rtw89_err(rtwdev, "roc end: find no link (link id %u)\n", 3469 roc->link_id); 3470 return; 3471 } 3472 3473 reg = rtw89_mac_reg_by_idx(rtwdev, mac->rx_fltr, rtwvif_link->mac_idx); 3474 rtw89_write32_mask(rtwdev, reg, B_AX_RX_FLTR_CFG_MASK, rtwdev->hal.rx_fltr); 3475 3476 roc->state = RTW89_ROC_IDLE; 3477 rtw89_config_roc_chandef(rtwdev, rtwvif_link, NULL); 3478 rtw89_chanctx_proceed(rtwdev, NULL); 3479 ret = rtw89_core_send_nullfunc(rtwdev, rtwvif_link, true, false); 3480 if (ret) 3481 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 3482 "roc send null-0 failed: %d\n", ret); 3483 3484 rtw89_for_each_rtwvif(rtwdev, tmp_vif) 3485 tmp_vif->offchan = false; 3486 3487 rtw89_core_handle_sta_pending_tx(rtwdev, rtwvif_link); 3488 queue_work(rtwdev->txq_wq, &rtwdev->txq_work); 3489 3490 if (hw->conf.flags & IEEE80211_CONF_IDLE) 3491 wiphy_delayed_work_queue(hw->wiphy, &roc->roc_work, 3492 msecs_to_jiffies(RTW89_ROC_IDLE_TIMEOUT)); 3493 } 3494 3495 void rtw89_roc_work(struct wiphy *wiphy, struct wiphy_work *work) 3496 { 3497 struct rtw89_vif *rtwvif = container_of(work, struct rtw89_vif, 3498 roc.roc_work.work); 3499 struct rtw89_dev *rtwdev = rtwvif->rtwdev; 3500 struct rtw89_roc *roc = &rtwvif->roc; 3501 3502 lockdep_assert_wiphy(wiphy); 3503 3504 switch (roc->state) { 3505 case RTW89_ROC_IDLE: 3506 rtw89_enter_ips_by_hwflags(rtwdev); 3507 break; 3508 case RTW89_ROC_MGMT: 3509 case RTW89_ROC_NORMAL: 3510 rtw89_roc_end(rtwdev, rtwvif); 3511 break; 3512 default: 3513 break; 3514 } 3515 } 3516 3517 static enum rtw89_tfc_lv rtw89_get_traffic_level(struct rtw89_dev *rtwdev, 3518 u32 throughput, u64 cnt) 3519 { 3520 if (cnt < 100) 3521 return RTW89_TFC_IDLE; 3522 if (throughput > 50) 3523 return RTW89_TFC_HIGH; 3524 if (throughput > 10) 3525 return RTW89_TFC_MID; 3526 if (throughput > 2) 3527 return RTW89_TFC_LOW; 3528 return RTW89_TFC_ULTRA_LOW; 3529 } 3530 3531 static bool rtw89_traffic_stats_calc(struct rtw89_dev *rtwdev, 3532 struct rtw89_traffic_stats *stats) 3533 { 3534 enum rtw89_tfc_lv tx_tfc_lv = stats->tx_tfc_lv; 3535 enum rtw89_tfc_lv rx_tfc_lv = stats->rx_tfc_lv; 3536 3537 stats->tx_throughput_raw = (u32)(stats->tx_unicast >> RTW89_TP_SHIFT); 3538 stats->rx_throughput_raw = (u32)(stats->rx_unicast >> RTW89_TP_SHIFT); 3539 3540 ewma_tp_add(&stats->tx_ewma_tp, stats->tx_throughput_raw); 3541 ewma_tp_add(&stats->rx_ewma_tp, stats->rx_throughput_raw); 3542 3543 stats->tx_throughput = ewma_tp_read(&stats->tx_ewma_tp); 3544 stats->rx_throughput = ewma_tp_read(&stats->rx_ewma_tp); 3545 stats->tx_tfc_lv = rtw89_get_traffic_level(rtwdev, stats->tx_throughput, 3546 stats->tx_cnt); 3547 stats->rx_tfc_lv = rtw89_get_traffic_level(rtwdev, stats->rx_throughput, 3548 stats->rx_cnt); 3549 stats->tx_avg_len = stats->tx_cnt ? 3550 DIV_ROUND_DOWN_ULL(stats->tx_unicast, stats->tx_cnt) : 0; 3551 stats->rx_avg_len = stats->rx_cnt ? 3552 DIV_ROUND_DOWN_ULL(stats->rx_unicast, stats->rx_cnt) : 0; 3553 3554 stats->tx_unicast = 0; 3555 stats->rx_unicast = 0; 3556 stats->tx_cnt = 0; 3557 stats->rx_cnt = 0; 3558 stats->rx_tf_periodic = stats->rx_tf_acc; 3559 stats->rx_tf_acc = 0; 3560 3561 if (tx_tfc_lv != stats->tx_tfc_lv || rx_tfc_lv != stats->rx_tfc_lv) 3562 return true; 3563 3564 return false; 3565 } 3566 3567 static bool rtw89_traffic_stats_track(struct rtw89_dev *rtwdev) 3568 { 3569 struct rtw89_vif_link *rtwvif_link; 3570 struct rtw89_vif *rtwvif; 3571 unsigned int link_id; 3572 bool tfc_changed; 3573 3574 tfc_changed = rtw89_traffic_stats_calc(rtwdev, &rtwdev->stats); 3575 3576 rtw89_for_each_rtwvif(rtwdev, rtwvif) { 3577 rtw89_traffic_stats_calc(rtwdev, &rtwvif->stats); 3578 3579 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) 3580 rtw89_fw_h2c_tp_offload(rtwdev, rtwvif_link); 3581 } 3582 3583 return tfc_changed; 3584 } 3585 3586 static void rtw89_enter_lps_track(struct rtw89_dev *rtwdev) 3587 { 3588 struct ieee80211_vif *vif; 3589 struct rtw89_vif *rtwvif; 3590 3591 rtw89_for_each_rtwvif(rtwdev, rtwvif) { 3592 if (rtwvif->tdls_peer) 3593 continue; 3594 if (rtwvif->offchan) 3595 continue; 3596 3597 if (rtwvif->stats.tx_tfc_lv != RTW89_TFC_IDLE || 3598 rtwvif->stats.rx_tfc_lv != RTW89_TFC_IDLE) 3599 continue; 3600 3601 vif = rtwvif_to_vif(rtwvif); 3602 3603 if (!(vif->type == NL80211_IFTYPE_STATION || 3604 vif->type == NL80211_IFTYPE_P2P_CLIENT)) 3605 continue; 3606 3607 rtw89_enter_lps(rtwdev, rtwvif, true); 3608 } 3609 } 3610 3611 static void rtw89_core_rfk_track(struct rtw89_dev *rtwdev) 3612 { 3613 enum rtw89_entity_mode mode; 3614 3615 mode = rtw89_get_entity_mode(rtwdev); 3616 if (mode == RTW89_ENTITY_MODE_MCC) 3617 return; 3618 3619 rtw89_chip_rfk_track(rtwdev); 3620 } 3621 3622 void rtw89_core_update_p2p_ps(struct rtw89_dev *rtwdev, 3623 struct rtw89_vif_link *rtwvif_link, 3624 struct ieee80211_bss_conf *bss_conf) 3625 { 3626 enum rtw89_entity_mode mode = rtw89_get_entity_mode(rtwdev); 3627 3628 if (mode == RTW89_ENTITY_MODE_MCC) 3629 rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_P2P_PS_CHANGE); 3630 else 3631 rtw89_process_p2p_ps(rtwdev, rtwvif_link, bss_conf); 3632 } 3633 3634 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev, 3635 struct rtw89_traffic_stats *stats) 3636 { 3637 stats->tx_unicast = 0; 3638 stats->rx_unicast = 0; 3639 stats->tx_cnt = 0; 3640 stats->rx_cnt = 0; 3641 ewma_tp_init(&stats->tx_ewma_tp); 3642 ewma_tp_init(&stats->rx_ewma_tp); 3643 } 3644 3645 #define RTW89_MLSR_GOTO_2GHZ_THRESHOLD -53 3646 #define RTW89_MLSR_EXIT_2GHZ_THRESHOLD -38 3647 static void rtw89_core_mlsr_link_decision(struct rtw89_dev *rtwdev, 3648 struct rtw89_vif *rtwvif) 3649 { 3650 unsigned int sel_link_id = IEEE80211_MLD_MAX_NUM_LINKS; 3651 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 3652 struct rtw89_vif_link *rtwvif_link; 3653 const struct rtw89_chan *chan; 3654 unsigned long usable_links; 3655 unsigned int link_id; 3656 u8 decided_bands; 3657 u8 rssi; 3658 3659 rssi = ewma_rssi_read(&rtwdev->phystat.bcn_rssi); 3660 if (unlikely(!rssi)) 3661 return; 3662 3663 if (RTW89_RSSI_RAW_TO_DBM(rssi) >= RTW89_MLSR_EXIT_2GHZ_THRESHOLD) 3664 decided_bands = BIT(RTW89_BAND_5G) | BIT(RTW89_BAND_6G); 3665 else if (RTW89_RSSI_RAW_TO_DBM(rssi) <= RTW89_MLSR_GOTO_2GHZ_THRESHOLD) 3666 decided_bands = BIT(RTW89_BAND_2G); 3667 else 3668 return; 3669 3670 usable_links = ieee80211_vif_usable_links(vif); 3671 3672 rtwvif_link = rtw89_get_designated_link(rtwvif); 3673 if (unlikely(!rtwvif_link)) 3674 goto select; 3675 3676 chan = rtw89_chan_get(rtwdev, rtwvif_link->chanctx_idx); 3677 if (decided_bands & BIT(chan->band_type)) 3678 return; 3679 3680 usable_links &= ~BIT(rtwvif_link->link_id); 3681 3682 select: 3683 rcu_read_lock(); 3684 3685 for_each_set_bit(link_id, &usable_links, IEEE80211_MLD_MAX_NUM_LINKS) { 3686 struct ieee80211_bss_conf *link_conf; 3687 struct ieee80211_channel *channel; 3688 enum rtw89_band band; 3689 3690 link_conf = rcu_dereference(vif->link_conf[link_id]); 3691 if (unlikely(!link_conf)) 3692 continue; 3693 3694 channel = link_conf->chanreq.oper.chan; 3695 if (unlikely(!channel)) 3696 continue; 3697 3698 band = rtw89_nl80211_to_hw_band(channel->band); 3699 if (decided_bands & BIT(band)) { 3700 sel_link_id = link_id; 3701 break; 3702 } 3703 } 3704 3705 rcu_read_unlock(); 3706 3707 if (sel_link_id == IEEE80211_MLD_MAX_NUM_LINKS) 3708 return; 3709 3710 rtw89_core_mlsr_switch(rtwdev, rtwvif, sel_link_id); 3711 } 3712 3713 static void rtw89_core_mlo_track(struct rtw89_dev *rtwdev) 3714 { 3715 struct rtw89_hal *hal = &rtwdev->hal; 3716 struct ieee80211_vif *vif; 3717 struct rtw89_vif *rtwvif; 3718 3719 if (hal->disabled_dm_bitmap & BIT(RTW89_DM_MLO)) 3720 return; 3721 3722 rtw89_for_each_rtwvif(rtwdev, rtwvif) { 3723 vif = rtwvif_to_vif(rtwvif); 3724 if (!vif->cfg.assoc || !ieee80211_vif_is_mld(vif)) 3725 continue; 3726 3727 switch (rtwvif->mlo_mode) { 3728 case RTW89_MLO_MODE_MLSR: 3729 rtw89_core_mlsr_link_decision(rtwdev, rtwvif); 3730 break; 3731 default: 3732 break; 3733 } 3734 } 3735 } 3736 3737 static void rtw89_track_work(struct wiphy *wiphy, struct wiphy_work *work) 3738 { 3739 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 3740 track_work.work); 3741 bool tfc_changed; 3742 3743 lockdep_assert_wiphy(wiphy); 3744 3745 if (test_bit(RTW89_FLAG_FORBIDDEN_TRACK_WROK, rtwdev->flags)) 3746 return; 3747 3748 if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags)) 3749 return; 3750 3751 wiphy_delayed_work_queue(wiphy, &rtwdev->track_work, 3752 RTW89_TRACK_WORK_PERIOD); 3753 3754 tfc_changed = rtw89_traffic_stats_track(rtwdev); 3755 if (rtwdev->scanning) 3756 return; 3757 3758 rtw89_leave_lps(rtwdev); 3759 3760 if (tfc_changed) { 3761 rtw89_hci_recalc_int_mit(rtwdev); 3762 rtw89_btc_ntfy_wl_sta(rtwdev); 3763 } 3764 rtw89_mac_bf_monitor_track(rtwdev); 3765 rtw89_phy_stat_track(rtwdev); 3766 rtw89_phy_env_monitor_track(rtwdev); 3767 rtw89_phy_dig(rtwdev); 3768 rtw89_core_rfk_track(rtwdev); 3769 rtw89_phy_ra_update(rtwdev); 3770 rtw89_phy_cfo_track(rtwdev); 3771 rtw89_phy_tx_path_div_track(rtwdev); 3772 rtw89_phy_antdiv_track(rtwdev); 3773 rtw89_phy_ul_tb_ctrl_track(rtwdev); 3774 rtw89_phy_edcca_track(rtwdev); 3775 rtw89_sar_track(rtwdev); 3776 rtw89_chanctx_track(rtwdev); 3777 rtw89_core_rfkill_poll(rtwdev, false); 3778 rtw89_core_mlo_track(rtwdev); 3779 3780 if (rtwdev->lps_enabled && !rtwdev->btc.lps) 3781 rtw89_enter_lps_track(rtwdev); 3782 } 3783 3784 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size) 3785 { 3786 unsigned long bit; 3787 3788 bit = find_first_zero_bit(addr, size); 3789 if (bit < size) 3790 set_bit(bit, addr); 3791 3792 return bit; 3793 } 3794 3795 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit) 3796 { 3797 clear_bit(bit, addr); 3798 } 3799 3800 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits) 3801 { 3802 bitmap_zero(addr, nbits); 3803 } 3804 3805 int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev, 3806 struct rtw89_sta_link *rtwsta_link, u8 tid, 3807 u8 *cam_idx) 3808 { 3809 const struct rtw89_chip_info *chip = rtwdev->chip; 3810 struct rtw89_cam_info *cam_info = &rtwdev->cam_info; 3811 struct rtw89_ba_cam_entry *entry = NULL, *tmp; 3812 u8 idx; 3813 int i; 3814 3815 lockdep_assert_wiphy(rtwdev->hw->wiphy); 3816 3817 idx = rtw89_core_acquire_bit_map(cam_info->ba_cam_map, chip->bacam_num); 3818 if (idx == chip->bacam_num) { 3819 /* allocate a static BA CAM to tid=0/5, so replace the existing 3820 * one if BA CAM is full. Hardware will process the original tid 3821 * automatically. 3822 */ 3823 if (tid != 0 && tid != 5) 3824 return -ENOSPC; 3825 3826 for_each_set_bit(i, cam_info->ba_cam_map, chip->bacam_num) { 3827 tmp = &cam_info->ba_cam_entry[i]; 3828 if (tmp->tid == 0 || tmp->tid == 5) 3829 continue; 3830 3831 idx = i; 3832 entry = tmp; 3833 list_del(&entry->list); 3834 break; 3835 } 3836 3837 if (!entry) 3838 return -ENOSPC; 3839 } else { 3840 entry = &cam_info->ba_cam_entry[idx]; 3841 } 3842 3843 entry->tid = tid; 3844 list_add_tail(&entry->list, &rtwsta_link->ba_cam_list); 3845 3846 *cam_idx = idx; 3847 3848 return 0; 3849 } 3850 3851 int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev, 3852 struct rtw89_sta_link *rtwsta_link, u8 tid, 3853 u8 *cam_idx) 3854 { 3855 struct rtw89_cam_info *cam_info = &rtwdev->cam_info; 3856 struct rtw89_ba_cam_entry *entry = NULL, *tmp; 3857 u8 idx; 3858 3859 lockdep_assert_wiphy(rtwdev->hw->wiphy); 3860 3861 list_for_each_entry_safe(entry, tmp, &rtwsta_link->ba_cam_list, list) { 3862 if (entry->tid != tid) 3863 continue; 3864 3865 idx = entry - cam_info->ba_cam_entry; 3866 list_del(&entry->list); 3867 3868 rtw89_core_release_bit_map(cam_info->ba_cam_map, idx); 3869 *cam_idx = idx; 3870 return 0; 3871 } 3872 3873 return -ENOENT; 3874 } 3875 3876 #define RTW89_TYPE_MAPPING(_type) \ 3877 case NL80211_IFTYPE_ ## _type: \ 3878 rtwvif_link->wifi_role = RTW89_WIFI_ROLE_ ## _type; \ 3879 break 3880 void rtw89_vif_type_mapping(struct rtw89_vif_link *rtwvif_link, bool assoc) 3881 { 3882 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 3883 const struct ieee80211_bss_conf *bss_conf; 3884 3885 switch (vif->type) { 3886 case NL80211_IFTYPE_STATION: 3887 if (vif->p2p) 3888 rtwvif_link->wifi_role = RTW89_WIFI_ROLE_P2P_CLIENT; 3889 else 3890 rtwvif_link->wifi_role = RTW89_WIFI_ROLE_STATION; 3891 break; 3892 case NL80211_IFTYPE_AP: 3893 if (vif->p2p) 3894 rtwvif_link->wifi_role = RTW89_WIFI_ROLE_P2P_GO; 3895 else 3896 rtwvif_link->wifi_role = RTW89_WIFI_ROLE_AP; 3897 break; 3898 RTW89_TYPE_MAPPING(ADHOC); 3899 RTW89_TYPE_MAPPING(MONITOR); 3900 RTW89_TYPE_MAPPING(MESH_POINT); 3901 default: 3902 WARN_ON(1); 3903 break; 3904 } 3905 3906 switch (vif->type) { 3907 case NL80211_IFTYPE_AP: 3908 case NL80211_IFTYPE_MESH_POINT: 3909 rtwvif_link->net_type = RTW89_NET_TYPE_AP_MODE; 3910 rtwvif_link->self_role = RTW89_SELF_ROLE_AP; 3911 break; 3912 case NL80211_IFTYPE_ADHOC: 3913 rtwvif_link->net_type = RTW89_NET_TYPE_AD_HOC; 3914 rtwvif_link->self_role = RTW89_SELF_ROLE_CLIENT; 3915 break; 3916 case NL80211_IFTYPE_STATION: 3917 if (assoc) { 3918 rtwvif_link->net_type = RTW89_NET_TYPE_INFRA; 3919 3920 rcu_read_lock(); 3921 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, false); 3922 rtwvif_link->trigger = bss_conf->he_support; 3923 rcu_read_unlock(); 3924 } else { 3925 rtwvif_link->net_type = RTW89_NET_TYPE_NO_LINK; 3926 rtwvif_link->trigger = false; 3927 } 3928 rtwvif_link->self_role = RTW89_SELF_ROLE_CLIENT; 3929 rtwvif_link->addr_cam.sec_ent_mode = RTW89_ADDR_CAM_SEC_NORMAL; 3930 break; 3931 case NL80211_IFTYPE_MONITOR: 3932 break; 3933 default: 3934 WARN_ON(1); 3935 break; 3936 } 3937 } 3938 3939 int rtw89_core_sta_link_add(struct rtw89_dev *rtwdev, 3940 struct rtw89_vif_link *rtwvif_link, 3941 struct rtw89_sta_link *rtwsta_link) 3942 { 3943 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 3944 const struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link); 3945 struct rtw89_hal *hal = &rtwdev->hal; 3946 u8 ant_num = hal->ant_diversity ? 2 : rtwdev->chip->rf_path_num; 3947 int i; 3948 int ret; 3949 3950 rtwsta_link->prev_rssi = 0; 3951 INIT_LIST_HEAD(&rtwsta_link->ba_cam_list); 3952 ewma_rssi_init(&rtwsta_link->avg_rssi); 3953 ewma_snr_init(&rtwsta_link->avg_snr); 3954 ewma_evm_init(&rtwsta_link->evm_1ss); 3955 for (i = 0; i < ant_num; i++) { 3956 ewma_rssi_init(&rtwsta_link->rssi[i]); 3957 ewma_evm_init(&rtwsta_link->evm_min[i]); 3958 ewma_evm_init(&rtwsta_link->evm_max[i]); 3959 } 3960 3961 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) { 3962 /* must do rtw89_reg_6ghz_recalc() before rfk channel */ 3963 ret = rtw89_reg_6ghz_recalc(rtwdev, rtwvif_link, true); 3964 if (ret) 3965 return ret; 3966 3967 rtw89_btc_ntfy_role_info(rtwdev, rtwvif_link, rtwsta_link, 3968 BTC_ROLE_MSTS_STA_CONN_START); 3969 rtw89_chip_rfk_channel(rtwdev, rtwvif_link); 3970 } else if (vif->type == NL80211_IFTYPE_AP || sta->tdls) { 3971 ret = rtw89_mac_set_macid_pause(rtwdev, rtwsta_link->mac_id, false); 3972 if (ret) { 3973 rtw89_warn(rtwdev, "failed to send h2c macid pause\n"); 3974 return ret; 3975 } 3976 3977 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif_link, rtwsta_link, 3978 RTW89_ROLE_CREATE); 3979 if (ret) { 3980 rtw89_warn(rtwdev, "failed to send h2c role info\n"); 3981 return ret; 3982 } 3983 3984 ret = rtw89_chip_h2c_default_cmac_tbl(rtwdev, rtwvif_link, rtwsta_link); 3985 if (ret) 3986 return ret; 3987 3988 ret = rtw89_chip_h2c_default_dmac_tbl(rtwdev, rtwvif_link, rtwsta_link); 3989 if (ret) 3990 return ret; 3991 } 3992 3993 return 0; 3994 } 3995 3996 int rtw89_core_sta_link_disassoc(struct rtw89_dev *rtwdev, 3997 struct rtw89_vif_link *rtwvif_link, 3998 struct rtw89_sta_link *rtwsta_link) 3999 { 4000 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 4001 4002 rtw89_assoc_link_clr(rtwsta_link); 4003 4004 if (vif->type == NL80211_IFTYPE_STATION) 4005 rtw89_fw_h2c_set_bcn_fltr_cfg(rtwdev, rtwvif_link, false); 4006 4007 if (rtwvif_link->wifi_role == RTW89_WIFI_ROLE_P2P_CLIENT) 4008 rtw89_p2p_noa_once_deinit(rtwvif_link); 4009 4010 return 0; 4011 } 4012 4013 int rtw89_core_sta_link_disconnect(struct rtw89_dev *rtwdev, 4014 struct rtw89_vif_link *rtwvif_link, 4015 struct rtw89_sta_link *rtwsta_link) 4016 { 4017 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 4018 const struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link); 4019 int ret; 4020 4021 rtw89_mac_bf_monitor_calc(rtwdev, rtwsta_link, true); 4022 rtw89_mac_bf_disassoc(rtwdev, rtwvif_link, rtwsta_link); 4023 4024 if (vif->type == NL80211_IFTYPE_AP || sta->tdls) 4025 rtw89_cam_deinit_addr_cam(rtwdev, &rtwsta_link->addr_cam); 4026 if (sta->tdls) 4027 rtw89_cam_deinit_bssid_cam(rtwdev, &rtwsta_link->bssid_cam); 4028 4029 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) { 4030 rtw89_vif_type_mapping(rtwvif_link, false); 4031 rtw89_fw_release_general_pkt_list_vif(rtwdev, rtwvif_link, true); 4032 } 4033 4034 ret = rtw89_chip_h2c_assoc_cmac_tbl(rtwdev, rtwvif_link, rtwsta_link); 4035 if (ret) { 4036 rtw89_warn(rtwdev, "failed to send h2c cmac table\n"); 4037 return ret; 4038 } 4039 4040 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif_link, rtwsta_link, true); 4041 if (ret) { 4042 rtw89_warn(rtwdev, "failed to send h2c join info\n"); 4043 return ret; 4044 } 4045 4046 /* update cam aid mac_id net_type */ 4047 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif_link, rtwsta_link, NULL); 4048 if (ret) { 4049 rtw89_warn(rtwdev, "failed to send h2c cam\n"); 4050 return ret; 4051 } 4052 4053 return ret; 4054 } 4055 4056 static bool rtw89_sta_link_can_er(struct rtw89_dev *rtwdev, 4057 struct ieee80211_bss_conf *bss_conf, 4058 struct ieee80211_link_sta *link_sta) 4059 { 4060 if (!bss_conf->he_support || 4061 bss_conf->he_oper.params & IEEE80211_HE_OPERATION_ER_SU_DISABLE) 4062 return false; 4063 4064 if (rtwdev->chip->chip_id == RTL8852C && 4065 rtw89_sta_link_has_su_mu_4xhe08(link_sta) && 4066 !rtw89_sta_link_has_er_su_4xhe08(link_sta)) 4067 return false; 4068 4069 return true; 4070 } 4071 4072 int rtw89_core_sta_link_assoc(struct rtw89_dev *rtwdev, 4073 struct rtw89_vif_link *rtwvif_link, 4074 struct rtw89_sta_link *rtwsta_link) 4075 { 4076 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 4077 const struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link); 4078 struct rtw89_bssid_cam_entry *bssid_cam = rtw89_get_bssid_cam_of(rtwvif_link, 4079 rtwsta_link); 4080 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, 4081 rtwvif_link->chanctx_idx); 4082 struct ieee80211_link_sta *link_sta; 4083 int ret; 4084 4085 if (vif->type == NL80211_IFTYPE_AP || sta->tdls) { 4086 if (sta->tdls) { 4087 rcu_read_lock(); 4088 4089 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true); 4090 ret = rtw89_cam_init_bssid_cam(rtwdev, rtwvif_link, bssid_cam, 4091 link_sta->addr); 4092 if (ret) { 4093 rtw89_warn(rtwdev, "failed to send h2c init bssid cam for TDLS\n"); 4094 rcu_read_unlock(); 4095 return ret; 4096 } 4097 4098 rcu_read_unlock(); 4099 } 4100 4101 ret = rtw89_cam_init_addr_cam(rtwdev, &rtwsta_link->addr_cam, bssid_cam); 4102 if (ret) { 4103 rtw89_warn(rtwdev, "failed to send h2c init addr cam\n"); 4104 return ret; 4105 } 4106 } 4107 4108 ret = rtw89_chip_h2c_assoc_cmac_tbl(rtwdev, rtwvif_link, rtwsta_link); 4109 if (ret) { 4110 rtw89_warn(rtwdev, "failed to send h2c cmac table\n"); 4111 return ret; 4112 } 4113 4114 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif_link, rtwsta_link, false); 4115 if (ret) { 4116 rtw89_warn(rtwdev, "failed to send h2c join info\n"); 4117 return ret; 4118 } 4119 4120 /* update cam aid mac_id net_type */ 4121 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif_link, rtwsta_link, NULL); 4122 if (ret) { 4123 rtw89_warn(rtwdev, "failed to send h2c cam\n"); 4124 return ret; 4125 } 4126 4127 rtw89_phy_ra_assoc(rtwdev, rtwsta_link); 4128 rtw89_mac_bf_assoc(rtwdev, rtwvif_link, rtwsta_link); 4129 rtw89_mac_bf_monitor_calc(rtwdev, rtwsta_link, false); 4130 4131 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) { 4132 struct ieee80211_bss_conf *bss_conf; 4133 4134 rcu_read_lock(); 4135 4136 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true); 4137 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true); 4138 rtwsta_link->er_cap = rtw89_sta_link_can_er(rtwdev, bss_conf, link_sta); 4139 4140 rcu_read_unlock(); 4141 4142 rtw89_btc_ntfy_role_info(rtwdev, rtwvif_link, rtwsta_link, 4143 BTC_ROLE_MSTS_STA_CONN_END); 4144 rtw89_core_get_no_ul_ofdma_htc(rtwdev, &rtwsta_link->htc_template, chan); 4145 rtw89_phy_ul_tb_assoc(rtwdev, rtwvif_link); 4146 4147 ret = rtw89_fw_h2c_general_pkt(rtwdev, rtwvif_link, rtwsta_link->mac_id); 4148 if (ret) { 4149 rtw89_warn(rtwdev, "failed to send h2c general packet\n"); 4150 return ret; 4151 } 4152 4153 rtw89_fw_h2c_set_bcn_fltr_cfg(rtwdev, rtwvif_link, true); 4154 } 4155 4156 rtw89_assoc_link_set(rtwsta_link); 4157 return ret; 4158 } 4159 4160 int rtw89_core_sta_link_remove(struct rtw89_dev *rtwdev, 4161 struct rtw89_vif_link *rtwvif_link, 4162 struct rtw89_sta_link *rtwsta_link) 4163 { 4164 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 4165 const struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link); 4166 int ret; 4167 4168 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) { 4169 rtw89_reg_6ghz_recalc(rtwdev, rtwvif_link, false); 4170 rtw89_btc_ntfy_role_info(rtwdev, rtwvif_link, rtwsta_link, 4171 BTC_ROLE_MSTS_STA_DIS_CONN); 4172 } else if (vif->type == NL80211_IFTYPE_AP || sta->tdls) { 4173 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif_link, rtwsta_link, 4174 RTW89_ROLE_REMOVE); 4175 if (ret) { 4176 rtw89_warn(rtwdev, "failed to send h2c role info\n"); 4177 return ret; 4178 } 4179 } 4180 4181 return 0; 4182 } 4183 4184 static void _rtw89_core_set_tid_config(struct rtw89_dev *rtwdev, 4185 struct ieee80211_sta *sta, 4186 struct cfg80211_tid_cfg *tid_conf) 4187 { 4188 struct ieee80211_txq *txq; 4189 struct rtw89_txq *rtwtxq; 4190 u32 mask = tid_conf->mask; 4191 u8 tids = tid_conf->tids; 4192 int tids_nbit = BITS_PER_BYTE; 4193 int i; 4194 4195 for (i = 0; i < tids_nbit; i++, tids >>= 1) { 4196 if (!tids) 4197 break; 4198 4199 if (!(tids & BIT(0))) 4200 continue; 4201 4202 txq = sta->txq[i]; 4203 rtwtxq = (struct rtw89_txq *)txq->drv_priv; 4204 4205 if (mask & BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL)) { 4206 if (tid_conf->ampdu == NL80211_TID_CONFIG_ENABLE) { 4207 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags); 4208 } else { 4209 if (test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags)) 4210 ieee80211_stop_tx_ba_session(sta, txq->tid); 4211 spin_lock_bh(&rtwdev->ba_lock); 4212 list_del_init(&rtwtxq->list); 4213 set_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags); 4214 spin_unlock_bh(&rtwdev->ba_lock); 4215 } 4216 } 4217 4218 if (mask & BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL) && tids == 0xff) { 4219 if (tid_conf->amsdu == NL80211_TID_CONFIG_ENABLE) 4220 sta->max_amsdu_subframes = 0; 4221 else 4222 sta->max_amsdu_subframes = 1; 4223 } 4224 } 4225 } 4226 4227 void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev, 4228 struct ieee80211_sta *sta, 4229 struct cfg80211_tid_config *tid_config) 4230 { 4231 int i; 4232 4233 for (i = 0; i < tid_config->n_tid_conf; i++) 4234 _rtw89_core_set_tid_config(rtwdev, sta, 4235 &tid_config->tid_conf[i]); 4236 } 4237 4238 static void rtw89_init_ht_cap(struct rtw89_dev *rtwdev, 4239 struct ieee80211_sta_ht_cap *ht_cap) 4240 { 4241 static const __le16 highest[RF_PATH_MAX] = { 4242 cpu_to_le16(150), cpu_to_le16(300), cpu_to_le16(450), cpu_to_le16(600), 4243 }; 4244 struct rtw89_hal *hal = &rtwdev->hal; 4245 u8 nss = hal->rx_nss; 4246 int i; 4247 4248 ht_cap->ht_supported = true; 4249 ht_cap->cap = 0; 4250 ht_cap->cap |= IEEE80211_HT_CAP_SGI_20 | 4251 IEEE80211_HT_CAP_MAX_AMSDU | 4252 IEEE80211_HT_CAP_TX_STBC | 4253 (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT); 4254 ht_cap->cap |= IEEE80211_HT_CAP_LDPC_CODING; 4255 ht_cap->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40 | 4256 IEEE80211_HT_CAP_DSSSCCK40 | 4257 IEEE80211_HT_CAP_SGI_40; 4258 ht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; 4259 ht_cap->ampdu_density = IEEE80211_HT_MPDU_DENSITY_NONE; 4260 ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; 4261 for (i = 0; i < nss; i++) 4262 ht_cap->mcs.rx_mask[i] = 0xFF; 4263 ht_cap->mcs.rx_mask[4] = 0x01; 4264 ht_cap->mcs.rx_highest = highest[nss - 1]; 4265 } 4266 4267 static void rtw89_init_vht_cap(struct rtw89_dev *rtwdev, 4268 struct ieee80211_sta_vht_cap *vht_cap) 4269 { 4270 static const __le16 highest_bw80[RF_PATH_MAX] = { 4271 cpu_to_le16(433), cpu_to_le16(867), cpu_to_le16(1300), cpu_to_le16(1733), 4272 }; 4273 static const __le16 highest_bw160[RF_PATH_MAX] = { 4274 cpu_to_le16(867), cpu_to_le16(1733), cpu_to_le16(2600), cpu_to_le16(3467), 4275 }; 4276 const struct rtw89_chip_info *chip = rtwdev->chip; 4277 const __le16 *highest = chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160) ? 4278 highest_bw160 : highest_bw80; 4279 struct rtw89_hal *hal = &rtwdev->hal; 4280 u16 tx_mcs_map = 0, rx_mcs_map = 0; 4281 u8 sts_cap = 3; 4282 int i; 4283 4284 for (i = 0; i < 8; i++) { 4285 if (i < hal->tx_nss) 4286 tx_mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << (i * 2); 4287 else 4288 tx_mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << (i * 2); 4289 if (i < hal->rx_nss) 4290 rx_mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << (i * 2); 4291 else 4292 rx_mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << (i * 2); 4293 } 4294 4295 vht_cap->vht_supported = true; 4296 vht_cap->cap = IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 | 4297 IEEE80211_VHT_CAP_SHORT_GI_80 | 4298 IEEE80211_VHT_CAP_RXSTBC_1 | 4299 IEEE80211_VHT_CAP_HTC_VHT | 4300 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK | 4301 0; 4302 vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC; 4303 vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC; 4304 vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE | 4305 IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE; 4306 vht_cap->cap |= sts_cap << IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT; 4307 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) 4308 vht_cap->cap |= IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ | 4309 IEEE80211_VHT_CAP_SHORT_GI_160; 4310 vht_cap->vht_mcs.rx_mcs_map = cpu_to_le16(rx_mcs_map); 4311 vht_cap->vht_mcs.tx_mcs_map = cpu_to_le16(tx_mcs_map); 4312 vht_cap->vht_mcs.rx_highest = highest[hal->rx_nss - 1]; 4313 vht_cap->vht_mcs.tx_highest = highest[hal->tx_nss - 1]; 4314 4315 if (ieee80211_hw_check(rtwdev->hw, SUPPORTS_VHT_EXT_NSS_BW)) 4316 vht_cap->vht_mcs.tx_highest |= 4317 cpu_to_le16(IEEE80211_VHT_EXT_NSS_BW_CAPABLE); 4318 } 4319 4320 static void rtw89_init_he_cap(struct rtw89_dev *rtwdev, 4321 enum nl80211_band band, 4322 enum nl80211_iftype iftype, 4323 struct ieee80211_sband_iftype_data *iftype_data) 4324 { 4325 const struct rtw89_chip_info *chip = rtwdev->chip; 4326 struct rtw89_hal *hal = &rtwdev->hal; 4327 bool no_ng16 = (chip->chip_id == RTL8852A && hal->cv == CHIP_CBV) || 4328 (chip->chip_id == RTL8852B && hal->cv == CHIP_CAV); 4329 struct ieee80211_sta_he_cap *he_cap; 4330 int nss = hal->rx_nss; 4331 u8 *mac_cap_info; 4332 u8 *phy_cap_info; 4333 u16 mcs_map = 0; 4334 int i; 4335 4336 for (i = 0; i < 8; i++) { 4337 if (i < nss) 4338 mcs_map |= IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2); 4339 else 4340 mcs_map |= IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2); 4341 } 4342 4343 he_cap = &iftype_data->he_cap; 4344 mac_cap_info = he_cap->he_cap_elem.mac_cap_info; 4345 phy_cap_info = he_cap->he_cap_elem.phy_cap_info; 4346 4347 he_cap->has_he = true; 4348 mac_cap_info[0] = IEEE80211_HE_MAC_CAP0_HTC_HE; 4349 if (iftype == NL80211_IFTYPE_STATION) 4350 mac_cap_info[1] = IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US; 4351 mac_cap_info[2] = IEEE80211_HE_MAC_CAP2_ALL_ACK | 4352 IEEE80211_HE_MAC_CAP2_BSR; 4353 mac_cap_info[3] = IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_2; 4354 if (iftype == NL80211_IFTYPE_AP) 4355 mac_cap_info[3] |= IEEE80211_HE_MAC_CAP3_OMI_CONTROL; 4356 mac_cap_info[4] = IEEE80211_HE_MAC_CAP4_OPS | 4357 IEEE80211_HE_MAC_CAP4_AMSDU_IN_AMPDU; 4358 if (iftype == NL80211_IFTYPE_STATION) 4359 mac_cap_info[5] = IEEE80211_HE_MAC_CAP5_HT_VHT_TRIG_FRAME_RX; 4360 if (band == NL80211_BAND_2GHZ) { 4361 phy_cap_info[0] = 4362 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G; 4363 } else { 4364 phy_cap_info[0] = 4365 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G; 4366 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) 4367 phy_cap_info[0] |= IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G; 4368 } 4369 phy_cap_info[1] = IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A | 4370 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD | 4371 IEEE80211_HE_PHY_CAP1_HE_LTF_AND_GI_FOR_HE_PPDUS_0_8US; 4372 phy_cap_info[2] = IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US | 4373 IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ | 4374 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ | 4375 IEEE80211_HE_PHY_CAP2_DOPPLER_TX; 4376 phy_cap_info[3] = IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_16_QAM; 4377 if (iftype == NL80211_IFTYPE_STATION) 4378 phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_16_QAM | 4379 IEEE80211_HE_PHY_CAP3_DCM_MAX_TX_NSS_2; 4380 if (iftype == NL80211_IFTYPE_AP) 4381 phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_RX_PARTIAL_BW_SU_IN_20MHZ_MU; 4382 phy_cap_info[4] = IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE | 4383 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_4; 4384 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) 4385 phy_cap_info[4] |= IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_4; 4386 phy_cap_info[5] = no_ng16 ? 0 : 4387 IEEE80211_HE_PHY_CAP5_NG16_SU_FEEDBACK | 4388 IEEE80211_HE_PHY_CAP5_NG16_MU_FEEDBACK; 4389 phy_cap_info[6] = IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_42_SU | 4390 IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_75_MU | 4391 IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB | 4392 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE; 4393 phy_cap_info[7] = IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_SUPP | 4394 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI | 4395 IEEE80211_HE_PHY_CAP7_MAX_NC_1; 4396 phy_cap_info[8] = IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI | 4397 IEEE80211_HE_PHY_CAP8_HE_ER_SU_1XLTF_AND_08_US_GI | 4398 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_996; 4399 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) 4400 phy_cap_info[8] |= IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU | 4401 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU; 4402 phy_cap_info[9] = IEEE80211_HE_PHY_CAP9_LONGER_THAN_16_SIGB_OFDM_SYM | 4403 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU | 4404 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB | 4405 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB | 4406 u8_encode_bits(IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_16US, 4407 IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_MASK); 4408 if (iftype == NL80211_IFTYPE_STATION) 4409 phy_cap_info[9] |= IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU; 4410 he_cap->he_mcs_nss_supp.rx_mcs_80 = cpu_to_le16(mcs_map); 4411 he_cap->he_mcs_nss_supp.tx_mcs_80 = cpu_to_le16(mcs_map); 4412 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) { 4413 he_cap->he_mcs_nss_supp.rx_mcs_160 = cpu_to_le16(mcs_map); 4414 he_cap->he_mcs_nss_supp.tx_mcs_160 = cpu_to_le16(mcs_map); 4415 } 4416 4417 if (band == NL80211_BAND_6GHZ) { 4418 __le16 capa; 4419 4420 capa = le16_encode_bits(IEEE80211_HT_MPDU_DENSITY_NONE, 4421 IEEE80211_HE_6GHZ_CAP_MIN_MPDU_START) | 4422 le16_encode_bits(IEEE80211_VHT_MAX_AMPDU_1024K, 4423 IEEE80211_HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP) | 4424 le16_encode_bits(IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454, 4425 IEEE80211_HE_6GHZ_CAP_MAX_MPDU_LEN); 4426 iftype_data->he_6ghz_capa.capa = capa; 4427 } 4428 } 4429 4430 static void rtw89_init_eht_cap(struct rtw89_dev *rtwdev, 4431 enum nl80211_band band, 4432 enum nl80211_iftype iftype, 4433 struct ieee80211_sband_iftype_data *iftype_data) 4434 { 4435 const struct rtw89_chip_info *chip = rtwdev->chip; 4436 struct ieee80211_eht_cap_elem_fixed *eht_cap_elem; 4437 struct ieee80211_eht_mcs_nss_supp *eht_nss; 4438 struct ieee80211_sta_eht_cap *eht_cap; 4439 struct rtw89_hal *hal = &rtwdev->hal; 4440 bool support_mcs_12_13 = true; 4441 bool support_320mhz = false; 4442 u8 val, val_mcs13; 4443 int sts = 8; 4444 4445 if (chip->chip_gen == RTW89_CHIP_AX) 4446 return; 4447 4448 if (hal->no_mcs_12_13) 4449 support_mcs_12_13 = false; 4450 4451 if (band == NL80211_BAND_6GHZ && 4452 chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_320)) 4453 support_320mhz = true; 4454 4455 eht_cap = &iftype_data->eht_cap; 4456 eht_cap_elem = &eht_cap->eht_cap_elem; 4457 eht_nss = &eht_cap->eht_mcs_nss_supp; 4458 4459 eht_cap->has_eht = true; 4460 4461 eht_cap_elem->mac_cap_info[0] = 4462 u8_encode_bits(IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_7991, 4463 IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_MASK); 4464 eht_cap_elem->mac_cap_info[1] = 0; 4465 4466 eht_cap_elem->phy_cap_info[0] = 4467 IEEE80211_EHT_PHY_CAP0_NDP_4_EHT_LFT_32_GI | 4468 IEEE80211_EHT_PHY_CAP0_SU_BEAMFORMEE; 4469 if (support_320mhz) 4470 eht_cap_elem->phy_cap_info[0] |= 4471 IEEE80211_EHT_PHY_CAP0_320MHZ_IN_6GHZ; 4472 4473 eht_cap_elem->phy_cap_info[0] |= 4474 u8_encode_bits(u8_get_bits(sts - 1, BIT(0)), 4475 IEEE80211_EHT_PHY_CAP0_BEAMFORMEE_SS_80MHZ_MASK); 4476 eht_cap_elem->phy_cap_info[1] = 4477 u8_encode_bits(u8_get_bits(sts - 1, GENMASK(2, 1)), 4478 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_80MHZ_MASK) | 4479 u8_encode_bits(sts - 1, 4480 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_160MHZ_MASK); 4481 if (support_320mhz) 4482 eht_cap_elem->phy_cap_info[1] |= 4483 u8_encode_bits(sts - 1, 4484 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_320MHZ_MASK); 4485 4486 eht_cap_elem->phy_cap_info[2] = 0; 4487 4488 eht_cap_elem->phy_cap_info[3] = 4489 IEEE80211_EHT_PHY_CAP3_CODEBOOK_4_2_SU_FDBK | 4490 IEEE80211_EHT_PHY_CAP3_CODEBOOK_7_5_MU_FDBK | 4491 IEEE80211_EHT_PHY_CAP3_TRIG_SU_BF_FDBK | 4492 IEEE80211_EHT_PHY_CAP3_TRIG_MU_BF_PART_BW_FDBK; 4493 4494 eht_cap_elem->phy_cap_info[4] = 4495 IEEE80211_EHT_PHY_CAP4_POWER_BOOST_FACT_SUPP | 4496 u8_encode_bits(1, IEEE80211_EHT_PHY_CAP4_MAX_NC_MASK); 4497 4498 eht_cap_elem->phy_cap_info[5] = 4499 u8_encode_bits(IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_20US, 4500 IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_MASK); 4501 4502 eht_cap_elem->phy_cap_info[6] = 0; 4503 eht_cap_elem->phy_cap_info[7] = 0; 4504 eht_cap_elem->phy_cap_info[8] = 0; 4505 4506 val = u8_encode_bits(hal->rx_nss, IEEE80211_EHT_MCS_NSS_RX) | 4507 u8_encode_bits(hal->tx_nss, IEEE80211_EHT_MCS_NSS_TX); 4508 val_mcs13 = support_mcs_12_13 ? val : 0; 4509 4510 eht_nss->bw._80.rx_tx_mcs9_max_nss = val; 4511 eht_nss->bw._80.rx_tx_mcs11_max_nss = val; 4512 eht_nss->bw._80.rx_tx_mcs13_max_nss = val_mcs13; 4513 eht_nss->bw._160.rx_tx_mcs9_max_nss = val; 4514 eht_nss->bw._160.rx_tx_mcs11_max_nss = val; 4515 eht_nss->bw._160.rx_tx_mcs13_max_nss = val_mcs13; 4516 if (support_320mhz) { 4517 eht_nss->bw._320.rx_tx_mcs9_max_nss = val; 4518 eht_nss->bw._320.rx_tx_mcs11_max_nss = val; 4519 eht_nss->bw._320.rx_tx_mcs13_max_nss = val_mcs13; 4520 } 4521 } 4522 4523 #define RTW89_SBAND_IFTYPES_NR 2 4524 4525 static int rtw89_init_he_eht_cap(struct rtw89_dev *rtwdev, 4526 enum nl80211_band band, 4527 struct ieee80211_supported_band *sband) 4528 { 4529 struct ieee80211_sband_iftype_data *iftype_data; 4530 enum nl80211_iftype iftype; 4531 int idx = 0; 4532 4533 iftype_data = devm_kcalloc(rtwdev->dev, RTW89_SBAND_IFTYPES_NR, 4534 sizeof(*iftype_data), GFP_KERNEL); 4535 if (!iftype_data) 4536 return -ENOMEM; 4537 4538 for (iftype = 0; iftype < NUM_NL80211_IFTYPES; iftype++) { 4539 switch (iftype) { 4540 case NL80211_IFTYPE_STATION: 4541 case NL80211_IFTYPE_AP: 4542 break; 4543 default: 4544 continue; 4545 } 4546 4547 if (idx >= RTW89_SBAND_IFTYPES_NR) { 4548 rtw89_warn(rtwdev, "run out of iftype_data\n"); 4549 break; 4550 } 4551 4552 iftype_data[idx].types_mask = BIT(iftype); 4553 4554 rtw89_init_he_cap(rtwdev, band, iftype, &iftype_data[idx]); 4555 rtw89_init_eht_cap(rtwdev, band, iftype, &iftype_data[idx]); 4556 4557 idx++; 4558 } 4559 4560 _ieee80211_set_sband_iftype_data(sband, iftype_data, idx); 4561 return 0; 4562 } 4563 4564 static struct ieee80211_supported_band * 4565 rtw89_core_sband_dup(struct rtw89_dev *rtwdev, 4566 const struct ieee80211_supported_band *sband) 4567 { 4568 struct ieee80211_supported_band *dup; 4569 4570 dup = devm_kmemdup(rtwdev->dev, sband, sizeof(*sband), GFP_KERNEL); 4571 if (!dup) 4572 return NULL; 4573 4574 dup->channels = devm_kmemdup(rtwdev->dev, sband->channels, 4575 sizeof(*sband->channels) * sband->n_channels, 4576 GFP_KERNEL); 4577 if (!dup->channels) 4578 return NULL; 4579 4580 dup->bitrates = devm_kmemdup(rtwdev->dev, sband->bitrates, 4581 sizeof(*sband->bitrates) * sband->n_bitrates, 4582 GFP_KERNEL); 4583 if (!dup->bitrates) 4584 return NULL; 4585 4586 return dup; 4587 } 4588 4589 static int rtw89_core_set_supported_band(struct rtw89_dev *rtwdev) 4590 { 4591 struct ieee80211_hw *hw = rtwdev->hw; 4592 struct ieee80211_supported_band *sband; 4593 u8 support_bands = rtwdev->chip->support_bands; 4594 int ret; 4595 4596 if (support_bands & BIT(NL80211_BAND_2GHZ)) { 4597 sband = rtw89_core_sband_dup(rtwdev, &rtw89_sband_2ghz); 4598 if (!sband) 4599 return -ENOMEM; 4600 rtw89_init_ht_cap(rtwdev, &sband->ht_cap); 4601 ret = rtw89_init_he_eht_cap(rtwdev, NL80211_BAND_2GHZ, sband); 4602 if (ret) 4603 return ret; 4604 hw->wiphy->bands[NL80211_BAND_2GHZ] = sband; 4605 } 4606 4607 if (support_bands & BIT(NL80211_BAND_5GHZ)) { 4608 sband = rtw89_core_sband_dup(rtwdev, &rtw89_sband_5ghz); 4609 if (!sband) 4610 return -ENOMEM; 4611 rtw89_init_ht_cap(rtwdev, &sband->ht_cap); 4612 rtw89_init_vht_cap(rtwdev, &sband->vht_cap); 4613 ret = rtw89_init_he_eht_cap(rtwdev, NL80211_BAND_5GHZ, sband); 4614 if (ret) 4615 return ret; 4616 hw->wiphy->bands[NL80211_BAND_5GHZ] = sband; 4617 } 4618 4619 if (support_bands & BIT(NL80211_BAND_6GHZ)) { 4620 sband = rtw89_core_sband_dup(rtwdev, &rtw89_sband_6ghz); 4621 if (!sband) 4622 return -ENOMEM; 4623 ret = rtw89_init_he_eht_cap(rtwdev, NL80211_BAND_6GHZ, sband); 4624 if (ret) 4625 return ret; 4626 hw->wiphy->bands[NL80211_BAND_6GHZ] = sband; 4627 } 4628 4629 return 0; 4630 } 4631 4632 static void rtw89_core_ppdu_sts_init(struct rtw89_dev *rtwdev) 4633 { 4634 int i; 4635 4636 for (i = 0; i < RTW89_PHY_NUM; i++) 4637 skb_queue_head_init(&rtwdev->ppdu_sts.rx_queue[i]); 4638 for (i = 0; i < RTW89_PHY_NUM; i++) 4639 rtwdev->ppdu_sts.curr_rx_ppdu_cnt[i] = U8_MAX; 4640 } 4641 4642 void rtw89_core_update_beacon_work(struct wiphy *wiphy, struct wiphy_work *work) 4643 { 4644 struct rtw89_dev *rtwdev; 4645 struct rtw89_vif_link *rtwvif_link = container_of(work, struct rtw89_vif_link, 4646 update_beacon_work); 4647 4648 lockdep_assert_wiphy(wiphy); 4649 4650 if (rtwvif_link->net_type != RTW89_NET_TYPE_AP_MODE) 4651 return; 4652 4653 rtwdev = rtwvif_link->rtwvif->rtwdev; 4654 4655 rtw89_chip_h2c_update_beacon(rtwdev, rtwvif_link); 4656 } 4657 4658 int rtw89_wait_for_cond(struct rtw89_wait_info *wait, unsigned int cond) 4659 { 4660 struct completion *cmpl = &wait->completion; 4661 unsigned long time_left; 4662 unsigned int cur; 4663 4664 cur = atomic_cmpxchg(&wait->cond, RTW89_WAIT_COND_IDLE, cond); 4665 if (cur != RTW89_WAIT_COND_IDLE) 4666 return -EBUSY; 4667 4668 time_left = wait_for_completion_timeout(cmpl, RTW89_WAIT_FOR_COND_TIMEOUT); 4669 if (time_left == 0) { 4670 atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE); 4671 return -ETIMEDOUT; 4672 } 4673 4674 if (wait->data.err) 4675 return -EFAULT; 4676 4677 return 0; 4678 } 4679 4680 void rtw89_complete_cond(struct rtw89_wait_info *wait, unsigned int cond, 4681 const struct rtw89_completion_data *data) 4682 { 4683 unsigned int cur; 4684 4685 cur = atomic_cmpxchg(&wait->cond, cond, RTW89_WAIT_COND_IDLE); 4686 if (cur != cond) 4687 return; 4688 4689 wait->data = *data; 4690 complete(&wait->completion); 4691 } 4692 4693 void rtw89_core_ntfy_btc_event(struct rtw89_dev *rtwdev, enum rtw89_btc_hmsg event) 4694 { 4695 u16 bt_req_len; 4696 4697 switch (event) { 4698 case RTW89_BTC_HMSG_SET_BT_REQ_SLOT: 4699 bt_req_len = rtw89_coex_query_bt_req_len(rtwdev, RTW89_PHY_0); 4700 rtw89_debug(rtwdev, RTW89_DBG_BTC, 4701 "coex updates BT req len to %d TU\n", bt_req_len); 4702 rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_BT_SLOT_CHANGE); 4703 break; 4704 default: 4705 if (event < NUM_OF_RTW89_BTC_HMSG) 4706 rtw89_debug(rtwdev, RTW89_DBG_BTC, 4707 "unhandled BTC HMSG event: %d\n", event); 4708 else 4709 rtw89_warn(rtwdev, 4710 "unrecognized BTC HMSG event: %d\n", event); 4711 break; 4712 } 4713 } 4714 4715 void rtw89_check_quirks(struct rtw89_dev *rtwdev, const struct dmi_system_id *quirks) 4716 { 4717 const struct dmi_system_id *match; 4718 enum rtw89_quirks quirk; 4719 4720 if (!quirks) 4721 return; 4722 4723 for (match = dmi_first_match(quirks); match; match = dmi_first_match(match + 1)) { 4724 quirk = (uintptr_t)match->driver_data; 4725 if (quirk >= NUM_OF_RTW89_QUIRKS) 4726 continue; 4727 4728 set_bit(quirk, rtwdev->quirks); 4729 } 4730 } 4731 EXPORT_SYMBOL(rtw89_check_quirks); 4732 4733 int rtw89_core_start(struct rtw89_dev *rtwdev) 4734 { 4735 int ret; 4736 4737 ret = rtw89_mac_init(rtwdev); 4738 if (ret) { 4739 rtw89_err(rtwdev, "mac init fail, ret:%d\n", ret); 4740 return ret; 4741 } 4742 4743 rtw89_btc_ntfy_poweron(rtwdev); 4744 4745 /* efuse process */ 4746 4747 /* pre-config BB/RF, BB reset/RFC reset */ 4748 ret = rtw89_chip_reset_bb_rf(rtwdev); 4749 if (ret) 4750 return ret; 4751 4752 rtw89_phy_init_bb_reg(rtwdev); 4753 rtw89_chip_bb_postinit(rtwdev); 4754 rtw89_phy_init_rf_reg(rtwdev, false); 4755 4756 rtw89_btc_ntfy_init(rtwdev, BTC_MODE_NORMAL); 4757 4758 rtw89_phy_dm_init(rtwdev); 4759 4760 rtw89_mac_cfg_ppdu_status_bands(rtwdev, true); 4761 rtw89_mac_cfg_phy_rpt_bands(rtwdev, true); 4762 rtw89_mac_update_rts_threshold(rtwdev); 4763 4764 ret = rtw89_hci_start(rtwdev); 4765 if (ret) { 4766 rtw89_err(rtwdev, "failed to start hci\n"); 4767 return ret; 4768 } 4769 4770 wiphy_delayed_work_queue(rtwdev->hw->wiphy, &rtwdev->track_work, 4771 RTW89_TRACK_WORK_PERIOD); 4772 4773 set_bit(RTW89_FLAG_RUNNING, rtwdev->flags); 4774 4775 rtw89_chip_rfk_init_late(rtwdev); 4776 rtw89_btc_ntfy_radio_state(rtwdev, BTC_RFCTRL_WL_ON); 4777 rtw89_fw_h2c_fw_log(rtwdev, rtwdev->fw.log.enable); 4778 rtw89_fw_h2c_init_ba_cam(rtwdev); 4779 4780 return 0; 4781 } 4782 4783 void rtw89_core_stop(struct rtw89_dev *rtwdev) 4784 { 4785 struct wiphy *wiphy = rtwdev->hw->wiphy; 4786 struct rtw89_btc *btc = &rtwdev->btc; 4787 4788 lockdep_assert_wiphy(wiphy); 4789 4790 /* Prvent to stop twice; enter_ips and ops_stop */ 4791 if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags)) 4792 return; 4793 4794 rtw89_btc_ntfy_radio_state(rtwdev, BTC_RFCTRL_WL_OFF); 4795 4796 clear_bit(RTW89_FLAG_RUNNING, rtwdev->flags); 4797 4798 wiphy_work_cancel(wiphy, &rtwdev->c2h_work); 4799 wiphy_work_cancel(wiphy, &rtwdev->cancel_6ghz_probe_work); 4800 wiphy_work_cancel(wiphy, &btc->eapol_notify_work); 4801 wiphy_work_cancel(wiphy, &btc->arp_notify_work); 4802 wiphy_work_cancel(wiphy, &btc->dhcp_notify_work); 4803 wiphy_work_cancel(wiphy, &btc->icmp_notify_work); 4804 cancel_delayed_work_sync(&rtwdev->txq_reinvoke_work); 4805 wiphy_delayed_work_cancel(wiphy, &rtwdev->track_work); 4806 wiphy_delayed_work_cancel(wiphy, &rtwdev->chanctx_work); 4807 wiphy_delayed_work_cancel(wiphy, &rtwdev->coex_act1_work); 4808 wiphy_delayed_work_cancel(wiphy, &rtwdev->coex_bt_devinfo_work); 4809 wiphy_delayed_work_cancel(wiphy, &rtwdev->coex_rfk_chk_work); 4810 wiphy_delayed_work_cancel(wiphy, &rtwdev->cfo_track_work); 4811 cancel_delayed_work_sync(&rtwdev->forbid_ba_work); 4812 wiphy_delayed_work_cancel(wiphy, &rtwdev->antdiv_work); 4813 4814 rtw89_btc_ntfy_poweroff(rtwdev); 4815 rtw89_hci_flush_queues(rtwdev, BIT(rtwdev->hw->queues) - 1, true); 4816 rtw89_mac_flush_txq(rtwdev, BIT(rtwdev->hw->queues) - 1, true); 4817 rtw89_hci_stop(rtwdev); 4818 rtw89_hci_deinit(rtwdev); 4819 rtw89_mac_pwr_off(rtwdev); 4820 rtw89_hci_reset(rtwdev); 4821 } 4822 4823 u8 rtw89_acquire_mac_id(struct rtw89_dev *rtwdev) 4824 { 4825 const struct rtw89_chip_info *chip = rtwdev->chip; 4826 u8 mac_id_num; 4827 u8 mac_id; 4828 4829 if (rtwdev->support_mlo) 4830 mac_id_num = chip->support_macid_num / chip->support_link_num; 4831 else 4832 mac_id_num = chip->support_macid_num; 4833 4834 mac_id = find_first_zero_bit(rtwdev->mac_id_map, mac_id_num); 4835 if (mac_id == mac_id_num) 4836 return RTW89_MAX_MAC_ID_NUM; 4837 4838 set_bit(mac_id, rtwdev->mac_id_map); 4839 return mac_id; 4840 } 4841 4842 void rtw89_release_mac_id(struct rtw89_dev *rtwdev, u8 mac_id) 4843 { 4844 clear_bit(mac_id, rtwdev->mac_id_map); 4845 } 4846 4847 void rtw89_init_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 4848 u8 mac_id, u8 port) 4849 { 4850 const struct rtw89_chip_info *chip = rtwdev->chip; 4851 u8 support_link_num = chip->support_link_num; 4852 u8 support_mld_num = 0; 4853 unsigned int link_id; 4854 u8 index; 4855 4856 bitmap_zero(rtwvif->links_inst_map, __RTW89_MLD_MAX_LINK_NUM); 4857 for (link_id = 0; link_id < IEEE80211_MLD_MAX_NUM_LINKS; link_id++) 4858 rtwvif->links[link_id] = NULL; 4859 4860 rtwvif->rtwdev = rtwdev; 4861 4862 if (rtwdev->support_mlo) { 4863 rtwvif->links_inst_valid_num = support_link_num; 4864 support_mld_num = chip->support_macid_num / support_link_num; 4865 } else { 4866 rtwvif->links_inst_valid_num = 1; 4867 } 4868 4869 for (index = 0; index < rtwvif->links_inst_valid_num; index++) { 4870 struct rtw89_vif_link *inst = &rtwvif->links_inst[index]; 4871 4872 inst->rtwvif = rtwvif; 4873 inst->mac_id = mac_id + index * support_mld_num; 4874 inst->mac_idx = RTW89_MAC_0 + index; 4875 inst->phy_idx = RTW89_PHY_0 + index; 4876 4877 /* multi-link use the same port id on different HW bands */ 4878 inst->port = port; 4879 } 4880 } 4881 4882 void rtw89_init_sta(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 4883 struct rtw89_sta *rtwsta, u8 mac_id) 4884 { 4885 const struct rtw89_chip_info *chip = rtwdev->chip; 4886 u8 support_link_num = chip->support_link_num; 4887 u8 support_mld_num = 0; 4888 unsigned int link_id; 4889 u8 index; 4890 4891 bitmap_zero(rtwsta->links_inst_map, __RTW89_MLD_MAX_LINK_NUM); 4892 for (link_id = 0; link_id < IEEE80211_MLD_MAX_NUM_LINKS; link_id++) 4893 rtwsta->links[link_id] = NULL; 4894 4895 rtwsta->rtwdev = rtwdev; 4896 rtwsta->rtwvif = rtwvif; 4897 4898 if (rtwdev->support_mlo) { 4899 rtwsta->links_inst_valid_num = support_link_num; 4900 support_mld_num = chip->support_macid_num / support_link_num; 4901 } else { 4902 rtwsta->links_inst_valid_num = 1; 4903 } 4904 4905 for (index = 0; index < rtwsta->links_inst_valid_num; index++) { 4906 struct rtw89_sta_link *inst = &rtwsta->links_inst[index]; 4907 4908 inst->rtwvif_link = &rtwvif->links_inst[index]; 4909 4910 inst->rtwsta = rtwsta; 4911 inst->mac_id = mac_id + index * support_mld_num; 4912 } 4913 } 4914 4915 struct rtw89_vif_link *rtw89_vif_set_link(struct rtw89_vif *rtwvif, 4916 unsigned int link_id) 4917 { 4918 struct rtw89_vif_link *rtwvif_link = rtwvif->links[link_id]; 4919 u8 index; 4920 int ret; 4921 4922 if (rtwvif_link) 4923 return rtwvif_link; 4924 4925 index = find_first_zero_bit(rtwvif->links_inst_map, 4926 rtwvif->links_inst_valid_num); 4927 if (index == rtwvif->links_inst_valid_num) { 4928 ret = -EBUSY; 4929 goto err; 4930 } 4931 4932 rtwvif_link = &rtwvif->links_inst[index]; 4933 rtwvif_link->link_id = link_id; 4934 4935 set_bit(index, rtwvif->links_inst_map); 4936 rtwvif->links[link_id] = rtwvif_link; 4937 list_add_tail(&rtwvif_link->dlink_schd, &rtwvif->dlink_pool); 4938 return rtwvif_link; 4939 4940 err: 4941 rtw89_err(rtwvif->rtwdev, "vif (link_id %u) failed to set link: %d\n", 4942 link_id, ret); 4943 return NULL; 4944 } 4945 4946 void rtw89_vif_unset_link(struct rtw89_vif *rtwvif, unsigned int link_id) 4947 { 4948 struct rtw89_vif_link **container = &rtwvif->links[link_id]; 4949 struct rtw89_vif_link *link = *container; 4950 u8 index; 4951 4952 if (!link) 4953 return; 4954 4955 index = rtw89_vif_link_inst_get_index(link); 4956 clear_bit(index, rtwvif->links_inst_map); 4957 *container = NULL; 4958 list_del(&link->dlink_schd); 4959 } 4960 4961 struct rtw89_sta_link *rtw89_sta_set_link(struct rtw89_sta *rtwsta, 4962 unsigned int link_id) 4963 { 4964 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 4965 struct rtw89_vif_link *rtwvif_link = rtwvif->links[link_id]; 4966 struct rtw89_sta_link *rtwsta_link = rtwsta->links[link_id]; 4967 u8 index; 4968 int ret; 4969 4970 if (rtwsta_link) 4971 return rtwsta_link; 4972 4973 if (!rtwvif_link) { 4974 ret = -ENOLINK; 4975 goto err; 4976 } 4977 4978 index = rtw89_vif_link_inst_get_index(rtwvif_link); 4979 if (test_bit(index, rtwsta->links_inst_map)) { 4980 ret = -EBUSY; 4981 goto err; 4982 } 4983 4984 rtwsta_link = &rtwsta->links_inst[index]; 4985 rtwsta_link->link_id = link_id; 4986 4987 set_bit(index, rtwsta->links_inst_map); 4988 rtwsta->links[link_id] = rtwsta_link; 4989 list_add_tail(&rtwsta_link->dlink_schd, &rtwsta->dlink_pool); 4990 return rtwsta_link; 4991 4992 err: 4993 rtw89_err(rtwsta->rtwdev, "sta (link_id %u) failed to set link: %d\n", 4994 link_id, ret); 4995 return NULL; 4996 } 4997 4998 void rtw89_sta_unset_link(struct rtw89_sta *rtwsta, unsigned int link_id) 4999 { 5000 struct rtw89_sta_link **container = &rtwsta->links[link_id]; 5001 struct rtw89_sta_link *link = *container; 5002 u8 index; 5003 5004 if (!link) 5005 return; 5006 5007 index = rtw89_sta_link_inst_get_index(link); 5008 clear_bit(index, rtwsta->links_inst_map); 5009 *container = NULL; 5010 list_del(&link->dlink_schd); 5011 } 5012 5013 int rtw89_core_init(struct rtw89_dev *rtwdev) 5014 { 5015 struct rtw89_btc *btc = &rtwdev->btc; 5016 u8 band; 5017 5018 INIT_LIST_HEAD(&rtwdev->ba_list); 5019 INIT_LIST_HEAD(&rtwdev->forbid_ba_list); 5020 INIT_LIST_HEAD(&rtwdev->rtwvifs_list); 5021 INIT_LIST_HEAD(&rtwdev->early_h2c_list); 5022 for (band = NL80211_BAND_2GHZ; band < NUM_NL80211_BANDS; band++) { 5023 if (!(rtwdev->chip->support_bands & BIT(band))) 5024 continue; 5025 INIT_LIST_HEAD(&rtwdev->scan_info.pkt_list[band]); 5026 } 5027 INIT_LIST_HEAD(&rtwdev->scan_info.chan_list); 5028 INIT_WORK(&rtwdev->ba_work, rtw89_core_ba_work); 5029 INIT_WORK(&rtwdev->txq_work, rtw89_core_txq_work); 5030 INIT_DELAYED_WORK(&rtwdev->txq_reinvoke_work, rtw89_core_txq_reinvoke_work); 5031 wiphy_delayed_work_init(&rtwdev->track_work, rtw89_track_work); 5032 wiphy_delayed_work_init(&rtwdev->chanctx_work, rtw89_chanctx_work); 5033 wiphy_delayed_work_init(&rtwdev->coex_act1_work, rtw89_coex_act1_work); 5034 wiphy_delayed_work_init(&rtwdev->coex_bt_devinfo_work, rtw89_coex_bt_devinfo_work); 5035 wiphy_delayed_work_init(&rtwdev->coex_rfk_chk_work, rtw89_coex_rfk_chk_work); 5036 wiphy_delayed_work_init(&rtwdev->cfo_track_work, rtw89_phy_cfo_track_work); 5037 INIT_DELAYED_WORK(&rtwdev->forbid_ba_work, rtw89_forbid_ba_work); 5038 wiphy_delayed_work_init(&rtwdev->antdiv_work, rtw89_phy_antdiv_work); 5039 rtwdev->txq_wq = alloc_workqueue("rtw89_tx_wq", WQ_UNBOUND | WQ_HIGHPRI, 0); 5040 if (!rtwdev->txq_wq) 5041 return -ENOMEM; 5042 spin_lock_init(&rtwdev->ba_lock); 5043 spin_lock_init(&rtwdev->rpwm_lock); 5044 mutex_init(&rtwdev->rf_mutex); 5045 rtwdev->total_sta_assoc = 0; 5046 5047 rtw89_init_wait(&rtwdev->mcc.wait); 5048 rtw89_init_wait(&rtwdev->mlo.wait); 5049 rtw89_init_wait(&rtwdev->mac.fw_ofld_wait); 5050 rtw89_init_wait(&rtwdev->wow.wait); 5051 rtw89_init_wait(&rtwdev->mac.ps_wait); 5052 5053 wiphy_work_init(&rtwdev->c2h_work, rtw89_fw_c2h_work); 5054 wiphy_work_init(&rtwdev->ips_work, rtw89_ips_work); 5055 wiphy_work_init(&rtwdev->cancel_6ghz_probe_work, rtw89_cancel_6ghz_probe_work); 5056 INIT_WORK(&rtwdev->load_firmware_work, rtw89_load_firmware_work); 5057 5058 skb_queue_head_init(&rtwdev->c2h_queue); 5059 rtw89_core_ppdu_sts_init(rtwdev); 5060 rtw89_traffic_stats_init(rtwdev, &rtwdev->stats); 5061 5062 rtwdev->hal.rx_fltr = DEFAULT_AX_RX_FLTR; 5063 rtwdev->dbcc_en = false; 5064 rtwdev->mlo_dbcc_mode = MLO_DBCC_NOT_SUPPORT; 5065 rtwdev->mac.qta_mode = RTW89_QTA_SCC; 5066 5067 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) { 5068 rtwdev->dbcc_en = true; 5069 rtwdev->mac.qta_mode = RTW89_QTA_DBCC; 5070 rtwdev->mlo_dbcc_mode = MLO_1_PLUS_1_1RF; 5071 } 5072 5073 rtwdev->bbs[RTW89_PHY_0].phy_idx = RTW89_PHY_0; 5074 rtwdev->bbs[RTW89_PHY_1].phy_idx = RTW89_PHY_1; 5075 5076 wiphy_work_init(&btc->eapol_notify_work, rtw89_btc_ntfy_eapol_packet_work); 5077 wiphy_work_init(&btc->arp_notify_work, rtw89_btc_ntfy_arp_packet_work); 5078 wiphy_work_init(&btc->dhcp_notify_work, rtw89_btc_ntfy_dhcp_packet_work); 5079 wiphy_work_init(&btc->icmp_notify_work, rtw89_btc_ntfy_icmp_packet_work); 5080 5081 init_completion(&rtwdev->fw.req.completion); 5082 init_completion(&rtwdev->rfk_wait.completion); 5083 5084 schedule_work(&rtwdev->load_firmware_work); 5085 5086 rtw89_ser_init(rtwdev); 5087 rtw89_entity_init(rtwdev); 5088 rtw89_sar_init(rtwdev); 5089 rtw89_phy_ant_gain_init(rtwdev); 5090 5091 return 0; 5092 } 5093 EXPORT_SYMBOL(rtw89_core_init); 5094 5095 void rtw89_core_deinit(struct rtw89_dev *rtwdev) 5096 { 5097 rtw89_ser_deinit(rtwdev); 5098 rtw89_unload_firmware(rtwdev); 5099 __rtw89_fw_free_all_early_h2c(rtwdev); 5100 5101 destroy_workqueue(rtwdev->txq_wq); 5102 mutex_destroy(&rtwdev->rf_mutex); 5103 } 5104 EXPORT_SYMBOL(rtw89_core_deinit); 5105 5106 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 5107 const u8 *mac_addr, bool hw_scan) 5108 { 5109 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, 5110 rtwvif_link->chanctx_idx); 5111 struct rtw89_bb_ctx *bb = rtw89_get_bb_ctx(rtwdev, rtwvif_link->phy_idx); 5112 5113 rtwdev->scanning = true; 5114 5115 ether_addr_copy(rtwvif_link->mac_addr, mac_addr); 5116 rtw89_btc_ntfy_scan_start(rtwdev, rtwvif_link->phy_idx, chan->band_type); 5117 rtw89_chip_rfk_scan(rtwdev, rtwvif_link, true); 5118 rtw89_hci_recalc_int_mit(rtwdev); 5119 rtw89_phy_config_edcca(rtwdev, bb, true); 5120 rtw89_tas_scan(rtwdev, true); 5121 5122 rtw89_fw_h2c_cam(rtwdev, rtwvif_link, NULL, mac_addr); 5123 } 5124 5125 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev, 5126 struct rtw89_vif_link *rtwvif_link, bool hw_scan) 5127 { 5128 struct ieee80211_bss_conf *bss_conf; 5129 struct rtw89_bb_ctx *bb; 5130 5131 if (!rtwvif_link) 5132 return; 5133 5134 rcu_read_lock(); 5135 5136 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true); 5137 ether_addr_copy(rtwvif_link->mac_addr, bss_conf->addr); 5138 5139 rcu_read_unlock(); 5140 5141 rtw89_fw_h2c_cam(rtwdev, rtwvif_link, NULL, NULL); 5142 5143 rtw89_chip_rfk_scan(rtwdev, rtwvif_link, false); 5144 rtw89_btc_ntfy_scan_finish(rtwdev, rtwvif_link->phy_idx); 5145 bb = rtw89_get_bb_ctx(rtwdev, rtwvif_link->phy_idx); 5146 rtw89_phy_config_edcca(rtwdev, bb, false); 5147 rtw89_tas_scan(rtwdev, false); 5148 5149 rtwdev->scanning = false; 5150 rtw89_for_each_active_bb(rtwdev, bb) 5151 bb->dig.bypass_dig = true; 5152 if (hw_scan && (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE)) 5153 wiphy_work_queue(rtwdev->hw->wiphy, &rtwdev->ips_work); 5154 } 5155 5156 static void rtw89_read_chip_ver(struct rtw89_dev *rtwdev) 5157 { 5158 const struct rtw89_chip_info *chip = rtwdev->chip; 5159 int ret; 5160 u8 val; 5161 u8 cv; 5162 5163 cv = rtw89_read32_mask(rtwdev, R_AX_SYS_CFG1, B_AX_CHIP_VER_MASK); 5164 if (chip->chip_id == RTL8852A && cv <= CHIP_CBV) { 5165 if (rtw89_read32(rtwdev, R_AX_GPIO0_7_FUNC_SEL) == RTW89_R32_DEAD) 5166 cv = CHIP_CAV; 5167 else 5168 cv = CHIP_CBV; 5169 } 5170 5171 rtwdev->hal.cv = cv; 5172 5173 if (rtw89_is_rtl885xb(rtwdev)) { 5174 ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_CV, &val); 5175 if (ret) 5176 return; 5177 5178 rtwdev->hal.acv = u8_get_bits(val, XTAL_SI_ACV_MASK); 5179 } 5180 } 5181 5182 static void rtw89_core_setup_phycap(struct rtw89_dev *rtwdev) 5183 { 5184 const struct rtw89_chip_info *chip = rtwdev->chip; 5185 5186 rtwdev->hal.support_cckpd = 5187 !(rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv <= CHIP_CBV) && 5188 !(rtwdev->chip->chip_id == RTL8852B && rtwdev->hal.cv <= CHIP_CAV); 5189 rtwdev->hal.support_igi = 5190 rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv <= CHIP_CBV; 5191 5192 if (test_bit(RTW89_QUIRK_THERMAL_PROT_120C, rtwdev->quirks)) 5193 rtwdev->hal.thermal_prot_th = chip->thermal_th[1]; 5194 else if (test_bit(RTW89_QUIRK_THERMAL_PROT_110C, rtwdev->quirks)) 5195 rtwdev->hal.thermal_prot_th = chip->thermal_th[0]; 5196 else 5197 rtwdev->hal.thermal_prot_th = 0; 5198 } 5199 5200 static void rtw89_core_setup_rfe_parms(struct rtw89_dev *rtwdev) 5201 { 5202 const struct rtw89_chip_info *chip = rtwdev->chip; 5203 const struct rtw89_rfe_parms_conf *conf = chip->rfe_parms_conf; 5204 struct rtw89_efuse *efuse = &rtwdev->efuse; 5205 const struct rtw89_rfe_parms *sel; 5206 u8 rfe_type = efuse->rfe_type; 5207 5208 if (!conf) { 5209 sel = chip->dflt_parms; 5210 goto out; 5211 } 5212 5213 while (conf->rfe_parms) { 5214 if (rfe_type == conf->rfe_type) { 5215 sel = conf->rfe_parms; 5216 goto out; 5217 } 5218 conf++; 5219 } 5220 5221 sel = chip->dflt_parms; 5222 5223 out: 5224 rtwdev->rfe_parms = rtw89_load_rfe_data_from_fw(rtwdev, sel); 5225 rtw89_load_txpwr_table(rtwdev, rtwdev->rfe_parms->byr_tbl); 5226 } 5227 5228 int rtw89_core_mlsr_switch(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 5229 unsigned int link_id) 5230 { 5231 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 5232 u16 usable_links = ieee80211_vif_usable_links(vif); 5233 u16 active_links = vif->active_links; 5234 struct rtw89_vif_link *target, *cur; 5235 int ret; 5236 5237 lockdep_assert_wiphy(rtwdev->hw->wiphy); 5238 5239 if (unlikely(!ieee80211_vif_is_mld(vif))) 5240 return -EOPNOTSUPP; 5241 5242 if (unlikely(!(usable_links & BIT(link_id)))) { 5243 rtw89_warn(rtwdev, "%s: link id %u is not usable\n", __func__, 5244 link_id); 5245 return -ENOLINK; 5246 } 5247 5248 if (active_links == BIT(link_id)) 5249 return 0; 5250 5251 rtw89_debug(rtwdev, RTW89_DBG_STATE, "%s: switch to link id %u MLSR\n", 5252 __func__, link_id); 5253 5254 rtw89_leave_lps(rtwdev); 5255 5256 ieee80211_stop_queues(rtwdev->hw); 5257 flush_work(&rtwdev->txq_work); 5258 5259 cur = rtw89_get_designated_link(rtwvif); 5260 5261 ret = ieee80211_set_active_links(vif, active_links | BIT(link_id)); 5262 if (ret) { 5263 rtw89_err(rtwdev, "%s: failed to activate link id %u\n", 5264 __func__, link_id); 5265 goto wake_queue; 5266 } 5267 5268 target = rtwvif->links[link_id]; 5269 if (unlikely(!target)) { 5270 rtw89_err(rtwdev, "%s: failed to confirm link id %u\n", 5271 __func__, link_id); 5272 5273 ieee80211_set_active_links(vif, active_links); 5274 ret = -EFAULT; 5275 goto wake_queue; 5276 } 5277 5278 if (likely(cur)) 5279 rtw89_fw_h2c_mlo_link_cfg(rtwdev, cur, false); 5280 5281 rtw89_fw_h2c_mlo_link_cfg(rtwdev, target, true); 5282 5283 ret = ieee80211_set_active_links(vif, BIT(link_id)); 5284 if (ret) 5285 rtw89_err(rtwdev, "%s: failed to inactivate links 0x%x\n", 5286 __func__, active_links); 5287 5288 rtw89_chip_rfk_channel(rtwdev, target); 5289 5290 rtwvif->mlo_mode = RTW89_MLO_MODE_MLSR; 5291 5292 wake_queue: 5293 ieee80211_wake_queues(rtwdev->hw); 5294 5295 return ret; 5296 } 5297 5298 static int rtw89_chip_efuse_info_setup(struct rtw89_dev *rtwdev) 5299 { 5300 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 5301 int ret; 5302 5303 ret = rtw89_mac_partial_init(rtwdev, false); 5304 if (ret) 5305 return ret; 5306 5307 ret = mac->parse_efuse_map(rtwdev); 5308 if (ret) 5309 return ret; 5310 5311 ret = mac->parse_phycap_map(rtwdev); 5312 if (ret) 5313 return ret; 5314 5315 ret = rtw89_mac_setup_phycap(rtwdev); 5316 if (ret) 5317 return ret; 5318 5319 rtw89_core_setup_phycap(rtwdev); 5320 5321 rtw89_hci_mac_pre_deinit(rtwdev); 5322 5323 return 0; 5324 } 5325 5326 static int rtw89_chip_board_info_setup(struct rtw89_dev *rtwdev) 5327 { 5328 rtw89_chip_fem_setup(rtwdev); 5329 5330 return 0; 5331 } 5332 5333 static bool rtw89_chip_has_rfkill(struct rtw89_dev *rtwdev) 5334 { 5335 return !!rtwdev->chip->rfkill_init; 5336 } 5337 5338 static void rtw89_core_rfkill_init(struct rtw89_dev *rtwdev) 5339 { 5340 const struct rtw89_rfkill_regs *regs = rtwdev->chip->rfkill_init; 5341 5342 rtw89_write16_mask(rtwdev, regs->pinmux.addr, 5343 regs->pinmux.mask, regs->pinmux.data); 5344 rtw89_write16_mask(rtwdev, regs->mode.addr, 5345 regs->mode.mask, regs->mode.data); 5346 } 5347 5348 static bool rtw89_core_rfkill_get(struct rtw89_dev *rtwdev) 5349 { 5350 const struct rtw89_reg_def *reg = &rtwdev->chip->rfkill_get; 5351 5352 return !rtw89_read8_mask(rtwdev, reg->addr, reg->mask); 5353 } 5354 5355 static void rtw89_rfkill_polling_init(struct rtw89_dev *rtwdev) 5356 { 5357 if (!rtw89_chip_has_rfkill(rtwdev)) 5358 return; 5359 5360 rtw89_core_rfkill_init(rtwdev); 5361 rtw89_core_rfkill_poll(rtwdev, true); 5362 wiphy_rfkill_start_polling(rtwdev->hw->wiphy); 5363 } 5364 5365 static void rtw89_rfkill_polling_deinit(struct rtw89_dev *rtwdev) 5366 { 5367 if (!rtw89_chip_has_rfkill(rtwdev)) 5368 return; 5369 5370 wiphy_rfkill_stop_polling(rtwdev->hw->wiphy); 5371 } 5372 5373 void rtw89_core_rfkill_poll(struct rtw89_dev *rtwdev, bool force) 5374 { 5375 bool prev, blocked; 5376 5377 if (!rtw89_chip_has_rfkill(rtwdev)) 5378 return; 5379 5380 prev = test_bit(RTW89_FLAG_HW_RFKILL_STATE, rtwdev->flags); 5381 blocked = rtw89_core_rfkill_get(rtwdev); 5382 5383 if (!force && prev == blocked) 5384 return; 5385 5386 rtw89_info(rtwdev, "rfkill hardware state changed to %s\n", 5387 blocked ? "disable" : "enable"); 5388 5389 if (blocked) 5390 set_bit(RTW89_FLAG_HW_RFKILL_STATE, rtwdev->flags); 5391 else 5392 clear_bit(RTW89_FLAG_HW_RFKILL_STATE, rtwdev->flags); 5393 5394 wiphy_rfkill_set_hw_state(rtwdev->hw->wiphy, blocked); 5395 } 5396 5397 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev) 5398 { 5399 int ret; 5400 5401 rtw89_read_chip_ver(rtwdev); 5402 5403 ret = rtw89_mac_pwr_on(rtwdev); 5404 if (ret) { 5405 rtw89_err(rtwdev, "failed to power on\n"); 5406 return ret; 5407 } 5408 5409 ret = rtw89_wait_firmware_completion(rtwdev); 5410 if (ret) { 5411 rtw89_err(rtwdev, "failed to wait firmware completion\n"); 5412 goto out; 5413 } 5414 5415 ret = rtw89_fw_recognize(rtwdev); 5416 if (ret) { 5417 rtw89_err(rtwdev, "failed to recognize firmware\n"); 5418 goto out; 5419 } 5420 5421 ret = rtw89_chip_efuse_info_setup(rtwdev); 5422 if (ret) 5423 goto out; 5424 5425 ret = rtw89_fw_recognize_elements(rtwdev); 5426 if (ret) { 5427 rtw89_err(rtwdev, "failed to recognize firmware elements\n"); 5428 goto out; 5429 } 5430 5431 ret = rtw89_chip_board_info_setup(rtwdev); 5432 if (ret) 5433 goto out; 5434 5435 rtw89_core_setup_rfe_parms(rtwdev); 5436 rtwdev->ps_mode = rtw89_update_ps_mode(rtwdev); 5437 5438 out: 5439 rtw89_mac_pwr_off(rtwdev); 5440 5441 return ret; 5442 } 5443 EXPORT_SYMBOL(rtw89_chip_info_setup); 5444 5445 void rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, 5446 struct rtw89_vif_link *rtwvif_link) 5447 { 5448 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 5449 const struct rtw89_chip_info *chip = rtwdev->chip; 5450 struct ieee80211_bss_conf *bss_conf; 5451 5452 rcu_read_lock(); 5453 5454 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, false); 5455 if (!bss_conf->he_support || !vif->cfg.assoc) { 5456 rcu_read_unlock(); 5457 return; 5458 } 5459 5460 rcu_read_unlock(); 5461 5462 if (chip->ops->set_txpwr_ul_tb_offset) 5463 chip->ops->set_txpwr_ul_tb_offset(rtwdev, 0, rtwvif_link->mac_idx); 5464 } 5465 5466 static int rtw89_core_register_hw(struct rtw89_dev *rtwdev) 5467 { 5468 const struct rtw89_chip_info *chip = rtwdev->chip; 5469 u8 n = rtwdev->support_mlo ? chip->support_link_num : 1; 5470 struct ieee80211_hw *hw = rtwdev->hw; 5471 struct rtw89_efuse *efuse = &rtwdev->efuse; 5472 struct rtw89_hal *hal = &rtwdev->hal; 5473 int ret; 5474 int tx_headroom = IEEE80211_HT_CTL_LEN; 5475 5476 hw->vif_data_size = struct_size_t(struct rtw89_vif, links_inst, n); 5477 hw->sta_data_size = struct_size_t(struct rtw89_sta, links_inst, n); 5478 hw->txq_data_size = sizeof(struct rtw89_txq); 5479 hw->chanctx_data_size = sizeof(struct rtw89_chanctx_cfg); 5480 5481 SET_IEEE80211_PERM_ADDR(hw, efuse->addr); 5482 5483 hw->extra_tx_headroom = tx_headroom; 5484 hw->queues = IEEE80211_NUM_ACS; 5485 hw->max_rx_aggregation_subframes = RTW89_MAX_RX_AGG_NUM; 5486 hw->max_tx_aggregation_subframes = RTW89_MAX_TX_AGG_NUM; 5487 hw->uapsd_max_sp_len = IEEE80211_WMM_IE_STA_QOSINFO_SP_ALL; 5488 5489 hw->radiotap_mcs_details |= IEEE80211_RADIOTAP_MCS_HAVE_FEC | 5490 IEEE80211_RADIOTAP_MCS_HAVE_STBC; 5491 hw->radiotap_vht_details |= IEEE80211_RADIOTAP_VHT_KNOWN_STBC; 5492 5493 ieee80211_hw_set(hw, SIGNAL_DBM); 5494 ieee80211_hw_set(hw, HAS_RATE_CONTROL); 5495 ieee80211_hw_set(hw, MFP_CAPABLE); 5496 ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS); 5497 ieee80211_hw_set(hw, AMPDU_AGGREGATION); 5498 ieee80211_hw_set(hw, RX_INCLUDES_FCS); 5499 ieee80211_hw_set(hw, TX_AMSDU); 5500 ieee80211_hw_set(hw, SUPPORT_FAST_XMIT); 5501 ieee80211_hw_set(hw, SUPPORTS_AMSDU_IN_AMPDU); 5502 ieee80211_hw_set(hw, SUPPORTS_PS); 5503 ieee80211_hw_set(hw, SUPPORTS_DYNAMIC_PS); 5504 ieee80211_hw_set(hw, SINGLE_SCAN_ON_ALL_BANDS); 5505 ieee80211_hw_set(hw, SUPPORTS_MULTI_BSSID); 5506 ieee80211_hw_set(hw, WANT_MONITOR_VIF); 5507 5508 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) 5509 ieee80211_hw_set(hw, SUPPORTS_VHT_EXT_NSS_BW); 5510 5511 if (RTW89_CHK_FW_FEATURE(BEACON_FILTER, &rtwdev->fw)) 5512 ieee80211_hw_set(hw, CONNECTION_MONITOR); 5513 5514 if (RTW89_CHK_FW_FEATURE(NOTIFY_AP_INFO, &rtwdev->fw)) 5515 ieee80211_hw_set(hw, AP_LINK_PS); 5516 5517 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) | 5518 BIT(NL80211_IFTYPE_AP) | 5519 BIT(NL80211_IFTYPE_P2P_CLIENT) | 5520 BIT(NL80211_IFTYPE_P2P_GO); 5521 5522 if (hal->ant_diversity) { 5523 hw->wiphy->available_antennas_tx = 0x3; 5524 hw->wiphy->available_antennas_rx = 0x3; 5525 } else { 5526 hw->wiphy->available_antennas_tx = BIT(rtwdev->chip->rf_path_num) - 1; 5527 hw->wiphy->available_antennas_rx = BIT(rtwdev->chip->rf_path_num) - 1; 5528 } 5529 5530 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS | 5531 WIPHY_FLAG_TDLS_EXTERNAL_SETUP | 5532 WIPHY_FLAG_AP_UAPSD | 5533 WIPHY_FLAG_SUPPORTS_EXT_KEK_KCK; 5534 5535 if (!chip->support_rnr) 5536 hw->wiphy->flags |= WIPHY_FLAG_SPLIT_SCAN_6GHZ; 5537 5538 if (chip->chip_gen == RTW89_CHIP_BE) 5539 hw->wiphy->flags |= WIPHY_FLAG_DISABLE_WEXT; 5540 5541 if (rtwdev->support_mlo) { 5542 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_MLO; 5543 hw->wiphy->iftype_ext_capab = rtw89_iftypes_ext_capa; 5544 hw->wiphy->num_iftype_ext_capab = ARRAY_SIZE(rtw89_iftypes_ext_capa); 5545 } 5546 5547 hw->wiphy->features |= NL80211_FEATURE_SCAN_RANDOM_MAC_ADDR; 5548 5549 hw->wiphy->max_scan_ssids = RTW89_SCANOFLD_MAX_SSID; 5550 hw->wiphy->max_scan_ie_len = RTW89_SCANOFLD_MAX_IE_LEN; 5551 5552 #ifdef CONFIG_PM 5553 hw->wiphy->wowlan = rtwdev->chip->wowlan_stub; 5554 hw->wiphy->max_sched_scan_ssids = RTW89_SCANOFLD_MAX_SSID; 5555 #endif 5556 5557 hw->wiphy->tid_config_support.vif |= BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL); 5558 hw->wiphy->tid_config_support.peer |= BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL); 5559 hw->wiphy->tid_config_support.vif |= BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL); 5560 hw->wiphy->tid_config_support.peer |= BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL); 5561 hw->wiphy->max_remain_on_channel_duration = 1000; 5562 5563 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0); 5564 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SCAN_RANDOM_SN); 5565 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SET_SCAN_DWELL); 5566 5567 ret = rtw89_core_set_supported_band(rtwdev); 5568 if (ret) { 5569 rtw89_err(rtwdev, "failed to set supported band\n"); 5570 return ret; 5571 } 5572 5573 ret = rtw89_regd_setup(rtwdev); 5574 if (ret) { 5575 rtw89_err(rtwdev, "failed to set up regd\n"); 5576 return ret; 5577 } 5578 5579 hw->wiphy->sar_capa = &rtw89_sar_capa; 5580 5581 ret = ieee80211_register_hw(hw); 5582 if (ret) { 5583 rtw89_err(rtwdev, "failed to register hw\n"); 5584 return ret; 5585 } 5586 5587 ret = rtw89_regd_init_hint(rtwdev); 5588 if (ret) { 5589 rtw89_err(rtwdev, "failed to init regd\n"); 5590 goto err_unregister_hw; 5591 } 5592 5593 rtw89_rfkill_polling_init(rtwdev); 5594 5595 return 0; 5596 5597 err_unregister_hw: 5598 ieee80211_unregister_hw(hw); 5599 5600 return ret; 5601 } 5602 5603 static void rtw89_core_unregister_hw(struct rtw89_dev *rtwdev) 5604 { 5605 struct ieee80211_hw *hw = rtwdev->hw; 5606 5607 rtw89_rfkill_polling_deinit(rtwdev); 5608 ieee80211_unregister_hw(hw); 5609 } 5610 5611 int rtw89_core_register(struct rtw89_dev *rtwdev) 5612 { 5613 int ret; 5614 5615 ret = rtw89_core_register_hw(rtwdev); 5616 if (ret) { 5617 rtw89_err(rtwdev, "failed to register core hw\n"); 5618 return ret; 5619 } 5620 5621 rtw89_debugfs_init(rtwdev); 5622 5623 return 0; 5624 } 5625 EXPORT_SYMBOL(rtw89_core_register); 5626 5627 void rtw89_core_unregister(struct rtw89_dev *rtwdev) 5628 { 5629 rtw89_core_unregister_hw(rtwdev); 5630 5631 rtw89_debugfs_deinit(rtwdev); 5632 } 5633 EXPORT_SYMBOL(rtw89_core_unregister); 5634 5635 struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device, 5636 u32 bus_data_size, 5637 const struct rtw89_chip_info *chip, 5638 const struct rtw89_chip_variant *variant) 5639 { 5640 struct rtw89_fw_info early_fw = {}; 5641 const struct firmware *firmware; 5642 struct ieee80211_hw *hw; 5643 struct rtw89_dev *rtwdev; 5644 struct ieee80211_ops *ops; 5645 u32 driver_data_size; 5646 int fw_format = -1; 5647 bool support_mlo; 5648 bool no_chanctx; 5649 5650 firmware = rtw89_early_fw_feature_recognize(device, chip, &early_fw, &fw_format); 5651 5652 ops = kmemdup(&rtw89_ops, sizeof(rtw89_ops), GFP_KERNEL); 5653 if (!ops) 5654 goto err; 5655 5656 no_chanctx = chip->support_chanctx_num == 0 || 5657 !RTW89_CHK_FW_FEATURE(SCAN_OFFLOAD, &early_fw) || 5658 !RTW89_CHK_FW_FEATURE(BEACON_FILTER, &early_fw); 5659 5660 if (no_chanctx) { 5661 ops->add_chanctx = ieee80211_emulate_add_chanctx; 5662 ops->remove_chanctx = ieee80211_emulate_remove_chanctx; 5663 ops->change_chanctx = ieee80211_emulate_change_chanctx; 5664 ops->switch_vif_chanctx = ieee80211_emulate_switch_vif_chanctx; 5665 ops->assign_vif_chanctx = NULL; 5666 ops->unassign_vif_chanctx = NULL; 5667 ops->remain_on_channel = NULL; 5668 ops->cancel_remain_on_channel = NULL; 5669 } 5670 5671 driver_data_size = sizeof(struct rtw89_dev) + bus_data_size; 5672 hw = ieee80211_alloc_hw(driver_data_size, ops); 5673 if (!hw) 5674 goto err; 5675 5676 /* Currently, our AP_LINK_PS handling only works for non-MLD softap 5677 * or MLD-single-link softap. If RTW89_MLD_NON_STA_LINK_NUM enlarges, 5678 * please tweak entire AP_LINKS_PS handling before supporting MLO. 5679 */ 5680 support_mlo = !no_chanctx && chip->support_link_num && 5681 RTW89_CHK_FW_FEATURE(NOTIFY_AP_INFO, &early_fw) && 5682 RTW89_MLD_NON_STA_LINK_NUM == 1; 5683 5684 hw->wiphy->iface_combinations = rtw89_iface_combs; 5685 5686 if (no_chanctx || chip->support_chanctx_num == 1) 5687 hw->wiphy->n_iface_combinations = 1; 5688 else 5689 hw->wiphy->n_iface_combinations = ARRAY_SIZE(rtw89_iface_combs); 5690 5691 rtwdev = hw->priv; 5692 rtwdev->hw = hw; 5693 rtwdev->dev = device; 5694 rtwdev->ops = ops; 5695 rtwdev->chip = chip; 5696 rtwdev->variant = variant; 5697 rtwdev->fw.req.firmware = firmware; 5698 rtwdev->fw.fw_format = fw_format; 5699 rtwdev->support_mlo = support_mlo; 5700 5701 rtw89_debug(rtwdev, RTW89_DBG_CHAN, "probe driver %s chanctx\n", 5702 no_chanctx ? "without" : "with"); 5703 rtw89_debug(rtwdev, RTW89_DBG_CHAN, "probe driver %s MLO cap\n", 5704 support_mlo ? "with" : "without"); 5705 5706 return rtwdev; 5707 5708 err: 5709 kfree(ops); 5710 release_firmware(firmware); 5711 return NULL; 5712 } 5713 EXPORT_SYMBOL(rtw89_alloc_ieee80211_hw); 5714 5715 void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev) 5716 { 5717 kfree(rtwdev->ops); 5718 kfree(rtwdev->rfe_data); 5719 release_firmware(rtwdev->fw.req.firmware); 5720 ieee80211_free_hw(rtwdev->hw); 5721 } 5722 EXPORT_SYMBOL(rtw89_free_ieee80211_hw); 5723 5724 MODULE_AUTHOR("Realtek Corporation"); 5725 MODULE_DESCRIPTION("Realtek 802.11ax wireless core module"); 5726 MODULE_LICENSE("Dual BSD/GPL"); 5727