1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2009-2012 Realtek Corporation.*/ 3 4 #include "wifi.h" 5 #include "core.h" 6 #include "pci.h" 7 #include "base.h" 8 #include "ps.h" 9 #include "efuse.h" 10 #include <linux/interrupt.h> 11 #include <linux/export.h> 12 #include <linux/module.h> 13 14 MODULE_AUTHOR("lizhaoming <chaoming_li@realsil.com.cn>"); 15 MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>"); 16 MODULE_AUTHOR("Larry Finger <Larry.FInger@lwfinger.net>"); 17 MODULE_LICENSE("GPL"); 18 MODULE_DESCRIPTION("PCI basic driver for rtlwifi"); 19 20 static const u16 pcibridge_vendors[PCI_BRIDGE_VENDOR_MAX] = { 21 INTEL_VENDOR_ID, 22 ATI_VENDOR_ID, 23 AMD_VENDOR_ID, 24 SIS_VENDOR_ID 25 }; 26 27 static const u8 ac_to_hwq[] = { 28 VO_QUEUE, 29 VI_QUEUE, 30 BE_QUEUE, 31 BK_QUEUE 32 }; 33 34 static u8 _rtl_mac_to_hwqueue(struct ieee80211_hw *hw, struct sk_buff *skb) 35 { 36 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 37 __le16 fc = rtl_get_fc(skb); 38 u8 queue_index = skb_get_queue_mapping(skb); 39 struct ieee80211_hdr *hdr; 40 41 if (unlikely(ieee80211_is_beacon(fc))) 42 return BEACON_QUEUE; 43 if (ieee80211_is_mgmt(fc) || ieee80211_is_ctl(fc)) 44 return MGNT_QUEUE; 45 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) 46 if (ieee80211_is_nullfunc(fc)) 47 return HIGH_QUEUE; 48 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8822BE) { 49 hdr = rtl_get_hdr(skb); 50 51 if (is_multicast_ether_addr(hdr->addr1) || 52 is_broadcast_ether_addr(hdr->addr1)) 53 return HIGH_QUEUE; 54 } 55 56 return ac_to_hwq[queue_index]; 57 } 58 59 /* Update PCI dependent default settings*/ 60 static void _rtl_pci_update_default_setting(struct ieee80211_hw *hw) 61 { 62 struct rtl_priv *rtlpriv = rtl_priv(hw); 63 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 64 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 65 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 66 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor; 67 u16 init_aspm; 68 69 ppsc->reg_rfps_level = 0; 70 ppsc->support_aspm = false; 71 72 /*Update PCI ASPM setting */ 73 switch (rtlpci->const_pci_aspm) { 74 case 0: 75 /*No ASPM */ 76 break; 77 78 case 1: 79 /*ASPM dynamically enabled/disable. */ 80 ppsc->reg_rfps_level |= RT_RF_LPS_LEVEL_ASPM; 81 break; 82 83 case 2: 84 /*ASPM with Clock Req dynamically enabled/disable. */ 85 ppsc->reg_rfps_level |= (RT_RF_LPS_LEVEL_ASPM | 86 RT_RF_OFF_LEVL_CLK_REQ); 87 break; 88 89 case 3: 90 /* Always enable ASPM and Clock Req 91 * from initialization to halt. 92 */ 93 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM); 94 ppsc->reg_rfps_level |= (RT_RF_PS_LEVEL_ALWAYS_ASPM | 95 RT_RF_OFF_LEVL_CLK_REQ); 96 break; 97 98 case 4: 99 /* Always enable ASPM without Clock Req 100 * from initialization to halt. 101 */ 102 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM | 103 RT_RF_OFF_LEVL_CLK_REQ); 104 ppsc->reg_rfps_level |= RT_RF_PS_LEVEL_ALWAYS_ASPM; 105 break; 106 } 107 108 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC; 109 110 /*Update Radio OFF setting */ 111 switch (rtlpci->const_hwsw_rfoff_d3) { 112 case 1: 113 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM) 114 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM; 115 break; 116 117 case 2: 118 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM) 119 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM; 120 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC; 121 break; 122 123 case 3: 124 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_PCI_D3; 125 break; 126 } 127 128 /*Set HW definition to determine if it supports ASPM. */ 129 switch (rtlpci->const_support_pciaspm) { 130 case 0: 131 /*Not support ASPM. */ 132 ppsc->support_aspm = false; 133 break; 134 case 1: 135 /*Support ASPM. */ 136 ppsc->support_aspm = true; 137 ppsc->support_backdoor = true; 138 break; 139 case 2: 140 /*ASPM value set by chipset. */ 141 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL) 142 ppsc->support_aspm = true; 143 break; 144 default: 145 pr_err("switch case %#x not processed\n", 146 rtlpci->const_support_pciaspm); 147 break; 148 } 149 150 /* toshiba aspm issue, toshiba will set aspm selfly 151 * so we should not set aspm in driver 152 */ 153 pcie_capability_read_word(rtlpci->pdev, PCI_EXP_LNKCTL, &init_aspm); 154 if (rtlpriv->rtlhal.hw_type == HARDWARE_TYPE_RTL8192SE && 155 ((u8)init_aspm) == (PCI_EXP_LNKCTL_ASPM_L0S | 156 PCI_EXP_LNKCTL_ASPM_L1 | PCI_EXP_LNKCTL_CCC)) 157 ppsc->support_aspm = false; 158 159 /* RTL8723BE found on some ASUSTek laptops, such as F441U and 160 * X555UQ with subsystem ID 11ad:1723 are known to output large 161 * amounts of PCIe AER errors during and after boot up, causing 162 * heavy lags, poor network throughput, and occasional lock-ups. 163 */ 164 if (rtlpriv->rtlhal.hw_type == HARDWARE_TYPE_RTL8723BE && 165 (rtlpci->pdev->subsystem_vendor == 0x11ad && 166 rtlpci->pdev->subsystem_device == 0x1723)) 167 ppsc->support_aspm = false; 168 } 169 170 static bool _rtl_pci_platform_switch_device_pci_aspm( 171 struct ieee80211_hw *hw, 172 u8 value) 173 { 174 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 175 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 176 177 value &= PCI_EXP_LNKCTL_ASPMC; 178 179 if (rtlhal->hw_type != HARDWARE_TYPE_RTL8192SE) 180 value |= PCI_EXP_LNKCTL_CCC; 181 182 pcie_capability_clear_and_set_word(rtlpci->pdev, PCI_EXP_LNKCTL, 183 PCI_EXP_LNKCTL_ASPMC | value, 184 value); 185 186 return false; 187 } 188 189 /* @value is PCI_EXP_LNKCTL_CLKREQ_EN or 0 to enable/disable clk request. */ 190 static void _rtl_pci_switch_clk_req(struct ieee80211_hw *hw, u16 value) 191 { 192 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 193 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 194 195 value &= PCI_EXP_LNKCTL_CLKREQ_EN; 196 197 pcie_capability_clear_and_set_word(rtlpci->pdev, PCI_EXP_LNKCTL, 198 PCI_EXP_LNKCTL_CLKREQ_EN, 199 value); 200 201 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) 202 udelay(100); 203 } 204 205 /*Disable RTL8192SE ASPM & Disable Pci Bridge ASPM*/ 206 static void rtl_pci_disable_aspm(struct ieee80211_hw *hw) 207 { 208 struct rtl_priv *rtlpriv = rtl_priv(hw); 209 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 210 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 211 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 212 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor; 213 /*Retrieve original configuration settings. */ 214 u8 linkctrl_reg = pcipriv->ndis_adapter.linkctrl_reg; 215 u16 aspmlevel = 0; 216 u16 tmp_u1b = 0; 217 218 if (!ppsc->support_aspm) 219 return; 220 221 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) { 222 rtl_dbg(rtlpriv, COMP_POWER, DBG_TRACE, 223 "PCI(Bridge) UNKNOWN\n"); 224 225 return; 226 } 227 228 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) { 229 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ); 230 _rtl_pci_switch_clk_req(hw, 0x0); 231 } 232 233 /*for promising device will in L0 state after an I/O. */ 234 pcie_capability_read_word(rtlpci->pdev, PCI_EXP_LNKCTL, &tmp_u1b); 235 236 /*Set corresponding value. */ 237 aspmlevel |= PCI_EXP_LNKCTL_ASPM_L0S | PCI_EXP_LNKCTL_ASPM_L1; 238 linkctrl_reg &= ~aspmlevel; 239 240 _rtl_pci_platform_switch_device_pci_aspm(hw, linkctrl_reg); 241 } 242 243 /*Enable RTL8192SE ASPM & Enable Pci Bridge ASPM for 244 *power saving We should follow the sequence to enable 245 *RTL8192SE first then enable Pci Bridge ASPM 246 *or the system will show bluescreen. 247 */ 248 static void rtl_pci_enable_aspm(struct ieee80211_hw *hw) 249 { 250 struct rtl_priv *rtlpriv = rtl_priv(hw); 251 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 252 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 253 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 254 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor; 255 u16 aspmlevel; 256 u8 u_device_aspmsetting; 257 258 if (!ppsc->support_aspm) 259 return; 260 261 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) { 262 rtl_dbg(rtlpriv, COMP_POWER, DBG_TRACE, 263 "PCI(Bridge) UNKNOWN\n"); 264 return; 265 } 266 267 /*Get ASPM level (with/without Clock Req) */ 268 aspmlevel = rtlpci->const_devicepci_aspm_setting; 269 u_device_aspmsetting = pcipriv->ndis_adapter.linkctrl_reg; 270 271 /*_rtl_pci_platform_switch_device_pci_aspm(dev,*/ 272 /*(priv->ndis_adapter.linkctrl_reg | ASPMLevel)); */ 273 274 u_device_aspmsetting |= aspmlevel; 275 276 _rtl_pci_platform_switch_device_pci_aspm(hw, u_device_aspmsetting); 277 278 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) { 279 _rtl_pci_switch_clk_req(hw, (ppsc->reg_rfps_level & 280 RT_RF_OFF_LEVL_CLK_REQ) ? 281 PCI_EXP_LNKCTL_CLKREQ_EN : 0); 282 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ); 283 } 284 udelay(100); 285 } 286 287 static bool rtl_pci_get_amd_l1_patch(struct ieee80211_hw *hw) 288 { 289 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 290 291 bool status = false; 292 u8 offset_e0; 293 unsigned int offset_e4; 294 295 pci_write_config_byte(rtlpci->pdev, 0xe0, 0xa0); 296 297 pci_read_config_byte(rtlpci->pdev, 0xe0, &offset_e0); 298 299 if (offset_e0 == 0xA0) { 300 pci_read_config_dword(rtlpci->pdev, 0xe4, &offset_e4); 301 if (offset_e4 & BIT(23)) 302 status = true; 303 } 304 305 return status; 306 } 307 308 static void rtl_pci_parse_configuration(struct pci_dev *pdev, 309 struct ieee80211_hw *hw) 310 { 311 struct rtl_priv *rtlpriv = rtl_priv(hw); 312 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 313 314 u8 tmp; 315 u16 linkctrl_reg; 316 317 /*Link Control Register */ 318 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &linkctrl_reg); 319 pcipriv->ndis_adapter.linkctrl_reg = (u8)linkctrl_reg; 320 321 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "Link Control Register =%x\n", 322 pcipriv->ndis_adapter.linkctrl_reg); 323 324 pcie_capability_set_word(pdev, PCI_EXP_DEVCTL2, 325 PCI_EXP_DEVCTL2_COMP_TMOUT_DIS); 326 327 tmp = 0x17; 328 pci_write_config_byte(pdev, 0x70f, tmp); 329 } 330 331 static void rtl_pci_init_aspm(struct ieee80211_hw *hw) 332 { 333 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 334 335 _rtl_pci_update_default_setting(hw); 336 337 if (ppsc->reg_rfps_level & RT_RF_PS_LEVEL_ALWAYS_ASPM) { 338 /*Always enable ASPM & Clock Req. */ 339 rtl_pci_enable_aspm(hw); 340 RT_SET_PS_LEVEL(ppsc, RT_RF_PS_LEVEL_ALWAYS_ASPM); 341 } 342 } 343 344 static void _rtl_pci_io_handler_init(struct device *dev, 345 struct ieee80211_hw *hw) 346 { 347 struct rtl_priv *rtlpriv = rtl_priv(hw); 348 349 rtlpriv->io.dev = dev; 350 351 rtlpriv->io.write8 = pci_write8_async; 352 rtlpriv->io.write16 = pci_write16_async; 353 rtlpriv->io.write32 = pci_write32_async; 354 355 rtlpriv->io.read8 = pci_read8_sync; 356 rtlpriv->io.read16 = pci_read16_sync; 357 rtlpriv->io.read32 = pci_read32_sync; 358 } 359 360 static bool _rtl_update_earlymode_info(struct ieee80211_hw *hw, 361 struct sk_buff *skb, 362 struct rtl_tcb_desc *tcb_desc, u8 tid) 363 { 364 struct rtl_priv *rtlpriv = rtl_priv(hw); 365 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 366 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 367 struct sk_buff *next_skb; 368 u8 additionlen = FCS_LEN; 369 370 /* here open is 4, wep/tkip is 8, aes is 12*/ 371 if (info->control.hw_key) 372 additionlen += info->control.hw_key->icv_len; 373 374 /* The most skb num is 6 */ 375 tcb_desc->empkt_num = 0; 376 spin_lock_bh(&rtlpriv->locks.waitq_lock); 377 skb_queue_walk(&rtlpriv->mac80211.skb_waitq[tid], next_skb) { 378 struct ieee80211_tx_info *next_info; 379 380 next_info = IEEE80211_SKB_CB(next_skb); 381 if (next_info->flags & IEEE80211_TX_CTL_AMPDU) { 382 tcb_desc->empkt_len[tcb_desc->empkt_num] = 383 next_skb->len + additionlen; 384 tcb_desc->empkt_num++; 385 } else { 386 break; 387 } 388 389 if (skb_queue_is_last(&rtlpriv->mac80211.skb_waitq[tid], 390 next_skb)) 391 break; 392 393 if (tcb_desc->empkt_num >= rtlhal->max_earlymode_num) 394 break; 395 } 396 spin_unlock_bh(&rtlpriv->locks.waitq_lock); 397 398 return true; 399 } 400 401 /* just for early mode now */ 402 static void _rtl_pci_tx_chk_waitq(struct ieee80211_hw *hw) 403 { 404 struct rtl_priv *rtlpriv = rtl_priv(hw); 405 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 406 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 407 struct sk_buff *skb = NULL; 408 struct ieee80211_tx_info *info = NULL; 409 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 410 int tid; 411 412 if (!rtlpriv->rtlhal.earlymode_enable) 413 return; 414 415 /* we just use em for BE/BK/VI/VO */ 416 for (tid = 7; tid >= 0; tid--) { 417 u8 hw_queue = ac_to_hwq[rtl_tid_to_ac(tid)]; 418 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue]; 419 420 while (!mac->act_scanning && 421 rtlpriv->psc.rfpwr_state == ERFON) { 422 struct rtl_tcb_desc tcb_desc; 423 424 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc)); 425 426 spin_lock(&rtlpriv->locks.waitq_lock); 427 if (!skb_queue_empty(&mac->skb_waitq[tid]) && 428 (ring->entries - skb_queue_len(&ring->queue) > 429 rtlhal->max_earlymode_num)) { 430 skb = skb_dequeue(&mac->skb_waitq[tid]); 431 } else { 432 spin_unlock(&rtlpriv->locks.waitq_lock); 433 break; 434 } 435 spin_unlock(&rtlpriv->locks.waitq_lock); 436 437 /* Some macaddr can't do early mode. like 438 * multicast/broadcast/no_qos data 439 */ 440 info = IEEE80211_SKB_CB(skb); 441 if (info->flags & IEEE80211_TX_CTL_AMPDU) 442 _rtl_update_earlymode_info(hw, skb, 443 &tcb_desc, tid); 444 445 rtlpriv->intf_ops->adapter_tx(hw, NULL, skb, &tcb_desc); 446 } 447 } 448 } 449 450 static void _rtl_pci_tx_isr(struct ieee80211_hw *hw, int prio) 451 { 452 struct rtl_priv *rtlpriv = rtl_priv(hw); 453 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 454 455 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio]; 456 457 while (skb_queue_len(&ring->queue)) { 458 struct sk_buff *skb; 459 struct ieee80211_tx_info *info; 460 __le16 fc; 461 u8 tid; 462 u8 *entry; 463 464 if (rtlpriv->use_new_trx_flow) 465 entry = (u8 *)(&ring->buffer_desc[ring->idx]); 466 else 467 entry = (u8 *)(&ring->desc[ring->idx]); 468 469 if (!rtlpriv->cfg->ops->is_tx_desc_closed(hw, prio, ring->idx)) 470 return; 471 ring->idx = (ring->idx + 1) % ring->entries; 472 473 skb = __skb_dequeue(&ring->queue); 474 dma_unmap_single(&rtlpci->pdev->dev, 475 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry, 476 true, HW_DESC_TXBUFF_ADDR), 477 skb->len, DMA_TO_DEVICE); 478 479 /* remove early mode header */ 480 if (rtlpriv->rtlhal.earlymode_enable) 481 skb_pull(skb, EM_HDR_LEN); 482 483 rtl_dbg(rtlpriv, (COMP_INTR | COMP_SEND), DBG_TRACE, 484 "new ring->idx:%d, free: skb_queue_len:%d, free: seq:%x\n", 485 ring->idx, 486 skb_queue_len(&ring->queue), 487 *(u16 *)(skb->data + 22)); 488 489 if (prio == TXCMD_QUEUE) { 490 dev_kfree_skb(skb); 491 goto tx_status_ok; 492 } 493 494 /* for sw LPS, just after NULL skb send out, we can 495 * sure AP knows we are sleeping, we should not let 496 * rf sleep 497 */ 498 fc = rtl_get_fc(skb); 499 if (ieee80211_is_nullfunc(fc)) { 500 if (ieee80211_has_pm(fc)) { 501 rtlpriv->mac80211.offchan_delay = true; 502 rtlpriv->psc.state_inap = true; 503 } else { 504 rtlpriv->psc.state_inap = false; 505 } 506 } 507 if (ieee80211_is_action(fc)) { 508 struct ieee80211_mgmt *action_frame = 509 (struct ieee80211_mgmt *)skb->data; 510 if (action_frame->u.action.u.ht_smps.action == 511 WLAN_HT_ACTION_SMPS) { 512 dev_kfree_skb(skb); 513 goto tx_status_ok; 514 } 515 } 516 517 /* update tid tx pkt num */ 518 tid = rtl_get_tid(skb); 519 if (tid <= 7) 520 rtlpriv->link_info.tidtx_inperiod[tid]++; 521 522 info = IEEE80211_SKB_CB(skb); 523 524 if (likely(!ieee80211_is_nullfunc(fc))) { 525 ieee80211_tx_info_clear_status(info); 526 info->flags |= IEEE80211_TX_STAT_ACK; 527 /*info->status.rates[0].count = 1; */ 528 ieee80211_tx_status_irqsafe(hw, skb); 529 } else { 530 rtl_tx_ackqueue(hw, skb); 531 } 532 533 if ((ring->entries - skb_queue_len(&ring->queue)) <= 4) { 534 rtl_dbg(rtlpriv, COMP_ERR, DBG_DMESG, 535 "more desc left, wake skb_queue@%d, ring->idx = %d, skb_queue_len = 0x%x\n", 536 prio, ring->idx, 537 skb_queue_len(&ring->queue)); 538 539 ieee80211_wake_queue(hw, skb_get_queue_mapping(skb)); 540 } 541 tx_status_ok: 542 skb = NULL; 543 } 544 545 if (((rtlpriv->link_info.num_rx_inperiod + 546 rtlpriv->link_info.num_tx_inperiod) > 8) || 547 rtlpriv->link_info.num_rx_inperiod > 2) 548 rtl_lps_leave(hw, false); 549 } 550 551 static int _rtl_pci_init_one_rxdesc(struct ieee80211_hw *hw, 552 struct sk_buff *new_skb, u8 *entry, 553 int rxring_idx, int desc_idx) 554 { 555 struct rtl_priv *rtlpriv = rtl_priv(hw); 556 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 557 u32 bufferaddress; 558 u8 tmp_one = 1; 559 struct sk_buff *skb; 560 561 if (likely(new_skb)) { 562 skb = new_skb; 563 goto remap; 564 } 565 skb = dev_alloc_skb(rtlpci->rxbuffersize); 566 if (!skb) 567 return 0; 568 569 remap: 570 /* just set skb->cb to mapping addr for pci_unmap_single use */ 571 *((dma_addr_t *)skb->cb) = 572 dma_map_single(&rtlpci->pdev->dev, skb_tail_pointer(skb), 573 rtlpci->rxbuffersize, DMA_FROM_DEVICE); 574 bufferaddress = *((dma_addr_t *)skb->cb); 575 if (dma_mapping_error(&rtlpci->pdev->dev, bufferaddress)) 576 return 0; 577 rtlpci->rx_ring[rxring_idx].rx_buf[desc_idx] = skb; 578 if (rtlpriv->use_new_trx_flow) { 579 /* skb->cb may be 64 bit address */ 580 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, 581 HW_DESC_RX_PREPARE, 582 (u8 *)(dma_addr_t *)skb->cb); 583 } else { 584 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, 585 HW_DESC_RXBUFF_ADDR, 586 (u8 *)&bufferaddress); 587 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, 588 HW_DESC_RXPKT_LEN, 589 (u8 *)&rtlpci->rxbuffersize); 590 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, 591 HW_DESC_RXOWN, 592 (u8 *)&tmp_one); 593 } 594 return 1; 595 } 596 597 /* inorder to receive 8K AMSDU we have set skb to 598 * 9100bytes in init rx ring, but if this packet is 599 * not a AMSDU, this large packet will be sent to 600 * TCP/IP directly, this cause big packet ping fail 601 * like: "ping -s 65507", so here we will realloc skb 602 * based on the true size of packet, Mac80211 603 * Probably will do it better, but does not yet. 604 * 605 * Some platform will fail when alloc skb sometimes. 606 * in this condition, we will send the old skb to 607 * mac80211 directly, this will not cause any other 608 * issues, but only this packet will be lost by TCP/IP 609 */ 610 static void _rtl_pci_rx_to_mac80211(struct ieee80211_hw *hw, 611 struct sk_buff *skb, 612 struct ieee80211_rx_status rx_status) 613 { 614 if (unlikely(!rtl_action_proc(hw, skb, false))) { 615 dev_kfree_skb_any(skb); 616 } else { 617 struct sk_buff *uskb = NULL; 618 619 uskb = dev_alloc_skb(skb->len + 128); 620 if (likely(uskb)) { 621 memcpy(IEEE80211_SKB_RXCB(uskb), &rx_status, 622 sizeof(rx_status)); 623 skb_put_data(uskb, skb->data, skb->len); 624 dev_kfree_skb_any(skb); 625 ieee80211_rx_irqsafe(hw, uskb); 626 } else { 627 ieee80211_rx_irqsafe(hw, skb); 628 } 629 } 630 } 631 632 /*hsisr interrupt handler*/ 633 static void _rtl_pci_hs_interrupt(struct ieee80211_hw *hw) 634 { 635 struct rtl_priv *rtlpriv = rtl_priv(hw); 636 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 637 638 rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[MAC_HSISR], 639 rtl_read_byte(rtlpriv, rtlpriv->cfg->maps[MAC_HSISR]) | 640 rtlpci->sys_irq_mask); 641 } 642 643 static void _rtl_pci_rx_interrupt(struct ieee80211_hw *hw) 644 { 645 struct rtl_priv *rtlpriv = rtl_priv(hw); 646 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 647 int rxring_idx = RTL_PCI_RX_MPDU_QUEUE; 648 struct ieee80211_rx_status rx_status = { 0 }; 649 unsigned int count = rtlpci->rxringcount; 650 u8 own; 651 u8 tmp_one; 652 bool unicast = false; 653 u8 hw_queue = 0; 654 unsigned int rx_remained_cnt = 0; 655 struct rtl_stats stats = { 656 .signal = 0, 657 .rate = 0, 658 }; 659 660 /*RX NORMAL PKT */ 661 while (count--) { 662 struct ieee80211_hdr *hdr; 663 __le16 fc; 664 u16 len; 665 /*rx buffer descriptor */ 666 struct rtl_rx_buffer_desc *buffer_desc = NULL; 667 /*if use new trx flow, it means wifi info */ 668 struct rtl_rx_desc *pdesc = NULL; 669 /*rx pkt */ 670 struct sk_buff *skb = rtlpci->rx_ring[rxring_idx].rx_buf[ 671 rtlpci->rx_ring[rxring_idx].idx]; 672 struct sk_buff *new_skb; 673 674 if (rtlpriv->use_new_trx_flow) { 675 if (rx_remained_cnt == 0) 676 rx_remained_cnt = 677 rtlpriv->cfg->ops->rx_desc_buff_remained_cnt(hw, 678 hw_queue); 679 if (rx_remained_cnt == 0) 680 return; 681 buffer_desc = &rtlpci->rx_ring[rxring_idx].buffer_desc[ 682 rtlpci->rx_ring[rxring_idx].idx]; 683 pdesc = (struct rtl_rx_desc *)skb->data; 684 } else { /* rx descriptor */ 685 pdesc = &rtlpci->rx_ring[rxring_idx].desc[ 686 rtlpci->rx_ring[rxring_idx].idx]; 687 688 own = (u8)rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc, 689 false, 690 HW_DESC_OWN); 691 if (own) /* wait data to be filled by hardware */ 692 return; 693 } 694 695 /* Reaching this point means: data is filled already 696 * AAAAAAttention !!! 697 * We can NOT access 'skb' before 'pci_unmap_single' 698 */ 699 dma_unmap_single(&rtlpci->pdev->dev, *((dma_addr_t *)skb->cb), 700 rtlpci->rxbuffersize, DMA_FROM_DEVICE); 701 702 /* get a new skb - if fail, old one will be reused */ 703 new_skb = dev_alloc_skb(rtlpci->rxbuffersize); 704 if (unlikely(!new_skb)) 705 goto no_new; 706 memset(&rx_status, 0, sizeof(rx_status)); 707 rtlpriv->cfg->ops->query_rx_desc(hw, &stats, 708 &rx_status, (u8 *)pdesc, skb); 709 710 if (rtlpriv->use_new_trx_flow) 711 rtlpriv->cfg->ops->rx_check_dma_ok(hw, 712 (u8 *)buffer_desc, 713 hw_queue); 714 715 len = rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc, false, 716 HW_DESC_RXPKT_LEN); 717 718 if (skb->end - skb->tail > len) { 719 skb_put(skb, len); 720 if (rtlpriv->use_new_trx_flow) 721 skb_reserve(skb, stats.rx_drvinfo_size + 722 stats.rx_bufshift + 24); 723 else 724 skb_reserve(skb, stats.rx_drvinfo_size + 725 stats.rx_bufshift); 726 } else { 727 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, 728 "skb->end - skb->tail = %d, len is %d\n", 729 skb->end - skb->tail, len); 730 dev_kfree_skb_any(skb); 731 goto new_trx_end; 732 } 733 /* handle command packet here */ 734 if (stats.packet_report_type == C2H_PACKET) { 735 rtl_c2hcmd_enqueue(hw, skb); 736 goto new_trx_end; 737 } 738 739 /* NOTICE This can not be use for mac80211, 740 * this is done in mac80211 code, 741 * if done here sec DHCP will fail 742 * skb_trim(skb, skb->len - 4); 743 */ 744 745 hdr = rtl_get_hdr(skb); 746 fc = rtl_get_fc(skb); 747 748 if (!stats.crc && !stats.hwerror && (skb->len > FCS_LEN)) { 749 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, 750 sizeof(rx_status)); 751 752 if (is_broadcast_ether_addr(hdr->addr1)) { 753 ;/*TODO*/ 754 } else if (is_multicast_ether_addr(hdr->addr1)) { 755 ;/*TODO*/ 756 } else { 757 unicast = true; 758 rtlpriv->stats.rxbytesunicast += skb->len; 759 } 760 rtl_is_special_data(hw, skb, false, true); 761 762 if (ieee80211_is_data(fc)) { 763 rtlpriv->cfg->ops->led_control(hw, LED_CTL_RX); 764 if (unicast) 765 rtlpriv->link_info.num_rx_inperiod++; 766 } 767 768 rtl_collect_scan_list(hw, skb); 769 770 /* static bcn for roaming */ 771 rtl_beacon_statistic(hw, skb); 772 rtl_p2p_info(hw, (void *)skb->data, skb->len); 773 /* for sw lps */ 774 rtl_swlps_beacon(hw, (void *)skb->data, skb->len); 775 rtl_recognize_peer(hw, (void *)skb->data, skb->len); 776 if (rtlpriv->mac80211.opmode == NL80211_IFTYPE_AP && 777 rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G && 778 (ieee80211_is_beacon(fc) || 779 ieee80211_is_probe_resp(fc))) { 780 dev_kfree_skb_any(skb); 781 } else { 782 _rtl_pci_rx_to_mac80211(hw, skb, rx_status); 783 } 784 } else { 785 /* drop packets with errors or those too short */ 786 dev_kfree_skb_any(skb); 787 } 788 new_trx_end: 789 if (rtlpriv->use_new_trx_flow) { 790 rtlpci->rx_ring[hw_queue].next_rx_rp += 1; 791 rtlpci->rx_ring[hw_queue].next_rx_rp %= 792 RTL_PCI_MAX_RX_COUNT; 793 794 rx_remained_cnt--; 795 rtl_write_word(rtlpriv, 0x3B4, 796 rtlpci->rx_ring[hw_queue].next_rx_rp); 797 } 798 if (((rtlpriv->link_info.num_rx_inperiod + 799 rtlpriv->link_info.num_tx_inperiod) > 8) || 800 rtlpriv->link_info.num_rx_inperiod > 2) 801 rtl_lps_leave(hw, false); 802 skb = new_skb; 803 no_new: 804 if (rtlpriv->use_new_trx_flow) { 805 _rtl_pci_init_one_rxdesc(hw, skb, (u8 *)buffer_desc, 806 rxring_idx, 807 rtlpci->rx_ring[rxring_idx].idx); 808 } else { 809 _rtl_pci_init_one_rxdesc(hw, skb, (u8 *)pdesc, 810 rxring_idx, 811 rtlpci->rx_ring[rxring_idx].idx); 812 if (rtlpci->rx_ring[rxring_idx].idx == 813 rtlpci->rxringcount - 1) 814 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, 815 false, 816 HW_DESC_RXERO, 817 (u8 *)&tmp_one); 818 } 819 rtlpci->rx_ring[rxring_idx].idx = 820 (rtlpci->rx_ring[rxring_idx].idx + 1) % 821 rtlpci->rxringcount; 822 } 823 } 824 825 static irqreturn_t _rtl_pci_interrupt(int irq, void *dev_id) 826 { 827 struct ieee80211_hw *hw = dev_id; 828 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 829 struct rtl_priv *rtlpriv = rtl_priv(hw); 830 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 831 unsigned long flags; 832 struct rtl_int intvec = {0}; 833 834 irqreturn_t ret = IRQ_HANDLED; 835 836 if (rtlpci->irq_enabled == 0) 837 return ret; 838 839 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags); 840 rtlpriv->cfg->ops->disable_interrupt(hw); 841 842 /*read ISR: 4/8bytes */ 843 rtlpriv->cfg->ops->interrupt_recognized(hw, &intvec); 844 845 /*Shared IRQ or HW disappeared */ 846 if (!intvec.inta || intvec.inta == 0xffff) 847 goto done; 848 849 /*<1> beacon related */ 850 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_TBDOK]) 851 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, 852 "beacon ok interrupt!\n"); 853 854 if (unlikely(intvec.inta & rtlpriv->cfg->maps[RTL_IMR_TBDER])) 855 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, 856 "beacon err interrupt!\n"); 857 858 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BDOK]) 859 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, "beacon interrupt!\n"); 860 861 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BCNINT]) { 862 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, 863 "prepare beacon for interrupt!\n"); 864 tasklet_schedule(&rtlpriv->works.irq_prepare_bcn_tasklet); 865 } 866 867 /*<2> Tx related */ 868 if (unlikely(intvec.intb & rtlpriv->cfg->maps[RTL_IMR_TXFOVW])) 869 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, "IMR_TXFOVW!\n"); 870 871 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_MGNTDOK]) { 872 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, 873 "Manage ok interrupt!\n"); 874 _rtl_pci_tx_isr(hw, MGNT_QUEUE); 875 } 876 877 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_HIGHDOK]) { 878 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, 879 "HIGH_QUEUE ok interrupt!\n"); 880 _rtl_pci_tx_isr(hw, HIGH_QUEUE); 881 } 882 883 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BKDOK]) { 884 rtlpriv->link_info.num_tx_inperiod++; 885 886 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, 887 "BK Tx OK interrupt!\n"); 888 _rtl_pci_tx_isr(hw, BK_QUEUE); 889 } 890 891 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BEDOK]) { 892 rtlpriv->link_info.num_tx_inperiod++; 893 894 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, 895 "BE TX OK interrupt!\n"); 896 _rtl_pci_tx_isr(hw, BE_QUEUE); 897 } 898 899 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_VIDOK]) { 900 rtlpriv->link_info.num_tx_inperiod++; 901 902 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, 903 "VI TX OK interrupt!\n"); 904 _rtl_pci_tx_isr(hw, VI_QUEUE); 905 } 906 907 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_VODOK]) { 908 rtlpriv->link_info.num_tx_inperiod++; 909 910 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, 911 "Vo TX OK interrupt!\n"); 912 _rtl_pci_tx_isr(hw, VO_QUEUE); 913 } 914 915 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8822BE) { 916 if (intvec.intd & rtlpriv->cfg->maps[RTL_IMR_H2CDOK]) { 917 rtlpriv->link_info.num_tx_inperiod++; 918 919 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, 920 "H2C TX OK interrupt!\n"); 921 _rtl_pci_tx_isr(hw, H2C_QUEUE); 922 } 923 } 924 925 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) { 926 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_COMDOK]) { 927 rtlpriv->link_info.num_tx_inperiod++; 928 929 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, 930 "CMD TX OK interrupt!\n"); 931 _rtl_pci_tx_isr(hw, TXCMD_QUEUE); 932 } 933 } 934 935 /*<3> Rx related */ 936 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_ROK]) { 937 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, "Rx ok interrupt!\n"); 938 _rtl_pci_rx_interrupt(hw); 939 } 940 941 if (unlikely(intvec.inta & rtlpriv->cfg->maps[RTL_IMR_RDU])) { 942 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, 943 "rx descriptor unavailable!\n"); 944 _rtl_pci_rx_interrupt(hw); 945 } 946 947 if (unlikely(intvec.intb & rtlpriv->cfg->maps[RTL_IMR_RXFOVW])) { 948 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, "rx overflow !\n"); 949 _rtl_pci_rx_interrupt(hw); 950 } 951 952 /*<4> fw related*/ 953 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8723AE) { 954 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_C2HCMD]) { 955 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, 956 "firmware interrupt!\n"); 957 queue_delayed_work(rtlpriv->works.rtl_wq, 958 &rtlpriv->works.fwevt_wq, 0); 959 } 960 } 961 962 /*<5> hsisr related*/ 963 /* Only 8188EE & 8723BE Supported. 964 * If Other ICs Come in, System will corrupt, 965 * because maps[RTL_IMR_HSISR_IND] & maps[MAC_HSISR] 966 * are not initialized 967 */ 968 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8188EE || 969 rtlhal->hw_type == HARDWARE_TYPE_RTL8723BE) { 970 if (unlikely(intvec.inta & 971 rtlpriv->cfg->maps[RTL_IMR_HSISR_IND])) { 972 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, 973 "hsisr interrupt!\n"); 974 _rtl_pci_hs_interrupt(hw); 975 } 976 } 977 978 if (rtlpriv->rtlhal.earlymode_enable) 979 tasklet_schedule(&rtlpriv->works.irq_tasklet); 980 981 done: 982 rtlpriv->cfg->ops->enable_interrupt(hw); 983 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags); 984 return ret; 985 } 986 987 static void _rtl_pci_irq_tasklet(struct tasklet_struct *t) 988 { 989 struct rtl_priv *rtlpriv = from_tasklet(rtlpriv, t, works.irq_tasklet); 990 struct ieee80211_hw *hw = rtlpriv->hw; 991 _rtl_pci_tx_chk_waitq(hw); 992 } 993 994 static void _rtl_pci_prepare_bcn_tasklet(struct tasklet_struct *t) 995 { 996 struct rtl_priv *rtlpriv = from_tasklet(rtlpriv, t, 997 works.irq_prepare_bcn_tasklet); 998 struct ieee80211_hw *hw = rtlpriv->hw; 999 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1000 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1001 struct rtl8192_tx_ring *ring = NULL; 1002 struct ieee80211_hdr *hdr = NULL; 1003 struct ieee80211_tx_info *info = NULL; 1004 struct sk_buff *pskb = NULL; 1005 struct rtl_tx_desc *pdesc = NULL; 1006 struct rtl_tcb_desc tcb_desc; 1007 /*This is for new trx flow*/ 1008 struct rtl_tx_buffer_desc *pbuffer_desc = NULL; 1009 u8 temp_one = 1; 1010 u8 *entry; 1011 1012 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc)); 1013 ring = &rtlpci->tx_ring[BEACON_QUEUE]; 1014 pskb = __skb_dequeue(&ring->queue); 1015 if (rtlpriv->use_new_trx_flow) 1016 entry = (u8 *)(&ring->buffer_desc[ring->idx]); 1017 else 1018 entry = (u8 *)(&ring->desc[ring->idx]); 1019 if (pskb) { 1020 dma_unmap_single(&rtlpci->pdev->dev, 1021 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry, 1022 true, HW_DESC_TXBUFF_ADDR), 1023 pskb->len, DMA_TO_DEVICE); 1024 kfree_skb(pskb); 1025 } 1026 1027 /*NB: the beacon data buffer must be 32-bit aligned. */ 1028 pskb = ieee80211_beacon_get(hw, mac->vif, 0); 1029 if (!pskb) 1030 return; 1031 hdr = rtl_get_hdr(pskb); 1032 info = IEEE80211_SKB_CB(pskb); 1033 pdesc = &ring->desc[0]; 1034 if (rtlpriv->use_new_trx_flow) 1035 pbuffer_desc = &ring->buffer_desc[0]; 1036 1037 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc, 1038 (u8 *)pbuffer_desc, info, NULL, pskb, 1039 BEACON_QUEUE, &tcb_desc); 1040 1041 __skb_queue_tail(&ring->queue, pskb); 1042 1043 if (rtlpriv->use_new_trx_flow) { 1044 temp_one = 4; 1045 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pbuffer_desc, true, 1046 HW_DESC_OWN, (u8 *)&temp_one); 1047 } else { 1048 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true, HW_DESC_OWN, 1049 &temp_one); 1050 } 1051 } 1052 1053 static void _rtl_pci_init_trx_var(struct ieee80211_hw *hw) 1054 { 1055 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1056 struct rtl_priv *rtlpriv = rtl_priv(hw); 1057 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 1058 u8 i; 1059 u16 desc_num; 1060 1061 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192EE) 1062 desc_num = TX_DESC_NUM_92E; 1063 else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8822BE) 1064 desc_num = TX_DESC_NUM_8822B; 1065 else 1066 desc_num = RT_TXDESC_NUM; 1067 1068 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) 1069 rtlpci->txringcount[i] = desc_num; 1070 1071 /*we just alloc 2 desc for beacon queue, 1072 *because we just need first desc in hw beacon. 1073 */ 1074 rtlpci->txringcount[BEACON_QUEUE] = 2; 1075 1076 /*BE queue need more descriptor for performance 1077 *consideration or, No more tx desc will happen, 1078 *and may cause mac80211 mem leakage. 1079 */ 1080 if (!rtl_priv(hw)->use_new_trx_flow) 1081 rtlpci->txringcount[BE_QUEUE] = RT_TXDESC_NUM_BE_QUEUE; 1082 1083 rtlpci->rxbuffersize = 9100; /*2048/1024; */ 1084 rtlpci->rxringcount = RTL_PCI_MAX_RX_COUNT; /*64; */ 1085 } 1086 1087 static void _rtl_pci_init_struct(struct ieee80211_hw *hw, 1088 struct pci_dev *pdev) 1089 { 1090 struct rtl_priv *rtlpriv = rtl_priv(hw); 1091 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1092 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1093 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1094 1095 rtlpci->up_first_time = true; 1096 rtlpci->being_init_adapter = false; 1097 1098 rtlhal->hw = hw; 1099 rtlpci->pdev = pdev; 1100 1101 /*Tx/Rx related var */ 1102 _rtl_pci_init_trx_var(hw); 1103 1104 /*IBSS*/ 1105 mac->beacon_interval = 100; 1106 1107 /*AMPDU*/ 1108 mac->min_space_cfg = 0; 1109 mac->max_mss_density = 0; 1110 /*set sane AMPDU defaults */ 1111 mac->current_ampdu_density = 7; 1112 mac->current_ampdu_factor = 3; 1113 1114 /*Retry Limit*/ 1115 mac->retry_short = 7; 1116 mac->retry_long = 7; 1117 1118 /*QOS*/ 1119 rtlpci->acm_method = EACMWAY2_SW; 1120 1121 /*task */ 1122 tasklet_setup(&rtlpriv->works.irq_tasklet, _rtl_pci_irq_tasklet); 1123 tasklet_setup(&rtlpriv->works.irq_prepare_bcn_tasklet, 1124 _rtl_pci_prepare_bcn_tasklet); 1125 INIT_WORK(&rtlpriv->works.lps_change_work, 1126 rtl_lps_change_work_callback); 1127 } 1128 1129 static int _rtl_pci_init_tx_ring(struct ieee80211_hw *hw, 1130 unsigned int prio, unsigned int entries) 1131 { 1132 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1133 struct rtl_priv *rtlpriv = rtl_priv(hw); 1134 struct rtl_tx_buffer_desc *buffer_desc; 1135 struct rtl_tx_desc *desc; 1136 dma_addr_t buffer_desc_dma, desc_dma; 1137 u32 nextdescaddress; 1138 int i; 1139 1140 /* alloc tx buffer desc for new trx flow*/ 1141 if (rtlpriv->use_new_trx_flow) { 1142 buffer_desc = 1143 dma_alloc_coherent(&rtlpci->pdev->dev, 1144 sizeof(*buffer_desc) * entries, 1145 &buffer_desc_dma, GFP_KERNEL); 1146 1147 if (!buffer_desc || (unsigned long)buffer_desc & 0xFF) { 1148 pr_err("Cannot allocate TX ring (prio = %d)\n", 1149 prio); 1150 return -ENOMEM; 1151 } 1152 1153 rtlpci->tx_ring[prio].buffer_desc = buffer_desc; 1154 rtlpci->tx_ring[prio].buffer_desc_dma = buffer_desc_dma; 1155 1156 rtlpci->tx_ring[prio].cur_tx_rp = 0; 1157 rtlpci->tx_ring[prio].cur_tx_wp = 0; 1158 } 1159 1160 /* alloc dma for this ring */ 1161 desc = dma_alloc_coherent(&rtlpci->pdev->dev, sizeof(*desc) * entries, 1162 &desc_dma, GFP_KERNEL); 1163 1164 if (!desc || (unsigned long)desc & 0xFF) { 1165 pr_err("Cannot allocate TX ring (prio = %d)\n", prio); 1166 return -ENOMEM; 1167 } 1168 1169 rtlpci->tx_ring[prio].desc = desc; 1170 rtlpci->tx_ring[prio].dma = desc_dma; 1171 1172 rtlpci->tx_ring[prio].idx = 0; 1173 rtlpci->tx_ring[prio].entries = entries; 1174 skb_queue_head_init(&rtlpci->tx_ring[prio].queue); 1175 1176 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "queue:%d, ring_addr:%p\n", 1177 prio, desc); 1178 1179 /* init every desc in this ring */ 1180 if (!rtlpriv->use_new_trx_flow) { 1181 for (i = 0; i < entries; i++) { 1182 nextdescaddress = (u32)desc_dma + 1183 ((i + 1) % entries) * 1184 sizeof(*desc); 1185 1186 rtlpriv->cfg->ops->set_desc(hw, (u8 *)&desc[i], 1187 true, 1188 HW_DESC_TX_NEXTDESC_ADDR, 1189 (u8 *)&nextdescaddress); 1190 } 1191 } 1192 return 0; 1193 } 1194 1195 static int _rtl_pci_init_rx_ring(struct ieee80211_hw *hw, int rxring_idx) 1196 { 1197 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1198 struct rtl_priv *rtlpriv = rtl_priv(hw); 1199 int i; 1200 1201 if (rtlpriv->use_new_trx_flow) { 1202 struct rtl_rx_buffer_desc *entry = NULL; 1203 /* alloc dma for this ring */ 1204 rtlpci->rx_ring[rxring_idx].buffer_desc = 1205 dma_alloc_coherent(&rtlpci->pdev->dev, 1206 sizeof(*rtlpci->rx_ring[rxring_idx].buffer_desc) * 1207 rtlpci->rxringcount, 1208 &rtlpci->rx_ring[rxring_idx].dma, GFP_KERNEL); 1209 if (!rtlpci->rx_ring[rxring_idx].buffer_desc || 1210 (ulong)rtlpci->rx_ring[rxring_idx].buffer_desc & 0xFF) { 1211 pr_err("Cannot allocate RX ring\n"); 1212 return -ENOMEM; 1213 } 1214 1215 /* init every desc in this ring */ 1216 rtlpci->rx_ring[rxring_idx].idx = 0; 1217 for (i = 0; i < rtlpci->rxringcount; i++) { 1218 entry = &rtlpci->rx_ring[rxring_idx].buffer_desc[i]; 1219 if (!_rtl_pci_init_one_rxdesc(hw, NULL, (u8 *)entry, 1220 rxring_idx, i)) 1221 return -ENOMEM; 1222 } 1223 } else { 1224 struct rtl_rx_desc *entry = NULL; 1225 u8 tmp_one = 1; 1226 /* alloc dma for this ring */ 1227 rtlpci->rx_ring[rxring_idx].desc = 1228 dma_alloc_coherent(&rtlpci->pdev->dev, 1229 sizeof(*rtlpci->rx_ring[rxring_idx].desc) * 1230 rtlpci->rxringcount, 1231 &rtlpci->rx_ring[rxring_idx].dma, GFP_KERNEL); 1232 if (!rtlpci->rx_ring[rxring_idx].desc || 1233 (unsigned long)rtlpci->rx_ring[rxring_idx].desc & 0xFF) { 1234 pr_err("Cannot allocate RX ring\n"); 1235 return -ENOMEM; 1236 } 1237 1238 /* init every desc in this ring */ 1239 rtlpci->rx_ring[rxring_idx].idx = 0; 1240 1241 for (i = 0; i < rtlpci->rxringcount; i++) { 1242 entry = &rtlpci->rx_ring[rxring_idx].desc[i]; 1243 if (!_rtl_pci_init_one_rxdesc(hw, NULL, (u8 *)entry, 1244 rxring_idx, i)) 1245 return -ENOMEM; 1246 } 1247 1248 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, 1249 HW_DESC_RXERO, &tmp_one); 1250 } 1251 return 0; 1252 } 1253 1254 static void _rtl_pci_free_tx_ring(struct ieee80211_hw *hw, 1255 unsigned int prio) 1256 { 1257 struct rtl_priv *rtlpriv = rtl_priv(hw); 1258 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1259 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio]; 1260 1261 /* free every desc in this ring */ 1262 while (skb_queue_len(&ring->queue)) { 1263 u8 *entry; 1264 struct sk_buff *skb = __skb_dequeue(&ring->queue); 1265 1266 if (rtlpriv->use_new_trx_flow) 1267 entry = (u8 *)(&ring->buffer_desc[ring->idx]); 1268 else 1269 entry = (u8 *)(&ring->desc[ring->idx]); 1270 1271 dma_unmap_single(&rtlpci->pdev->dev, 1272 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry, 1273 true, HW_DESC_TXBUFF_ADDR), 1274 skb->len, DMA_TO_DEVICE); 1275 kfree_skb(skb); 1276 ring->idx = (ring->idx + 1) % ring->entries; 1277 } 1278 1279 /* free dma of this ring */ 1280 dma_free_coherent(&rtlpci->pdev->dev, 1281 sizeof(*ring->desc) * ring->entries, ring->desc, 1282 ring->dma); 1283 ring->desc = NULL; 1284 if (rtlpriv->use_new_trx_flow) { 1285 dma_free_coherent(&rtlpci->pdev->dev, 1286 sizeof(*ring->buffer_desc) * ring->entries, 1287 ring->buffer_desc, ring->buffer_desc_dma); 1288 ring->buffer_desc = NULL; 1289 } 1290 } 1291 1292 static void _rtl_pci_free_rx_ring(struct ieee80211_hw *hw, int rxring_idx) 1293 { 1294 struct rtl_priv *rtlpriv = rtl_priv(hw); 1295 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1296 int i; 1297 1298 /* free every desc in this ring */ 1299 for (i = 0; i < rtlpci->rxringcount; i++) { 1300 struct sk_buff *skb = rtlpci->rx_ring[rxring_idx].rx_buf[i]; 1301 1302 if (!skb) 1303 continue; 1304 dma_unmap_single(&rtlpci->pdev->dev, *((dma_addr_t *)skb->cb), 1305 rtlpci->rxbuffersize, DMA_FROM_DEVICE); 1306 kfree_skb(skb); 1307 } 1308 1309 /* free dma of this ring */ 1310 if (rtlpriv->use_new_trx_flow) { 1311 dma_free_coherent(&rtlpci->pdev->dev, 1312 sizeof(*rtlpci->rx_ring[rxring_idx].buffer_desc) * 1313 rtlpci->rxringcount, 1314 rtlpci->rx_ring[rxring_idx].buffer_desc, 1315 rtlpci->rx_ring[rxring_idx].dma); 1316 rtlpci->rx_ring[rxring_idx].buffer_desc = NULL; 1317 } else { 1318 dma_free_coherent(&rtlpci->pdev->dev, 1319 sizeof(*rtlpci->rx_ring[rxring_idx].desc) * 1320 rtlpci->rxringcount, 1321 rtlpci->rx_ring[rxring_idx].desc, 1322 rtlpci->rx_ring[rxring_idx].dma); 1323 rtlpci->rx_ring[rxring_idx].desc = NULL; 1324 } 1325 } 1326 1327 static int _rtl_pci_init_trx_ring(struct ieee80211_hw *hw) 1328 { 1329 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1330 int ret; 1331 int i, rxring_idx; 1332 1333 /* rxring_idx 0:RX_MPDU_QUEUE 1334 * rxring_idx 1:RX_CMD_QUEUE 1335 */ 1336 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) { 1337 ret = _rtl_pci_init_rx_ring(hw, rxring_idx); 1338 if (ret) 1339 return ret; 1340 } 1341 1342 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) { 1343 ret = _rtl_pci_init_tx_ring(hw, i, rtlpci->txringcount[i]); 1344 if (ret) 1345 goto err_free_rings; 1346 } 1347 1348 return 0; 1349 1350 err_free_rings: 1351 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) 1352 _rtl_pci_free_rx_ring(hw, rxring_idx); 1353 1354 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) 1355 if (rtlpci->tx_ring[i].desc || 1356 rtlpci->tx_ring[i].buffer_desc) 1357 _rtl_pci_free_tx_ring(hw, i); 1358 1359 return 1; 1360 } 1361 1362 static int _rtl_pci_deinit_trx_ring(struct ieee80211_hw *hw) 1363 { 1364 u32 i, rxring_idx; 1365 1366 /*free rx rings */ 1367 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) 1368 _rtl_pci_free_rx_ring(hw, rxring_idx); 1369 1370 /*free tx rings */ 1371 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) 1372 _rtl_pci_free_tx_ring(hw, i); 1373 1374 return 0; 1375 } 1376 1377 int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw) 1378 { 1379 struct rtl_priv *rtlpriv = rtl_priv(hw); 1380 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1381 int i, rxring_idx; 1382 unsigned long flags; 1383 u8 tmp_one = 1; 1384 u32 bufferaddress; 1385 /* rxring_idx 0:RX_MPDU_QUEUE */ 1386 /* rxring_idx 1:RX_CMD_QUEUE */ 1387 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) { 1388 /* force the rx_ring[RX_MPDU_QUEUE/ 1389 * RX_CMD_QUEUE].idx to the first one 1390 *new trx flow, do nothing 1391 */ 1392 if (!rtlpriv->use_new_trx_flow && 1393 rtlpci->rx_ring[rxring_idx].desc) { 1394 struct rtl_rx_desc *entry = NULL; 1395 1396 rtlpci->rx_ring[rxring_idx].idx = 0; 1397 for (i = 0; i < rtlpci->rxringcount; i++) { 1398 entry = &rtlpci->rx_ring[rxring_idx].desc[i]; 1399 bufferaddress = 1400 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry, 1401 false, HW_DESC_RXBUFF_ADDR); 1402 memset((u8 *)entry, 0, 1403 sizeof(*rtlpci->rx_ring 1404 [rxring_idx].desc));/*clear one entry*/ 1405 if (rtlpriv->use_new_trx_flow) { 1406 rtlpriv->cfg->ops->set_desc(hw, 1407 (u8 *)entry, false, 1408 HW_DESC_RX_PREPARE, 1409 (u8 *)&bufferaddress); 1410 } else { 1411 rtlpriv->cfg->ops->set_desc(hw, 1412 (u8 *)entry, false, 1413 HW_DESC_RXBUFF_ADDR, 1414 (u8 *)&bufferaddress); 1415 rtlpriv->cfg->ops->set_desc(hw, 1416 (u8 *)entry, false, 1417 HW_DESC_RXPKT_LEN, 1418 (u8 *)&rtlpci->rxbuffersize); 1419 rtlpriv->cfg->ops->set_desc(hw, 1420 (u8 *)entry, false, 1421 HW_DESC_RXOWN, 1422 (u8 *)&tmp_one); 1423 } 1424 } 1425 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, 1426 HW_DESC_RXERO, (u8 *)&tmp_one); 1427 } 1428 rtlpci->rx_ring[rxring_idx].idx = 0; 1429 } 1430 1431 /*after reset, release previous pending packet, 1432 *and force the tx idx to the first one 1433 */ 1434 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags); 1435 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) { 1436 if (rtlpci->tx_ring[i].desc || 1437 rtlpci->tx_ring[i].buffer_desc) { 1438 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[i]; 1439 1440 while (skb_queue_len(&ring->queue)) { 1441 u8 *entry; 1442 struct sk_buff *skb = 1443 __skb_dequeue(&ring->queue); 1444 if (rtlpriv->use_new_trx_flow) 1445 entry = (u8 *)(&ring->buffer_desc 1446 [ring->idx]); 1447 else 1448 entry = (u8 *)(&ring->desc[ring->idx]); 1449 1450 dma_unmap_single(&rtlpci->pdev->dev, 1451 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry, 1452 true, HW_DESC_TXBUFF_ADDR), 1453 skb->len, DMA_TO_DEVICE); 1454 dev_kfree_skb_irq(skb); 1455 ring->idx = (ring->idx + 1) % ring->entries; 1456 } 1457 1458 if (rtlpriv->use_new_trx_flow) { 1459 rtlpci->tx_ring[i].cur_tx_rp = 0; 1460 rtlpci->tx_ring[i].cur_tx_wp = 0; 1461 } 1462 1463 ring->idx = 0; 1464 ring->entries = rtlpci->txringcount[i]; 1465 } 1466 } 1467 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags); 1468 1469 return 0; 1470 } 1471 1472 static bool rtl_pci_tx_chk_waitq_insert(struct ieee80211_hw *hw, 1473 struct ieee80211_sta *sta, 1474 struct sk_buff *skb) 1475 { 1476 struct rtl_priv *rtlpriv = rtl_priv(hw); 1477 struct rtl_sta_info *sta_entry = NULL; 1478 u8 tid = rtl_get_tid(skb); 1479 __le16 fc = rtl_get_fc(skb); 1480 1481 if (!sta) 1482 return false; 1483 sta_entry = (struct rtl_sta_info *)sta->drv_priv; 1484 1485 if (!rtlpriv->rtlhal.earlymode_enable) 1486 return false; 1487 if (ieee80211_is_nullfunc(fc)) 1488 return false; 1489 if (ieee80211_is_qos_nullfunc(fc)) 1490 return false; 1491 if (ieee80211_is_pspoll(fc)) 1492 return false; 1493 if (sta_entry->tids[tid].agg.agg_state != RTL_AGG_OPERATIONAL) 1494 return false; 1495 if (_rtl_mac_to_hwqueue(hw, skb) > VO_QUEUE) 1496 return false; 1497 if (tid > 7) 1498 return false; 1499 1500 /* maybe every tid should be checked */ 1501 if (!rtlpriv->link_info.higher_busytxtraffic[tid]) 1502 return false; 1503 1504 spin_lock_bh(&rtlpriv->locks.waitq_lock); 1505 skb_queue_tail(&rtlpriv->mac80211.skb_waitq[tid], skb); 1506 spin_unlock_bh(&rtlpriv->locks.waitq_lock); 1507 1508 return true; 1509 } 1510 1511 static int rtl_pci_tx(struct ieee80211_hw *hw, 1512 struct ieee80211_sta *sta, 1513 struct sk_buff *skb, 1514 struct rtl_tcb_desc *ptcb_desc) 1515 { 1516 struct rtl_priv *rtlpriv = rtl_priv(hw); 1517 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1518 struct rtl8192_tx_ring *ring; 1519 struct rtl_tx_desc *pdesc; 1520 struct rtl_tx_buffer_desc *ptx_bd_desc = NULL; 1521 u16 idx; 1522 u8 hw_queue = _rtl_mac_to_hwqueue(hw, skb); 1523 unsigned long flags; 1524 struct ieee80211_hdr *hdr = rtl_get_hdr(skb); 1525 __le16 fc = rtl_get_fc(skb); 1526 u8 *pda_addr = hdr->addr1; 1527 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1528 u8 own; 1529 u8 temp_one = 1; 1530 1531 if (ieee80211_is_mgmt(fc)) 1532 rtl_tx_mgmt_proc(hw, skb); 1533 1534 if (rtlpriv->psc.sw_ps_enabled) { 1535 if (ieee80211_is_data(fc) && !ieee80211_is_nullfunc(fc) && 1536 !ieee80211_has_pm(fc)) 1537 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); 1538 } 1539 1540 rtl_action_proc(hw, skb, true); 1541 1542 if (is_multicast_ether_addr(pda_addr)) 1543 rtlpriv->stats.txbytesmulticast += skb->len; 1544 else if (is_broadcast_ether_addr(pda_addr)) 1545 rtlpriv->stats.txbytesbroadcast += skb->len; 1546 else 1547 rtlpriv->stats.txbytesunicast += skb->len; 1548 1549 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags); 1550 ring = &rtlpci->tx_ring[hw_queue]; 1551 if (hw_queue != BEACON_QUEUE) { 1552 if (rtlpriv->use_new_trx_flow) 1553 idx = ring->cur_tx_wp; 1554 else 1555 idx = (ring->idx + skb_queue_len(&ring->queue)) % 1556 ring->entries; 1557 } else { 1558 idx = 0; 1559 } 1560 1561 pdesc = &ring->desc[idx]; 1562 if (rtlpriv->use_new_trx_flow) { 1563 ptx_bd_desc = &ring->buffer_desc[idx]; 1564 } else { 1565 own = (u8)rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc, 1566 true, HW_DESC_OWN); 1567 1568 if (own == 1 && hw_queue != BEACON_QUEUE) { 1569 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, 1570 "No more TX desc@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%x\n", 1571 hw_queue, ring->idx, idx, 1572 skb_queue_len(&ring->queue)); 1573 1574 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, 1575 flags); 1576 return skb->len; 1577 } 1578 } 1579 1580 if (rtlpriv->cfg->ops->get_available_desc && 1581 rtlpriv->cfg->ops->get_available_desc(hw, hw_queue) == 0) { 1582 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, 1583 "get_available_desc fail\n"); 1584 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags); 1585 return skb->len; 1586 } 1587 1588 if (ieee80211_is_data(fc)) 1589 rtlpriv->cfg->ops->led_control(hw, LED_CTL_TX); 1590 1591 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc, 1592 (u8 *)ptx_bd_desc, info, sta, skb, hw_queue, ptcb_desc); 1593 1594 __skb_queue_tail(&ring->queue, skb); 1595 1596 if (rtlpriv->use_new_trx_flow) { 1597 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true, 1598 HW_DESC_OWN, &hw_queue); 1599 } else { 1600 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true, 1601 HW_DESC_OWN, &temp_one); 1602 } 1603 1604 if ((ring->entries - skb_queue_len(&ring->queue)) < 2 && 1605 hw_queue != BEACON_QUEUE) { 1606 rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD, 1607 "less desc left, stop skb_queue@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%x\n", 1608 hw_queue, ring->idx, idx, 1609 skb_queue_len(&ring->queue)); 1610 1611 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb)); 1612 } 1613 1614 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags); 1615 1616 rtlpriv->cfg->ops->tx_polling(hw, hw_queue); 1617 1618 return 0; 1619 } 1620 1621 static void rtl_pci_flush(struct ieee80211_hw *hw, u32 queues, bool drop) 1622 { 1623 struct rtl_priv *rtlpriv = rtl_priv(hw); 1624 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 1625 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1626 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1627 u16 i = 0; 1628 int queue_id; 1629 struct rtl8192_tx_ring *ring; 1630 1631 if (mac->skip_scan) 1632 return; 1633 1634 for (queue_id = RTL_PCI_MAX_TX_QUEUE_COUNT - 1; queue_id >= 0;) { 1635 u32 queue_len; 1636 1637 if (((queues >> queue_id) & 0x1) == 0) { 1638 queue_id--; 1639 continue; 1640 } 1641 ring = &pcipriv->dev.tx_ring[queue_id]; 1642 queue_len = skb_queue_len(&ring->queue); 1643 if (queue_len == 0 || queue_id == BEACON_QUEUE || 1644 queue_id == TXCMD_QUEUE) { 1645 queue_id--; 1646 continue; 1647 } else { 1648 msleep(20); 1649 i++; 1650 } 1651 1652 /* we just wait 1s for all queues */ 1653 if (rtlpriv->psc.rfpwr_state == ERFOFF || 1654 is_hal_stop(rtlhal) || i >= 200) 1655 return; 1656 } 1657 } 1658 1659 static void rtl_pci_deinit(struct ieee80211_hw *hw) 1660 { 1661 struct rtl_priv *rtlpriv = rtl_priv(hw); 1662 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1663 1664 _rtl_pci_deinit_trx_ring(hw); 1665 1666 synchronize_irq(rtlpci->pdev->irq); 1667 tasklet_kill(&rtlpriv->works.irq_tasklet); 1668 cancel_work_sync(&rtlpriv->works.lps_change_work); 1669 } 1670 1671 static int rtl_pci_init(struct ieee80211_hw *hw, struct pci_dev *pdev) 1672 { 1673 int err; 1674 1675 _rtl_pci_init_struct(hw, pdev); 1676 1677 err = _rtl_pci_init_trx_ring(hw); 1678 if (err) { 1679 pr_err("tx ring initialization failed\n"); 1680 return err; 1681 } 1682 1683 return 0; 1684 } 1685 1686 static int rtl_pci_start(struct ieee80211_hw *hw) 1687 { 1688 struct rtl_priv *rtlpriv = rtl_priv(hw); 1689 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1690 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1691 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1692 struct rtl_mac *rtlmac = rtl_mac(rtl_priv(hw)); 1693 struct rtl_btc_ops *btc_ops = rtlpriv->btcoexist.btc_ops; 1694 1695 int err; 1696 1697 rtl_pci_reset_trx_ring(hw); 1698 1699 rtlpci->driver_is_goingto_unload = false; 1700 if (rtlpriv->cfg->ops->get_btc_status && 1701 rtlpriv->cfg->ops->get_btc_status()) { 1702 rtlpriv->btcoexist.btc_info.ap_num = 36; 1703 btc_ops->btc_init_variables(rtlpriv); 1704 btc_ops->btc_init_hal_vars(rtlpriv); 1705 } else if (btc_ops) { 1706 btc_ops->btc_init_variables_wifi_only(rtlpriv); 1707 } 1708 1709 err = rtlpriv->cfg->ops->hw_init(hw); 1710 if (err) { 1711 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, 1712 "Failed to config hardware!\n"); 1713 kfree(rtlpriv->btcoexist.btc_context); 1714 kfree(rtlpriv->btcoexist.wifi_only_context); 1715 return err; 1716 } 1717 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RETRY_LIMIT, 1718 &rtlmac->retry_long); 1719 1720 rtlpriv->cfg->ops->enable_interrupt(hw); 1721 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "enable_interrupt OK\n"); 1722 1723 rtl_init_rx_config(hw); 1724 1725 /*should be after adapter start and interrupt enable. */ 1726 set_hal_start(rtlhal); 1727 1728 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); 1729 1730 rtlpci->up_first_time = false; 1731 1732 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "%s OK\n", __func__); 1733 return 0; 1734 } 1735 1736 static void rtl_pci_stop(struct ieee80211_hw *hw) 1737 { 1738 struct rtl_priv *rtlpriv = rtl_priv(hw); 1739 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1740 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1741 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1742 unsigned long flags; 1743 u8 rf_timeout = 0; 1744 1745 if (rtlpriv->cfg->ops->get_btc_status()) 1746 rtlpriv->btcoexist.btc_ops->btc_halt_notify(rtlpriv); 1747 1748 if (rtlpriv->btcoexist.btc_ops) 1749 rtlpriv->btcoexist.btc_ops->btc_deinit_variables(rtlpriv); 1750 1751 /*should be before disable interrupt&adapter 1752 *and will do it immediately. 1753 */ 1754 set_hal_stop(rtlhal); 1755 1756 rtlpci->driver_is_goingto_unload = true; 1757 rtlpriv->cfg->ops->disable_interrupt(hw); 1758 cancel_work_sync(&rtlpriv->works.lps_change_work); 1759 1760 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags); 1761 while (ppsc->rfchange_inprogress) { 1762 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags); 1763 if (rf_timeout > 100) { 1764 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags); 1765 break; 1766 } 1767 mdelay(1); 1768 rf_timeout++; 1769 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags); 1770 } 1771 ppsc->rfchange_inprogress = true; 1772 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags); 1773 1774 rtlpriv->cfg->ops->hw_disable(hw); 1775 /* some things are not needed if firmware not available */ 1776 if (!rtlpriv->max_fw_size) 1777 return; 1778 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF); 1779 1780 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags); 1781 ppsc->rfchange_inprogress = false; 1782 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags); 1783 1784 rtl_pci_enable_aspm(hw); 1785 } 1786 1787 static bool _rtl_pci_find_adapter(struct pci_dev *pdev, 1788 struct ieee80211_hw *hw) 1789 { 1790 struct rtl_priv *rtlpriv = rtl_priv(hw); 1791 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 1792 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1793 struct pci_dev *bridge_pdev = pdev->bus->self; 1794 u16 venderid; 1795 u16 deviceid; 1796 u8 revisionid; 1797 u16 irqline; 1798 u8 tmp; 1799 1800 pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN; 1801 venderid = pdev->vendor; 1802 deviceid = pdev->device; 1803 pci_read_config_byte(pdev, 0x8, &revisionid); 1804 pci_read_config_word(pdev, 0x3C, &irqline); 1805 1806 /* PCI ID 0x10ec:0x8192 occurs for both RTL8192E, which uses 1807 * r8192e_pci, and RTL8192SE, which uses this driver. If the 1808 * revision ID is RTL_PCI_REVISION_ID_8192PCIE (0x01), then 1809 * the correct driver is r8192e_pci, thus this routine should 1810 * return false. 1811 */ 1812 if (deviceid == RTL_PCI_8192SE_DID && 1813 revisionid == RTL_PCI_REVISION_ID_8192PCIE) 1814 return false; 1815 1816 if (deviceid == RTL_PCI_8192_DID || 1817 deviceid == RTL_PCI_0044_DID || 1818 deviceid == RTL_PCI_0047_DID || 1819 deviceid == RTL_PCI_8192SE_DID || 1820 deviceid == RTL_PCI_8174_DID || 1821 deviceid == RTL_PCI_8173_DID || 1822 deviceid == RTL_PCI_8172_DID || 1823 deviceid == RTL_PCI_8171_DID) { 1824 switch (revisionid) { 1825 case RTL_PCI_REVISION_ID_8192PCIE: 1826 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, 1827 "8192 PCI-E is found - vid/did=%x/%x\n", 1828 venderid, deviceid); 1829 rtlhal->hw_type = HARDWARE_TYPE_RTL8192E; 1830 return false; 1831 case RTL_PCI_REVISION_ID_8192SE: 1832 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, 1833 "8192SE is found - vid/did=%x/%x\n", 1834 venderid, deviceid); 1835 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE; 1836 break; 1837 default: 1838 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, 1839 "Err: Unknown device - vid/did=%x/%x\n", 1840 venderid, deviceid); 1841 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE; 1842 break; 1843 } 1844 } else if (deviceid == RTL_PCI_8723AE_DID) { 1845 rtlhal->hw_type = HARDWARE_TYPE_RTL8723AE; 1846 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, 1847 "8723AE PCI-E is found - vid/did=%x/%x\n", 1848 venderid, deviceid); 1849 } else if (deviceid == RTL_PCI_8192CET_DID || 1850 deviceid == RTL_PCI_8192CE_DID || 1851 deviceid == RTL_PCI_8191CE_DID || 1852 deviceid == RTL_PCI_8188CE_DID) { 1853 rtlhal->hw_type = HARDWARE_TYPE_RTL8192CE; 1854 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, 1855 "8192C PCI-E is found - vid/did=%x/%x\n", 1856 venderid, deviceid); 1857 } else if (deviceid == RTL_PCI_8192DE_DID || 1858 deviceid == RTL_PCI_8192DE_DID2) { 1859 rtlhal->hw_type = HARDWARE_TYPE_RTL8192DE; 1860 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, 1861 "8192D PCI-E is found - vid/did=%x/%x\n", 1862 venderid, deviceid); 1863 } else if (deviceid == RTL_PCI_8188EE_DID) { 1864 rtlhal->hw_type = HARDWARE_TYPE_RTL8188EE; 1865 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1866 "Find adapter, Hardware type is 8188EE\n"); 1867 } else if (deviceid == RTL_PCI_8723BE_DID) { 1868 rtlhal->hw_type = HARDWARE_TYPE_RTL8723BE; 1869 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1870 "Find adapter, Hardware type is 8723BE\n"); 1871 } else if (deviceid == RTL_PCI_8192EE_DID) { 1872 rtlhal->hw_type = HARDWARE_TYPE_RTL8192EE; 1873 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1874 "Find adapter, Hardware type is 8192EE\n"); 1875 } else if (deviceid == RTL_PCI_8821AE_DID) { 1876 rtlhal->hw_type = HARDWARE_TYPE_RTL8821AE; 1877 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1878 "Find adapter, Hardware type is 8821AE\n"); 1879 } else if (deviceid == RTL_PCI_8812AE_DID) { 1880 rtlhal->hw_type = HARDWARE_TYPE_RTL8812AE; 1881 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1882 "Find adapter, Hardware type is 8812AE\n"); 1883 } else if (deviceid == RTL_PCI_8822BE_DID) { 1884 rtlhal->hw_type = HARDWARE_TYPE_RTL8822BE; 1885 rtlhal->bandset = BAND_ON_BOTH; 1886 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1887 "Find adapter, Hardware type is 8822BE\n"); 1888 } else { 1889 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, 1890 "Err: Unknown device - vid/did=%x/%x\n", 1891 venderid, deviceid); 1892 1893 rtlhal->hw_type = RTL_DEFAULT_HARDWARE_TYPE; 1894 } 1895 1896 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE) { 1897 if (revisionid == 0 || revisionid == 1) { 1898 if (revisionid == 0) { 1899 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1900 "Find 92DE MAC0\n"); 1901 rtlhal->interfaceindex = 0; 1902 } else if (revisionid == 1) { 1903 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1904 "Find 92DE MAC1\n"); 1905 rtlhal->interfaceindex = 1; 1906 } 1907 } else { 1908 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1909 "Unknown device - VendorID/DeviceID=%x/%x, Revision=%x\n", 1910 venderid, deviceid, revisionid); 1911 rtlhal->interfaceindex = 0; 1912 } 1913 } 1914 1915 switch (rtlhal->hw_type) { 1916 case HARDWARE_TYPE_RTL8192EE: 1917 case HARDWARE_TYPE_RTL8822BE: 1918 /* use new trx flow */ 1919 rtlpriv->use_new_trx_flow = true; 1920 break; 1921 1922 default: 1923 rtlpriv->use_new_trx_flow = false; 1924 break; 1925 } 1926 1927 /*find bus info */ 1928 pcipriv->ndis_adapter.busnumber = pdev->bus->number; 1929 pcipriv->ndis_adapter.devnumber = PCI_SLOT(pdev->devfn); 1930 pcipriv->ndis_adapter.funcnumber = PCI_FUNC(pdev->devfn); 1931 1932 /*find bridge info */ 1933 pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN; 1934 /* some ARM have no bridge_pdev and will crash here 1935 * so we should check if bridge_pdev is NULL 1936 */ 1937 if (bridge_pdev) { 1938 /*find bridge info if available */ 1939 for (tmp = 0; tmp < PCI_BRIDGE_VENDOR_MAX; tmp++) { 1940 if (bridge_pdev->vendor == pcibridge_vendors[tmp]) { 1941 pcipriv->ndis_adapter.pcibridge_vendor = tmp; 1942 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, 1943 "Pci Bridge Vendor is found index: %d\n", 1944 tmp); 1945 break; 1946 } 1947 } 1948 } 1949 1950 if (pcipriv->ndis_adapter.pcibridge_vendor != 1951 PCI_BRIDGE_VENDOR_UNKNOWN) { 1952 pcipriv->ndis_adapter.pcibridge_busnum = 1953 bridge_pdev->bus->number; 1954 pcipriv->ndis_adapter.pcibridge_devnum = 1955 PCI_SLOT(bridge_pdev->devfn); 1956 pcipriv->ndis_adapter.pcibridge_funcnum = 1957 PCI_FUNC(bridge_pdev->devfn); 1958 1959 if (pcipriv->ndis_adapter.pcibridge_vendor == 1960 PCI_BRIDGE_VENDOR_AMD) { 1961 pcipriv->ndis_adapter.amd_l1_patch = 1962 rtl_pci_get_amd_l1_patch(hw); 1963 } 1964 } 1965 1966 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, 1967 "pcidev busnumber:devnumber:funcnumber:vendor:link_ctl %d:%d:%d:%x:%x\n", 1968 pcipriv->ndis_adapter.busnumber, 1969 pcipriv->ndis_adapter.devnumber, 1970 pcipriv->ndis_adapter.funcnumber, 1971 pdev->vendor, pcipriv->ndis_adapter.linkctrl_reg); 1972 1973 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, 1974 "pci_bridge busnumber:devnumber:funcnumber:vendor:amd %d:%d:%d:%x:%x\n", 1975 pcipriv->ndis_adapter.pcibridge_busnum, 1976 pcipriv->ndis_adapter.pcibridge_devnum, 1977 pcipriv->ndis_adapter.pcibridge_funcnum, 1978 pcibridge_vendors[pcipriv->ndis_adapter.pcibridge_vendor], 1979 pcipriv->ndis_adapter.amd_l1_patch); 1980 1981 rtl_pci_parse_configuration(pdev, hw); 1982 1983 return true; 1984 } 1985 1986 static int rtl_pci_intr_mode_msi(struct ieee80211_hw *hw) 1987 { 1988 struct rtl_priv *rtlpriv = rtl_priv(hw); 1989 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 1990 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv); 1991 int ret; 1992 1993 ret = pci_enable_msi(rtlpci->pdev); 1994 if (ret < 0) 1995 return ret; 1996 1997 ret = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt, 1998 IRQF_SHARED, KBUILD_MODNAME, hw); 1999 if (ret < 0) { 2000 pci_disable_msi(rtlpci->pdev); 2001 return ret; 2002 } 2003 2004 rtlpci->using_msi = true; 2005 2006 rtl_dbg(rtlpriv, COMP_INIT | COMP_INTR, DBG_DMESG, 2007 "MSI Interrupt Mode!\n"); 2008 return 0; 2009 } 2010 2011 static int rtl_pci_intr_mode_legacy(struct ieee80211_hw *hw) 2012 { 2013 struct rtl_priv *rtlpriv = rtl_priv(hw); 2014 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 2015 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv); 2016 int ret; 2017 2018 ret = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt, 2019 IRQF_SHARED, KBUILD_MODNAME, hw); 2020 if (ret < 0) 2021 return ret; 2022 2023 rtlpci->using_msi = false; 2024 rtl_dbg(rtlpriv, COMP_INIT | COMP_INTR, DBG_DMESG, 2025 "Pin-based Interrupt Mode!\n"); 2026 return 0; 2027 } 2028 2029 static int rtl_pci_intr_mode_decide(struct ieee80211_hw *hw) 2030 { 2031 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 2032 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv); 2033 int ret; 2034 2035 if (rtlpci->msi_support) { 2036 ret = rtl_pci_intr_mode_msi(hw); 2037 if (ret < 0) 2038 ret = rtl_pci_intr_mode_legacy(hw); 2039 } else { 2040 ret = rtl_pci_intr_mode_legacy(hw); 2041 } 2042 return ret; 2043 } 2044 2045 static void platform_enable_dma64(struct pci_dev *pdev, bool dma64) 2046 { 2047 u8 value; 2048 2049 pci_read_config_byte(pdev, 0x719, &value); 2050 2051 /* 0x719 Bit5 is DMA64 bit fetch. */ 2052 if (dma64) 2053 value |= BIT(5); 2054 else 2055 value &= ~BIT(5); 2056 2057 pci_write_config_byte(pdev, 0x719, value); 2058 } 2059 2060 int rtl_pci_probe(struct pci_dev *pdev, 2061 const struct pci_device_id *id) 2062 { 2063 struct ieee80211_hw *hw = NULL; 2064 2065 struct rtl_priv *rtlpriv = NULL; 2066 struct rtl_pci_priv *pcipriv = NULL; 2067 struct rtl_pci *rtlpci; 2068 unsigned long pmem_start, pmem_len, pmem_flags; 2069 int err; 2070 2071 err = pci_enable_device(pdev); 2072 if (err) { 2073 WARN_ONCE(true, "%s : Cannot enable new PCI device\n", 2074 pci_name(pdev)); 2075 return err; 2076 } 2077 2078 if (((struct rtl_hal_cfg *)id->driver_data)->mod_params->dma64 && 2079 !dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) { 2080 if (dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) { 2081 WARN_ONCE(true, 2082 "Unable to obtain 64bit DMA for consistent allocations\n"); 2083 err = -ENOMEM; 2084 goto fail1; 2085 } 2086 2087 platform_enable_dma64(pdev, true); 2088 } else if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))) { 2089 if (dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32))) { 2090 WARN_ONCE(true, 2091 "rtlwifi: Unable to obtain 32bit DMA for consistent allocations\n"); 2092 err = -ENOMEM; 2093 goto fail1; 2094 } 2095 2096 platform_enable_dma64(pdev, false); 2097 } 2098 2099 pci_set_master(pdev); 2100 2101 hw = ieee80211_alloc_hw(sizeof(struct rtl_pci_priv) + 2102 sizeof(struct rtl_priv), &rtl_ops); 2103 if (!hw) { 2104 WARN_ONCE(true, 2105 "%s : ieee80211 alloc failed\n", pci_name(pdev)); 2106 err = -ENOMEM; 2107 goto fail1; 2108 } 2109 2110 SET_IEEE80211_DEV(hw, &pdev->dev); 2111 pci_set_drvdata(pdev, hw); 2112 2113 rtlpriv = hw->priv; 2114 rtlpriv->hw = hw; 2115 pcipriv = (void *)rtlpriv->priv; 2116 pcipriv->dev.pdev = pdev; 2117 init_completion(&rtlpriv->firmware_loading_complete); 2118 /*proximity init here*/ 2119 rtlpriv->proximity.proxim_on = false; 2120 2121 pcipriv = (void *)rtlpriv->priv; 2122 pcipriv->dev.pdev = pdev; 2123 2124 /* init cfg & intf_ops */ 2125 rtlpriv->rtlhal.interface = INTF_PCI; 2126 rtlpriv->cfg = (struct rtl_hal_cfg *)(id->driver_data); 2127 rtlpriv->intf_ops = &rtl_pci_ops; 2128 rtl_efuse_ops_init(hw); 2129 2130 /* MEM map */ 2131 err = pci_request_regions(pdev, KBUILD_MODNAME); 2132 if (err) { 2133 WARN_ONCE(true, "rtlwifi: Can't obtain PCI resources\n"); 2134 goto fail1; 2135 } 2136 2137 pmem_start = pci_resource_start(pdev, rtlpriv->cfg->bar_id); 2138 pmem_len = pci_resource_len(pdev, rtlpriv->cfg->bar_id); 2139 pmem_flags = pci_resource_flags(pdev, rtlpriv->cfg->bar_id); 2140 2141 /*shared mem start */ 2142 rtlpriv->io.pci_mem_start = 2143 (unsigned long)pci_iomap(pdev, 2144 rtlpriv->cfg->bar_id, pmem_len); 2145 if (rtlpriv->io.pci_mem_start == 0) { 2146 WARN_ONCE(true, "rtlwifi: Can't map PCI mem\n"); 2147 err = -ENOMEM; 2148 goto fail2; 2149 } 2150 2151 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, 2152 "mem mapped space: start: 0x%08lx len:%08lx flags:%08lx, after map:0x%08lx\n", 2153 pmem_start, pmem_len, pmem_flags, 2154 rtlpriv->io.pci_mem_start); 2155 2156 /* Disable Clk Request */ 2157 pci_write_config_byte(pdev, 0x81, 0); 2158 /* leave D3 mode */ 2159 pci_write_config_byte(pdev, 0x44, 0); 2160 pci_write_config_byte(pdev, 0x04, 0x06); 2161 pci_write_config_byte(pdev, 0x04, 0x07); 2162 2163 /* find adapter */ 2164 if (!_rtl_pci_find_adapter(pdev, hw)) { 2165 err = -ENODEV; 2166 goto fail2; 2167 } 2168 2169 /* Init IO handler */ 2170 _rtl_pci_io_handler_init(&pdev->dev, hw); 2171 2172 /*like read eeprom and so on */ 2173 rtlpriv->cfg->ops->read_eeprom_info(hw); 2174 2175 if (rtlpriv->cfg->ops->init_sw_vars(hw)) { 2176 pr_err("Can't init_sw_vars\n"); 2177 err = -ENODEV; 2178 goto fail2; 2179 } 2180 rtl_init_sw_leds(hw); 2181 2182 /*aspm */ 2183 rtl_pci_init_aspm(hw); 2184 2185 /* Init mac80211 sw */ 2186 err = rtl_init_core(hw); 2187 if (err) { 2188 pr_err("Can't allocate sw for mac80211\n"); 2189 goto fail3; 2190 } 2191 2192 /* Init PCI sw */ 2193 err = rtl_pci_init(hw, pdev); 2194 if (err) { 2195 pr_err("Failed to init PCI\n"); 2196 goto fail4; 2197 } 2198 2199 err = ieee80211_register_hw(hw); 2200 if (err) { 2201 pr_err("Can't register mac80211 hw.\n"); 2202 err = -ENODEV; 2203 goto fail5; 2204 } 2205 rtlpriv->mac80211.mac80211_registered = 1; 2206 2207 /* add for debug */ 2208 rtl_debug_add_one(hw); 2209 2210 /*init rfkill */ 2211 rtl_init_rfkill(hw); /* Init PCI sw */ 2212 2213 rtlpci = rtl_pcidev(pcipriv); 2214 err = rtl_pci_intr_mode_decide(hw); 2215 if (err) { 2216 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, 2217 "%s: failed to register IRQ handler\n", 2218 wiphy_name(hw->wiphy)); 2219 goto fail3; 2220 } 2221 rtlpci->irq_alloc = 1; 2222 2223 set_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status); 2224 return 0; 2225 2226 fail5: 2227 rtl_pci_deinit(hw); 2228 fail4: 2229 rtl_deinit_core(hw); 2230 fail3: 2231 wait_for_completion(&rtlpriv->firmware_loading_complete); 2232 rtlpriv->cfg->ops->deinit_sw_vars(hw); 2233 2234 fail2: 2235 if (rtlpriv->io.pci_mem_start != 0) 2236 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start); 2237 2238 pci_release_regions(pdev); 2239 2240 fail1: 2241 if (hw) 2242 ieee80211_free_hw(hw); 2243 pci_disable_device(pdev); 2244 2245 return err; 2246 } 2247 EXPORT_SYMBOL(rtl_pci_probe); 2248 2249 void rtl_pci_disconnect(struct pci_dev *pdev) 2250 { 2251 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 2252 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 2253 struct rtl_priv *rtlpriv = rtl_priv(hw); 2254 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv); 2255 struct rtl_mac *rtlmac = rtl_mac(rtlpriv); 2256 2257 /* just in case driver is removed before firmware callback */ 2258 wait_for_completion(&rtlpriv->firmware_loading_complete); 2259 clear_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status); 2260 2261 /* remove form debug */ 2262 rtl_debug_remove_one(hw); 2263 2264 /*ieee80211_unregister_hw will call ops_stop */ 2265 if (rtlmac->mac80211_registered == 1) { 2266 ieee80211_unregister_hw(hw); 2267 rtlmac->mac80211_registered = 0; 2268 } else { 2269 rtl_deinit_deferred_work(hw, false); 2270 rtlpriv->intf_ops->adapter_stop(hw); 2271 } 2272 rtlpriv->cfg->ops->disable_interrupt(hw); 2273 2274 /*deinit rfkill */ 2275 rtl_deinit_rfkill(hw); 2276 2277 rtl_pci_deinit(hw); 2278 rtl_deinit_core(hw); 2279 rtlpriv->cfg->ops->deinit_sw_vars(hw); 2280 2281 if (rtlpci->irq_alloc) { 2282 free_irq(rtlpci->pdev->irq, hw); 2283 rtlpci->irq_alloc = 0; 2284 } 2285 2286 if (rtlpci->using_msi) 2287 pci_disable_msi(rtlpci->pdev); 2288 2289 if (rtlpriv->io.pci_mem_start != 0) { 2290 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start); 2291 pci_release_regions(pdev); 2292 } 2293 2294 pci_disable_device(pdev); 2295 2296 rtl_pci_disable_aspm(hw); 2297 2298 pci_set_drvdata(pdev, NULL); 2299 2300 ieee80211_free_hw(hw); 2301 } 2302 EXPORT_SYMBOL(rtl_pci_disconnect); 2303 2304 #ifdef CONFIG_PM_SLEEP 2305 /*************************************** 2306 * kernel pci power state define: 2307 * PCI_D0 ((pci_power_t __force) 0) 2308 * PCI_D1 ((pci_power_t __force) 1) 2309 * PCI_D2 ((pci_power_t __force) 2) 2310 * PCI_D3hot ((pci_power_t __force) 3) 2311 * PCI_D3cold ((pci_power_t __force) 4) 2312 * PCI_UNKNOWN ((pci_power_t __force) 5) 2313 2314 * This function is called when system 2315 * goes into suspend state mac80211 will 2316 * call rtl_mac_stop() from the mac80211 2317 * suspend function first, So there is 2318 * no need to call hw_disable here. 2319 ****************************************/ 2320 int rtl_pci_suspend(struct device *dev) 2321 { 2322 struct ieee80211_hw *hw = dev_get_drvdata(dev); 2323 struct rtl_priv *rtlpriv = rtl_priv(hw); 2324 2325 rtlpriv->cfg->ops->hw_suspend(hw); 2326 rtl_deinit_rfkill(hw); 2327 2328 return 0; 2329 } 2330 EXPORT_SYMBOL(rtl_pci_suspend); 2331 2332 int rtl_pci_resume(struct device *dev) 2333 { 2334 struct ieee80211_hw *hw = dev_get_drvdata(dev); 2335 struct rtl_priv *rtlpriv = rtl_priv(hw); 2336 2337 rtlpriv->cfg->ops->hw_resume(hw); 2338 rtl_init_rfkill(hw); 2339 return 0; 2340 } 2341 EXPORT_SYMBOL(rtl_pci_resume); 2342 #endif /* CONFIG_PM_SLEEP */ 2343 2344 const struct rtl_intf_ops rtl_pci_ops = { 2345 .adapter_start = rtl_pci_start, 2346 .adapter_stop = rtl_pci_stop, 2347 .adapter_tx = rtl_pci_tx, 2348 .flush = rtl_pci_flush, 2349 .reset_trx_ring = rtl_pci_reset_trx_ring, 2350 .waitq_insert = rtl_pci_tx_chk_waitq_insert, 2351 2352 .disable_aspm = rtl_pci_disable_aspm, 2353 .enable_aspm = rtl_pci_enable_aspm, 2354 }; 2355