1 /* SPDX-License-Identifier: ISC */ 2 /* Copyright (C) 2020 MediaTek Inc. */ 3 4 #ifndef __MT76_CONNAC_MCU_H 5 #define __MT76_CONNAC_MCU_H 6 7 #include "mt76_connac.h" 8 9 #define FW_FEATURE_SET_ENCRYPT BIT(0) 10 #define FW_FEATURE_SET_KEY_IDX GENMASK(2, 1) 11 #define FW_FEATURE_ENCRY_MODE BIT(4) 12 #define FW_FEATURE_OVERRIDE_ADDR BIT(5) 13 #define FW_FEATURE_NON_DL BIT(6) 14 15 #define DL_MODE_ENCRYPT BIT(0) 16 #define DL_MODE_KEY_IDX GENMASK(2, 1) 17 #define DL_MODE_RESET_SEC_IV BIT(3) 18 #define DL_MODE_WORKING_PDA_CR4 BIT(4) 19 #define DL_MODE_VALID_RAM_ENTRY BIT(5) 20 #define DL_CONFIG_ENCRY_MODE_SEL BIT(6) 21 #define DL_MODE_NEED_RSP BIT(31) 22 23 #define FW_START_OVERRIDE BIT(0) 24 #define FW_START_WORKING_PDA_CR4 BIT(2) 25 #define FW_START_WORKING_PDA_DSP BIT(3) 26 27 #define PATCH_SEC_NOT_SUPPORT GENMASK(31, 0) 28 #define PATCH_SEC_TYPE_MASK GENMASK(15, 0) 29 #define PATCH_SEC_TYPE_INFO 0x2 30 31 #define PATCH_SEC_ENC_TYPE_MASK GENMASK(31, 24) 32 #define PATCH_SEC_ENC_TYPE_PLAIN 0x00 33 #define PATCH_SEC_ENC_TYPE_AES 0x01 34 #define PATCH_SEC_ENC_TYPE_SCRAMBLE 0x02 35 #define PATCH_SEC_ENC_SCRAMBLE_INFO_MASK GENMASK(15, 0) 36 #define PATCH_SEC_ENC_AES_KEY_MASK GENMASK(7, 0) 37 38 enum { 39 FW_TYPE_DEFAULT = 0, 40 FW_TYPE_CLC = 2, 41 FW_TYPE_MAX_NUM = 255 42 }; 43 44 #define MCU_PQ_ID(p, q) (((p) << 15) | ((q) << 10)) 45 #define MCU_PKT_ID 0xa0 46 47 struct mt76_connac2_mcu_txd { 48 __le32 txd[8]; 49 50 __le16 len; 51 __le16 pq_id; 52 53 u8 cid; 54 u8 pkt_type; 55 u8 set_query; /* FW don't care */ 56 u8 seq; 57 58 u8 uc_d2b0_rev; 59 u8 ext_cid; 60 u8 s2d_index; 61 u8 ext_cid_ack; 62 63 u32 rsv[5]; 64 } __packed __aligned(4); 65 66 /** 67 * struct mt76_connac2_mcu_uni_txd - mcu command descriptor for connac2 and connac3 68 * @txd: hardware descriptor 69 * @len: total length not including txd 70 * @cid: command identifier 71 * @pkt_type: must be 0xa0 (cmd packet by long format) 72 * @frag_n: fragment number 73 * @seq: sequence number 74 * @checksum: 0 mean there is no checksum 75 * @s2d_index: index for command source and destination 76 * Definition | value | note 77 * CMD_S2D_IDX_H2N | 0x00 | command from HOST to WM 78 * CMD_S2D_IDX_C2N | 0x01 | command from WA to WM 79 * CMD_S2D_IDX_H2C | 0x02 | command from HOST to WA 80 * CMD_S2D_IDX_H2N_AND_H2C | 0x03 | command from HOST to WA and WM 81 * 82 * @option: command option 83 * BIT[0]: UNI_CMD_OPT_BIT_ACK 84 * set to 1 to request a fw reply 85 * if UNI_CMD_OPT_BIT_0_ACK is set and UNI_CMD_OPT_BIT_2_SET_QUERY 86 * is set, mcu firmware will send response event EID = 0x01 87 * (UNI_EVENT_ID_CMD_RESULT) to the host. 88 * BIT[1]: UNI_CMD_OPT_BIT_UNI_CMD 89 * 0: original command 90 * 1: unified command 91 * BIT[2]: UNI_CMD_OPT_BIT_SET_QUERY 92 * 0: QUERY command 93 * 1: SET command 94 */ 95 struct mt76_connac2_mcu_uni_txd { 96 __le32 txd[8]; 97 98 /* DW1 */ 99 __le16 len; 100 __le16 cid; 101 102 /* DW2 */ 103 u8 rsv; 104 u8 pkt_type; 105 u8 frag_n; 106 u8 seq; 107 108 /* DW3 */ 109 __le16 checksum; 110 u8 s2d_index; 111 u8 option; 112 113 /* DW4 */ 114 u8 rsv1[4]; 115 } __packed __aligned(4); 116 117 struct mt76_connac2_mcu_rxd { 118 /* New members MUST be added within the struct_group() macro below. */ 119 struct_group_tagged(mt76_connac2_mcu_rxd_hdr, hdr, 120 __le32 rxd[6]; 121 122 __le16 len; 123 __le16 pkt_type_id; 124 125 u8 eid; 126 u8 seq; 127 u8 option; 128 u8 rsv; 129 u8 ext_eid; 130 u8 rsv1[2]; 131 u8 s2d_index; 132 ); 133 134 u8 tlv[]; 135 }; 136 static_assert(offsetof(struct mt76_connac2_mcu_rxd, tlv) == sizeof(struct mt76_connac2_mcu_rxd_hdr), 137 "struct member likely outside of struct_group_tagged()"); 138 139 struct mt76_connac2_patch_hdr { 140 char build_date[16]; 141 char platform[4]; 142 __be32 hw_sw_ver; 143 __be32 patch_ver; 144 __be16 checksum; 145 u16 rsv; 146 struct { 147 __be32 patch_ver; 148 __be32 subsys; 149 __be32 feature; 150 __be32 n_region; 151 __be32 crc; 152 u32 rsv[11]; 153 } desc; 154 } __packed; 155 156 struct mt76_connac2_patch_sec { 157 __be32 type; 158 __be32 offs; 159 __be32 size; 160 union { 161 __be32 spec[13]; 162 struct { 163 __be32 addr; 164 __be32 len; 165 __be32 sec_key_idx; 166 __be32 align_len; 167 u32 rsv[9]; 168 } info; 169 }; 170 } __packed; 171 172 struct mt76_connac2_fw_trailer { 173 u8 chip_id; 174 u8 eco_code; 175 u8 n_region; 176 u8 format_ver; 177 u8 format_flag; 178 u8 rsv[2]; 179 char fw_ver[10]; 180 char build_date[15]; 181 __le32 crc; 182 } __packed; 183 184 struct mt76_connac2_fw_region { 185 __le32 decomp_crc; 186 __le32 decomp_len; 187 __le32 decomp_blk_sz; 188 u8 rsv[4]; 189 __le32 addr; 190 __le32 len; 191 u8 feature_set; 192 u8 type; 193 u8 rsv1[14]; 194 } __packed; 195 196 struct tlv { 197 __le16 tag; 198 __le16 len; 199 u8 data[]; 200 } __packed; 201 202 struct bss_info_omac { 203 __le16 tag; 204 __le16 len; 205 u8 hw_bss_idx; 206 u8 omac_idx; 207 u8 band_idx; 208 u8 rsv0; 209 __le32 conn_type; 210 u32 rsv1; 211 } __packed; 212 213 struct bss_info_basic { 214 __le16 tag; 215 __le16 len; 216 __le32 network_type; 217 u8 active; 218 u8 rsv0; 219 __le16 bcn_interval; 220 u8 bssid[ETH_ALEN]; 221 u8 wmm_idx; 222 u8 dtim_period; 223 u8 bmc_wcid_lo; 224 u8 cipher; 225 u8 phy_mode; 226 u8 max_bssid; /* max BSSID. range: 1 ~ 8, 0: MBSSID disabled */ 227 u8 non_tx_bssid;/* non-transmitted BSSID, 0: transmitted BSSID */ 228 u8 bmc_wcid_hi; /* high Byte and version */ 229 u8 rsv[2]; 230 } __packed; 231 232 struct bss_info_rf_ch { 233 __le16 tag; 234 __le16 len; 235 u8 pri_ch; 236 u8 center_ch0; 237 u8 center_ch1; 238 u8 bw; 239 u8 he_ru26_block; /* 1: don't send HETB in RU26, 0: allow */ 240 u8 he_all_disable; /* 1: disallow all HETB, 0: allow */ 241 u8 rsv[2]; 242 } __packed; 243 244 struct bss_info_ext_bss { 245 __le16 tag; 246 __le16 len; 247 __le32 mbss_tsf_offset; /* in unit of us */ 248 u8 rsv[8]; 249 } __packed; 250 251 enum { 252 BSS_INFO_OMAC, 253 BSS_INFO_BASIC, 254 BSS_INFO_RF_CH, /* optional, for BT/LTE coex */ 255 BSS_INFO_PM, /* sta only */ 256 BSS_INFO_UAPSD, /* sta only */ 257 BSS_INFO_ROAM_DETECT, /* obsoleted */ 258 BSS_INFO_LQ_RM, /* obsoleted */ 259 BSS_INFO_EXT_BSS, 260 BSS_INFO_BMC_RATE, /* for bmc rate control in CR4 */ 261 BSS_INFO_SYNC_MODE, /* obsoleted */ 262 BSS_INFO_RA, 263 BSS_INFO_HW_AMSDU, 264 BSS_INFO_BSS_COLOR, 265 BSS_INFO_HE_BASIC, 266 BSS_INFO_PROTECT_INFO, 267 BSS_INFO_OFFLOAD, 268 BSS_INFO_11V_MBSSID, 269 BSS_INFO_MAX_NUM 270 }; 271 272 /* sta_rec */ 273 274 struct sta_ntlv_hdr { 275 u8 rsv[2]; 276 __le16 tlv_num; 277 } __packed; 278 279 struct sta_req_hdr { 280 u8 bss_idx; 281 u8 wlan_idx_lo; 282 __le16 tlv_num; 283 u8 is_tlv_append; 284 u8 muar_idx; 285 u8 wlan_idx_hi; 286 u8 rsv; 287 } __packed; 288 289 struct sta_rec_basic { 290 __le16 tag; 291 __le16 len; 292 __le32 conn_type; 293 u8 conn_state; 294 u8 qos; 295 __le16 aid; 296 u8 peer_addr[ETH_ALEN]; 297 #define EXTRA_INFO_VER BIT(0) 298 #define EXTRA_INFO_NEW BIT(1) 299 __le16 extra_info; 300 } __packed; 301 302 struct sta_rec_ht { 303 __le16 tag; 304 __le16 len; 305 __le16 ht_cap; 306 u16 rsv; 307 } __packed; 308 309 struct sta_rec_vht { 310 __le16 tag; 311 __le16 len; 312 __le32 vht_cap; 313 __le16 vht_rx_mcs_map; 314 __le16 vht_tx_mcs_map; 315 /* mt7915 - mt7921 */ 316 u8 rts_bw_sig; 317 u8 rsv[3]; 318 } __packed; 319 320 struct sta_rec_uapsd { 321 __le16 tag; 322 __le16 len; 323 u8 dac_map; 324 u8 tac_map; 325 u8 max_sp; 326 u8 rsv0; 327 __le16 listen_interval; 328 u8 rsv1[2]; 329 } __packed; 330 331 struct sta_rec_ba { 332 __le16 tag; 333 __le16 len; 334 u8 tid; 335 u8 ba_type; 336 u8 amsdu; 337 u8 ba_en; 338 __le16 ssn; 339 __le16 winsize; 340 } __packed; 341 342 struct sta_rec_he { 343 __le16 tag; 344 __le16 len; 345 346 __le32 he_cap; 347 348 u8 t_frame_dur; 349 u8 max_ampdu_exp; 350 u8 bw_set; 351 u8 device_class; 352 u8 dcm_tx_mode; 353 u8 dcm_tx_max_nss; 354 u8 dcm_rx_mode; 355 u8 dcm_rx_max_nss; 356 u8 dcm_max_ru; 357 u8 punc_pream_rx; 358 u8 pkt_ext; 359 u8 rsv1; 360 361 __le16 max_nss_mcs[CMD_HE_MCS_BW_NUM]; 362 363 u8 rsv2[2]; 364 } __packed; 365 366 struct sta_rec_he_v2 { 367 __le16 tag; 368 __le16 len; 369 u8 he_mac_cap[6]; 370 u8 he_phy_cap[11]; 371 u8 pkt_ext; 372 /* 0: BW80, 1: BW160, 2: BW8080 */ 373 __le16 max_nss_mcs[CMD_HE_MCS_BW_NUM]; 374 } __packed; 375 376 struct sta_rec_amsdu { 377 __le16 tag; 378 __le16 len; 379 u8 max_amsdu_num; 380 u8 max_mpdu_size; 381 u8 amsdu_en; 382 u8 rsv; 383 } __packed; 384 385 struct sta_rec_state { 386 __le16 tag; 387 __le16 len; 388 __le32 flags; 389 u8 state; 390 u8 vht_opmode; 391 u8 action; 392 u8 rsv[1]; 393 } __packed; 394 395 #define RA_LEGACY_OFDM GENMASK(13, 6) 396 #define RA_LEGACY_CCK GENMASK(3, 0) 397 #define HT_MCS_MASK_NUM 10 398 struct sta_rec_ra_info { 399 __le16 tag; 400 __le16 len; 401 __le16 legacy; 402 u8 rx_mcs_bitmask[HT_MCS_MASK_NUM]; 403 } __packed; 404 405 struct sta_rec_phy { 406 __le16 tag; 407 __le16 len; 408 __le16 basic_rate; 409 u8 phy_type; 410 u8 ampdu; 411 u8 rts_policy; 412 u8 rcpi; 413 u8 max_ampdu_len; /* connac3 */ 414 u8 rsv[1]; 415 } __packed; 416 417 struct sta_rec_he_6g_capa { 418 __le16 tag; 419 __le16 len; 420 __le16 capa; 421 u8 rsv[2]; 422 } __packed; 423 424 struct sta_rec_pn_info { 425 __le16 tag; 426 __le16 len; 427 u8 pn[6]; 428 u8 tsc_type; 429 u8 rsv; 430 } __packed; 431 432 struct sec_key { 433 u8 cipher_id; 434 u8 cipher_len; 435 u8 key_id; 436 u8 key_len; 437 u8 key[32]; 438 } __packed; 439 440 struct sta_rec_sec { 441 __le16 tag; 442 __le16 len; 443 u8 add; 444 u8 n_cipher; 445 u8 rsv[2]; 446 447 struct sec_key key[2]; 448 } __packed; 449 450 struct sta_rec_bf { 451 __le16 tag; 452 __le16 len; 453 454 __le16 pfmu; /* 0xffff: no access right for PFMU */ 455 bool su_mu; /* 0: SU, 1: MU */ 456 u8 bf_cap; /* 0: iBF, 1: eBF */ 457 u8 sounding_phy; /* 0: legacy, 1: OFDM, 2: HT, 4: VHT */ 458 u8 ndpa_rate; 459 u8 ndp_rate; 460 u8 rept_poll_rate; 461 u8 tx_mode; /* 0: legacy, 1: OFDM, 2: HT, 4: VHT ... */ 462 u8 ncol; 463 u8 nrow; 464 u8 bw; /* 0: 20M, 1: 40M, 2: 80M, 3: 160M */ 465 466 u8 mem_total; 467 u8 mem_20m; 468 struct { 469 u8 row; 470 u8 col: 6, row_msb: 2; 471 } mem[4]; 472 473 __le16 smart_ant; 474 u8 se_idx; 475 u8 auto_sounding; /* b7: low traffic indicator 476 * b6: Stop sounding for this entry 477 * b5 ~ b0: postpone sounding 478 */ 479 u8 ibf_timeout; 480 u8 ibf_dbw; 481 u8 ibf_ncol; 482 u8 ibf_nrow; 483 u8 nrow_gt_bw80; 484 u8 ncol_gt_bw80; 485 u8 ru_start_idx; 486 u8 ru_end_idx; 487 488 bool trigger_su; 489 bool trigger_mu; 490 bool ng16_su; 491 bool ng16_mu; 492 bool codebook42_su; 493 bool codebook75_mu; 494 495 u8 he_ltf; 496 u8 rsv[3]; 497 } __packed; 498 499 struct sta_rec_bfee { 500 __le16 tag; 501 __le16 len; 502 bool fb_identity_matrix; /* 1: feedback identity matrix */ 503 bool ignore_feedback; /* 1: ignore */ 504 u8 rsv[2]; 505 } __packed; 506 507 struct sta_rec_muru { 508 __le16 tag; 509 __le16 len; 510 511 struct { 512 bool ofdma_dl_en; 513 bool ofdma_ul_en; 514 bool mimo_dl_en; 515 bool mimo_ul_en; 516 u8 rsv[4]; 517 } cfg; 518 519 struct { 520 u8 punc_pream_rx; 521 bool he_20m_in_40m_2g; 522 bool he_20m_in_160m; 523 bool he_80m_in_160m; 524 bool lt16_sigb; 525 bool rx_su_comp_sigb; 526 bool rx_su_non_comp_sigb; 527 u8 rsv; 528 } ofdma_dl; 529 530 struct { 531 u8 t_frame_dur; 532 u8 mu_cascading; 533 u8 uo_ra; 534 u8 he_2x996_tone; 535 u8 rx_t_frame_11ac; 536 u8 rx_ctrl_frame_to_mbss; 537 u8 rsv[2]; 538 } ofdma_ul; 539 540 struct { 541 bool vht_mu_bfee; 542 bool partial_bw_dl_mimo; 543 u8 rsv[2]; 544 } mimo_dl; 545 546 struct { 547 bool full_ul_mimo; 548 bool partial_ul_mimo; 549 u8 rsv[2]; 550 } mimo_ul; 551 } __packed; 552 553 struct sta_rec_remove { 554 __le16 tag; 555 __le16 len; 556 u8 action; 557 u8 pad[3]; 558 } __packed; 559 560 struct sta_phy { 561 u8 type; 562 u8 flag; 563 u8 stbc; 564 u8 sgi; 565 u8 bw; 566 u8 ldpc; 567 u8 mcs; 568 u8 nss; 569 u8 he_ltf; 570 }; 571 572 struct sta_rec_ra { 573 __le16 tag; 574 __le16 len; 575 576 u8 valid; 577 u8 auto_rate; 578 u8 phy_mode; 579 u8 channel; 580 u8 bw; 581 u8 disable_cck; 582 u8 ht_mcs32; 583 u8 ht_gf; 584 u8 ht_mcs[4]; 585 u8 mmps_mode; 586 u8 gband_256; 587 u8 af; 588 u8 auth_wapi_mode; 589 u8 rate_len; 590 591 u8 supp_mode; 592 u8 supp_cck_rate; 593 u8 supp_ofdm_rate; 594 __le32 supp_ht_mcs; 595 __le16 supp_vht_mcs[4]; 596 597 u8 op_mode; 598 u8 op_vht_chan_width; 599 u8 op_vht_rx_nss; 600 u8 op_vht_rx_nss_type; 601 602 __le32 sta_cap; 603 604 struct sta_phy phy; 605 } __packed; 606 607 struct sta_rec_ra_fixed { 608 __le16 tag; 609 __le16 len; 610 611 __le32 field; 612 u8 op_mode; 613 u8 op_vht_chan_width; 614 u8 op_vht_rx_nss; 615 u8 op_vht_rx_nss_type; 616 617 struct sta_phy phy; 618 619 u8 spe_idx; 620 u8 short_preamble; 621 u8 is_5g; 622 u8 mmps_mode; 623 } __packed; 624 625 struct sta_rec_tx_proc { 626 __le16 tag; 627 __le16 len; 628 __le32 flag; 629 } __packed; 630 631 /* wtbl_rec */ 632 633 struct wtbl_req_hdr { 634 u8 wlan_idx_lo; 635 u8 operation; 636 __le16 tlv_num; 637 u8 wlan_idx_hi; 638 u8 rsv[3]; 639 } __packed; 640 641 struct wtbl_generic { 642 __le16 tag; 643 __le16 len; 644 u8 peer_addr[ETH_ALEN]; 645 u8 muar_idx; 646 u8 skip_tx; 647 u8 cf_ack; 648 u8 qos; 649 u8 mesh; 650 u8 adm; 651 __le16 partial_aid; 652 u8 baf_en; 653 u8 aad_om; 654 } __packed; 655 656 struct wtbl_rx { 657 __le16 tag; 658 __le16 len; 659 u8 rcid; 660 u8 rca1; 661 u8 rca2; 662 u8 rv; 663 u8 rsv[4]; 664 } __packed; 665 666 struct wtbl_ht { 667 __le16 tag; 668 __le16 len; 669 u8 ht; 670 u8 ldpc; 671 u8 af; 672 u8 mm; 673 u8 rsv[4]; 674 } __packed; 675 676 struct wtbl_vht { 677 __le16 tag; 678 __le16 len; 679 u8 ldpc; 680 u8 dyn_bw; 681 u8 vht; 682 u8 txop_ps; 683 u8 rsv[4]; 684 } __packed; 685 686 struct wtbl_tx_ps { 687 __le16 tag; 688 __le16 len; 689 u8 txps; 690 u8 rsv[3]; 691 } __packed; 692 693 struct wtbl_hdr_trans { 694 __le16 tag; 695 __le16 len; 696 u8 to_ds; 697 u8 from_ds; 698 u8 no_rx_trans; 699 u8 rsv; 700 } __packed; 701 702 struct wtbl_ba { 703 __le16 tag; 704 __le16 len; 705 /* common */ 706 u8 tid; 707 u8 ba_type; 708 u8 rsv0[2]; 709 /* originator only */ 710 __le16 sn; 711 u8 ba_en; 712 u8 ba_winsize_idx; 713 /* originator & recipient */ 714 __le16 ba_winsize; 715 /* recipient only */ 716 u8 peer_addr[ETH_ALEN]; 717 u8 rst_ba_tid; 718 u8 rst_ba_sel; 719 u8 rst_ba_sb; 720 u8 band_idx; 721 u8 rsv1[4]; 722 } __packed; 723 724 struct wtbl_smps { 725 __le16 tag; 726 __le16 len; 727 u8 smps; 728 u8 rsv[3]; 729 } __packed; 730 731 /* mt7615 only */ 732 733 struct wtbl_bf { 734 __le16 tag; 735 __le16 len; 736 u8 ibf; 737 u8 ebf; 738 u8 ibf_vht; 739 u8 ebf_vht; 740 u8 gid; 741 u8 pfmu_idx; 742 u8 rsv[2]; 743 } __packed; 744 745 struct wtbl_pn { 746 __le16 tag; 747 __le16 len; 748 u8 pn[6]; 749 u8 rsv[2]; 750 } __packed; 751 752 struct wtbl_spe { 753 __le16 tag; 754 __le16 len; 755 u8 spe_idx; 756 u8 rsv[3]; 757 } __packed; 758 759 struct wtbl_raw { 760 __le16 tag; 761 __le16 len; 762 u8 wtbl_idx; 763 u8 dw; 764 u8 rsv[2]; 765 __le32 msk; 766 __le32 val; 767 } __packed; 768 769 #define MT76_CONNAC_WTBL_UPDATE_MAX_SIZE (sizeof(struct wtbl_req_hdr) + \ 770 sizeof(struct wtbl_generic) + \ 771 sizeof(struct wtbl_rx) + \ 772 sizeof(struct wtbl_ht) + \ 773 sizeof(struct wtbl_vht) + \ 774 sizeof(struct wtbl_tx_ps) + \ 775 sizeof(struct wtbl_hdr_trans) +\ 776 sizeof(struct wtbl_ba) + \ 777 sizeof(struct wtbl_bf) + \ 778 sizeof(struct wtbl_smps) + \ 779 sizeof(struct wtbl_pn) + \ 780 sizeof(struct wtbl_spe)) 781 782 #define MT76_CONNAC_STA_UPDATE_MAX_SIZE (sizeof(struct sta_req_hdr) + \ 783 sizeof(struct sta_rec_basic) + \ 784 sizeof(struct sta_rec_bf) + \ 785 sizeof(struct sta_rec_ht) + \ 786 sizeof(struct sta_rec_he) + \ 787 sizeof(struct sta_rec_ba) + \ 788 sizeof(struct sta_rec_vht) + \ 789 sizeof(struct sta_rec_uapsd) + \ 790 sizeof(struct sta_rec_amsdu) + \ 791 sizeof(struct sta_rec_muru) + \ 792 sizeof(struct sta_rec_bfee) + \ 793 sizeof(struct sta_rec_ra) + \ 794 sizeof(struct sta_rec_sec) + \ 795 sizeof(struct sta_rec_ra_fixed) + \ 796 sizeof(struct sta_rec_he_6g_capa) + \ 797 sizeof(struct sta_rec_pn_info) + \ 798 sizeof(struct sta_rec_tx_proc) + \ 799 sizeof(struct tlv) + \ 800 MT76_CONNAC_WTBL_UPDATE_MAX_SIZE) 801 802 enum { 803 STA_REC_BASIC, 804 STA_REC_RA, 805 STA_REC_RA_CMM_INFO, 806 STA_REC_RA_UPDATE, 807 STA_REC_BF, 808 STA_REC_AMSDU, 809 STA_REC_BA, 810 STA_REC_STATE, 811 STA_REC_TX_PROC, /* for hdr trans and CSO in CR4 */ 812 STA_REC_HT, 813 STA_REC_VHT, 814 STA_REC_APPS, 815 STA_REC_KEY, 816 STA_REC_WTBL, 817 STA_REC_HE, 818 STA_REC_HW_AMSDU, 819 STA_REC_WTBL_AADOM, 820 STA_REC_KEY_V2, 821 STA_REC_MURU, 822 STA_REC_MUEDCA, 823 STA_REC_BFEE, 824 STA_REC_PHY = 0x15, 825 STA_REC_HE_6G = 0x17, 826 STA_REC_HE_V2 = 0x19, 827 STA_REC_MLD = 0x20, 828 STA_REC_EHT_MLD = 0x21, 829 STA_REC_EHT = 0x22, 830 STA_REC_MLD_OFF = 0x23, 831 STA_REC_REMOVE = 0x25, 832 STA_REC_PN_INFO = 0x26, 833 STA_REC_KEY_V3 = 0x27, 834 STA_REC_HDRT = 0x28, 835 STA_REC_HDR_TRANS = 0x2B, 836 STA_REC_MAX_NUM 837 }; 838 839 enum { 840 WTBL_GENERIC, 841 WTBL_RX, 842 WTBL_HT, 843 WTBL_VHT, 844 WTBL_PEER_PS, /* not used */ 845 WTBL_TX_PS, 846 WTBL_HDR_TRANS, 847 WTBL_SEC_KEY, 848 WTBL_BA, 849 WTBL_RDG, /* obsoleted */ 850 WTBL_PROTECT, /* not used */ 851 WTBL_CLEAR, /* not used */ 852 WTBL_BF, 853 WTBL_SMPS, 854 WTBL_RAW_DATA, /* debug only */ 855 WTBL_PN, 856 WTBL_SPE, 857 WTBL_MAX_NUM 858 }; 859 860 #define STA_TYPE_STA BIT(0) 861 #define STA_TYPE_AP BIT(1) 862 #define STA_TYPE_ADHOC BIT(2) 863 #define STA_TYPE_WDS BIT(4) 864 #define STA_TYPE_BC BIT(5) 865 866 #define NETWORK_INFRA BIT(16) 867 #define NETWORK_P2P BIT(17) 868 #define NETWORK_IBSS BIT(18) 869 #define NETWORK_WDS BIT(21) 870 871 #define SCAN_FUNC_RANDOM_MAC BIT(0) 872 #define SCAN_FUNC_RNR_SCAN BIT(3) 873 #define SCAN_FUNC_SPLIT_SCAN BIT(5) 874 875 #define CONNECTION_INFRA_STA (STA_TYPE_STA | NETWORK_INFRA) 876 #define CONNECTION_INFRA_AP (STA_TYPE_AP | NETWORK_INFRA) 877 #define CONNECTION_P2P_GC (STA_TYPE_STA | NETWORK_P2P) 878 #define CONNECTION_P2P_GO (STA_TYPE_AP | NETWORK_P2P) 879 #define CONNECTION_IBSS_ADHOC (STA_TYPE_ADHOC | NETWORK_IBSS) 880 #define CONNECTION_WDS (STA_TYPE_WDS | NETWORK_WDS) 881 #define CONNECTION_INFRA_BC (STA_TYPE_BC | NETWORK_INFRA) 882 883 #define CONN_STATE_DISCONNECT 0 884 #define CONN_STATE_CONNECT 1 885 #define CONN_STATE_PORT_SECURE 2 886 887 /* HE MAC */ 888 #define STA_REC_HE_CAP_HTC BIT(0) 889 #define STA_REC_HE_CAP_BQR BIT(1) 890 #define STA_REC_HE_CAP_BSR BIT(2) 891 #define STA_REC_HE_CAP_OM BIT(3) 892 #define STA_REC_HE_CAP_AMSDU_IN_AMPDU BIT(4) 893 /* HE PHY */ 894 #define STA_REC_HE_CAP_DUAL_BAND BIT(5) 895 #define STA_REC_HE_CAP_LDPC BIT(6) 896 #define STA_REC_HE_CAP_TRIG_CQI_FK BIT(7) 897 #define STA_REC_HE_CAP_PARTIAL_BW_EXT_RANGE BIT(8) 898 /* STBC */ 899 #define STA_REC_HE_CAP_LE_EQ_80M_TX_STBC BIT(9) 900 #define STA_REC_HE_CAP_LE_EQ_80M_RX_STBC BIT(10) 901 #define STA_REC_HE_CAP_GT_80M_TX_STBC BIT(11) 902 #define STA_REC_HE_CAP_GT_80M_RX_STBC BIT(12) 903 /* GI */ 904 #define STA_REC_HE_CAP_SU_PPDU_1LTF_8US_GI BIT(13) 905 #define STA_REC_HE_CAP_SU_MU_PPDU_4LTF_8US_GI BIT(14) 906 #define STA_REC_HE_CAP_ER_SU_PPDU_1LTF_8US_GI BIT(15) 907 #define STA_REC_HE_CAP_ER_SU_PPDU_4LTF_8US_GI BIT(16) 908 #define STA_REC_HE_CAP_NDP_4LTF_3DOT2MS_GI BIT(17) 909 /* 242 TONE */ 910 #define STA_REC_HE_CAP_BW20_RU242_SUPPORT BIT(18) 911 #define STA_REC_HE_CAP_TX_1024QAM_UNDER_RU242 BIT(19) 912 #define STA_REC_HE_CAP_RX_1024QAM_UNDER_RU242 BIT(20) 913 914 #define PHY_MODE_A BIT(0) 915 #define PHY_MODE_B BIT(1) 916 #define PHY_MODE_G BIT(2) 917 #define PHY_MODE_GN BIT(3) 918 #define PHY_MODE_AN BIT(4) 919 #define PHY_MODE_AC BIT(5) 920 #define PHY_MODE_AX_24G BIT(6) 921 #define PHY_MODE_AX_5G BIT(7) 922 923 #define PHY_MODE_AX_6G BIT(0) /* phymode_ext */ 924 #define PHY_MODE_BE_24G BIT(1) 925 #define PHY_MODE_BE_5G BIT(2) 926 #define PHY_MODE_BE_6G BIT(3) 927 928 #define MODE_CCK BIT(0) 929 #define MODE_OFDM BIT(1) 930 #define MODE_HT BIT(2) 931 #define MODE_VHT BIT(3) 932 #define MODE_HE BIT(4) 933 #define MODE_EHT BIT(5) 934 935 #define STA_CAP_WMM BIT(0) 936 #define STA_CAP_SGI_20 BIT(4) 937 #define STA_CAP_SGI_40 BIT(5) 938 #define STA_CAP_TX_STBC BIT(6) 939 #define STA_CAP_RX_STBC BIT(7) 940 #define STA_CAP_VHT_SGI_80 BIT(16) 941 #define STA_CAP_VHT_SGI_160 BIT(17) 942 #define STA_CAP_VHT_TX_STBC BIT(18) 943 #define STA_CAP_VHT_RX_STBC BIT(19) 944 #define STA_CAP_VHT_LDPC BIT(23) 945 #define STA_CAP_LDPC BIT(24) 946 #define STA_CAP_HT BIT(26) 947 #define STA_CAP_VHT BIT(27) 948 #define STA_CAP_HE BIT(28) 949 950 enum { 951 PHY_TYPE_HR_DSSS_INDEX = 0, 952 PHY_TYPE_ERP_INDEX, 953 PHY_TYPE_ERP_P2P_INDEX, 954 PHY_TYPE_OFDM_INDEX, 955 PHY_TYPE_HT_INDEX, 956 PHY_TYPE_VHT_INDEX, 957 PHY_TYPE_HE_INDEX, 958 PHY_TYPE_BE_INDEX, 959 PHY_TYPE_INDEX_NUM 960 }; 961 962 #define HR_DSSS_ERP_BASIC_RATE GENMASK(3, 0) 963 #define OFDM_BASIC_RATE (BIT(6) | BIT(8) | BIT(10)) 964 965 #define PHY_TYPE_BIT_HR_DSSS BIT(PHY_TYPE_HR_DSSS_INDEX) 966 #define PHY_TYPE_BIT_ERP BIT(PHY_TYPE_ERP_INDEX) 967 #define PHY_TYPE_BIT_OFDM BIT(PHY_TYPE_OFDM_INDEX) 968 #define PHY_TYPE_BIT_HT BIT(PHY_TYPE_HT_INDEX) 969 #define PHY_TYPE_BIT_VHT BIT(PHY_TYPE_VHT_INDEX) 970 #define PHY_TYPE_BIT_HE BIT(PHY_TYPE_HE_INDEX) 971 #define PHY_TYPE_BIT_BE BIT(PHY_TYPE_BE_INDEX) 972 973 #define MT_WTBL_RATE_TX_MODE GENMASK(9, 6) 974 #define MT_WTBL_RATE_MCS GENMASK(5, 0) 975 #define MT_WTBL_RATE_NSS GENMASK(12, 10) 976 #define MT_WTBL_RATE_HE_GI GENMASK(7, 4) 977 #define MT_WTBL_RATE_GI GENMASK(3, 0) 978 979 #define MT_WTBL_W5_CHANGE_BW_RATE GENMASK(7, 5) 980 #define MT_WTBL_W5_SHORT_GI_20 BIT(8) 981 #define MT_WTBL_W5_SHORT_GI_40 BIT(9) 982 #define MT_WTBL_W5_SHORT_GI_80 BIT(10) 983 #define MT_WTBL_W5_SHORT_GI_160 BIT(11) 984 #define MT_WTBL_W5_BW_CAP GENMASK(13, 12) 985 #define MT_WTBL_W5_MPDU_FAIL_COUNT GENMASK(25, 23) 986 #define MT_WTBL_W5_MPDU_OK_COUNT GENMASK(28, 26) 987 #define MT_WTBL_W5_RATE_IDX GENMASK(31, 29) 988 989 enum { 990 WTBL_RESET_AND_SET = 1, 991 WTBL_SET, 992 WTBL_QUERY, 993 WTBL_RESET_ALL 994 }; 995 996 enum { 997 MT_BA_TYPE_INVALID, 998 MT_BA_TYPE_ORIGINATOR, 999 MT_BA_TYPE_RECIPIENT 1000 }; 1001 1002 enum { 1003 RST_BA_MAC_TID_MATCH, 1004 RST_BA_MAC_MATCH, 1005 RST_BA_NO_MATCH 1006 }; 1007 1008 enum { 1009 DEV_INFO_ACTIVE, 1010 DEV_INFO_MAX_NUM 1011 }; 1012 1013 /* event table */ 1014 enum { 1015 MCU_EVENT_TARGET_ADDRESS_LEN = 0x01, 1016 MCU_EVENT_FW_START = 0x01, 1017 MCU_EVENT_GENERIC = 0x01, 1018 MCU_EVENT_ACCESS_REG = 0x02, 1019 MCU_EVENT_MT_PATCH_SEM = 0x04, 1020 MCU_EVENT_REG_ACCESS = 0x05, 1021 MCU_EVENT_LP_INFO = 0x07, 1022 MCU_EVENT_SCAN_DONE = 0x0d, 1023 MCU_EVENT_TX_DONE = 0x0f, 1024 MCU_EVENT_ROC = 0x10, 1025 MCU_EVENT_BSS_ABSENCE = 0x11, 1026 MCU_EVENT_BSS_BEACON_LOSS = 0x13, 1027 MCU_EVENT_CH_PRIVILEGE = 0x18, 1028 MCU_EVENT_SCHED_SCAN_DONE = 0x23, 1029 MCU_EVENT_DBG_MSG = 0x27, 1030 MCU_EVENT_RSSI_NOTIFY = 0x96, 1031 MCU_EVENT_TXPWR = 0xd0, 1032 MCU_EVENT_EXT = 0xed, 1033 MCU_EVENT_RESTART_DL = 0xef, 1034 MCU_EVENT_COREDUMP = 0xf0, 1035 }; 1036 1037 /* ext event table */ 1038 enum { 1039 MCU_EXT_EVENT_PS_SYNC = 0x5, 1040 MCU_EXT_EVENT_FW_LOG_2_HOST = 0x13, 1041 MCU_EXT_EVENT_THERMAL_PROTECT = 0x22, 1042 MCU_EXT_EVENT_ASSERT_DUMP = 0x23, 1043 MCU_EXT_EVENT_RDD_REPORT = 0x3a, 1044 MCU_EXT_EVENT_CSA_NOTIFY = 0x4f, 1045 MCU_EXT_EVENT_WA_TX_STAT = 0x74, 1046 MCU_EXT_EVENT_BCC_NOTIFY = 0x75, 1047 MCU_EXT_EVENT_WF_RF_PIN_CTRL = 0x9a, 1048 MCU_EXT_EVENT_MURU_CTRL = 0x9f, 1049 }; 1050 1051 /* unified event table */ 1052 enum { 1053 MCU_UNI_EVENT_RESULT = 0x01, 1054 MCU_UNI_EVENT_HIF_CTRL = 0x03, 1055 MCU_UNI_EVENT_FW_LOG_2_HOST = 0x04, 1056 MCU_UNI_EVENT_ACCESS_REG = 0x6, 1057 MCU_UNI_EVENT_IE_COUNTDOWN = 0x09, 1058 MCU_UNI_EVENT_COREDUMP = 0x0a, 1059 MCU_UNI_EVENT_BSS_BEACON_LOSS = 0x0c, 1060 MCU_UNI_EVENT_SCAN_DONE = 0x0e, 1061 MCU_UNI_EVENT_RDD_REPORT = 0x11, 1062 MCU_UNI_EVENT_ROC = 0x27, 1063 MCU_UNI_EVENT_TX_DONE = 0x2d, 1064 MCU_UNI_EVENT_THERMAL = 0x35, 1065 MCU_UNI_EVENT_NIC_CAPAB = 0x43, 1066 MCU_UNI_EVENT_WED_RRO = 0x57, 1067 MCU_UNI_EVENT_PER_STA_INFO = 0x6d, 1068 MCU_UNI_EVENT_ALL_STA_INFO = 0x6e, 1069 MCU_UNI_EVENT_SDO = 0x83, 1070 }; 1071 1072 #define MCU_UNI_CMD_EVENT BIT(1) 1073 #define MCU_UNI_CMD_UNSOLICITED_EVENT BIT(2) 1074 1075 enum { 1076 MCU_Q_QUERY, 1077 MCU_Q_SET, 1078 MCU_Q_RESERVED, 1079 MCU_Q_NA 1080 }; 1081 1082 enum { 1083 MCU_S2D_H2N, 1084 MCU_S2D_C2N, 1085 MCU_S2D_H2C, 1086 MCU_S2D_H2CN 1087 }; 1088 1089 enum { 1090 PATCH_NOT_DL_SEM_FAIL, 1091 PATCH_IS_DL, 1092 PATCH_NOT_DL_SEM_SUCCESS, 1093 PATCH_REL_SEM_SUCCESS 1094 }; 1095 1096 enum { 1097 FW_STATE_INITIAL, 1098 FW_STATE_FW_DOWNLOAD, 1099 FW_STATE_NORMAL_OPERATION, 1100 FW_STATE_NORMAL_TRX, 1101 FW_STATE_RDY = 7 1102 }; 1103 1104 enum { 1105 CH_SWITCH_NORMAL = 0, 1106 CH_SWITCH_SCAN = 3, 1107 CH_SWITCH_MCC = 4, 1108 CH_SWITCH_DFS = 5, 1109 CH_SWITCH_BACKGROUND_SCAN_START = 6, 1110 CH_SWITCH_BACKGROUND_SCAN_RUNNING = 7, 1111 CH_SWITCH_BACKGROUND_SCAN_STOP = 8, 1112 CH_SWITCH_SCAN_BYPASS_DPD = 9 1113 }; 1114 1115 enum { 1116 THERMAL_SENSOR_TEMP_QUERY, 1117 THERMAL_SENSOR_MANUAL_CTRL, 1118 THERMAL_SENSOR_INFO_QUERY, 1119 THERMAL_SENSOR_TASK_CTRL, 1120 }; 1121 1122 enum mcu_cipher_type { 1123 MCU_CIPHER_NONE = 0, 1124 MCU_CIPHER_WEP40, 1125 MCU_CIPHER_WEP104, 1126 MCU_CIPHER_WEP128, 1127 MCU_CIPHER_TKIP, 1128 MCU_CIPHER_AES_CCMP, 1129 MCU_CIPHER_CCMP_256, 1130 MCU_CIPHER_GCMP, 1131 MCU_CIPHER_GCMP_256, 1132 MCU_CIPHER_WAPI, 1133 MCU_CIPHER_BIP_CMAC_128, 1134 MCU_CIPHER_BIP_CMAC_256, 1135 MCU_CIPHER_BCN_PROT_CMAC_128, 1136 MCU_CIPHER_BCN_PROT_CMAC_256, 1137 MCU_CIPHER_BCN_PROT_GMAC_128, 1138 MCU_CIPHER_BCN_PROT_GMAC_256, 1139 MCU_CIPHER_BIP_GMAC_128, 1140 MCU_CIPHER_BIP_GMAC_256, 1141 }; 1142 1143 enum { 1144 EE_MODE_EFUSE, 1145 EE_MODE_BUFFER, 1146 }; 1147 1148 enum { 1149 EE_FORMAT_BIN, 1150 EE_FORMAT_WHOLE, 1151 EE_FORMAT_MULTIPLE, 1152 }; 1153 1154 enum { 1155 MCU_PHY_STATE_TX_RATE, 1156 MCU_PHY_STATE_RX_RATE, 1157 MCU_PHY_STATE_RSSI, 1158 MCU_PHY_STATE_CONTENTION_RX_RATE, 1159 MCU_PHY_STATE_OFDMLQ_CNINFO, 1160 }; 1161 1162 #define MCU_CMD_ACK BIT(0) 1163 #define MCU_CMD_UNI BIT(1) 1164 #define MCU_CMD_SET BIT(2) 1165 1166 #define MCU_CMD_UNI_EXT_ACK (MCU_CMD_ACK | MCU_CMD_UNI | \ 1167 MCU_CMD_SET) 1168 #define MCU_CMD_UNI_QUERY_ACK (MCU_CMD_ACK | MCU_CMD_UNI) 1169 1170 #define __MCU_CMD_FIELD_ID GENMASK(7, 0) 1171 #define __MCU_CMD_FIELD_EXT_ID GENMASK(15, 8) 1172 #define __MCU_CMD_FIELD_QUERY BIT(16) 1173 #define __MCU_CMD_FIELD_UNI BIT(17) 1174 #define __MCU_CMD_FIELD_CE BIT(18) 1175 #define __MCU_CMD_FIELD_WA BIT(19) 1176 #define __MCU_CMD_FIELD_WM BIT(20) 1177 1178 #define MCU_CMD(_t) FIELD_PREP(__MCU_CMD_FIELD_ID, \ 1179 MCU_CMD_##_t) 1180 #define MCU_EXT_CMD(_t) (MCU_CMD(EXT_CID) | \ 1181 FIELD_PREP(__MCU_CMD_FIELD_EXT_ID, \ 1182 MCU_EXT_CMD_##_t)) 1183 #define MCU_EXT_QUERY(_t) (MCU_EXT_CMD(_t) | __MCU_CMD_FIELD_QUERY) 1184 #define MCU_UNI_CMD(_t) (__MCU_CMD_FIELD_UNI | \ 1185 FIELD_PREP(__MCU_CMD_FIELD_ID, \ 1186 MCU_UNI_CMD_##_t)) 1187 1188 #define MCU_UNI_QUERY(_t) (__MCU_CMD_FIELD_UNI | __MCU_CMD_FIELD_QUERY | \ 1189 FIELD_PREP(__MCU_CMD_FIELD_ID, \ 1190 MCU_UNI_CMD_##_t)) 1191 1192 #define MCU_CE_CMD(_t) (__MCU_CMD_FIELD_CE | \ 1193 FIELD_PREP(__MCU_CMD_FIELD_ID, \ 1194 MCU_CE_CMD_##_t)) 1195 #define MCU_CE_QUERY(_t) (MCU_CE_CMD(_t) | __MCU_CMD_FIELD_QUERY) 1196 1197 #define MCU_WA_CMD(_t) (MCU_CMD(_t) | __MCU_CMD_FIELD_WA) 1198 #define MCU_WA_EXT_CMD(_t) (MCU_EXT_CMD(_t) | __MCU_CMD_FIELD_WA) 1199 #define MCU_WA_PARAM_CMD(_t) (MCU_WA_CMD(WA_PARAM) | \ 1200 FIELD_PREP(__MCU_CMD_FIELD_EXT_ID, \ 1201 MCU_WA_PARAM_CMD_##_t)) 1202 1203 #define MCU_WM_UNI_CMD(_t) (MCU_UNI_CMD(_t) | \ 1204 __MCU_CMD_FIELD_WM) 1205 #define MCU_WM_UNI_CMD_QUERY(_t) (MCU_UNI_CMD(_t) | \ 1206 __MCU_CMD_FIELD_QUERY | \ 1207 __MCU_CMD_FIELD_WM) 1208 #define MCU_WA_UNI_CMD(_t) (MCU_UNI_CMD(_t) | \ 1209 __MCU_CMD_FIELD_WA) 1210 #define MCU_WMWA_UNI_CMD(_t) (MCU_WM_UNI_CMD(_t) | \ 1211 __MCU_CMD_FIELD_WA) 1212 1213 enum { 1214 MCU_EXT_CMD_EFUSE_ACCESS = 0x01, 1215 MCU_EXT_CMD_RF_REG_ACCESS = 0x02, 1216 MCU_EXT_CMD_RF_TEST = 0x04, 1217 MCU_EXT_CMD_ID_RADIO_ON_OFF_CTRL = 0x05, 1218 MCU_EXT_CMD_PM_STATE_CTRL = 0x07, 1219 MCU_EXT_CMD_CHANNEL_SWITCH = 0x08, 1220 MCU_EXT_CMD_SET_TX_POWER_CTRL = 0x11, 1221 MCU_EXT_CMD_FW_LOG_2_HOST = 0x13, 1222 MCU_EXT_CMD_TXBF_ACTION = 0x1e, 1223 MCU_EXT_CMD_EFUSE_BUFFER_MODE = 0x21, 1224 MCU_EXT_CMD_THERMAL_PROT = 0x23, 1225 MCU_EXT_CMD_STA_REC_UPDATE = 0x25, 1226 MCU_EXT_CMD_BSS_INFO_UPDATE = 0x26, 1227 MCU_EXT_CMD_EDCA_UPDATE = 0x27, 1228 MCU_EXT_CMD_DEV_INFO_UPDATE = 0x2A, 1229 MCU_EXT_CMD_THERMAL_CTRL = 0x2c, 1230 MCU_EXT_CMD_WTBL_UPDATE = 0x32, 1231 MCU_EXT_CMD_SET_DRR_CTRL = 0x36, 1232 MCU_EXT_CMD_SET_RDD_CTRL = 0x3a, 1233 MCU_EXT_CMD_ATE_CTRL = 0x3d, 1234 MCU_EXT_CMD_PROTECT_CTRL = 0x3e, 1235 MCU_EXT_CMD_DBDC_CTRL = 0x45, 1236 MCU_EXT_CMD_MAC_INIT_CTRL = 0x46, 1237 MCU_EXT_CMD_RX_HDR_TRANS = 0x47, 1238 MCU_EXT_CMD_MUAR_UPDATE = 0x48, 1239 MCU_EXT_CMD_BCN_OFFLOAD = 0x49, 1240 MCU_EXT_CMD_RX_AIRTIME_CTRL = 0x4a, 1241 MCU_EXT_CMD_SET_RX_PATH = 0x4e, 1242 MCU_EXT_CMD_EFUSE_FREE_BLOCK = 0x4f, 1243 MCU_EXT_CMD_TX_POWER_FEATURE_CTRL = 0x58, 1244 MCU_EXT_CMD_RXDCOC_CAL = 0x59, 1245 MCU_EXT_CMD_GET_MIB_INFO = 0x5a, 1246 MCU_EXT_CMD_TXDPD_CAL = 0x60, 1247 MCU_EXT_CMD_CAL_CACHE = 0x67, 1248 MCU_EXT_CMD_RED_ENABLE = 0x68, 1249 MCU_EXT_CMD_CP_SUPPORT = 0x75, 1250 MCU_EXT_CMD_SET_RADAR_TH = 0x7c, 1251 MCU_EXT_CMD_SET_RDD_PATTERN = 0x7d, 1252 MCU_EXT_CMD_MWDS_SUPPORT = 0x80, 1253 MCU_EXT_CMD_SET_SER_TRIGGER = 0x81, 1254 MCU_EXT_CMD_TWT_AGRT_UPDATE = 0x94, 1255 MCU_EXT_CMD_FW_DBG_CTRL = 0x95, 1256 MCU_EXT_CMD_OFFCH_SCAN_CTRL = 0x9a, 1257 MCU_EXT_CMD_SET_RDD_TH = 0x9d, 1258 MCU_EXT_CMD_MURU_CTRL = 0x9f, 1259 MCU_EXT_CMD_SET_SPR = 0xa8, 1260 MCU_EXT_CMD_GROUP_PRE_CAL_INFO = 0xab, 1261 MCU_EXT_CMD_DPD_PRE_CAL_INFO = 0xac, 1262 MCU_EXT_CMD_PHY_STAT_INFO = 0xad, 1263 MCU_EXT_CMD_WF_RF_PIN_CTRL = 0xbd, 1264 }; 1265 1266 enum { 1267 MCU_UNI_CMD_DEV_INFO_UPDATE = 0x01, 1268 MCU_UNI_CMD_BSS_INFO_UPDATE = 0x02, 1269 MCU_UNI_CMD_STA_REC_UPDATE = 0x03, 1270 MCU_UNI_CMD_EDCA_UPDATE = 0x04, 1271 MCU_UNI_CMD_SUSPEND = 0x05, 1272 MCU_UNI_CMD_OFFLOAD = 0x06, 1273 MCU_UNI_CMD_HIF_CTRL = 0x07, 1274 MCU_UNI_CMD_BAND_CONFIG = 0x08, 1275 MCU_UNI_CMD_REPT_MUAR = 0x09, 1276 MCU_UNI_CMD_WSYS_CONFIG = 0x0b, 1277 MCU_UNI_CMD_REG_ACCESS = 0x0d, 1278 MCU_UNI_CMD_CHIP_CONFIG = 0x0e, 1279 MCU_UNI_CMD_POWER_CTRL = 0x0f, 1280 MCU_UNI_CMD_RX_HDR_TRANS = 0x12, 1281 MCU_UNI_CMD_SER = 0x13, 1282 MCU_UNI_CMD_TWT = 0x14, 1283 MCU_UNI_CMD_SET_DOMAIN_INFO = 0x15, 1284 MCU_UNI_CMD_SCAN_REQ = 0x16, 1285 MCU_UNI_CMD_RDD_CTRL = 0x19, 1286 MCU_UNI_CMD_GET_MIB_INFO = 0x22, 1287 MCU_UNI_CMD_GET_STAT_INFO = 0x23, 1288 MCU_UNI_CMD_SNIFFER = 0x24, 1289 MCU_UNI_CMD_SR = 0x25, 1290 MCU_UNI_CMD_ROC = 0x27, 1291 MCU_UNI_CMD_SET_DBDC_PARMS = 0x28, 1292 MCU_UNI_CMD_TXPOWER = 0x2b, 1293 MCU_UNI_CMD_SET_POWER_LIMIT = 0x2c, 1294 MCU_UNI_CMD_EFUSE_CTRL = 0x2d, 1295 MCU_UNI_CMD_RA = 0x2f, 1296 MCU_UNI_CMD_MURU = 0x31, 1297 MCU_UNI_CMD_TESTMODE_RX_STAT = 0x32, 1298 MCU_UNI_CMD_BF = 0x33, 1299 MCU_UNI_CMD_CHANNEL_SWITCH = 0x34, 1300 MCU_UNI_CMD_THERMAL = 0x35, 1301 MCU_UNI_CMD_VOW = 0x37, 1302 MCU_UNI_CMD_FIXED_RATE_TABLE = 0x40, 1303 MCU_UNI_CMD_TESTMODE_CTRL = 0x46, 1304 MCU_UNI_CMD_RRO = 0x57, 1305 MCU_UNI_CMD_OFFCH_SCAN_CTRL = 0x58, 1306 MCU_UNI_CMD_PER_STA_INFO = 0x6d, 1307 MCU_UNI_CMD_ALL_STA_INFO = 0x6e, 1308 MCU_UNI_CMD_ASSERT_DUMP = 0x6f, 1309 MCU_UNI_CMD_RADIO_STATUS = 0x80, 1310 MCU_UNI_CMD_SDO = 0x88, 1311 }; 1312 1313 enum { 1314 MCU_CMD_TARGET_ADDRESS_LEN_REQ = 0x01, 1315 MCU_CMD_FW_START_REQ = 0x02, 1316 MCU_CMD_INIT_ACCESS_REG = 0x3, 1317 MCU_CMD_NIC_POWER_CTRL = 0x4, 1318 MCU_CMD_PATCH_START_REQ = 0x05, 1319 MCU_CMD_PATCH_FINISH_REQ = 0x07, 1320 MCU_CMD_PATCH_SEM_CONTROL = 0x10, 1321 MCU_CMD_WA_PARAM = 0xc4, 1322 MCU_CMD_EXT_CID = 0xed, 1323 MCU_CMD_FW_SCATTER = 0xee, 1324 MCU_CMD_RESTART_DL_REQ = 0xef, 1325 }; 1326 1327 /* offload mcu commands */ 1328 enum { 1329 MCU_CE_CMD_TEST_CTRL = 0x01, 1330 MCU_CE_CMD_START_HW_SCAN = 0x03, 1331 MCU_CE_CMD_SET_PS_PROFILE = 0x05, 1332 MCU_CE_CMD_SET_RX_FILTER = 0x0a, 1333 MCU_CE_CMD_SET_CHAN_DOMAIN = 0x0f, 1334 MCU_CE_CMD_SET_BSS_CONNECTED = 0x16, 1335 MCU_CE_CMD_SET_BSS_ABORT = 0x17, 1336 MCU_CE_CMD_CANCEL_HW_SCAN = 0x1b, 1337 MCU_CE_CMD_SET_ROC = 0x1c, 1338 MCU_CE_CMD_SET_EDCA_PARMS = 0x1d, 1339 MCU_CE_CMD_SET_P2P_OPPPS = 0x33, 1340 MCU_CE_CMD_SET_CLC = 0x5c, 1341 MCU_CE_CMD_SET_RATE_TX_POWER = 0x5d, 1342 MCU_CE_CMD_SCHED_SCAN_ENABLE = 0x61, 1343 MCU_CE_CMD_SCHED_SCAN_REQ = 0x62, 1344 MCU_CE_CMD_GET_NIC_CAPAB = 0x8a, 1345 MCU_CE_CMD_RSSI_MONITOR = 0xa1, 1346 MCU_CE_CMD_SET_MU_EDCA_PARMS = 0xb0, 1347 MCU_CE_CMD_REG_WRITE = 0xc0, 1348 MCU_CE_CMD_REG_READ = 0xc0, 1349 MCU_CE_CMD_CHIP_CONFIG = 0xca, 1350 MCU_CE_CMD_FWLOG_2_HOST = 0xc5, 1351 MCU_CE_CMD_GET_WTBL = 0xcd, 1352 MCU_CE_CMD_GET_TXPWR = 0xd0, 1353 }; 1354 1355 enum { 1356 PATCH_SEM_RELEASE, 1357 PATCH_SEM_GET 1358 }; 1359 1360 enum { 1361 UNI_BSS_INFO_BASIC = 0, 1362 UNI_BSS_INFO_RA = 1, 1363 UNI_BSS_INFO_RLM = 2, 1364 UNI_BSS_INFO_BSS_COLOR = 4, 1365 UNI_BSS_INFO_HE_BASIC = 5, 1366 UNI_BSS_INFO_11V_MBSSID = 6, 1367 UNI_BSS_INFO_BCN_CONTENT = 7, 1368 UNI_BSS_INFO_BCN_CSA = 8, 1369 UNI_BSS_INFO_BCN_BCC = 9, 1370 UNI_BSS_INFO_BCN_MBSSID = 10, 1371 UNI_BSS_INFO_RATE = 11, 1372 UNI_BSS_INFO_QBSS = 15, 1373 UNI_BSS_INFO_SEC = 16, 1374 UNI_BSS_INFO_BCN_PROT = 17, 1375 UNI_BSS_INFO_TXCMD = 18, 1376 UNI_BSS_INFO_UAPSD = 19, 1377 UNI_BSS_INFO_PS = 21, 1378 UNI_BSS_INFO_BCNFT = 22, 1379 UNI_BSS_INFO_IFS_TIME = 23, 1380 UNI_BSS_INFO_OFFLOAD = 25, 1381 UNI_BSS_INFO_MLD = 26, 1382 UNI_BSS_INFO_PM_DISABLE = 27, 1383 UNI_BSS_INFO_EHT = 30, 1384 }; 1385 1386 enum { 1387 UNI_OFFLOAD_OFFLOAD_ARP, 1388 UNI_OFFLOAD_OFFLOAD_ND, 1389 UNI_OFFLOAD_OFFLOAD_GTK_REKEY, 1390 UNI_OFFLOAD_OFFLOAD_BMC_RPY_DETECT, 1391 }; 1392 1393 enum UNI_ALL_STA_INFO_TAG { 1394 UNI_ALL_STA_TXRX_RATE, 1395 UNI_ALL_STA_TX_STAT, 1396 UNI_ALL_STA_TXRX_ADM_STAT, 1397 UNI_ALL_STA_TXRX_AIR_TIME, 1398 UNI_ALL_STA_DATA_TX_RETRY_COUNT, 1399 UNI_ALL_STA_GI_MODE, 1400 UNI_ALL_STA_TXRX_MSDU_COUNT, 1401 UNI_ALL_STA_MAX_NUM 1402 }; 1403 1404 enum { 1405 MT_NIC_CAP_TX_RESOURCE, 1406 MT_NIC_CAP_TX_EFUSE_ADDR, 1407 MT_NIC_CAP_COEX, 1408 MT_NIC_CAP_SINGLE_SKU, 1409 MT_NIC_CAP_CSUM_OFFLOAD, 1410 MT_NIC_CAP_HW_VER, 1411 MT_NIC_CAP_SW_VER, 1412 MT_NIC_CAP_MAC_ADDR, 1413 MT_NIC_CAP_PHY, 1414 MT_NIC_CAP_MAC, 1415 MT_NIC_CAP_FRAME_BUF, 1416 MT_NIC_CAP_BEAM_FORM, 1417 MT_NIC_CAP_LOCATION, 1418 MT_NIC_CAP_MUMIMO, 1419 MT_NIC_CAP_BUFFER_MODE_INFO, 1420 MT_NIC_CAP_HW_ADIE_VERSION = 0x14, 1421 MT_NIC_CAP_ANTSWP = 0x16, 1422 MT_NIC_CAP_WFDMA_REALLOC, 1423 MT_NIC_CAP_6G, 1424 MT_NIC_CAP_CHIP_CAP = 0x20, 1425 MT_NIC_CAP_EML_CAP = 0x22, 1426 }; 1427 1428 #define UNI_WOW_DETECT_TYPE_MAGIC BIT(0) 1429 #define UNI_WOW_DETECT_TYPE_ANY BIT(1) 1430 #define UNI_WOW_DETECT_TYPE_DISCONNECT BIT(2) 1431 #define UNI_WOW_DETECT_TYPE_GTK_REKEY_FAIL BIT(3) 1432 #define UNI_WOW_DETECT_TYPE_BCN_LOST BIT(4) 1433 #define UNI_WOW_DETECT_TYPE_SCH_SCAN_HIT BIT(5) 1434 #define UNI_WOW_DETECT_TYPE_BITMAP BIT(6) 1435 1436 enum { 1437 UNI_SUSPEND_MODE_SETTING, 1438 UNI_SUSPEND_WOW_CTRL, 1439 UNI_SUSPEND_WOW_GPIO_PARAM, 1440 UNI_SUSPEND_WOW_WAKEUP_PORT, 1441 UNI_SUSPEND_WOW_PATTERN, 1442 }; 1443 1444 enum { 1445 WOW_USB = 1, 1446 WOW_PCIE = 2, 1447 WOW_GPIO = 3, 1448 }; 1449 1450 struct mt76_connac_bss_basic_tlv { 1451 __le16 tag; 1452 __le16 len; 1453 u8 active; 1454 u8 omac_idx; 1455 u8 hw_bss_idx; 1456 u8 band_idx; 1457 __le32 conn_type; 1458 u8 conn_state; 1459 u8 wmm_idx; 1460 u8 bssid[ETH_ALEN]; 1461 __le16 bmc_tx_wlan_idx; 1462 __le16 bcn_interval; 1463 u8 dtim_period; 1464 u8 phymode; /* bit(0): A 1465 * bit(1): B 1466 * bit(2): G 1467 * bit(3): GN 1468 * bit(4): AN 1469 * bit(5): AC 1470 * bit(6): AX2 1471 * bit(7): AX5 1472 * bit(8): AX6 1473 */ 1474 __le16 sta_idx; 1475 __le16 nonht_basic_phy; 1476 u8 phymode_ext; /* bit(0) AX_6G */ 1477 u8 link_idx; 1478 } __packed; 1479 1480 struct mt76_connac_bss_qos_tlv { 1481 __le16 tag; 1482 __le16 len; 1483 u8 qos; 1484 u8 pad[3]; 1485 } __packed; 1486 1487 struct mt76_connac_beacon_loss_event { 1488 u8 bss_idx; 1489 u8 reason; 1490 u8 pad[2]; 1491 } __packed; 1492 1493 struct mt76_connac_rssi_notify_event { 1494 __le32 rssi[4]; 1495 } __packed; 1496 1497 struct mt76_connac_mcu_bss_event { 1498 u8 bss_idx; 1499 u8 is_absent; 1500 u8 free_quota; 1501 u8 pad; 1502 } __packed; 1503 1504 struct mt76_connac_mcu_scan_ssid { 1505 __le32 ssid_len; 1506 u8 ssid[IEEE80211_MAX_SSID_LEN]; 1507 } __packed; 1508 1509 struct mt76_connac_mcu_scan_channel { 1510 u8 band; /* 1: 2.4GHz 1511 * 2: 5.0GHz 1512 * Others: Reserved 1513 */ 1514 u8 channel_num; 1515 } __packed; 1516 1517 struct mt76_connac_mcu_scan_match { 1518 __le32 rssi_th; 1519 u8 ssid[IEEE80211_MAX_SSID_LEN]; 1520 u8 ssid_len; 1521 u8 rsv[3]; 1522 } __packed; 1523 1524 struct mt76_connac_hw_scan_req { 1525 u8 seq_num; 1526 u8 bss_idx; 1527 u8 scan_type; /* 0: PASSIVE SCAN 1528 * 1: ACTIVE SCAN 1529 */ 1530 u8 ssid_type; /* BIT(0) wildcard SSID 1531 * BIT(1) P2P wildcard SSID 1532 * BIT(2) specified SSID + wildcard SSID 1533 * BIT(2) + ssid_type_ext BIT(0) specified SSID only 1534 */ 1535 u8 ssids_num; 1536 u8 probe_req_num; /* Number of probe request for each SSID */ 1537 u8 scan_func; /* BIT(0) Enable random MAC scan 1538 * BIT(1) Disable DBDC scan type 1~3. 1539 * BIT(2) Use DBDC scan type 3 (dedicated one RF to scan). 1540 */ 1541 u8 version; /* 0: Not support fields after ies. 1542 * 1: Support fields after ies. 1543 */ 1544 struct mt76_connac_mcu_scan_ssid ssids[4]; 1545 __le16 probe_delay_time; 1546 __le16 channel_dwell_time; /* channel Dwell interval */ 1547 __le16 timeout_value; 1548 u8 channel_type; /* 0: Full channels 1549 * 1: Only 2.4GHz channels 1550 * 2: Only 5GHz channels 1551 * 3: P2P social channel only (channel #1, #6 and #11) 1552 * 4: Specified channels 1553 * Others: Reserved 1554 */ 1555 u8 channels_num; /* valid when channel_type is 4 */ 1556 /* valid when channels_num is set */ 1557 struct mt76_connac_mcu_scan_channel channels[32]; 1558 __le16 ies_len; 1559 u8 ies[MT76_CONNAC_SCAN_IE_LEN]; 1560 /* following fields are valid if version > 0 */ 1561 u8 ext_channels_num; 1562 u8 ext_ssids_num; 1563 __le16 channel_min_dwell_time; 1564 struct mt76_connac_mcu_scan_channel ext_channels[32]; 1565 struct mt76_connac_mcu_scan_ssid ext_ssids[6]; 1566 u8 bssid[ETH_ALEN]; 1567 u8 random_mac[ETH_ALEN]; /* valid when BIT(1) in scan_func is set. */ 1568 u8 pad[63]; 1569 u8 ssid_type_ext; 1570 } __packed; 1571 1572 #define MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM 64 1573 1574 struct mt76_connac_hw_scan_done { 1575 u8 seq_num; 1576 u8 sparse_channel_num; 1577 struct mt76_connac_mcu_scan_channel sparse_channel; 1578 u8 complete_channel_num; 1579 u8 current_state; 1580 u8 version; 1581 u8 pad; 1582 __le32 beacon_scan_num; 1583 u8 pno_enabled; 1584 u8 pad2[3]; 1585 u8 sparse_channel_valid_num; 1586 u8 pad3[3]; 1587 u8 channel_num[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM]; 1588 /* idle format for channel_idle_time 1589 * 0: first bytes: idle time(ms) 2nd byte: dwell time(ms) 1590 * 1: first bytes: idle time(8ms) 2nd byte: dwell time(8ms) 1591 * 2: dwell time (16us) 1592 */ 1593 __le16 channel_idle_time[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM]; 1594 /* beacon and probe response count */ 1595 u8 beacon_probe_num[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM]; 1596 u8 mdrdy_count[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM]; 1597 __le32 beacon_2g_num; 1598 __le32 beacon_5g_num; 1599 } __packed; 1600 1601 struct mt76_connac_sched_scan_req { 1602 u8 version; 1603 u8 seq_num; 1604 u8 stop_on_match; 1605 u8 ssids_num; 1606 u8 match_num; 1607 u8 pad; 1608 __le16 ie_len; 1609 struct mt76_connac_mcu_scan_ssid ssids[MT76_CONNAC_MAX_SCHED_SCAN_SSID]; 1610 struct mt76_connac_mcu_scan_match match[MT76_CONNAC_MAX_SCAN_MATCH]; 1611 u8 channel_type; 1612 u8 channels_num; 1613 u8 intervals_num; 1614 u8 scan_func; /* MT7663: BIT(0) eable random mac address */ 1615 struct mt76_connac_mcu_scan_channel channels[64]; 1616 __le16 intervals[MT76_CONNAC_MAX_NUM_SCHED_SCAN_INTERVAL]; 1617 union { 1618 struct { 1619 u8 random_mac[ETH_ALEN]; 1620 u8 pad2[58]; 1621 } mt7663; 1622 struct { 1623 u8 bss_idx; 1624 u8 pad1[3]; 1625 __le32 delay; 1626 u8 pad2[12]; 1627 u8 random_mac[ETH_ALEN]; 1628 u8 pad3[38]; 1629 } mt7921; 1630 }; 1631 } __packed; 1632 1633 struct mt76_connac_sched_scan_done { 1634 u8 seq_num; 1635 u8 status; /* 0: ssid found */ 1636 __le16 pad; 1637 } __packed; 1638 1639 struct bss_info_uni_bss_color { 1640 __le16 tag; 1641 __le16 len; 1642 u8 enable; 1643 u8 bss_color; 1644 u8 rsv[2]; 1645 } __packed; 1646 1647 struct bss_info_uni_he { 1648 __le16 tag; 1649 __le16 len; 1650 __le16 he_rts_thres; 1651 u8 he_pe_duration; 1652 u8 su_disable; 1653 __le16 max_nss_mcs[CMD_HE_MCS_BW_NUM]; 1654 u8 rsv[2]; 1655 } __packed; 1656 1657 struct bss_info_uni_mbssid { 1658 __le16 tag; 1659 __le16 len; 1660 u8 max_indicator; 1661 u8 mbss_idx; 1662 u8 tx_bss_omac_idx; 1663 u8 rsv; 1664 } __packed; 1665 1666 struct mt76_connac_gtk_rekey_tlv { 1667 __le16 tag; 1668 __le16 len; 1669 u8 kek[NL80211_KEK_LEN]; 1670 u8 kck[NL80211_KCK_LEN]; 1671 u8 replay_ctr[NL80211_REPLAY_CTR_LEN]; 1672 u8 rekey_mode; /* 0: rekey offload enable 1673 * 1: rekey offload disable 1674 * 2: rekey update 1675 */ 1676 u8 keyid; 1677 u8 option; /* 1: rekey data update without enabling offload */ 1678 u8 pad[1]; 1679 __le32 proto; /* WPA-RSN-WAPI-OPSN */ 1680 __le32 pairwise_cipher; 1681 __le32 group_cipher; 1682 __le32 key_mgmt; /* NONE-PSK-IEEE802.1X */ 1683 __le32 mgmt_group_cipher; 1684 u8 reserverd[4]; 1685 } __packed; 1686 1687 #define MT76_CONNAC_WOW_MASK_MAX_LEN 16 1688 #define MT76_CONNAC_WOW_PATTEN_MAX_LEN 128 1689 1690 struct mt76_connac_wow_pattern_tlv { 1691 __le16 tag; 1692 __le16 len; 1693 u8 index; /* pattern index */ 1694 u8 enable; /* 0: disable 1695 * 1: enable 1696 */ 1697 u8 data_len; /* pattern length */ 1698 u8 pad; 1699 u8 mask[MT76_CONNAC_WOW_MASK_MAX_LEN]; 1700 u8 pattern[MT76_CONNAC_WOW_PATTEN_MAX_LEN]; 1701 u8 rsv[4]; 1702 } __packed; 1703 1704 struct mt76_connac_wow_ctrl_tlv { 1705 __le16 tag; 1706 __le16 len; 1707 u8 cmd; /* 0x1: PM_WOWLAN_REQ_START 1708 * 0x2: PM_WOWLAN_REQ_STOP 1709 * 0x3: PM_WOWLAN_PARAM_CLEAR 1710 */ 1711 u8 trigger; /* 0: NONE 1712 * BIT(0): NL80211_WOWLAN_TRIG_MAGIC_PKT 1713 * BIT(1): NL80211_WOWLAN_TRIG_ANY 1714 * BIT(2): NL80211_WOWLAN_TRIG_DISCONNECT 1715 * BIT(3): NL80211_WOWLAN_TRIG_GTK_REKEY_FAILURE 1716 * BIT(4): BEACON_LOST 1717 * BIT(5): NL80211_WOWLAN_TRIG_NET_DETECT 1718 */ 1719 u8 wakeup_hif; /* 0x0: HIF_SDIO 1720 * 0x1: HIF_USB 1721 * 0x2: HIF_PCIE 1722 * 0x3: HIF_GPIO 1723 */ 1724 u8 pad; 1725 u8 rsv[4]; 1726 } __packed; 1727 1728 struct mt76_connac_wow_gpio_param_tlv { 1729 __le16 tag; 1730 __le16 len; 1731 u8 gpio_pin; 1732 u8 trigger_lvl; 1733 u8 pad[2]; 1734 __le32 gpio_interval; 1735 u8 rsv[4]; 1736 } __packed; 1737 1738 struct mt76_connac_arpns_tlv { 1739 __le16 tag; 1740 __le16 len; 1741 u8 mode; 1742 u8 ips_num; 1743 u8 option; 1744 u8 pad[1]; 1745 } __packed; 1746 1747 struct mt76_connac_suspend_tlv { 1748 __le16 tag; 1749 __le16 len; 1750 u8 enable; /* 0: suspend mode disabled 1751 * 1: suspend mode enabled 1752 */ 1753 u8 mdtim; /* LP parameter */ 1754 u8 wow_suspend; /* 0: update by origin policy 1755 * 1: update by wow dtim 1756 */ 1757 u8 pad[5]; 1758 } __packed; 1759 1760 enum mt76_sta_info_state { 1761 MT76_STA_INFO_STATE_NONE, 1762 MT76_STA_INFO_STATE_AUTH, 1763 MT76_STA_INFO_STATE_ASSOC 1764 }; 1765 1766 struct mt76_sta_cmd_info { 1767 union { 1768 struct ieee80211_sta *sta; 1769 struct ieee80211_link_sta *link_sta; 1770 }; 1771 struct mt76_wcid *wcid; 1772 1773 struct ieee80211_vif *vif; 1774 struct ieee80211_bss_conf *link_conf; 1775 1776 bool offload_fw; 1777 bool enable; 1778 bool newly; 1779 int cmd; 1780 u8 rcpi; 1781 u8 state; 1782 }; 1783 1784 #define MT_SKU_POWER_LIMIT 161 1785 1786 struct mt76_connac_sku_tlv { 1787 u8 channel; 1788 s8 pwr_limit[MT_SKU_POWER_LIMIT]; 1789 } __packed; 1790 1791 struct mt76_connac_tx_power_limit_tlv { 1792 /* DW0 - common info*/ 1793 u8 ver; 1794 u8 pad0; 1795 __le16 len; 1796 /* DW1 - cmd hint */ 1797 u8 n_chan; /* # channel */ 1798 u8 band; /* 2.4GHz - 5GHz - 6GHz */ 1799 u8 last_msg; 1800 u8 pad1; 1801 /* DW3 */ 1802 u8 alpha2[4]; /* regulatory_request.alpha2 */ 1803 u8 pad2[32]; 1804 } __packed; 1805 1806 struct mt76_connac_config { 1807 __le16 id; 1808 u8 type; 1809 u8 resp_type; 1810 __le16 data_size; 1811 __le16 resv; 1812 u8 data[320]; 1813 } __packed; 1814 1815 struct mt76_connac_mcu_uni_event { 1816 u8 cid; 1817 u8 pad[3]; 1818 __le32 status; /* 0: success, others: fail */ 1819 } __packed; 1820 1821 struct mt76_connac_mcu_reg_event { 1822 __le32 reg; 1823 __le32 val; 1824 } __packed; 1825 1826 static inline enum mcu_cipher_type 1827 mt76_connac_mcu_get_cipher(int cipher) 1828 { 1829 switch (cipher) { 1830 case WLAN_CIPHER_SUITE_WEP40: 1831 return MCU_CIPHER_WEP40; 1832 case WLAN_CIPHER_SUITE_WEP104: 1833 return MCU_CIPHER_WEP104; 1834 case WLAN_CIPHER_SUITE_TKIP: 1835 return MCU_CIPHER_TKIP; 1836 case WLAN_CIPHER_SUITE_AES_CMAC: 1837 return MCU_CIPHER_BIP_CMAC_128; 1838 case WLAN_CIPHER_SUITE_CCMP: 1839 return MCU_CIPHER_AES_CCMP; 1840 case WLAN_CIPHER_SUITE_CCMP_256: 1841 return MCU_CIPHER_CCMP_256; 1842 case WLAN_CIPHER_SUITE_GCMP: 1843 return MCU_CIPHER_GCMP; 1844 case WLAN_CIPHER_SUITE_GCMP_256: 1845 return MCU_CIPHER_GCMP_256; 1846 case WLAN_CIPHER_SUITE_BIP_GMAC_128: 1847 return MCU_CIPHER_BIP_GMAC_128; 1848 case WLAN_CIPHER_SUITE_BIP_GMAC_256: 1849 return MCU_CIPHER_BIP_GMAC_256; 1850 case WLAN_CIPHER_SUITE_BIP_CMAC_256: 1851 return MCU_CIPHER_BIP_CMAC_256; 1852 case WLAN_CIPHER_SUITE_SMS4: 1853 return MCU_CIPHER_WAPI; 1854 default: 1855 return MCU_CIPHER_NONE; 1856 } 1857 } 1858 1859 static inline u32 1860 mt76_connac_mcu_gen_dl_mode(struct mt76_dev *dev, u8 feature_set, bool is_wa) 1861 { 1862 u32 ret = 0; 1863 1864 ret |= feature_set & FW_FEATURE_SET_ENCRYPT ? 1865 DL_MODE_ENCRYPT | DL_MODE_RESET_SEC_IV : 0; 1866 if (is_mt7921(dev) || is_mt7925(dev)) 1867 ret |= feature_set & FW_FEATURE_ENCRY_MODE ? 1868 DL_CONFIG_ENCRY_MODE_SEL : 0; 1869 ret |= FIELD_PREP(DL_MODE_KEY_IDX, 1870 FIELD_GET(FW_FEATURE_SET_KEY_IDX, feature_set)); 1871 ret |= DL_MODE_NEED_RSP; 1872 ret |= is_wa ? DL_MODE_WORKING_PDA_CR4 : 0; 1873 1874 return ret; 1875 } 1876 1877 #define to_wcid_lo(id) FIELD_GET(GENMASK(7, 0), (u16)id) 1878 #define to_wcid_hi(id) FIELD_GET(GENMASK(10, 8), (u16)id) 1879 1880 static inline void 1881 mt76_connac_mcu_get_wlan_idx(struct mt76_dev *dev, struct mt76_wcid *wcid, 1882 u8 *wlan_idx_lo, u8 *wlan_idx_hi) 1883 { 1884 *wlan_idx_hi = 0; 1885 1886 if (!is_connac_v1(dev)) { 1887 *wlan_idx_lo = wcid ? to_wcid_lo(wcid->idx) : 0; 1888 *wlan_idx_hi = wcid ? to_wcid_hi(wcid->idx) : 0; 1889 } else { 1890 *wlan_idx_lo = wcid ? wcid->idx : 0; 1891 } 1892 } 1893 1894 struct sk_buff * 1895 __mt76_connac_mcu_alloc_sta_req(struct mt76_dev *dev, struct mt76_vif_link *mvif, 1896 struct mt76_wcid *wcid, int len); 1897 static inline struct sk_buff * 1898 mt76_connac_mcu_alloc_sta_req(struct mt76_dev *dev, struct mt76_vif_link *mvif, 1899 struct mt76_wcid *wcid) 1900 { 1901 return __mt76_connac_mcu_alloc_sta_req(dev, mvif, wcid, 1902 MT76_CONNAC_STA_UPDATE_MAX_SIZE); 1903 } 1904 1905 struct wtbl_req_hdr * 1906 mt76_connac_mcu_alloc_wtbl_req(struct mt76_dev *dev, struct mt76_wcid *wcid, 1907 int cmd, void *sta_wtbl, struct sk_buff **skb); 1908 struct tlv *mt76_connac_mcu_add_nested_tlv(struct sk_buff *skb, int tag, 1909 int len, void *sta_ntlv, 1910 void *sta_wtbl); 1911 static inline struct tlv * 1912 mt76_connac_mcu_add_tlv(struct sk_buff *skb, int tag, int len) 1913 { 1914 return mt76_connac_mcu_add_nested_tlv(skb, tag, len, skb->data, NULL); 1915 } 1916 1917 int mt76_connac_mcu_set_channel_domain(struct mt76_phy *phy); 1918 int mt76_connac_mcu_set_vif_ps(struct mt76_dev *dev, struct ieee80211_vif *vif); 1919 void mt76_connac_mcu_sta_basic_tlv(struct mt76_dev *dev, struct sk_buff *skb, 1920 struct ieee80211_bss_conf *link_conf, 1921 struct ieee80211_link_sta *link_sta, 1922 int state, bool newly); 1923 void mt76_connac_mcu_wtbl_generic_tlv(struct mt76_dev *dev, struct sk_buff *skb, 1924 struct ieee80211_vif *vif, 1925 struct ieee80211_sta *sta, void *sta_wtbl, 1926 void *wtbl_tlv); 1927 void mt76_connac_mcu_wtbl_hdr_trans_tlv(struct sk_buff *skb, 1928 struct ieee80211_vif *vif, 1929 struct mt76_wcid *wcid, 1930 void *sta_wtbl, void *wtbl_tlv); 1931 int mt76_connac_mcu_sta_update_hdr_trans(struct mt76_dev *dev, 1932 struct ieee80211_vif *vif, 1933 struct mt76_wcid *wcid, int cmd); 1934 void mt76_connac_mcu_sta_he_tlv_v2(struct sk_buff *skb, struct ieee80211_sta *sta); 1935 u8 mt76_connac_get_phy_mode_v2(struct mt76_phy *mphy, struct ieee80211_vif *vif, 1936 enum nl80211_band band, 1937 struct ieee80211_link_sta *link_sta); 1938 int mt76_connac_mcu_wtbl_update_hdr_trans(struct mt76_dev *dev, 1939 struct ieee80211_vif *vif, 1940 struct ieee80211_sta *sta); 1941 void mt76_connac_mcu_sta_tlv(struct mt76_phy *mphy, struct sk_buff *skb, 1942 struct ieee80211_sta *sta, 1943 struct ieee80211_vif *vif, 1944 u8 rcpi, u8 state); 1945 void mt76_connac_mcu_wtbl_ht_tlv(struct mt76_dev *dev, struct sk_buff *skb, 1946 struct ieee80211_sta *sta, void *sta_wtbl, 1947 void *wtbl_tlv, bool ht_ldpc, bool vht_ldpc); 1948 void mt76_connac_mcu_wtbl_ba_tlv(struct mt76_dev *dev, struct sk_buff *skb, 1949 struct ieee80211_ampdu_params *params, 1950 bool enable, bool tx, void *sta_wtbl, 1951 void *wtbl_tlv); 1952 void mt76_connac_mcu_sta_ba_tlv(struct sk_buff *skb, 1953 struct ieee80211_ampdu_params *params, 1954 bool enable, bool tx); 1955 int mt76_connac_mcu_uni_add_dev(struct mt76_phy *phy, 1956 struct ieee80211_bss_conf *bss_conf, 1957 struct mt76_vif_link *mvif, 1958 struct mt76_wcid *wcid, 1959 bool enable); 1960 int mt76_connac_mcu_sta_ba(struct mt76_dev *dev, struct mt76_vif_link *mvif, 1961 struct ieee80211_ampdu_params *params, 1962 int cmd, bool enable, bool tx); 1963 int mt76_connac_mcu_uni_set_chctx(struct mt76_phy *phy, 1964 struct mt76_vif_link *vif, 1965 struct ieee80211_chanctx_conf *ctx); 1966 int mt76_connac_mcu_uni_add_bss(struct mt76_phy *phy, 1967 struct ieee80211_vif *vif, 1968 struct mt76_wcid *wcid, 1969 bool enable, 1970 struct ieee80211_chanctx_conf *ctx); 1971 int mt76_connac_mcu_sta_cmd(struct mt76_phy *phy, 1972 struct mt76_sta_cmd_info *info); 1973 void mt76_connac_mcu_beacon_loss_iter(void *priv, u8 *mac, 1974 struct ieee80211_vif *vif); 1975 int mt76_connac_mcu_set_rts_thresh(struct mt76_dev *dev, u32 val, u8 band); 1976 int mt76_connac_mcu_set_mac_enable(struct mt76_dev *dev, int band, bool enable, 1977 bool hdr_trans); 1978 int mt76_connac_mcu_init_download(struct mt76_dev *dev, u32 addr, u32 len, 1979 u32 mode); 1980 int mt76_connac_mcu_start_patch(struct mt76_dev *dev); 1981 int mt76_connac_mcu_patch_sem_ctrl(struct mt76_dev *dev, bool get); 1982 int mt76_connac_mcu_start_firmware(struct mt76_dev *dev, u32 addr, u32 option); 1983 1984 void mt76_connac_mcu_build_rnr_scan_param(struct mt76_dev *mdev, 1985 struct cfg80211_scan_request *sreq); 1986 int mt76_connac_mcu_hw_scan(struct mt76_phy *phy, struct ieee80211_vif *vif, 1987 struct ieee80211_scan_request *scan_req); 1988 int mt76_connac_mcu_cancel_hw_scan(struct mt76_phy *phy, 1989 struct ieee80211_vif *vif); 1990 int mt76_connac_mcu_sched_scan_req(struct mt76_phy *phy, 1991 struct ieee80211_vif *vif, 1992 struct cfg80211_sched_scan_request *sreq); 1993 int mt76_connac_mcu_sched_scan_enable(struct mt76_phy *phy, 1994 struct ieee80211_vif *vif, 1995 bool enable); 1996 int mt76_connac_mcu_update_arp_filter(struct mt76_dev *dev, 1997 struct mt76_vif_link *vif, 1998 struct ieee80211_bss_conf *info); 1999 int mt76_connac_mcu_set_gtk_rekey(struct mt76_dev *dev, struct ieee80211_vif *vif, 2000 bool suspend); 2001 int mt76_connac_mcu_set_wow_ctrl(struct mt76_phy *phy, struct ieee80211_vif *vif, 2002 bool suspend, struct cfg80211_wowlan *wowlan); 2003 int mt76_connac_mcu_update_gtk_rekey(struct ieee80211_hw *hw, 2004 struct ieee80211_vif *vif, 2005 struct cfg80211_gtk_rekey_data *key); 2006 int mt76_connac_mcu_set_suspend_mode(struct mt76_dev *dev, 2007 struct ieee80211_vif *vif, 2008 bool enable, u8 mdtim, 2009 bool wow_suspend); 2010 int mt76_connac_mcu_set_hif_suspend(struct mt76_dev *dev, bool suspend, bool wait_resp); 2011 void mt76_connac_mcu_set_suspend_iter(void *priv, u8 *mac, 2012 struct ieee80211_vif *vif); 2013 int mt76_connac_sta_state_dp(struct mt76_dev *dev, 2014 enum ieee80211_sta_state old_state, 2015 enum ieee80211_sta_state new_state); 2016 int mt76_connac_mcu_chip_config(struct mt76_dev *dev); 2017 int mt76_connac_mcu_set_deep_sleep(struct mt76_dev *dev, bool enable); 2018 void mt76_connac_mcu_coredump_event(struct mt76_dev *dev, struct sk_buff *skb, 2019 struct mt76_connac_coredump *coredump); 2020 s8 mt76_connac_get_ch_power(struct mt76_phy *phy, 2021 struct ieee80211_channel *chan, 2022 s8 target_power); 2023 int mt76_connac_mcu_set_rate_txpower(struct mt76_phy *phy); 2024 int mt76_connac_mcu_set_p2p_oppps(struct ieee80211_hw *hw, 2025 struct ieee80211_vif *vif); 2026 u32 mt76_connac_mcu_reg_rr(struct mt76_dev *dev, u32 offset); 2027 void mt76_connac_mcu_reg_wr(struct mt76_dev *dev, u32 offset, u32 val); 2028 2029 const struct ieee80211_sta_he_cap * 2030 mt76_connac_get_he_phy_cap(struct mt76_phy *phy, struct ieee80211_vif *vif); 2031 const struct ieee80211_sta_eht_cap * 2032 mt76_connac_get_eht_phy_cap(struct mt76_phy *phy, struct ieee80211_vif *vif); 2033 u8 mt76_connac_get_phy_mode(struct mt76_phy *phy, struct ieee80211_vif *vif, 2034 enum nl80211_band band, 2035 struct ieee80211_link_sta *sta); 2036 u8 mt76_connac_get_phy_mode_ext(struct mt76_phy *phy, struct ieee80211_bss_conf *conf, 2037 enum nl80211_band band); 2038 2039 int mt76_connac_mcu_add_key(struct mt76_dev *dev, struct ieee80211_vif *vif, 2040 struct mt76_connac_sta_key_conf *sta_key_conf, 2041 struct ieee80211_key_conf *key, int mcu_cmd, 2042 struct mt76_wcid *wcid, enum set_key_cmd cmd); 2043 2044 void mt76_connac_mcu_bss_ext_tlv(struct sk_buff *skb, struct mt76_vif_link *mvif); 2045 void mt76_connac_mcu_bss_omac_tlv(struct sk_buff *skb, 2046 struct ieee80211_vif *vif); 2047 int mt76_connac_mcu_bss_basic_tlv(struct sk_buff *skb, 2048 struct ieee80211_vif *vif, 2049 struct ieee80211_sta *sta, 2050 struct mt76_phy *phy, u16 wlan_idx, 2051 bool enable); 2052 void mt76_connac_mcu_sta_uapsd(struct sk_buff *skb, struct ieee80211_vif *vif, 2053 struct ieee80211_sta *sta); 2054 void mt76_connac_mcu_wtbl_smps_tlv(struct sk_buff *skb, 2055 struct ieee80211_sta *sta, 2056 void *sta_wtbl, void *wtbl_tlv); 2057 int mt76_connac_mcu_set_pm(struct mt76_dev *dev, int band, int enter); 2058 int mt76_connac_mcu_restart(struct mt76_dev *dev); 2059 int mt76_connac_mcu_del_wtbl_all(struct mt76_dev *dev); 2060 int mt76_connac_mcu_rdd_cmd(struct mt76_dev *dev, int cmd, u8 index, 2061 u8 rx_sel, u8 val); 2062 int mt76_connac_mcu_sta_wed_update(struct mt76_dev *dev, struct sk_buff *skb); 2063 int mt76_connac2_load_ram(struct mt76_dev *dev, const char *fw_wm, 2064 const char *fw_wa); 2065 int mt76_connac2_load_patch(struct mt76_dev *dev, const char *fw_name); 2066 int mt76_connac2_mcu_fill_message(struct mt76_dev *mdev, struct sk_buff *skb, 2067 int cmd, int *wait_seq); 2068 #endif /* __MT76_CONNAC_MCU_H */ 2069