1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Texas Instruments Ethernet Switch Driver 4 * 5 * Copyright (C) 2019 Texas Instruments 6 */ 7 8 #include <linux/bpf.h> 9 #include <linux/bpf_trace.h> 10 #include <linux/if_ether.h> 11 #include <linux/if_vlan.h> 12 #include <linux/kmemleak.h> 13 #include <linux/module.h> 14 #include <linux/netdevice.h> 15 #include <linux/net_tstamp.h> 16 #include <linux/of.h> 17 #include <linux/phy.h> 18 #include <linux/platform_device.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/skbuff.h> 21 #include <net/page_pool/helpers.h> 22 #include <net/pkt_cls.h> 23 #include <net/pkt_sched.h> 24 25 #include "cpsw.h" 26 #include "cpts.h" 27 #include "cpsw_ale.h" 28 #include "cpsw_priv.h" 29 #include "cpsw_sl.h" 30 #include "davinci_cpdma.h" 31 32 #define CPTS_N_ETX_TS 4 33 34 int (*cpsw_slave_index)(struct cpsw_common *cpsw, struct cpsw_priv *priv); 35 36 void cpsw_intr_enable(struct cpsw_common *cpsw) 37 { 38 writel_relaxed(0xFF, &cpsw->wr_regs->tx_en); 39 writel_relaxed(0xFF, &cpsw->wr_regs->rx_en); 40 41 cpdma_ctlr_int_ctrl(cpsw->dma, true); 42 } 43 44 void cpsw_intr_disable(struct cpsw_common *cpsw) 45 { 46 writel_relaxed(0, &cpsw->wr_regs->tx_en); 47 writel_relaxed(0, &cpsw->wr_regs->rx_en); 48 49 cpdma_ctlr_int_ctrl(cpsw->dma, false); 50 } 51 52 void cpsw_tx_handler(void *token, int len, int status) 53 { 54 struct cpsw_meta_xdp *xmeta; 55 struct xdp_frame *xdpf; 56 struct net_device *ndev; 57 struct netdev_queue *txq; 58 struct sk_buff *skb; 59 int ch; 60 61 if (cpsw_is_xdpf_handle(token)) { 62 xdpf = cpsw_handle_to_xdpf(token); 63 xmeta = (void *)xdpf + CPSW_XMETA_OFFSET; 64 ndev = xmeta->ndev; 65 ch = xmeta->ch; 66 xdp_return_frame(xdpf); 67 } else { 68 skb = token; 69 ndev = skb->dev; 70 ch = skb_get_queue_mapping(skb); 71 cpts_tx_timestamp(ndev_to_cpsw(ndev)->cpts, skb); 72 dev_kfree_skb_any(skb); 73 } 74 75 /* Check whether the queue is stopped due to stalled tx dma, if the 76 * queue is stopped then start the queue as we have free desc for tx 77 */ 78 txq = netdev_get_tx_queue(ndev, ch); 79 if (unlikely(netif_tx_queue_stopped(txq))) 80 netif_tx_wake_queue(txq); 81 82 ndev->stats.tx_packets++; 83 ndev->stats.tx_bytes += len; 84 } 85 86 irqreturn_t cpsw_tx_interrupt(int irq, void *dev_id) 87 { 88 struct cpsw_common *cpsw = dev_id; 89 90 writel(0, &cpsw->wr_regs->tx_en); 91 cpdma_ctlr_eoi(cpsw->dma, CPDMA_EOI_TX); 92 93 if (cpsw->quirk_irq) { 94 disable_irq_nosync(cpsw->irqs_table[1]); 95 cpsw->tx_irq_disabled = true; 96 } 97 98 napi_schedule(&cpsw->napi_tx); 99 return IRQ_HANDLED; 100 } 101 102 irqreturn_t cpsw_rx_interrupt(int irq, void *dev_id) 103 { 104 struct cpsw_common *cpsw = dev_id; 105 106 writel(0, &cpsw->wr_regs->rx_en); 107 cpdma_ctlr_eoi(cpsw->dma, CPDMA_EOI_RX); 108 109 if (cpsw->quirk_irq) { 110 disable_irq_nosync(cpsw->irqs_table[0]); 111 cpsw->rx_irq_disabled = true; 112 } 113 114 napi_schedule(&cpsw->napi_rx); 115 return IRQ_HANDLED; 116 } 117 118 irqreturn_t cpsw_misc_interrupt(int irq, void *dev_id) 119 { 120 struct cpsw_common *cpsw = dev_id; 121 122 writel(0, &cpsw->wr_regs->misc_en); 123 cpdma_ctlr_eoi(cpsw->dma, CPDMA_EOI_MISC); 124 cpts_misc_interrupt(cpsw->cpts); 125 writel(0x10, &cpsw->wr_regs->misc_en); 126 127 return IRQ_HANDLED; 128 } 129 130 int cpsw_tx_mq_poll(struct napi_struct *napi_tx, int budget) 131 { 132 struct cpsw_common *cpsw = napi_to_cpsw(napi_tx); 133 int num_tx, cur_budget, ch; 134 u32 ch_map; 135 struct cpsw_vector *txv; 136 137 /* process every unprocessed channel */ 138 ch_map = cpdma_ctrl_txchs_state(cpsw->dma); 139 for (ch = 0, num_tx = 0; ch_map & 0xff; ch_map <<= 1, ch++) { 140 if (!(ch_map & 0x80)) 141 continue; 142 143 txv = &cpsw->txv[ch]; 144 if (unlikely(txv->budget > budget - num_tx)) 145 cur_budget = budget - num_tx; 146 else 147 cur_budget = txv->budget; 148 149 num_tx += cpdma_chan_process(txv->ch, cur_budget); 150 if (num_tx >= budget) 151 break; 152 } 153 154 if (num_tx < budget) { 155 napi_complete(napi_tx); 156 writel(0xff, &cpsw->wr_regs->tx_en); 157 } 158 159 return num_tx; 160 } 161 162 int cpsw_tx_poll(struct napi_struct *napi_tx, int budget) 163 { 164 struct cpsw_common *cpsw = napi_to_cpsw(napi_tx); 165 int num_tx; 166 167 num_tx = cpdma_chan_process(cpsw->txv[0].ch, budget); 168 if (num_tx < budget) { 169 napi_complete(napi_tx); 170 writel(0xff, &cpsw->wr_regs->tx_en); 171 if (cpsw->tx_irq_disabled) { 172 cpsw->tx_irq_disabled = false; 173 enable_irq(cpsw->irqs_table[1]); 174 } 175 } 176 177 return num_tx; 178 } 179 180 int cpsw_rx_mq_poll(struct napi_struct *napi_rx, int budget) 181 { 182 struct cpsw_common *cpsw = napi_to_cpsw(napi_rx); 183 int num_rx, cur_budget, ch; 184 u32 ch_map; 185 struct cpsw_vector *rxv; 186 187 /* process every unprocessed channel */ 188 ch_map = cpdma_ctrl_rxchs_state(cpsw->dma); 189 for (ch = 0, num_rx = 0; ch_map; ch_map >>= 1, ch++) { 190 if (!(ch_map & 0x01)) 191 continue; 192 193 rxv = &cpsw->rxv[ch]; 194 if (unlikely(rxv->budget > budget - num_rx)) 195 cur_budget = budget - num_rx; 196 else 197 cur_budget = rxv->budget; 198 199 num_rx += cpdma_chan_process(rxv->ch, cur_budget); 200 if (num_rx >= budget) 201 break; 202 } 203 204 if (num_rx < budget) { 205 napi_complete_done(napi_rx, num_rx); 206 writel(0xff, &cpsw->wr_regs->rx_en); 207 } 208 209 return num_rx; 210 } 211 212 int cpsw_rx_poll(struct napi_struct *napi_rx, int budget) 213 { 214 struct cpsw_common *cpsw = napi_to_cpsw(napi_rx); 215 int num_rx; 216 217 num_rx = cpdma_chan_process(cpsw->rxv[0].ch, budget); 218 if (num_rx < budget) { 219 napi_complete_done(napi_rx, num_rx); 220 writel(0xff, &cpsw->wr_regs->rx_en); 221 if (cpsw->rx_irq_disabled) { 222 cpsw->rx_irq_disabled = false; 223 enable_irq(cpsw->irqs_table[0]); 224 } 225 } 226 227 return num_rx; 228 } 229 230 void cpsw_rx_vlan_encap(struct sk_buff *skb) 231 { 232 struct cpsw_priv *priv = netdev_priv(skb->dev); 233 u32 rx_vlan_encap_hdr = *((u32 *)skb->data); 234 struct cpsw_common *cpsw = priv->cpsw; 235 u16 vtag, vid, prio, pkt_type; 236 237 /* Remove VLAN header encapsulation word */ 238 skb_pull(skb, CPSW_RX_VLAN_ENCAP_HDR_SIZE); 239 240 pkt_type = (rx_vlan_encap_hdr >> 241 CPSW_RX_VLAN_ENCAP_HDR_PKT_TYPE_SHIFT) & 242 CPSW_RX_VLAN_ENCAP_HDR_PKT_TYPE_MSK; 243 /* Ignore unknown & Priority-tagged packets*/ 244 if (pkt_type == CPSW_RX_VLAN_ENCAP_HDR_PKT_RESERV || 245 pkt_type == CPSW_RX_VLAN_ENCAP_HDR_PKT_PRIO_TAG) 246 return; 247 248 vid = (rx_vlan_encap_hdr >> 249 CPSW_RX_VLAN_ENCAP_HDR_VID_SHIFT) & 250 VLAN_VID_MASK; 251 /* Ignore vid 0 and pass packet as is */ 252 if (!vid) 253 return; 254 255 /* Untag P0 packets if set for vlan */ 256 if (!cpsw_ale_get_vlan_p0_untag(cpsw->ale, vid)) { 257 prio = (rx_vlan_encap_hdr >> 258 CPSW_RX_VLAN_ENCAP_HDR_PRIO_SHIFT) & 259 CPSW_RX_VLAN_ENCAP_HDR_PRIO_MSK; 260 261 vtag = (prio << VLAN_PRIO_SHIFT) | vid; 262 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vtag); 263 } 264 265 /* strip vlan tag for VLAN-tagged packet */ 266 if (pkt_type == CPSW_RX_VLAN_ENCAP_HDR_PKT_VLAN_TAG) { 267 memmove(skb->data + VLAN_HLEN, skb->data, 2 * ETH_ALEN); 268 skb_pull(skb, VLAN_HLEN); 269 } 270 } 271 272 void cpsw_set_slave_mac(struct cpsw_slave *slave, struct cpsw_priv *priv) 273 { 274 slave_write(slave, mac_hi(priv->mac_addr), SA_HI); 275 slave_write(slave, mac_lo(priv->mac_addr), SA_LO); 276 } 277 278 void soft_reset(const char *module, void __iomem *reg) 279 { 280 unsigned long timeout = jiffies + HZ; 281 282 writel_relaxed(1, reg); 283 do { 284 cpu_relax(); 285 } while ((readl_relaxed(reg) & 1) && time_after(timeout, jiffies)); 286 287 WARN(readl_relaxed(reg) & 1, "failed to soft-reset %s\n", module); 288 } 289 290 void cpsw_ndo_tx_timeout(struct net_device *ndev, unsigned int txqueue) 291 { 292 struct cpsw_priv *priv = netdev_priv(ndev); 293 struct cpsw_common *cpsw = priv->cpsw; 294 int ch; 295 296 cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n"); 297 ndev->stats.tx_errors++; 298 cpsw_intr_disable(cpsw); 299 for (ch = 0; ch < cpsw->tx_ch_num; ch++) { 300 cpdma_chan_stop(cpsw->txv[ch].ch); 301 cpdma_chan_start(cpsw->txv[ch].ch); 302 } 303 304 cpsw_intr_enable(cpsw); 305 netif_trans_update(ndev); 306 netif_tx_wake_all_queues(ndev); 307 } 308 309 static int cpsw_get_common_speed(struct cpsw_common *cpsw) 310 { 311 int i, speed; 312 313 for (i = 0, speed = 0; i < cpsw->data.slaves; i++) 314 if (cpsw->slaves[i].phy && cpsw->slaves[i].phy->link) 315 speed += cpsw->slaves[i].phy->speed; 316 317 return speed; 318 } 319 320 int cpsw_need_resplit(struct cpsw_common *cpsw) 321 { 322 int i, rlim_ch_num; 323 int speed, ch_rate; 324 325 /* re-split resources only in case speed was changed */ 326 speed = cpsw_get_common_speed(cpsw); 327 if (speed == cpsw->speed || !speed) 328 return 0; 329 330 cpsw->speed = speed; 331 332 for (i = 0, rlim_ch_num = 0; i < cpsw->tx_ch_num; i++) { 333 ch_rate = cpdma_chan_get_rate(cpsw->txv[i].ch); 334 if (!ch_rate) 335 break; 336 337 rlim_ch_num++; 338 } 339 340 /* cases not dependent on speed */ 341 if (!rlim_ch_num || rlim_ch_num == cpsw->tx_ch_num) 342 return 0; 343 344 return 1; 345 } 346 347 void cpsw_split_res(struct cpsw_common *cpsw) 348 { 349 u32 consumed_rate = 0, bigest_rate = 0; 350 struct cpsw_vector *txv = cpsw->txv; 351 int i, ch_weight, rlim_ch_num = 0; 352 int budget, bigest_rate_ch = 0; 353 u32 ch_rate, max_rate; 354 int ch_budget = 0; 355 356 for (i = 0; i < cpsw->tx_ch_num; i++) { 357 ch_rate = cpdma_chan_get_rate(txv[i].ch); 358 if (!ch_rate) 359 continue; 360 361 rlim_ch_num++; 362 consumed_rate += ch_rate; 363 } 364 365 if (cpsw->tx_ch_num == rlim_ch_num) { 366 max_rate = consumed_rate; 367 } else if (!rlim_ch_num) { 368 ch_budget = NAPI_POLL_WEIGHT / cpsw->tx_ch_num; 369 bigest_rate = 0; 370 max_rate = consumed_rate; 371 } else { 372 max_rate = cpsw->speed * 1000; 373 374 /* if max_rate is less then expected due to reduced link speed, 375 * split proportionally according next potential max speed 376 */ 377 if (max_rate < consumed_rate) 378 max_rate *= 10; 379 380 if (max_rate < consumed_rate) 381 max_rate *= 10; 382 383 ch_budget = (consumed_rate * NAPI_POLL_WEIGHT) / max_rate; 384 ch_budget = (NAPI_POLL_WEIGHT - ch_budget) / 385 (cpsw->tx_ch_num - rlim_ch_num); 386 bigest_rate = (max_rate - consumed_rate) / 387 (cpsw->tx_ch_num - rlim_ch_num); 388 } 389 390 /* split tx weight/budget */ 391 budget = NAPI_POLL_WEIGHT; 392 for (i = 0; i < cpsw->tx_ch_num; i++) { 393 ch_rate = cpdma_chan_get_rate(txv[i].ch); 394 if (ch_rate) { 395 txv[i].budget = (ch_rate * NAPI_POLL_WEIGHT) / max_rate; 396 if (!txv[i].budget) 397 txv[i].budget++; 398 if (ch_rate > bigest_rate) { 399 bigest_rate_ch = i; 400 bigest_rate = ch_rate; 401 } 402 403 ch_weight = (ch_rate * 100) / max_rate; 404 if (!ch_weight) 405 ch_weight++; 406 cpdma_chan_set_weight(cpsw->txv[i].ch, ch_weight); 407 } else { 408 txv[i].budget = ch_budget; 409 if (!bigest_rate_ch) 410 bigest_rate_ch = i; 411 cpdma_chan_set_weight(cpsw->txv[i].ch, 0); 412 } 413 414 budget -= txv[i].budget; 415 } 416 417 if (budget) 418 txv[bigest_rate_ch].budget += budget; 419 420 /* split rx budget */ 421 budget = NAPI_POLL_WEIGHT; 422 ch_budget = budget / cpsw->rx_ch_num; 423 for (i = 0; i < cpsw->rx_ch_num; i++) { 424 cpsw->rxv[i].budget = ch_budget; 425 budget -= ch_budget; 426 } 427 428 if (budget) 429 cpsw->rxv[0].budget += budget; 430 } 431 432 int cpsw_init_common(struct cpsw_common *cpsw, void __iomem *ss_regs, 433 int ale_ageout, phys_addr_t desc_mem_phys, 434 int descs_pool_size) 435 { 436 u32 slave_offset, sliver_offset, slave_size; 437 struct cpsw_ale_params ale_params; 438 struct cpsw_platform_data *data; 439 struct cpdma_params dma_params; 440 struct device *dev = cpsw->dev; 441 struct device_node *cpts_node; 442 void __iomem *cpts_regs; 443 int ret = 0, i; 444 445 data = &cpsw->data; 446 cpsw->rx_ch_num = 1; 447 cpsw->tx_ch_num = 1; 448 449 cpsw->version = readl(&cpsw->regs->id_ver); 450 451 memset(&dma_params, 0, sizeof(dma_params)); 452 memset(&ale_params, 0, sizeof(ale_params)); 453 454 switch (cpsw->version) { 455 case CPSW_VERSION_1: 456 cpsw->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET; 457 cpts_regs = ss_regs + CPSW1_CPTS_OFFSET; 458 cpsw->hw_stats = ss_regs + CPSW1_HW_STATS; 459 dma_params.dmaregs = ss_regs + CPSW1_CPDMA_OFFSET; 460 dma_params.txhdp = ss_regs + CPSW1_STATERAM_OFFSET; 461 ale_params.ale_regs = ss_regs + CPSW1_ALE_OFFSET; 462 slave_offset = CPSW1_SLAVE_OFFSET; 463 slave_size = CPSW1_SLAVE_SIZE; 464 sliver_offset = CPSW1_SLIVER_OFFSET; 465 dma_params.desc_mem_phys = 0; 466 break; 467 case CPSW_VERSION_2: 468 case CPSW_VERSION_3: 469 case CPSW_VERSION_4: 470 cpsw->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET; 471 cpts_regs = ss_regs + CPSW2_CPTS_OFFSET; 472 cpsw->hw_stats = ss_regs + CPSW2_HW_STATS; 473 dma_params.dmaregs = ss_regs + CPSW2_CPDMA_OFFSET; 474 dma_params.txhdp = ss_regs + CPSW2_STATERAM_OFFSET; 475 ale_params.ale_regs = ss_regs + CPSW2_ALE_OFFSET; 476 slave_offset = CPSW2_SLAVE_OFFSET; 477 slave_size = CPSW2_SLAVE_SIZE; 478 sliver_offset = CPSW2_SLIVER_OFFSET; 479 dma_params.desc_mem_phys = desc_mem_phys; 480 break; 481 default: 482 dev_err(dev, "unknown version 0x%08x\n", cpsw->version); 483 return -ENODEV; 484 } 485 486 for (i = 0; i < cpsw->data.slaves; i++) { 487 struct cpsw_slave *slave = &cpsw->slaves[i]; 488 void __iomem *regs = cpsw->regs; 489 490 slave->slave_num = i; 491 slave->data = &cpsw->data.slave_data[i]; 492 slave->regs = regs + slave_offset; 493 slave->port_vlan = slave->data->dual_emac_res_vlan; 494 slave->mac_sl = cpsw_sl_get("cpsw", dev, regs + sliver_offset); 495 if (IS_ERR(slave->mac_sl)) 496 return PTR_ERR(slave->mac_sl); 497 498 slave_offset += slave_size; 499 sliver_offset += SLIVER_SIZE; 500 } 501 502 ale_params.dev = dev; 503 ale_params.ale_ageout = ale_ageout; 504 ale_params.ale_ports = CPSW_ALE_PORTS_NUM; 505 ale_params.dev_id = "cpsw"; 506 ale_params.bus_freq = cpsw->bus_freq_mhz * 1000000; 507 508 cpsw->ale = cpsw_ale_create(&ale_params); 509 if (IS_ERR(cpsw->ale)) { 510 dev_err(dev, "error initializing ale engine\n"); 511 return PTR_ERR(cpsw->ale); 512 } 513 514 dma_params.dev = dev; 515 dma_params.rxthresh = dma_params.dmaregs + CPDMA_RXTHRESH; 516 dma_params.rxfree = dma_params.dmaregs + CPDMA_RXFREE; 517 dma_params.rxhdp = dma_params.txhdp + CPDMA_RXHDP; 518 dma_params.txcp = dma_params.txhdp + CPDMA_TXCP; 519 dma_params.rxcp = dma_params.txhdp + CPDMA_RXCP; 520 521 dma_params.num_chan = data->channels; 522 dma_params.has_soft_reset = true; 523 dma_params.min_packet_size = CPSW_MIN_PACKET_SIZE; 524 dma_params.desc_mem_size = data->bd_ram_size; 525 dma_params.desc_align = 16; 526 dma_params.has_ext_regs = true; 527 dma_params.desc_hw_addr = dma_params.desc_mem_phys; 528 dma_params.bus_freq_mhz = cpsw->bus_freq_mhz; 529 dma_params.descs_pool_size = descs_pool_size; 530 531 cpsw->dma = cpdma_ctlr_create(&dma_params); 532 if (!cpsw->dma) { 533 dev_err(dev, "error initializing dma\n"); 534 return -ENOMEM; 535 } 536 537 cpts_node = of_get_child_by_name(cpsw->dev->of_node, "cpts"); 538 if (!cpts_node) 539 cpts_node = cpsw->dev->of_node; 540 541 cpsw->cpts = cpts_create(cpsw->dev, cpts_regs, cpts_node, 542 CPTS_N_ETX_TS); 543 if (IS_ERR(cpsw->cpts)) { 544 ret = PTR_ERR(cpsw->cpts); 545 cpdma_ctlr_destroy(cpsw->dma); 546 } 547 of_node_put(cpts_node); 548 549 return ret; 550 } 551 552 #if IS_ENABLED(CONFIG_TI_CPTS) 553 554 static void cpsw_hwtstamp_v1(struct cpsw_priv *priv) 555 { 556 struct cpsw_common *cpsw = priv->cpsw; 557 struct cpsw_slave *slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)]; 558 u32 ts_en, seq_id; 559 560 if (!priv->tx_ts_enabled && !priv->rx_ts_enabled) { 561 slave_write(slave, 0, CPSW1_TS_CTL); 562 return; 563 } 564 565 seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588; 566 ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS; 567 568 if (priv->tx_ts_enabled) 569 ts_en |= CPSW_V1_TS_TX_EN; 570 571 if (priv->rx_ts_enabled) 572 ts_en |= CPSW_V1_TS_RX_EN; 573 574 slave_write(slave, ts_en, CPSW1_TS_CTL); 575 slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE); 576 } 577 578 static void cpsw_hwtstamp_v2(struct cpsw_priv *priv) 579 { 580 struct cpsw_common *cpsw = priv->cpsw; 581 struct cpsw_slave *slave; 582 u32 ctrl, mtype; 583 584 slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)]; 585 586 ctrl = slave_read(slave, CPSW2_CONTROL); 587 switch (cpsw->version) { 588 case CPSW_VERSION_2: 589 ctrl &= ~CTRL_V2_ALL_TS_MASK; 590 591 if (priv->tx_ts_enabled) 592 ctrl |= CTRL_V2_TX_TS_BITS; 593 594 if (priv->rx_ts_enabled) 595 ctrl |= CTRL_V2_RX_TS_BITS; 596 break; 597 case CPSW_VERSION_3: 598 default: 599 ctrl &= ~CTRL_V3_ALL_TS_MASK; 600 601 if (priv->tx_ts_enabled) 602 ctrl |= CTRL_V3_TX_TS_BITS; 603 604 if (priv->rx_ts_enabled) 605 ctrl |= CTRL_V3_RX_TS_BITS; 606 break; 607 } 608 609 mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS; 610 611 slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE); 612 slave_write(slave, ctrl, CPSW2_CONTROL); 613 writel_relaxed(ETH_P_1588, &cpsw->regs->ts_ltype); 614 writel_relaxed(ETH_P_8021Q, &cpsw->regs->vlan_ltype); 615 } 616 617 int cpsw_hwtstamp_set(struct net_device *dev, 618 struct kernel_hwtstamp_config *cfg, 619 struct netlink_ext_ack *extack) 620 { 621 struct cpsw_priv *priv = netdev_priv(dev); 622 struct cpsw_common *cpsw = priv->cpsw; 623 624 /* This will only execute if dev->see_all_hwtstamp_requests is set */ 625 if (cfg->source != HWTSTAMP_SOURCE_NETDEV) { 626 NL_SET_ERR_MSG_MOD(extack, 627 "Switch mode only supports MAC timestamping"); 628 return -EOPNOTSUPP; 629 } 630 631 if (cpsw->version != CPSW_VERSION_1 && 632 cpsw->version != CPSW_VERSION_2 && 633 cpsw->version != CPSW_VERSION_3) 634 return -EOPNOTSUPP; 635 636 if (cfg->tx_type != HWTSTAMP_TX_OFF && cfg->tx_type != HWTSTAMP_TX_ON) 637 return -ERANGE; 638 639 switch (cfg->rx_filter) { 640 case HWTSTAMP_FILTER_NONE: 641 priv->rx_ts_enabled = 0; 642 break; 643 case HWTSTAMP_FILTER_ALL: 644 case HWTSTAMP_FILTER_NTP_ALL: 645 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 646 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 647 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 648 return -ERANGE; 649 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 650 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 651 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 652 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 653 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 654 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 655 case HWTSTAMP_FILTER_PTP_V2_EVENT: 656 case HWTSTAMP_FILTER_PTP_V2_SYNC: 657 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 658 priv->rx_ts_enabled = HWTSTAMP_FILTER_PTP_V2_EVENT; 659 cfg->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 660 break; 661 default: 662 return -ERANGE; 663 } 664 665 priv->tx_ts_enabled = cfg->tx_type == HWTSTAMP_TX_ON; 666 667 switch (cpsw->version) { 668 case CPSW_VERSION_1: 669 cpsw_hwtstamp_v1(priv); 670 break; 671 case CPSW_VERSION_2: 672 case CPSW_VERSION_3: 673 cpsw_hwtstamp_v2(priv); 674 break; 675 default: 676 WARN_ON(1); 677 } 678 679 return 0; 680 } 681 682 int cpsw_hwtstamp_get(struct net_device *dev, 683 struct kernel_hwtstamp_config *cfg) 684 { 685 struct cpsw_common *cpsw = ndev_to_cpsw(dev); 686 struct cpsw_priv *priv = netdev_priv(dev); 687 688 if (cpsw->version != CPSW_VERSION_1 && 689 cpsw->version != CPSW_VERSION_2 && 690 cpsw->version != CPSW_VERSION_3) 691 return -EOPNOTSUPP; 692 693 cfg->tx_type = priv->tx_ts_enabled ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF; 694 cfg->rx_filter = priv->rx_ts_enabled; 695 696 return 0; 697 } 698 #else 699 int cpsw_hwtstamp_get(struct net_device *dev, 700 struct kernel_hwtstamp_config *cfg) 701 { 702 return -EOPNOTSUPP; 703 } 704 705 int cpsw_hwtstamp_set(struct net_device *dev, 706 struct kernel_hwtstamp_config *cfg, 707 struct netlink_ext_ack *extack) 708 { 709 return -EOPNOTSUPP; 710 } 711 #endif /*CONFIG_TI_CPTS*/ 712 713 int cpsw_ndo_set_tx_maxrate(struct net_device *ndev, int queue, u32 rate) 714 { 715 struct cpsw_priv *priv = netdev_priv(ndev); 716 struct cpsw_common *cpsw = priv->cpsw; 717 struct cpsw_slave *slave; 718 u32 min_rate; 719 u32 ch_rate; 720 int i, ret; 721 722 ch_rate = netdev_get_tx_queue(ndev, queue)->tx_maxrate; 723 if (ch_rate == rate) 724 return 0; 725 726 ch_rate = rate * 1000; 727 min_rate = cpdma_chan_get_min_rate(cpsw->dma); 728 if ((ch_rate < min_rate && ch_rate)) { 729 dev_err(priv->dev, "The channel rate cannot be less than %dMbps", 730 min_rate); 731 return -EINVAL; 732 } 733 734 if (rate > cpsw->speed) { 735 dev_err(priv->dev, "The channel rate cannot be more than 2Gbps"); 736 return -EINVAL; 737 } 738 739 ret = pm_runtime_resume_and_get(cpsw->dev); 740 if (ret < 0) 741 return ret; 742 743 ret = cpdma_chan_set_rate(cpsw->txv[queue].ch, ch_rate); 744 pm_runtime_put(cpsw->dev); 745 746 if (ret) 747 return ret; 748 749 /* update rates for slaves tx queues */ 750 for (i = 0; i < cpsw->data.slaves; i++) { 751 slave = &cpsw->slaves[i]; 752 if (!slave->ndev) 753 continue; 754 755 netdev_get_tx_queue(slave->ndev, queue)->tx_maxrate = rate; 756 } 757 758 cpsw_split_res(cpsw); 759 return ret; 760 } 761 762 static int cpsw_tc_to_fifo(int tc, int num_tc) 763 { 764 if (tc == num_tc - 1) 765 return 0; 766 767 return CPSW_FIFO_SHAPERS_NUM - tc; 768 } 769 770 bool cpsw_shp_is_off(struct cpsw_priv *priv) 771 { 772 struct cpsw_common *cpsw = priv->cpsw; 773 struct cpsw_slave *slave; 774 u32 shift, mask, val; 775 776 val = readl_relaxed(&cpsw->regs->ptype); 777 778 slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)]; 779 shift = CPSW_FIFO_SHAPE_EN_SHIFT + 3 * slave->slave_num; 780 mask = 7 << shift; 781 val = val & mask; 782 783 return !val; 784 } 785 786 static void cpsw_fifo_shp_on(struct cpsw_priv *priv, int fifo, int on) 787 { 788 struct cpsw_common *cpsw = priv->cpsw; 789 struct cpsw_slave *slave; 790 u32 shift, mask, val; 791 792 val = readl_relaxed(&cpsw->regs->ptype); 793 794 slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)]; 795 shift = CPSW_FIFO_SHAPE_EN_SHIFT + 3 * slave->slave_num; 796 mask = (1 << --fifo) << shift; 797 val = on ? val | mask : val & ~mask; 798 799 writel_relaxed(val, &cpsw->regs->ptype); 800 } 801 802 static int cpsw_set_fifo_bw(struct cpsw_priv *priv, int fifo, int bw) 803 { 804 struct cpsw_common *cpsw = priv->cpsw; 805 u32 val = 0, send_pct, shift; 806 struct cpsw_slave *slave; 807 int pct = 0, i; 808 809 if (bw > priv->shp_cfg_speed * 1000) 810 goto err; 811 812 /* shaping has to stay enabled for highest fifos linearly 813 * and fifo bw no more then interface can allow 814 */ 815 slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)]; 816 send_pct = slave_read(slave, SEND_PERCENT); 817 for (i = CPSW_FIFO_SHAPERS_NUM; i > 0; i--) { 818 if (!bw) { 819 if (i >= fifo || !priv->fifo_bw[i]) 820 continue; 821 822 dev_warn(priv->dev, "Prev FIFO%d is shaped", i); 823 continue; 824 } 825 826 if (!priv->fifo_bw[i] && i > fifo) { 827 dev_err(priv->dev, "Upper FIFO%d is not shaped", i); 828 return -EINVAL; 829 } 830 831 shift = (i - 1) * 8; 832 if (i == fifo) { 833 send_pct &= ~(CPSW_PCT_MASK << shift); 834 val = DIV_ROUND_UP(bw, priv->shp_cfg_speed * 10); 835 if (!val) 836 val = 1; 837 838 send_pct |= val << shift; 839 pct += val; 840 continue; 841 } 842 843 if (priv->fifo_bw[i]) 844 pct += (send_pct >> shift) & CPSW_PCT_MASK; 845 } 846 847 if (pct >= 100) 848 goto err; 849 850 slave_write(slave, send_pct, SEND_PERCENT); 851 priv->fifo_bw[fifo] = bw; 852 853 dev_warn(priv->dev, "set FIFO%d bw = %d\n", fifo, 854 DIV_ROUND_CLOSEST(val * priv->shp_cfg_speed, 100)); 855 856 return 0; 857 err: 858 dev_err(priv->dev, "Bandwidth doesn't fit in tc configuration"); 859 return -EINVAL; 860 } 861 862 static int cpsw_set_fifo_rlimit(struct cpsw_priv *priv, int fifo, int bw) 863 { 864 struct cpsw_common *cpsw = priv->cpsw; 865 struct cpsw_slave *slave; 866 u32 tx_in_ctl_rg, val; 867 int ret; 868 869 ret = cpsw_set_fifo_bw(priv, fifo, bw); 870 if (ret) 871 return ret; 872 873 slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)]; 874 tx_in_ctl_rg = cpsw->version == CPSW_VERSION_1 ? 875 CPSW1_TX_IN_CTL : CPSW2_TX_IN_CTL; 876 877 if (!bw) 878 cpsw_fifo_shp_on(priv, fifo, bw); 879 880 val = slave_read(slave, tx_in_ctl_rg); 881 if (cpsw_shp_is_off(priv)) { 882 /* disable FIFOs rate limited queues */ 883 val &= ~(0xf << CPSW_FIFO_RATE_EN_SHIFT); 884 885 /* set type of FIFO queues to normal priority mode */ 886 val &= ~(3 << CPSW_FIFO_QUEUE_TYPE_SHIFT); 887 888 /* set type of FIFO queues to be rate limited */ 889 if (bw) 890 val |= 2 << CPSW_FIFO_QUEUE_TYPE_SHIFT; 891 else 892 priv->shp_cfg_speed = 0; 893 } 894 895 /* toggle a FIFO rate limited queue */ 896 if (bw) 897 val |= BIT(fifo + CPSW_FIFO_RATE_EN_SHIFT); 898 else 899 val &= ~BIT(fifo + CPSW_FIFO_RATE_EN_SHIFT); 900 slave_write(slave, val, tx_in_ctl_rg); 901 902 /* FIFO transmit shape enable */ 903 cpsw_fifo_shp_on(priv, fifo, bw); 904 return 0; 905 } 906 907 /* Defaults: 908 * class A - prio 3 909 * class B - prio 2 910 * shaping for class A should be set first 911 */ 912 static int cpsw_set_cbs(struct net_device *ndev, 913 struct tc_cbs_qopt_offload *qopt) 914 { 915 struct cpsw_priv *priv = netdev_priv(ndev); 916 struct cpsw_common *cpsw = priv->cpsw; 917 struct cpsw_slave *slave; 918 int prev_speed = 0; 919 int tc, ret, fifo; 920 u32 bw = 0; 921 922 tc = netdev_txq_to_tc(priv->ndev, qopt->queue); 923 924 /* enable channels in backward order, as highest FIFOs must be rate 925 * limited first and for compliance with CPDMA rate limited channels 926 * that also used in bacward order. FIFO0 cannot be rate limited. 927 */ 928 fifo = cpsw_tc_to_fifo(tc, ndev->num_tc); 929 if (!fifo) { 930 dev_err(priv->dev, "Last tc%d can't be rate limited", tc); 931 return -EINVAL; 932 } 933 934 /* do nothing, it's disabled anyway */ 935 if (!qopt->enable && !priv->fifo_bw[fifo]) 936 return 0; 937 938 /* shapers can be set if link speed is known */ 939 slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)]; 940 if (slave->phy && slave->phy->link) { 941 if (priv->shp_cfg_speed && 942 priv->shp_cfg_speed != slave->phy->speed) 943 prev_speed = priv->shp_cfg_speed; 944 945 priv->shp_cfg_speed = slave->phy->speed; 946 } 947 948 if (!priv->shp_cfg_speed) { 949 dev_err(priv->dev, "Link speed is not known"); 950 return -1; 951 } 952 953 ret = pm_runtime_resume_and_get(cpsw->dev); 954 if (ret < 0) 955 return ret; 956 957 bw = qopt->enable ? qopt->idleslope : 0; 958 ret = cpsw_set_fifo_rlimit(priv, fifo, bw); 959 if (ret) { 960 priv->shp_cfg_speed = prev_speed; 961 prev_speed = 0; 962 } 963 964 if (bw && prev_speed) 965 dev_warn(priv->dev, 966 "Speed was changed, CBS shaper speeds are changed!"); 967 968 pm_runtime_put_sync(cpsw->dev); 969 return ret; 970 } 971 972 static int cpsw_set_mqprio(struct net_device *ndev, void *type_data) 973 { 974 struct tc_mqprio_qopt_offload *mqprio = type_data; 975 struct cpsw_priv *priv = netdev_priv(ndev); 976 struct cpsw_common *cpsw = priv->cpsw; 977 int fifo, num_tc, count, offset; 978 struct cpsw_slave *slave; 979 u32 tx_prio_map = 0; 980 int i, tc, ret; 981 982 num_tc = mqprio->qopt.num_tc; 983 if (num_tc > CPSW_TC_NUM) 984 return -EINVAL; 985 986 if (mqprio->mode != TC_MQPRIO_MODE_DCB) 987 return -EINVAL; 988 989 ret = pm_runtime_resume_and_get(cpsw->dev); 990 if (ret < 0) 991 return ret; 992 993 if (num_tc) { 994 for (i = 0; i < 8; i++) { 995 tc = mqprio->qopt.prio_tc_map[i]; 996 fifo = cpsw_tc_to_fifo(tc, num_tc); 997 tx_prio_map |= fifo << (4 * i); 998 } 999 1000 netdev_set_num_tc(ndev, num_tc); 1001 for (i = 0; i < num_tc; i++) { 1002 count = mqprio->qopt.count[i]; 1003 offset = mqprio->qopt.offset[i]; 1004 netdev_set_tc_queue(ndev, i, count, offset); 1005 } 1006 } 1007 1008 if (!mqprio->qopt.hw) { 1009 /* restore default configuration */ 1010 netdev_reset_tc(ndev); 1011 tx_prio_map = TX_PRIORITY_MAPPING; 1012 } 1013 1014 priv->mqprio_hw = mqprio->qopt.hw; 1015 1016 offset = cpsw->version == CPSW_VERSION_1 ? 1017 CPSW1_TX_PRI_MAP : CPSW2_TX_PRI_MAP; 1018 1019 slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)]; 1020 slave_write(slave, tx_prio_map, offset); 1021 1022 pm_runtime_put_sync(cpsw->dev); 1023 1024 return 0; 1025 } 1026 1027 static int cpsw_qos_setup_tc_block(struct net_device *ndev, struct flow_block_offload *f); 1028 1029 int cpsw_ndo_setup_tc(struct net_device *ndev, enum tc_setup_type type, 1030 void *type_data) 1031 { 1032 switch (type) { 1033 case TC_SETUP_QDISC_CBS: 1034 return cpsw_set_cbs(ndev, type_data); 1035 1036 case TC_SETUP_QDISC_MQPRIO: 1037 return cpsw_set_mqprio(ndev, type_data); 1038 1039 case TC_SETUP_BLOCK: 1040 return cpsw_qos_setup_tc_block(ndev, type_data); 1041 1042 default: 1043 return -EOPNOTSUPP; 1044 } 1045 } 1046 1047 void cpsw_cbs_resume(struct cpsw_slave *slave, struct cpsw_priv *priv) 1048 { 1049 int fifo, bw; 1050 1051 for (fifo = CPSW_FIFO_SHAPERS_NUM; fifo > 0; fifo--) { 1052 bw = priv->fifo_bw[fifo]; 1053 if (!bw) 1054 continue; 1055 1056 cpsw_set_fifo_rlimit(priv, fifo, bw); 1057 } 1058 } 1059 1060 void cpsw_mqprio_resume(struct cpsw_slave *slave, struct cpsw_priv *priv) 1061 { 1062 struct cpsw_common *cpsw = priv->cpsw; 1063 u32 tx_prio_map = 0; 1064 int i, tc, fifo; 1065 u32 tx_prio_rg; 1066 1067 if (!priv->mqprio_hw) 1068 return; 1069 1070 for (i = 0; i < 8; i++) { 1071 tc = netdev_get_prio_tc_map(priv->ndev, i); 1072 fifo = CPSW_FIFO_SHAPERS_NUM - tc; 1073 tx_prio_map |= fifo << (4 * i); 1074 } 1075 1076 tx_prio_rg = cpsw->version == CPSW_VERSION_1 ? 1077 CPSW1_TX_PRI_MAP : CPSW2_TX_PRI_MAP; 1078 1079 slave_write(slave, tx_prio_map, tx_prio_rg); 1080 } 1081 1082 int cpsw_fill_rx_channels(struct cpsw_priv *priv) 1083 { 1084 struct cpsw_common *cpsw = priv->cpsw; 1085 struct cpsw_meta_xdp *xmeta; 1086 struct page_pool *pool; 1087 struct page *page; 1088 int ch_buf_num; 1089 int ch, i, ret; 1090 dma_addr_t dma; 1091 1092 for (ch = 0; ch < cpsw->rx_ch_num; ch++) { 1093 pool = cpsw->page_pool[ch]; 1094 ch_buf_num = cpdma_chan_get_rx_buf_num(cpsw->rxv[ch].ch); 1095 for (i = 0; i < ch_buf_num; i++) { 1096 page = page_pool_dev_alloc_pages(pool); 1097 if (!page) { 1098 cpsw_err(priv, ifup, "allocate rx page err\n"); 1099 return -ENOMEM; 1100 } 1101 1102 xmeta = page_address(page) + CPSW_XMETA_OFFSET; 1103 xmeta->ndev = priv->ndev; 1104 xmeta->ch = ch; 1105 1106 dma = page_pool_get_dma_addr(page) + CPSW_HEADROOM_NA; 1107 ret = cpdma_chan_idle_submit_mapped(cpsw->rxv[ch].ch, 1108 page, dma, 1109 cpsw->rx_packet_max, 1110 0); 1111 if (ret < 0) { 1112 cpsw_err(priv, ifup, 1113 "cannot submit page to channel %d rx, error %d\n", 1114 ch, ret); 1115 page_pool_recycle_direct(pool, page); 1116 return ret; 1117 } 1118 } 1119 1120 cpsw_info(priv, ifup, "ch %d rx, submitted %d descriptors\n", 1121 ch, ch_buf_num); 1122 } 1123 1124 return 0; 1125 } 1126 1127 static struct page_pool *cpsw_create_page_pool(struct cpsw_common *cpsw, 1128 int size) 1129 { 1130 struct page_pool_params pp_params = {}; 1131 struct page_pool *pool; 1132 1133 pp_params.order = 0; 1134 pp_params.flags = PP_FLAG_DMA_MAP; 1135 pp_params.pool_size = size; 1136 pp_params.nid = NUMA_NO_NODE; 1137 pp_params.dma_dir = DMA_BIDIRECTIONAL; 1138 pp_params.dev = cpsw->dev; 1139 1140 pool = page_pool_create(&pp_params); 1141 if (IS_ERR(pool)) 1142 dev_err(cpsw->dev, "cannot create rx page pool\n"); 1143 1144 return pool; 1145 } 1146 1147 static int cpsw_create_rx_pool(struct cpsw_common *cpsw, int ch) 1148 { 1149 struct page_pool *pool; 1150 int ret = 0, pool_size; 1151 1152 pool_size = cpdma_chan_get_rx_buf_num(cpsw->rxv[ch].ch); 1153 pool = cpsw_create_page_pool(cpsw, pool_size); 1154 if (IS_ERR(pool)) 1155 ret = PTR_ERR(pool); 1156 else 1157 cpsw->page_pool[ch] = pool; 1158 1159 return ret; 1160 } 1161 1162 static int cpsw_ndev_create_xdp_rxq(struct cpsw_priv *priv, int ch) 1163 { 1164 struct cpsw_common *cpsw = priv->cpsw; 1165 struct xdp_rxq_info *rxq; 1166 struct page_pool *pool; 1167 int ret; 1168 1169 pool = cpsw->page_pool[ch]; 1170 rxq = &priv->xdp_rxq[ch]; 1171 1172 ret = xdp_rxq_info_reg(rxq, priv->ndev, ch, 0); 1173 if (ret) 1174 return ret; 1175 1176 ret = xdp_rxq_info_reg_mem_model(rxq, MEM_TYPE_PAGE_POOL, pool); 1177 if (ret) 1178 xdp_rxq_info_unreg(rxq); 1179 1180 return ret; 1181 } 1182 1183 static void cpsw_ndev_destroy_xdp_rxq(struct cpsw_priv *priv, int ch) 1184 { 1185 struct xdp_rxq_info *rxq = &priv->xdp_rxq[ch]; 1186 1187 if (!xdp_rxq_info_is_reg(rxq)) 1188 return; 1189 1190 xdp_rxq_info_unreg(rxq); 1191 } 1192 1193 void cpsw_destroy_xdp_rxqs(struct cpsw_common *cpsw) 1194 { 1195 struct net_device *ndev; 1196 int i, ch; 1197 1198 for (ch = 0; ch < cpsw->rx_ch_num; ch++) { 1199 for (i = 0; i < cpsw->data.slaves; i++) { 1200 ndev = cpsw->slaves[i].ndev; 1201 if (!ndev) 1202 continue; 1203 1204 cpsw_ndev_destroy_xdp_rxq(netdev_priv(ndev), ch); 1205 } 1206 1207 page_pool_destroy(cpsw->page_pool[ch]); 1208 cpsw->page_pool[ch] = NULL; 1209 } 1210 } 1211 1212 int cpsw_create_xdp_rxqs(struct cpsw_common *cpsw) 1213 { 1214 struct net_device *ndev; 1215 int i, ch, ret; 1216 1217 for (ch = 0; ch < cpsw->rx_ch_num; ch++) { 1218 ret = cpsw_create_rx_pool(cpsw, ch); 1219 if (ret) 1220 goto err_cleanup; 1221 1222 /* using same page pool is allowed as no running rx handlers 1223 * simultaneously for both ndevs 1224 */ 1225 for (i = 0; i < cpsw->data.slaves; i++) { 1226 ndev = cpsw->slaves[i].ndev; 1227 if (!ndev) 1228 continue; 1229 1230 ret = cpsw_ndev_create_xdp_rxq(netdev_priv(ndev), ch); 1231 if (ret) 1232 goto err_cleanup; 1233 } 1234 } 1235 1236 return 0; 1237 1238 err_cleanup: 1239 cpsw_destroy_xdp_rxqs(cpsw); 1240 1241 return ret; 1242 } 1243 1244 static int cpsw_xdp_prog_setup(struct cpsw_priv *priv, struct netdev_bpf *bpf) 1245 { 1246 struct bpf_prog *prog = bpf->prog; 1247 1248 if (!priv->xdpi.prog && !prog) 1249 return 0; 1250 1251 WRITE_ONCE(priv->xdp_prog, prog); 1252 1253 xdp_attachment_setup(&priv->xdpi, bpf); 1254 1255 return 0; 1256 } 1257 1258 int cpsw_ndo_bpf(struct net_device *ndev, struct netdev_bpf *bpf) 1259 { 1260 struct cpsw_priv *priv = netdev_priv(ndev); 1261 1262 switch (bpf->command) { 1263 case XDP_SETUP_PROG: 1264 return cpsw_xdp_prog_setup(priv, bpf); 1265 1266 default: 1267 return -EINVAL; 1268 } 1269 } 1270 1271 int cpsw_xdp_tx_frame(struct cpsw_priv *priv, struct xdp_frame *xdpf, 1272 struct page *page, int port) 1273 { 1274 struct cpsw_common *cpsw = priv->cpsw; 1275 struct cpsw_meta_xdp *xmeta; 1276 struct cpdma_chan *txch; 1277 dma_addr_t dma; 1278 int ret; 1279 1280 xmeta = (void *)xdpf + CPSW_XMETA_OFFSET; 1281 xmeta->ndev = priv->ndev; 1282 xmeta->ch = 0; 1283 txch = cpsw->txv[0].ch; 1284 1285 if (page) { 1286 dma = page_pool_get_dma_addr(page); 1287 dma += xdpf->headroom + sizeof(struct xdp_frame); 1288 ret = cpdma_chan_submit_mapped(txch, cpsw_xdpf_to_handle(xdpf), 1289 dma, xdpf->len, port); 1290 } else { 1291 if (sizeof(*xmeta) > xdpf->headroom) 1292 return -EINVAL; 1293 1294 ret = cpdma_chan_submit(txch, cpsw_xdpf_to_handle(xdpf), 1295 xdpf->data, xdpf->len, port); 1296 } 1297 1298 if (ret) 1299 priv->ndev->stats.tx_dropped++; 1300 1301 return ret; 1302 } 1303 1304 int cpsw_run_xdp(struct cpsw_priv *priv, int ch, struct xdp_buff *xdp, 1305 struct page *page, int port, int *len) 1306 { 1307 struct cpsw_common *cpsw = priv->cpsw; 1308 struct net_device *ndev = priv->ndev; 1309 int ret = CPSW_XDP_CONSUMED; 1310 struct xdp_frame *xdpf; 1311 struct bpf_prog *prog; 1312 u32 act; 1313 1314 prog = READ_ONCE(priv->xdp_prog); 1315 if (!prog) 1316 return CPSW_XDP_PASS; 1317 1318 act = bpf_prog_run_xdp(prog, xdp); 1319 /* XDP prog might have changed packet data and boundaries */ 1320 *len = xdp->data_end - xdp->data; 1321 1322 switch (act) { 1323 case XDP_PASS: 1324 ret = CPSW_XDP_PASS; 1325 goto out; 1326 case XDP_TX: 1327 xdpf = xdp_convert_buff_to_frame(xdp); 1328 if (unlikely(!xdpf)) 1329 goto drop; 1330 1331 if (cpsw_xdp_tx_frame(priv, xdpf, page, port)) 1332 xdp_return_frame_rx_napi(xdpf); 1333 break; 1334 case XDP_REDIRECT: 1335 if (xdp_do_redirect(ndev, xdp, prog)) 1336 goto drop; 1337 1338 /* Have to flush here, per packet, instead of doing it in bulk 1339 * at the end of the napi handler. The RX devices on this 1340 * particular hardware is sharing a common queue, so the 1341 * incoming device might change per packet. 1342 */ 1343 xdp_do_flush(); 1344 break; 1345 default: 1346 bpf_warn_invalid_xdp_action(ndev, prog, act); 1347 fallthrough; 1348 case XDP_ABORTED: 1349 trace_xdp_exception(ndev, prog, act); 1350 fallthrough; /* handle aborts by dropping packet */ 1351 case XDP_DROP: 1352 ndev->stats.rx_bytes += *len; 1353 ndev->stats.rx_packets++; 1354 goto drop; 1355 } 1356 1357 ndev->stats.rx_bytes += *len; 1358 ndev->stats.rx_packets++; 1359 out: 1360 return ret; 1361 drop: 1362 page_pool_recycle_direct(cpsw->page_pool[ch], page); 1363 return ret; 1364 } 1365 1366 static int cpsw_qos_clsflower_add_policer(struct cpsw_priv *priv, 1367 struct netlink_ext_ack *extack, 1368 struct flow_cls_offload *cls, 1369 u64 rate_pkt_ps) 1370 { 1371 struct flow_rule *rule = flow_cls_offload_flow_rule(cls); 1372 struct flow_dissector *dissector = rule->match.dissector; 1373 static const u8 mc_mac[] = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00}; 1374 struct flow_match_eth_addrs match; 1375 u32 port_id; 1376 int ret; 1377 1378 if (dissector->used_keys & 1379 ~(BIT_ULL(FLOW_DISSECTOR_KEY_BASIC) | 1380 BIT_ULL(FLOW_DISSECTOR_KEY_CONTROL) | 1381 BIT_ULL(FLOW_DISSECTOR_KEY_ETH_ADDRS))) { 1382 NL_SET_ERR_MSG_MOD(extack, 1383 "Unsupported keys used"); 1384 return -EOPNOTSUPP; 1385 } 1386 1387 if (flow_rule_match_has_control_flags(rule, extack)) 1388 return -EOPNOTSUPP; 1389 1390 if (!flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) { 1391 NL_SET_ERR_MSG_MOD(extack, "Not matching on eth address"); 1392 return -EOPNOTSUPP; 1393 } 1394 1395 flow_rule_match_eth_addrs(rule, &match); 1396 1397 if (!is_zero_ether_addr(match.mask->src)) { 1398 NL_SET_ERR_MSG_MOD(extack, 1399 "Matching on source MAC not supported"); 1400 return -EOPNOTSUPP; 1401 } 1402 1403 port_id = cpsw_slave_index(priv->cpsw, priv) + 1; 1404 1405 if (is_broadcast_ether_addr(match.key->dst) && 1406 is_broadcast_ether_addr(match.mask->dst)) { 1407 ret = cpsw_ale_rx_ratelimit_bc(priv->cpsw->ale, port_id, rate_pkt_ps); 1408 if (ret) 1409 return ret; 1410 1411 priv->ale_bc_ratelimit.cookie = cls->cookie; 1412 priv->ale_bc_ratelimit.rate_packet_ps = rate_pkt_ps; 1413 } else if (ether_addr_equal_unaligned(match.key->dst, mc_mac) && 1414 ether_addr_equal_unaligned(match.mask->dst, mc_mac)) { 1415 ret = cpsw_ale_rx_ratelimit_mc(priv->cpsw->ale, port_id, rate_pkt_ps); 1416 if (ret) 1417 return ret; 1418 1419 priv->ale_mc_ratelimit.cookie = cls->cookie; 1420 priv->ale_mc_ratelimit.rate_packet_ps = rate_pkt_ps; 1421 } else { 1422 NL_SET_ERR_MSG_MOD(extack, "Not supported matching key"); 1423 return -EOPNOTSUPP; 1424 } 1425 1426 return 0; 1427 } 1428 1429 static int cpsw_qos_clsflower_policer_validate(const struct flow_action *action, 1430 const struct flow_action_entry *act, 1431 struct netlink_ext_ack *extack) 1432 { 1433 if (act->police.exceed.act_id != FLOW_ACTION_DROP) { 1434 NL_SET_ERR_MSG_MOD(extack, 1435 "Offload not supported when exceed action is not drop"); 1436 return -EOPNOTSUPP; 1437 } 1438 1439 if (act->police.notexceed.act_id != FLOW_ACTION_PIPE && 1440 act->police.notexceed.act_id != FLOW_ACTION_ACCEPT) { 1441 NL_SET_ERR_MSG_MOD(extack, 1442 "Offload not supported when conform action is not pipe or ok"); 1443 return -EOPNOTSUPP; 1444 } 1445 1446 if (act->police.notexceed.act_id == FLOW_ACTION_ACCEPT && 1447 !flow_action_is_last_entry(action, act)) { 1448 NL_SET_ERR_MSG_MOD(extack, 1449 "Offload not supported when conform action is ok, but action is not last"); 1450 return -EOPNOTSUPP; 1451 } 1452 1453 if (act->police.rate_bytes_ps || act->police.peakrate_bytes_ps || 1454 act->police.avrate || act->police.overhead) { 1455 NL_SET_ERR_MSG_MOD(extack, 1456 "Offload not supported when bytes per second/peakrate/avrate/overhead is configured"); 1457 return -EOPNOTSUPP; 1458 } 1459 1460 return 0; 1461 } 1462 1463 static int cpsw_qos_configure_clsflower(struct cpsw_priv *priv, struct flow_cls_offload *cls) 1464 { 1465 struct flow_rule *rule = flow_cls_offload_flow_rule(cls); 1466 struct netlink_ext_ack *extack = cls->common.extack; 1467 const struct flow_action_entry *act; 1468 int i, ret; 1469 1470 flow_action_for_each(i, act, &rule->action) { 1471 switch (act->id) { 1472 case FLOW_ACTION_POLICE: 1473 ret = cpsw_qos_clsflower_policer_validate(&rule->action, act, extack); 1474 if (ret) 1475 return ret; 1476 1477 return cpsw_qos_clsflower_add_policer(priv, extack, cls, 1478 act->police.rate_pkt_ps); 1479 default: 1480 NL_SET_ERR_MSG_MOD(extack, "Action not supported"); 1481 return -EOPNOTSUPP; 1482 } 1483 } 1484 return -EOPNOTSUPP; 1485 } 1486 1487 static int cpsw_qos_delete_clsflower(struct cpsw_priv *priv, struct flow_cls_offload *cls) 1488 { 1489 u32 port_id = cpsw_slave_index(priv->cpsw, priv) + 1; 1490 1491 if (cls->cookie == priv->ale_bc_ratelimit.cookie) { 1492 priv->ale_bc_ratelimit.cookie = 0; 1493 priv->ale_bc_ratelimit.rate_packet_ps = 0; 1494 cpsw_ale_rx_ratelimit_bc(priv->cpsw->ale, port_id, 0); 1495 } 1496 1497 if (cls->cookie == priv->ale_mc_ratelimit.cookie) { 1498 priv->ale_mc_ratelimit.cookie = 0; 1499 priv->ale_mc_ratelimit.rate_packet_ps = 0; 1500 cpsw_ale_rx_ratelimit_mc(priv->cpsw->ale, port_id, 0); 1501 } 1502 1503 return 0; 1504 } 1505 1506 static int cpsw_qos_setup_tc_clsflower(struct cpsw_priv *priv, struct flow_cls_offload *cls_flower) 1507 { 1508 switch (cls_flower->command) { 1509 case FLOW_CLS_REPLACE: 1510 return cpsw_qos_configure_clsflower(priv, cls_flower); 1511 case FLOW_CLS_DESTROY: 1512 return cpsw_qos_delete_clsflower(priv, cls_flower); 1513 default: 1514 return -EOPNOTSUPP; 1515 } 1516 } 1517 1518 static int cpsw_qos_setup_tc_block_cb(enum tc_setup_type type, void *type_data, void *cb_priv) 1519 { 1520 struct cpsw_priv *priv = cb_priv; 1521 int ret; 1522 1523 if (!tc_cls_can_offload_and_chain0(priv->ndev, type_data)) 1524 return -EOPNOTSUPP; 1525 1526 ret = pm_runtime_get_sync(priv->dev); 1527 if (ret < 0) { 1528 pm_runtime_put_noidle(priv->dev); 1529 return ret; 1530 } 1531 1532 switch (type) { 1533 case TC_SETUP_CLSFLOWER: 1534 ret = cpsw_qos_setup_tc_clsflower(priv, type_data); 1535 break; 1536 default: 1537 ret = -EOPNOTSUPP; 1538 } 1539 1540 pm_runtime_put(priv->dev); 1541 return ret; 1542 } 1543 1544 static LIST_HEAD(cpsw_qos_block_cb_list); 1545 1546 static int cpsw_qos_setup_tc_block(struct net_device *ndev, struct flow_block_offload *f) 1547 { 1548 struct cpsw_priv *priv = netdev_priv(ndev); 1549 1550 return flow_block_cb_setup_simple(f, &cpsw_qos_block_cb_list, 1551 cpsw_qos_setup_tc_block_cb, 1552 priv, priv, true); 1553 } 1554 1555 void cpsw_qos_clsflower_resume(struct cpsw_priv *priv) 1556 { 1557 u32 port_id = cpsw_slave_index(priv->cpsw, priv) + 1; 1558 1559 if (priv->ale_bc_ratelimit.cookie) 1560 cpsw_ale_rx_ratelimit_bc(priv->cpsw->ale, port_id, 1561 priv->ale_bc_ratelimit.rate_packet_ps); 1562 1563 if (priv->ale_mc_ratelimit.cookie) 1564 cpsw_ale_rx_ratelimit_mc(priv->cpsw->ale, port_id, 1565 priv->ale_mc_ratelimit.rate_packet_ps); 1566 } 1567