1 // SPDX-License-Identifier: GPL-2.0 2 /* Texas Instruments K3 AM65 Ethernet Switch SubSystem Driver 3 * 4 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ 5 * 6 */ 7 8 #include <linux/bpf_trace.h> 9 #include <linux/clk.h> 10 #include <linux/etherdevice.h> 11 #include <linux/if_vlan.h> 12 #include <linux/interrupt.h> 13 #include <linux/irqdomain.h> 14 #include <linux/kernel.h> 15 #include <linux/kmemleak.h> 16 #include <linux/module.h> 17 #include <linux/netdevice.h> 18 #include <linux/net_tstamp.h> 19 #include <linux/of.h> 20 #include <linux/of_mdio.h> 21 #include <linux/of_net.h> 22 #include <linux/of_device.h> 23 #include <linux/of_platform.h> 24 #include <linux/phylink.h> 25 #include <linux/phy/phy.h> 26 #include <linux/platform_device.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/regmap.h> 29 #include <linux/rtnetlink.h> 30 #include <linux/mfd/syscon.h> 31 #include <linux/sys_soc.h> 32 #include <linux/dma/ti-cppi5.h> 33 #include <linux/dma/k3-udma-glue.h> 34 #include <net/page_pool/helpers.h> 35 #include <net/dsa.h> 36 #include <net/switchdev.h> 37 38 #include "cpsw_ale.h" 39 #include "cpsw_sl.h" 40 #include "am65-cpsw-nuss.h" 41 #include "am65-cpsw-switchdev.h" 42 #include "k3-cppi-desc-pool.h" 43 #include "am65-cpts.h" 44 45 #define AM65_CPSW_SS_BASE 0x0 46 #define AM65_CPSW_SGMII_BASE 0x100 47 #define AM65_CPSW_XGMII_BASE 0x2100 48 #define AM65_CPSW_CPSW_NU_BASE 0x20000 49 #define AM65_CPSW_NU_PORTS_BASE 0x1000 50 #define AM65_CPSW_NU_FRAM_BASE 0x12000 51 #define AM65_CPSW_NU_STATS_BASE 0x1a000 52 #define AM65_CPSW_NU_ALE_BASE 0x1e000 53 #define AM65_CPSW_NU_CPTS_BASE 0x1d000 54 55 #define AM65_CPSW_NU_PORTS_OFFSET 0x1000 56 #define AM65_CPSW_NU_STATS_PORT_OFFSET 0x200 57 #define AM65_CPSW_NU_FRAM_PORT_OFFSET 0x200 58 59 #define AM65_CPSW_MAX_PORTS 8 60 61 #define AM65_CPSW_MIN_PACKET_SIZE VLAN_ETH_ZLEN 62 #define AM65_CPSW_MAX_PACKET_SIZE 2024 63 64 #define AM65_CPSW_REG_CTL 0x004 65 #define AM65_CPSW_REG_STAT_PORT_EN 0x014 66 #define AM65_CPSW_REG_PTYPE 0x018 67 68 #define AM65_CPSW_P0_REG_CTL 0x004 69 #define AM65_CPSW_PORT0_REG_FLOW_ID_OFFSET 0x008 70 71 #define AM65_CPSW_PORT_REG_PRI_CTL 0x01c 72 #define AM65_CPSW_PORT_REG_RX_PRI_MAP 0x020 73 #define AM65_CPSW_PORT_REG_RX_MAXLEN 0x024 74 75 #define AM65_CPSW_PORTN_REG_CTL 0x004 76 #define AM65_CPSW_PORTN_REG_DSCP_MAP 0x120 77 #define AM65_CPSW_PORTN_REG_SA_L 0x308 78 #define AM65_CPSW_PORTN_REG_SA_H 0x30c 79 #define AM65_CPSW_PORTN_REG_TS_CTL 0x310 80 #define AM65_CPSW_PORTN_REG_TS_SEQ_LTYPE_REG 0x314 81 #define AM65_CPSW_PORTN_REG_TS_VLAN_LTYPE_REG 0x318 82 #define AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2 0x31C 83 84 #define AM65_CPSW_SGMII_CONTROL_REG 0x010 85 #define AM65_CPSW_SGMII_MR_ADV_ABILITY_REG 0x018 86 #define AM65_CPSW_SGMII_CONTROL_MR_AN_ENABLE BIT(0) 87 88 #define AM65_CPSW_CTL_VLAN_AWARE BIT(1) 89 #define AM65_CPSW_CTL_P0_ENABLE BIT(2) 90 #define AM65_CPSW_CTL_P0_TX_CRC_REMOVE BIT(13) 91 #define AM65_CPSW_CTL_P0_RX_PAD BIT(14) 92 93 /* AM65_CPSW_P0_REG_CTL */ 94 #define AM65_CPSW_P0_REG_CTL_RX_CHECKSUM_EN BIT(0) 95 #define AM65_CPSW_P0_REG_CTL_RX_REMAP_VLAN BIT(16) 96 97 /* AM65_CPSW_PORT_REG_PRI_CTL */ 98 #define AM65_CPSW_PORT_REG_PRI_CTL_RX_PTYPE_RROBIN BIT(8) 99 100 /* AM65_CPSW_PN_REG_CTL */ 101 #define AM65_CPSW_PN_REG_CTL_DSCP_IPV4_EN BIT(1) 102 #define AM65_CPSW_PN_REG_CTL_DSCP_IPV6_EN BIT(2) 103 104 /* AM65_CPSW_PN_TS_CTL register fields */ 105 #define AM65_CPSW_PN_TS_CTL_TX_ANX_F_EN BIT(4) 106 #define AM65_CPSW_PN_TS_CTL_TX_VLAN_LT1_EN BIT(5) 107 #define AM65_CPSW_PN_TS_CTL_TX_VLAN_LT2_EN BIT(6) 108 #define AM65_CPSW_PN_TS_CTL_TX_ANX_D_EN BIT(7) 109 #define AM65_CPSW_PN_TS_CTL_TX_ANX_E_EN BIT(10) 110 #define AM65_CPSW_PN_TS_CTL_TX_HOST_TS_EN BIT(11) 111 #define AM65_CPSW_PN_TS_CTL_MSG_TYPE_EN_SHIFT 16 112 113 #define AM65_CPSW_PN_TS_CTL_RX_ANX_F_EN BIT(0) 114 #define AM65_CPSW_PN_TS_CTL_RX_VLAN_LT1_EN BIT(1) 115 #define AM65_CPSW_PN_TS_CTL_RX_VLAN_LT2_EN BIT(2) 116 #define AM65_CPSW_PN_TS_CTL_RX_ANX_D_EN BIT(3) 117 #define AM65_CPSW_PN_TS_CTL_RX_ANX_E_EN BIT(9) 118 119 /* AM65_CPSW_PORTN_REG_TS_SEQ_LTYPE_REG register fields */ 120 #define AM65_CPSW_PN_TS_SEQ_ID_OFFSET_SHIFT 16 121 122 /* AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2 */ 123 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_107 BIT(16) 124 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_129 BIT(17) 125 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_130 BIT(18) 126 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_131 BIT(19) 127 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_132 BIT(20) 128 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_319 BIT(21) 129 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_320 BIT(22) 130 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_TTL_NONZERO BIT(23) 131 132 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */ 133 #define AM65_CPSW_TS_EVENT_MSG_TYPE_BITS (BIT(0) | BIT(1) | BIT(2) | BIT(3)) 134 135 #define AM65_CPSW_TS_SEQ_ID_OFFSET (0x1e) 136 137 #define AM65_CPSW_TS_TX_ANX_ALL_EN \ 138 (AM65_CPSW_PN_TS_CTL_TX_ANX_D_EN | \ 139 AM65_CPSW_PN_TS_CTL_TX_ANX_E_EN | \ 140 AM65_CPSW_PN_TS_CTL_TX_ANX_F_EN) 141 142 #define AM65_CPSW_TS_RX_ANX_ALL_EN \ 143 (AM65_CPSW_PN_TS_CTL_RX_ANX_D_EN | \ 144 AM65_CPSW_PN_TS_CTL_RX_ANX_E_EN | \ 145 AM65_CPSW_PN_TS_CTL_RX_ANX_F_EN) 146 147 #define AM65_CPSW_ALE_AGEOUT_DEFAULT 30 148 /* Number of TX/RX descriptors per channel/flow */ 149 #define AM65_CPSW_MAX_TX_DESC 500 150 #define AM65_CPSW_MAX_RX_DESC 500 151 152 #define AM65_CPSW_NAV_PS_DATA_SIZE 16 153 #define AM65_CPSW_NAV_SW_DATA_SIZE 16 154 155 #define AM65_CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_DRV | NETIF_MSG_LINK | \ 156 NETIF_MSG_IFUP | NETIF_MSG_PROBE | NETIF_MSG_IFDOWN | \ 157 NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR) 158 159 #define AM65_CPSW_DEFAULT_TX_CHNS 8 160 #define AM65_CPSW_DEFAULT_RX_CHN_FLOWS 1 161 162 /* CPPI streaming packet interface */ 163 #define AM65_CPSW_CPPI_TX_FLOW_ID 0x3FFF 164 #define AM65_CPSW_CPPI_TX_PKT_TYPE 0x7 165 166 /* XDP */ 167 #define AM65_CPSW_XDP_TX BIT(2) 168 #define AM65_CPSW_XDP_CONSUMED BIT(1) 169 #define AM65_CPSW_XDP_REDIRECT BIT(0) 170 #define AM65_CPSW_XDP_PASS 0 171 172 /* Include headroom compatible with both skb and xdpf */ 173 #define AM65_CPSW_HEADROOM_NA (max(NET_SKB_PAD, XDP_PACKET_HEADROOM) + NET_IP_ALIGN) 174 #define AM65_CPSW_HEADROOM ALIGN(AM65_CPSW_HEADROOM_NA, sizeof(long)) 175 176 static void am65_cpsw_port_set_sl_mac(struct am65_cpsw_port *slave, 177 const u8 *dev_addr) 178 { 179 u32 mac_hi = (dev_addr[0] << 0) | (dev_addr[1] << 8) | 180 (dev_addr[2] << 16) | (dev_addr[3] << 24); 181 u32 mac_lo = (dev_addr[4] << 0) | (dev_addr[5] << 8); 182 183 writel(mac_hi, slave->port_base + AM65_CPSW_PORTN_REG_SA_H); 184 writel(mac_lo, slave->port_base + AM65_CPSW_PORTN_REG_SA_L); 185 } 186 187 #define AM65_CPSW_DSCP_MAX GENMASK(5, 0) 188 #define AM65_CPSW_PRI_MAX GENMASK(2, 0) 189 #define AM65_CPSW_DSCP_PRI_PER_REG 8 190 #define AM65_CPSW_DSCP_PRI_SIZE 4 /* in bits */ 191 static int am65_cpsw_port_set_dscp_map(struct am65_cpsw_port *slave, u8 dscp, u8 pri) 192 { 193 int reg_ofs; 194 int bit_ofs; 195 u32 val; 196 197 if (dscp > AM65_CPSW_DSCP_MAX) 198 return -EINVAL; 199 200 if (pri > AM65_CPSW_PRI_MAX) 201 return -EINVAL; 202 203 /* 32-bit register offset to this dscp */ 204 reg_ofs = (dscp / AM65_CPSW_DSCP_PRI_PER_REG) * 4; 205 /* bit field offset to this dscp */ 206 bit_ofs = AM65_CPSW_DSCP_PRI_SIZE * (dscp % AM65_CPSW_DSCP_PRI_PER_REG); 207 208 val = readl(slave->port_base + AM65_CPSW_PORTN_REG_DSCP_MAP + reg_ofs); 209 val &= ~(AM65_CPSW_PRI_MAX << bit_ofs); /* clear */ 210 val |= pri << bit_ofs; /* set */ 211 writel(val, slave->port_base + AM65_CPSW_PORTN_REG_DSCP_MAP + reg_ofs); 212 213 return 0; 214 } 215 216 static void am65_cpsw_port_enable_dscp_map(struct am65_cpsw_port *slave) 217 { 218 int dscp, pri; 219 u32 val; 220 221 /* Default DSCP to User Priority mapping as per: 222 * https://datatracker.ietf.org/doc/html/rfc8325#section-4.3 223 * and 224 * https://datatracker.ietf.org/doc/html/rfc8622#section-11 225 */ 226 for (dscp = 0; dscp <= AM65_CPSW_DSCP_MAX; dscp++) { 227 switch (dscp) { 228 case 56: /* CS7 */ 229 case 48: /* CS6 */ 230 pri = 7; 231 break; 232 case 46: /* EF */ 233 case 44: /* VA */ 234 pri = 6; 235 break; 236 case 40: /* CS5 */ 237 pri = 5; 238 break; 239 case 34: /* AF41 */ 240 case 36: /* AF42 */ 241 case 38: /* AF43 */ 242 case 32: /* CS4 */ 243 case 26: /* AF31 */ 244 case 28: /* AF32 */ 245 case 30: /* AF33 */ 246 case 24: /* CS3 */ 247 pri = 4; 248 break; 249 case 18: /* AF21 */ 250 case 20: /* AF22 */ 251 case 22: /* AF23 */ 252 pri = 3; 253 break; 254 case 16: /* CS2 */ 255 case 10: /* AF11 */ 256 case 12: /* AF12 */ 257 case 14: /* AF13 */ 258 case 0: /* DF */ 259 pri = 0; 260 break; 261 case 8: /* CS1 */ 262 case 1: /* LE */ 263 pri = 1; 264 break; 265 default: 266 pri = 0; 267 break; 268 } 269 270 am65_cpsw_port_set_dscp_map(slave, dscp, pri); 271 } 272 273 /* enable port IPV4 and IPV6 DSCP for this port */ 274 val = readl(slave->port_base + AM65_CPSW_PORTN_REG_CTL); 275 val |= AM65_CPSW_PN_REG_CTL_DSCP_IPV4_EN | 276 AM65_CPSW_PN_REG_CTL_DSCP_IPV6_EN; 277 writel(val, slave->port_base + AM65_CPSW_PORTN_REG_CTL); 278 } 279 280 static void am65_cpsw_sl_ctl_reset(struct am65_cpsw_port *port) 281 { 282 cpsw_sl_reset(port->slave.mac_sl, 100); 283 /* Max length register has to be restored after MAC SL reset */ 284 writel(AM65_CPSW_MAX_PACKET_SIZE, 285 port->port_base + AM65_CPSW_PORT_REG_RX_MAXLEN); 286 } 287 288 static void am65_cpsw_nuss_get_ver(struct am65_cpsw_common *common) 289 { 290 common->nuss_ver = readl(common->ss_base); 291 common->cpsw_ver = readl(common->cpsw_base); 292 dev_info(common->dev, 293 "initializing am65 cpsw nuss version 0x%08X, cpsw version 0x%08X Ports: %u quirks:%08x\n", 294 common->nuss_ver, 295 common->cpsw_ver, 296 common->port_num + 1, 297 common->pdata.quirks); 298 } 299 300 static int am65_cpsw_nuss_ndo_slave_add_vid(struct net_device *ndev, 301 __be16 proto, u16 vid) 302 { 303 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 304 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 305 u32 port_mask, unreg_mcast = 0; 306 int ret; 307 308 if (!common->is_emac_mode) 309 return 0; 310 311 if (!netif_running(ndev) || !vid) 312 return 0; 313 314 ret = pm_runtime_resume_and_get(common->dev); 315 if (ret < 0) 316 return ret; 317 318 port_mask = BIT(port->port_id) | ALE_PORT_HOST; 319 if (!vid) 320 unreg_mcast = port_mask; 321 dev_info(common->dev, "Adding vlan %d to vlan filter\n", vid); 322 ret = cpsw_ale_vlan_add_modify(common->ale, vid, port_mask, 323 unreg_mcast, port_mask, 0); 324 325 pm_runtime_put(common->dev); 326 return ret; 327 } 328 329 static int am65_cpsw_nuss_ndo_slave_kill_vid(struct net_device *ndev, 330 __be16 proto, u16 vid) 331 { 332 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 333 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 334 int ret; 335 336 if (!common->is_emac_mode) 337 return 0; 338 339 if (!netif_running(ndev) || !vid) 340 return 0; 341 342 ret = pm_runtime_resume_and_get(common->dev); 343 if (ret < 0) 344 return ret; 345 346 dev_info(common->dev, "Removing vlan %d from vlan filter\n", vid); 347 ret = cpsw_ale_del_vlan(common->ale, vid, 348 BIT(port->port_id) | ALE_PORT_HOST); 349 350 pm_runtime_put(common->dev); 351 return ret; 352 } 353 354 static void am65_cpsw_slave_set_promisc(struct am65_cpsw_port *port, 355 bool promisc) 356 { 357 struct am65_cpsw_common *common = port->common; 358 359 if (promisc && !common->is_emac_mode) { 360 dev_dbg(common->dev, "promisc mode requested in switch mode"); 361 return; 362 } 363 364 if (promisc) { 365 /* Enable promiscuous mode */ 366 cpsw_ale_control_set(common->ale, port->port_id, 367 ALE_PORT_MACONLY_CAF, 1); 368 dev_dbg(common->dev, "promisc enabled\n"); 369 } else { 370 /* Disable promiscuous mode */ 371 cpsw_ale_control_set(common->ale, port->port_id, 372 ALE_PORT_MACONLY_CAF, 0); 373 dev_dbg(common->dev, "promisc disabled\n"); 374 } 375 } 376 377 static void am65_cpsw_nuss_ndo_slave_set_rx_mode(struct net_device *ndev) 378 { 379 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 380 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 381 u32 port_mask; 382 bool promisc; 383 384 promisc = !!(ndev->flags & IFF_PROMISC); 385 am65_cpsw_slave_set_promisc(port, promisc); 386 387 if (promisc) 388 return; 389 390 /* Restore allmulti on vlans if necessary */ 391 cpsw_ale_set_allmulti(common->ale, 392 ndev->flags & IFF_ALLMULTI, port->port_id); 393 394 port_mask = ALE_PORT_HOST; 395 /* Clear all mcast from ALE */ 396 cpsw_ale_flush_multicast(common->ale, port_mask, -1); 397 398 if (!netdev_mc_empty(ndev)) { 399 struct netdev_hw_addr *ha; 400 401 /* program multicast address list into ALE register */ 402 netdev_for_each_mc_addr(ha, ndev) { 403 cpsw_ale_add_mcast(common->ale, ha->addr, 404 port_mask, 0, 0, 0); 405 } 406 } 407 } 408 409 static void am65_cpsw_nuss_ndo_host_tx_timeout(struct net_device *ndev, 410 unsigned int txqueue) 411 { 412 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 413 struct am65_cpsw_tx_chn *tx_chn; 414 struct netdev_queue *netif_txq; 415 unsigned long trans_start; 416 417 netif_txq = netdev_get_tx_queue(ndev, txqueue); 418 tx_chn = &common->tx_chns[txqueue]; 419 trans_start = READ_ONCE(netif_txq->trans_start); 420 421 netdev_err(ndev, "txq:%d DRV_XOFF:%d tmo:%u dql_avail:%d free_desc:%zu\n", 422 txqueue, 423 netif_tx_queue_stopped(netif_txq), 424 jiffies_to_msecs(jiffies - trans_start), 425 netdev_queue_dql_avail(netif_txq), 426 k3_cppi_desc_pool_avail(tx_chn->desc_pool)); 427 428 if (netif_tx_queue_stopped(netif_txq)) { 429 /* try recover if stopped by us */ 430 txq_trans_update(ndev, netif_txq); 431 netif_tx_wake_queue(netif_txq); 432 } 433 } 434 435 static int am65_cpsw_nuss_rx_push(struct am65_cpsw_common *common, 436 struct page *page, u32 flow_idx) 437 { 438 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; 439 struct cppi5_host_desc_t *desc_rx; 440 struct device *dev = common->dev; 441 struct am65_cpsw_swdata *swdata; 442 dma_addr_t desc_dma; 443 dma_addr_t buf_dma; 444 445 desc_rx = k3_cppi_desc_pool_alloc(rx_chn->desc_pool); 446 if (!desc_rx) { 447 dev_err(dev, "Failed to allocate RXFDQ descriptor\n"); 448 return -ENOMEM; 449 } 450 desc_dma = k3_cppi_desc_pool_virt2dma(rx_chn->desc_pool, desc_rx); 451 452 buf_dma = dma_map_single(rx_chn->dma_dev, 453 page_address(page) + AM65_CPSW_HEADROOM, 454 AM65_CPSW_MAX_PACKET_SIZE, DMA_FROM_DEVICE); 455 if (unlikely(dma_mapping_error(rx_chn->dma_dev, buf_dma))) { 456 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx); 457 dev_err(dev, "Failed to map rx buffer\n"); 458 return -EINVAL; 459 } 460 461 cppi5_hdesc_init(desc_rx, CPPI5_INFO0_HDESC_EPIB_PRESENT, 462 AM65_CPSW_NAV_PS_DATA_SIZE); 463 k3_udma_glue_rx_dma_to_cppi5_addr(rx_chn->rx_chn, &buf_dma); 464 cppi5_hdesc_attach_buf(desc_rx, buf_dma, AM65_CPSW_MAX_PACKET_SIZE, 465 buf_dma, AM65_CPSW_MAX_PACKET_SIZE); 466 swdata = cppi5_hdesc_get_swdata(desc_rx); 467 swdata->page = page; 468 swdata->flow_id = flow_idx; 469 470 return k3_udma_glue_push_rx_chn(rx_chn->rx_chn, flow_idx, 471 desc_rx, desc_dma); 472 } 473 474 void am65_cpsw_nuss_set_p0_ptype(struct am65_cpsw_common *common) 475 { 476 struct am65_cpsw_host *host_p = am65_common_get_host(common); 477 u32 val, pri_map; 478 479 /* P0 set Receive Priority Type */ 480 val = readl(host_p->port_base + AM65_CPSW_PORT_REG_PRI_CTL); 481 482 if (common->pf_p0_rx_ptype_rrobin) { 483 val |= AM65_CPSW_PORT_REG_PRI_CTL_RX_PTYPE_RROBIN; 484 /* Enet Ports fifos works in fixed priority mode only, so 485 * reset P0_Rx_Pri_Map so all packet will go in Enet fifo 0 486 */ 487 pri_map = 0x0; 488 } else { 489 val &= ~AM65_CPSW_PORT_REG_PRI_CTL_RX_PTYPE_RROBIN; 490 /* restore P0_Rx_Pri_Map */ 491 pri_map = 0x76543210; 492 } 493 494 writel(pri_map, host_p->port_base + AM65_CPSW_PORT_REG_RX_PRI_MAP); 495 writel(val, host_p->port_base + AM65_CPSW_PORT_REG_PRI_CTL); 496 } 497 498 static void am65_cpsw_init_host_port_switch(struct am65_cpsw_common *common); 499 static void am65_cpsw_init_host_port_emac(struct am65_cpsw_common *common); 500 static void am65_cpsw_init_port_switch_ale(struct am65_cpsw_port *port); 501 static void am65_cpsw_init_port_emac_ale(struct am65_cpsw_port *port); 502 static inline void am65_cpsw_put_page(struct am65_cpsw_rx_flow *flow, 503 struct page *page, 504 bool allow_direct); 505 static void am65_cpsw_nuss_rx_cleanup(void *data, dma_addr_t desc_dma); 506 static void am65_cpsw_nuss_tx_cleanup(void *data, dma_addr_t desc_dma); 507 508 static void am65_cpsw_destroy_rxq(struct am65_cpsw_common *common, int id) 509 { 510 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; 511 struct am65_cpsw_rx_flow *flow; 512 struct xdp_rxq_info *rxq; 513 int port; 514 515 flow = &rx_chn->flows[id]; 516 napi_disable(&flow->napi_rx); 517 hrtimer_cancel(&flow->rx_hrtimer); 518 k3_udma_glue_reset_rx_chn(rx_chn->rx_chn, id, rx_chn, 519 am65_cpsw_nuss_rx_cleanup); 520 521 for (port = 0; port < common->port_num; port++) { 522 if (!common->ports[port].ndev) 523 continue; 524 525 rxq = &common->ports[port].xdp_rxq[id]; 526 527 if (xdp_rxq_info_is_reg(rxq)) 528 xdp_rxq_info_unreg(rxq); 529 } 530 531 if (flow->page_pool) { 532 page_pool_destroy(flow->page_pool); 533 flow->page_pool = NULL; 534 } 535 } 536 537 static void am65_cpsw_destroy_rxqs(struct am65_cpsw_common *common) 538 { 539 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; 540 int id; 541 542 reinit_completion(&common->tdown_complete); 543 k3_udma_glue_tdown_rx_chn(rx_chn->rx_chn, true); 544 545 if (common->pdata.quirks & AM64_CPSW_QUIRK_DMA_RX_TDOWN_IRQ) { 546 id = wait_for_completion_timeout(&common->tdown_complete, msecs_to_jiffies(1000)); 547 if (!id) 548 dev_err(common->dev, "rx teardown timeout\n"); 549 } 550 551 for (id = common->rx_ch_num_flows - 1; id >= 0; id--) 552 am65_cpsw_destroy_rxq(common, id); 553 554 k3_udma_glue_disable_rx_chn(common->rx_chns.rx_chn); 555 } 556 557 static int am65_cpsw_create_rxq(struct am65_cpsw_common *common, int id) 558 { 559 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; 560 struct page_pool_params pp_params = { 561 .flags = PP_FLAG_DMA_MAP, 562 .order = 0, 563 .pool_size = AM65_CPSW_MAX_RX_DESC, 564 .nid = dev_to_node(common->dev), 565 .dev = common->dev, 566 .dma_dir = DMA_BIDIRECTIONAL, 567 /* .napi set dynamically */ 568 }; 569 struct am65_cpsw_rx_flow *flow; 570 struct xdp_rxq_info *rxq; 571 struct page_pool *pool; 572 struct page *page; 573 int port, ret, i; 574 575 flow = &rx_chn->flows[id]; 576 pp_params.napi = &flow->napi_rx; 577 pool = page_pool_create(&pp_params); 578 if (IS_ERR(pool)) { 579 ret = PTR_ERR(pool); 580 return ret; 581 } 582 583 flow->page_pool = pool; 584 585 /* using same page pool is allowed as no running rx handlers 586 * simultaneously for both ndevs 587 */ 588 for (port = 0; port < common->port_num; port++) { 589 if (!common->ports[port].ndev) 590 /* FIXME should we BUG here? */ 591 continue; 592 593 rxq = &common->ports[port].xdp_rxq[id]; 594 ret = xdp_rxq_info_reg(rxq, common->ports[port].ndev, 595 id, flow->napi_rx.napi_id); 596 if (ret) 597 goto err; 598 599 ret = xdp_rxq_info_reg_mem_model(rxq, 600 MEM_TYPE_PAGE_POOL, 601 pool); 602 if (ret) 603 goto err; 604 } 605 606 for (i = 0; i < AM65_CPSW_MAX_RX_DESC; i++) { 607 page = page_pool_dev_alloc_pages(flow->page_pool); 608 if (!page) { 609 dev_err(common->dev, "cannot allocate page in flow %d\n", 610 id); 611 ret = -ENOMEM; 612 goto err; 613 } 614 615 ret = am65_cpsw_nuss_rx_push(common, page, id); 616 if (ret < 0) { 617 dev_err(common->dev, 618 "cannot submit page to rx channel flow %d, error %d\n", 619 id, ret); 620 am65_cpsw_put_page(flow, page, false); 621 goto err; 622 } 623 } 624 625 napi_enable(&flow->napi_rx); 626 return 0; 627 628 err: 629 am65_cpsw_destroy_rxq(common, id); 630 return ret; 631 } 632 633 static int am65_cpsw_create_rxqs(struct am65_cpsw_common *common) 634 { 635 int id, ret; 636 637 for (id = 0; id < common->rx_ch_num_flows; id++) { 638 ret = am65_cpsw_create_rxq(common, id); 639 if (ret) { 640 dev_err(common->dev, "couldn't create rxq %d: %d\n", 641 id, ret); 642 goto err; 643 } 644 } 645 646 ret = k3_udma_glue_enable_rx_chn(common->rx_chns.rx_chn); 647 if (ret) { 648 dev_err(common->dev, "couldn't enable rx chn: %d\n", ret); 649 goto err; 650 } 651 652 return 0; 653 654 err: 655 for (--id; id >= 0; id--) 656 am65_cpsw_destroy_rxq(common, id); 657 658 return ret; 659 } 660 661 static void am65_cpsw_destroy_txq(struct am65_cpsw_common *common, int id) 662 { 663 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[id]; 664 665 napi_disable(&tx_chn->napi_tx); 666 hrtimer_cancel(&tx_chn->tx_hrtimer); 667 k3_udma_glue_reset_tx_chn(tx_chn->tx_chn, tx_chn, 668 am65_cpsw_nuss_tx_cleanup); 669 k3_udma_glue_disable_tx_chn(tx_chn->tx_chn); 670 } 671 672 static void am65_cpsw_destroy_txqs(struct am65_cpsw_common *common) 673 { 674 struct am65_cpsw_tx_chn *tx_chn = common->tx_chns; 675 int id; 676 677 /* shutdown tx channels */ 678 atomic_set(&common->tdown_cnt, common->tx_ch_num); 679 /* ensure new tdown_cnt value is visible */ 680 smp_mb__after_atomic(); 681 reinit_completion(&common->tdown_complete); 682 683 for (id = 0; id < common->tx_ch_num; id++) 684 k3_udma_glue_tdown_tx_chn(tx_chn[id].tx_chn, false); 685 686 id = wait_for_completion_timeout(&common->tdown_complete, 687 msecs_to_jiffies(1000)); 688 if (!id) 689 dev_err(common->dev, "tx teardown timeout\n"); 690 691 for (id = common->tx_ch_num - 1; id >= 0; id--) 692 am65_cpsw_destroy_txq(common, id); 693 } 694 695 static int am65_cpsw_create_txq(struct am65_cpsw_common *common, int id) 696 { 697 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[id]; 698 int ret; 699 700 ret = k3_udma_glue_enable_tx_chn(tx_chn->tx_chn); 701 if (ret) 702 return ret; 703 704 napi_enable(&tx_chn->napi_tx); 705 706 return 0; 707 } 708 709 static int am65_cpsw_create_txqs(struct am65_cpsw_common *common) 710 { 711 int id, ret; 712 713 for (id = 0; id < common->tx_ch_num; id++) { 714 ret = am65_cpsw_create_txq(common, id); 715 if (ret) { 716 dev_err(common->dev, "couldn't create txq %d: %d\n", 717 id, ret); 718 goto err; 719 } 720 } 721 722 return 0; 723 724 err: 725 for (--id; id >= 0; id--) 726 am65_cpsw_destroy_txq(common, id); 727 728 return ret; 729 } 730 731 static int am65_cpsw_nuss_desc_idx(struct k3_cppi_desc_pool *desc_pool, 732 void *desc, 733 unsigned char dsize_log2) 734 { 735 void *pool_addr = k3_cppi_desc_pool_cpuaddr(desc_pool); 736 737 return (desc - pool_addr) >> dsize_log2; 738 } 739 740 static void am65_cpsw_nuss_set_buf_type(struct am65_cpsw_tx_chn *tx_chn, 741 struct cppi5_host_desc_t *desc, 742 enum am65_cpsw_tx_buf_type buf_type) 743 { 744 int desc_idx; 745 746 desc_idx = am65_cpsw_nuss_desc_idx(tx_chn->desc_pool, desc, 747 tx_chn->dsize_log2); 748 k3_cppi_desc_pool_desc_info_set(tx_chn->desc_pool, desc_idx, 749 (void *)buf_type); 750 } 751 752 static enum am65_cpsw_tx_buf_type am65_cpsw_nuss_buf_type(struct am65_cpsw_tx_chn *tx_chn, 753 dma_addr_t desc_dma) 754 { 755 struct cppi5_host_desc_t *desc_tx; 756 int desc_idx; 757 758 desc_tx = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, desc_dma); 759 desc_idx = am65_cpsw_nuss_desc_idx(tx_chn->desc_pool, desc_tx, 760 tx_chn->dsize_log2); 761 762 return (enum am65_cpsw_tx_buf_type)k3_cppi_desc_pool_desc_info(tx_chn->desc_pool, 763 desc_idx); 764 } 765 766 static inline void am65_cpsw_put_page(struct am65_cpsw_rx_flow *flow, 767 struct page *page, 768 bool allow_direct) 769 { 770 page_pool_put_full_page(flow->page_pool, page, allow_direct); 771 } 772 773 static void am65_cpsw_nuss_rx_cleanup(void *data, dma_addr_t desc_dma) 774 { 775 struct am65_cpsw_rx_chn *rx_chn = data; 776 struct cppi5_host_desc_t *desc_rx; 777 struct am65_cpsw_swdata *swdata; 778 dma_addr_t buf_dma; 779 struct page *page; 780 u32 buf_dma_len; 781 u32 flow_id; 782 783 desc_rx = k3_cppi_desc_pool_dma2virt(rx_chn->desc_pool, desc_dma); 784 swdata = cppi5_hdesc_get_swdata(desc_rx); 785 page = swdata->page; 786 flow_id = swdata->flow_id; 787 cppi5_hdesc_get_obuf(desc_rx, &buf_dma, &buf_dma_len); 788 k3_udma_glue_rx_cppi5_to_dma_addr(rx_chn->rx_chn, &buf_dma); 789 dma_unmap_single(rx_chn->dma_dev, buf_dma, buf_dma_len, DMA_FROM_DEVICE); 790 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx); 791 am65_cpsw_put_page(&rx_chn->flows[flow_id], page, false); 792 } 793 794 static void am65_cpsw_nuss_xmit_free(struct am65_cpsw_tx_chn *tx_chn, 795 struct cppi5_host_desc_t *desc) 796 { 797 struct cppi5_host_desc_t *first_desc, *next_desc; 798 dma_addr_t buf_dma, next_desc_dma; 799 u32 buf_dma_len; 800 801 first_desc = desc; 802 next_desc = first_desc; 803 804 cppi5_hdesc_get_obuf(first_desc, &buf_dma, &buf_dma_len); 805 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &buf_dma); 806 807 dma_unmap_single(tx_chn->dma_dev, buf_dma, buf_dma_len, DMA_TO_DEVICE); 808 809 next_desc_dma = cppi5_hdesc_get_next_hbdesc(first_desc); 810 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &next_desc_dma); 811 while (next_desc_dma) { 812 next_desc = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, 813 next_desc_dma); 814 cppi5_hdesc_get_obuf(next_desc, &buf_dma, &buf_dma_len); 815 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &buf_dma); 816 817 dma_unmap_page(tx_chn->dma_dev, buf_dma, buf_dma_len, 818 DMA_TO_DEVICE); 819 820 next_desc_dma = cppi5_hdesc_get_next_hbdesc(next_desc); 821 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &next_desc_dma); 822 823 k3_cppi_desc_pool_free(tx_chn->desc_pool, next_desc); 824 } 825 826 k3_cppi_desc_pool_free(tx_chn->desc_pool, first_desc); 827 } 828 829 static void am65_cpsw_nuss_tx_cleanup(void *data, dma_addr_t desc_dma) 830 { 831 struct am65_cpsw_tx_chn *tx_chn = data; 832 enum am65_cpsw_tx_buf_type buf_type; 833 struct am65_cpsw_tx_swdata *swdata; 834 struct cppi5_host_desc_t *desc_tx; 835 struct xdp_frame *xdpf; 836 struct sk_buff *skb; 837 838 desc_tx = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, desc_dma); 839 swdata = cppi5_hdesc_get_swdata(desc_tx); 840 buf_type = am65_cpsw_nuss_buf_type(tx_chn, desc_dma); 841 if (buf_type == AM65_CPSW_TX_BUF_TYPE_SKB) { 842 skb = swdata->skb; 843 dev_kfree_skb_any(skb); 844 } else { 845 xdpf = swdata->xdpf; 846 xdp_return_frame(xdpf); 847 } 848 849 am65_cpsw_nuss_xmit_free(tx_chn, desc_tx); 850 } 851 852 static struct sk_buff *am65_cpsw_build_skb(void *page_addr, 853 struct net_device *ndev, 854 unsigned int len, 855 unsigned int headroom) 856 { 857 struct sk_buff *skb; 858 859 len += AM65_CPSW_HEADROOM; 860 861 skb = build_skb(page_addr, len); 862 if (unlikely(!skb)) 863 return NULL; 864 865 skb_reserve(skb, headroom); 866 skb->dev = ndev; 867 868 return skb; 869 } 870 871 static int am65_cpsw_nuss_common_open(struct am65_cpsw_common *common) 872 { 873 struct am65_cpsw_host *host_p = am65_common_get_host(common); 874 u32 val, port_mask; 875 int port_idx, ret; 876 877 if (common->usage_count) 878 return 0; 879 880 /* Control register */ 881 writel(AM65_CPSW_CTL_P0_ENABLE | AM65_CPSW_CTL_P0_TX_CRC_REMOVE | 882 AM65_CPSW_CTL_VLAN_AWARE | AM65_CPSW_CTL_P0_RX_PAD, 883 common->cpsw_base + AM65_CPSW_REG_CTL); 884 /* Max length register */ 885 writel(AM65_CPSW_MAX_PACKET_SIZE, 886 host_p->port_base + AM65_CPSW_PORT_REG_RX_MAXLEN); 887 /* set base flow_id */ 888 writel(common->rx_flow_id_base, 889 host_p->port_base + AM65_CPSW_PORT0_REG_FLOW_ID_OFFSET); 890 writel(AM65_CPSW_P0_REG_CTL_RX_CHECKSUM_EN | AM65_CPSW_P0_REG_CTL_RX_REMAP_VLAN, 891 host_p->port_base + AM65_CPSW_P0_REG_CTL); 892 893 am65_cpsw_nuss_set_p0_ptype(common); 894 895 /* enable statistic */ 896 val = BIT(HOST_PORT_NUM); 897 for (port_idx = 0; port_idx < common->port_num; port_idx++) { 898 struct am65_cpsw_port *port = &common->ports[port_idx]; 899 900 if (!port->disabled) 901 val |= BIT(port->port_id); 902 } 903 writel(val, common->cpsw_base + AM65_CPSW_REG_STAT_PORT_EN); 904 905 /* disable priority elevation */ 906 writel(0, common->cpsw_base + AM65_CPSW_REG_PTYPE); 907 908 cpsw_ale_start(common->ale); 909 910 /* limit to one RX flow only */ 911 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 912 ALE_DEFAULT_THREAD_ID, 0); 913 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 914 ALE_DEFAULT_THREAD_ENABLE, 1); 915 /* switch to vlan aware mode */ 916 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_VLAN_AWARE, 1); 917 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 918 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 919 920 /* default vlan cfg: create mask based on enabled ports */ 921 port_mask = GENMASK(common->port_num, 0) & 922 ~common->disabled_ports_mask; 923 924 cpsw_ale_add_vlan(common->ale, 0, port_mask, 925 port_mask, port_mask, 926 port_mask & ~ALE_PORT_HOST); 927 928 if (common->is_emac_mode) 929 am65_cpsw_init_host_port_emac(common); 930 else 931 am65_cpsw_init_host_port_switch(common); 932 933 am65_cpsw_qos_tx_p0_rate_init(common); 934 935 ret = am65_cpsw_create_rxqs(common); 936 if (ret) 937 return ret; 938 939 ret = am65_cpsw_create_txqs(common); 940 if (ret) 941 goto cleanup_rx; 942 943 dev_dbg(common->dev, "cpsw_nuss started\n"); 944 return 0; 945 946 cleanup_rx: 947 am65_cpsw_destroy_rxqs(common); 948 949 return ret; 950 } 951 952 static int am65_cpsw_nuss_common_stop(struct am65_cpsw_common *common) 953 { 954 if (common->usage_count != 1) 955 return 0; 956 957 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 958 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 959 960 am65_cpsw_destroy_txqs(common); 961 am65_cpsw_destroy_rxqs(common); 962 cpsw_ale_stop(common->ale); 963 964 writel(0, common->cpsw_base + AM65_CPSW_REG_CTL); 965 writel(0, common->cpsw_base + AM65_CPSW_REG_STAT_PORT_EN); 966 967 dev_dbg(common->dev, "cpsw_nuss stopped\n"); 968 return 0; 969 } 970 971 static int am65_cpsw_nuss_ndo_slave_stop(struct net_device *ndev) 972 { 973 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 974 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 975 int ret; 976 977 phylink_stop(port->slave.phylink); 978 979 netif_tx_stop_all_queues(ndev); 980 981 phylink_disconnect_phy(port->slave.phylink); 982 983 ret = am65_cpsw_nuss_common_stop(common); 984 if (ret) 985 return ret; 986 987 common->usage_count--; 988 pm_runtime_put(common->dev); 989 return 0; 990 } 991 992 static int cpsw_restore_vlans(struct net_device *vdev, int vid, void *arg) 993 { 994 struct am65_cpsw_port *port = arg; 995 996 if (!vdev) 997 return 0; 998 999 return am65_cpsw_nuss_ndo_slave_add_vid(port->ndev, 0, vid); 1000 } 1001 1002 static int am65_cpsw_nuss_ndo_slave_open(struct net_device *ndev) 1003 { 1004 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 1005 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1006 int ret, i; 1007 u32 reg; 1008 1009 ret = pm_runtime_resume_and_get(common->dev); 1010 if (ret < 0) 1011 return ret; 1012 1013 /* Idle MAC port */ 1014 cpsw_sl_ctl_set(port->slave.mac_sl, CPSW_SL_CTL_CMD_IDLE); 1015 cpsw_sl_wait_for_idle(port->slave.mac_sl, 100); 1016 cpsw_sl_ctl_reset(port->slave.mac_sl); 1017 1018 /* soft reset MAC */ 1019 cpsw_sl_reg_write(port->slave.mac_sl, CPSW_SL_SOFT_RESET, 1); 1020 mdelay(1); 1021 reg = cpsw_sl_reg_read(port->slave.mac_sl, CPSW_SL_SOFT_RESET); 1022 if (reg) { 1023 dev_err(common->dev, "soft RESET didn't complete\n"); 1024 ret = -ETIMEDOUT; 1025 goto runtime_put; 1026 } 1027 1028 /* Notify the stack of the actual queue counts. */ 1029 ret = netif_set_real_num_tx_queues(ndev, common->tx_ch_num); 1030 if (ret) { 1031 dev_err(common->dev, "cannot set real number of tx queues\n"); 1032 goto runtime_put; 1033 } 1034 1035 ret = netif_set_real_num_rx_queues(ndev, common->rx_ch_num_flows); 1036 if (ret) { 1037 dev_err(common->dev, "cannot set real number of rx queues\n"); 1038 goto runtime_put; 1039 } 1040 1041 for (i = 0; i < common->tx_ch_num; i++) { 1042 struct netdev_queue *txq = netdev_get_tx_queue(ndev, i); 1043 1044 netdev_tx_reset_queue(txq); 1045 txq->tx_maxrate = common->tx_chns[i].rate_mbps; 1046 } 1047 1048 ret = am65_cpsw_nuss_common_open(common); 1049 if (ret) 1050 goto runtime_put; 1051 1052 common->usage_count++; 1053 1054 /* VLAN aware CPSW mode is incompatible with some DSA tagging schemes. 1055 * Therefore disable VLAN_AWARE mode if any of the ports is a DSA Port. 1056 */ 1057 if (netdev_uses_dsa(ndev)) { 1058 reg = readl(common->cpsw_base + AM65_CPSW_REG_CTL); 1059 reg &= ~AM65_CPSW_CTL_VLAN_AWARE; 1060 writel(reg, common->cpsw_base + AM65_CPSW_REG_CTL); 1061 } 1062 1063 am65_cpsw_port_set_sl_mac(port, ndev->dev_addr); 1064 am65_cpsw_port_enable_dscp_map(port); 1065 1066 if (common->is_emac_mode) 1067 am65_cpsw_init_port_emac_ale(port); 1068 else 1069 am65_cpsw_init_port_switch_ale(port); 1070 1071 /* mac_sl should be configured via phy-link interface */ 1072 am65_cpsw_sl_ctl_reset(port); 1073 1074 ret = phylink_of_phy_connect(port->slave.phylink, port->slave.port_np, 0); 1075 if (ret) 1076 goto error_cleanup; 1077 1078 /* restore vlan configurations */ 1079 vlan_for_each(ndev, cpsw_restore_vlans, port); 1080 1081 phylink_start(port->slave.phylink); 1082 1083 return 0; 1084 1085 error_cleanup: 1086 am65_cpsw_nuss_ndo_slave_stop(ndev); 1087 return ret; 1088 1089 runtime_put: 1090 pm_runtime_put(common->dev); 1091 return ret; 1092 } 1093 1094 static int am65_cpsw_xdp_tx_frame(struct net_device *ndev, 1095 struct am65_cpsw_tx_chn *tx_chn, 1096 struct xdp_frame *xdpf, 1097 enum am65_cpsw_tx_buf_type buf_type) 1098 { 1099 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 1100 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1101 struct cppi5_host_desc_t *host_desc; 1102 struct am65_cpsw_tx_swdata *swdata; 1103 struct netdev_queue *netif_txq; 1104 dma_addr_t dma_desc, dma_buf; 1105 u32 pkt_len = xdpf->len; 1106 int ret; 1107 1108 host_desc = k3_cppi_desc_pool_alloc(tx_chn->desc_pool); 1109 if (unlikely(!host_desc)) { 1110 ndev->stats.tx_dropped++; 1111 return AM65_CPSW_XDP_CONSUMED; /* drop */ 1112 } 1113 1114 am65_cpsw_nuss_set_buf_type(tx_chn, host_desc, buf_type); 1115 1116 dma_buf = dma_map_single(tx_chn->dma_dev, xdpf->data, 1117 pkt_len, DMA_TO_DEVICE); 1118 if (unlikely(dma_mapping_error(tx_chn->dma_dev, dma_buf))) { 1119 ndev->stats.tx_dropped++; 1120 ret = AM65_CPSW_XDP_CONSUMED; /* drop */ 1121 goto pool_free; 1122 } 1123 1124 cppi5_hdesc_init(host_desc, CPPI5_INFO0_HDESC_EPIB_PRESENT, 1125 AM65_CPSW_NAV_PS_DATA_SIZE); 1126 cppi5_hdesc_set_pkttype(host_desc, AM65_CPSW_CPPI_TX_PKT_TYPE); 1127 cppi5_hdesc_set_pktlen(host_desc, pkt_len); 1128 cppi5_desc_set_pktids(&host_desc->hdr, 0, AM65_CPSW_CPPI_TX_FLOW_ID); 1129 cppi5_desc_set_tags_ids(&host_desc->hdr, 0, port->port_id); 1130 1131 k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &dma_buf); 1132 cppi5_hdesc_attach_buf(host_desc, dma_buf, pkt_len, dma_buf, pkt_len); 1133 1134 swdata = cppi5_hdesc_get_swdata(host_desc); 1135 swdata->ndev = ndev; 1136 swdata->xdpf = xdpf; 1137 1138 /* Report BQL before sending the packet */ 1139 netif_txq = netdev_get_tx_queue(ndev, tx_chn->id); 1140 netdev_tx_sent_queue(netif_txq, pkt_len); 1141 1142 dma_desc = k3_cppi_desc_pool_virt2dma(tx_chn->desc_pool, host_desc); 1143 if (AM65_CPSW_IS_CPSW2G(common)) { 1144 ret = k3_udma_glue_push_tx_chn(tx_chn->tx_chn, host_desc, 1145 dma_desc); 1146 } else { 1147 spin_lock_bh(&tx_chn->lock); 1148 ret = k3_udma_glue_push_tx_chn(tx_chn->tx_chn, host_desc, 1149 dma_desc); 1150 spin_unlock_bh(&tx_chn->lock); 1151 } 1152 if (ret) { 1153 /* Inform BQL */ 1154 netdev_tx_completed_queue(netif_txq, 1, pkt_len); 1155 ndev->stats.tx_errors++; 1156 ret = AM65_CPSW_XDP_CONSUMED; /* drop */ 1157 goto dma_unmap; 1158 } 1159 1160 return 0; 1161 1162 dma_unmap: 1163 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &dma_buf); 1164 dma_unmap_single(tx_chn->dma_dev, dma_buf, pkt_len, DMA_TO_DEVICE); 1165 pool_free: 1166 k3_cppi_desc_pool_free(tx_chn->desc_pool, host_desc); 1167 return ret; 1168 } 1169 1170 static int am65_cpsw_run_xdp(struct am65_cpsw_rx_flow *flow, 1171 struct am65_cpsw_port *port, 1172 struct xdp_buff *xdp, int *len) 1173 { 1174 struct am65_cpsw_common *common = flow->common; 1175 struct net_device *ndev = port->ndev; 1176 int ret = AM65_CPSW_XDP_CONSUMED; 1177 struct am65_cpsw_tx_chn *tx_chn; 1178 struct netdev_queue *netif_txq; 1179 int cpu = smp_processor_id(); 1180 struct xdp_frame *xdpf; 1181 struct bpf_prog *prog; 1182 int pkt_len; 1183 u32 act; 1184 int err; 1185 1186 pkt_len = *len; 1187 prog = READ_ONCE(port->xdp_prog); 1188 if (!prog) 1189 return AM65_CPSW_XDP_PASS; 1190 1191 act = bpf_prog_run_xdp(prog, xdp); 1192 /* XDP prog might have changed packet data and boundaries */ 1193 *len = xdp->data_end - xdp->data; 1194 1195 switch (act) { 1196 case XDP_PASS: 1197 return AM65_CPSW_XDP_PASS; 1198 case XDP_TX: 1199 tx_chn = &common->tx_chns[cpu % AM65_CPSW_MAX_QUEUES]; 1200 netif_txq = netdev_get_tx_queue(ndev, tx_chn->id); 1201 1202 xdpf = xdp_convert_buff_to_frame(xdp); 1203 if (unlikely(!xdpf)) { 1204 ndev->stats.tx_dropped++; 1205 goto drop; 1206 } 1207 1208 __netif_tx_lock(netif_txq, cpu); 1209 err = am65_cpsw_xdp_tx_frame(ndev, tx_chn, xdpf, 1210 AM65_CPSW_TX_BUF_TYPE_XDP_TX); 1211 __netif_tx_unlock(netif_txq); 1212 if (err) 1213 goto drop; 1214 1215 dev_sw_netstats_rx_add(ndev, pkt_len); 1216 return AM65_CPSW_XDP_TX; 1217 case XDP_REDIRECT: 1218 if (unlikely(xdp_do_redirect(ndev, xdp, prog))) 1219 goto drop; 1220 1221 dev_sw_netstats_rx_add(ndev, pkt_len); 1222 return AM65_CPSW_XDP_REDIRECT; 1223 default: 1224 bpf_warn_invalid_xdp_action(ndev, prog, act); 1225 fallthrough; 1226 case XDP_ABORTED: 1227 drop: 1228 trace_xdp_exception(ndev, prog, act); 1229 fallthrough; 1230 case XDP_DROP: 1231 ndev->stats.rx_dropped++; 1232 } 1233 1234 return ret; 1235 } 1236 1237 /* RX psdata[2] word format - checksum information */ 1238 #define AM65_CPSW_RX_PSD_CSUM_ADD GENMASK(15, 0) 1239 #define AM65_CPSW_RX_PSD_CSUM_ERR BIT(16) 1240 #define AM65_CPSW_RX_PSD_IS_FRAGMENT BIT(17) 1241 #define AM65_CPSW_RX_PSD_IS_TCP BIT(18) 1242 #define AM65_CPSW_RX_PSD_IPV6_VALID BIT(19) 1243 #define AM65_CPSW_RX_PSD_IPV4_VALID BIT(20) 1244 1245 static void am65_cpsw_nuss_rx_csum(struct sk_buff *skb, u32 csum_info) 1246 { 1247 /* HW can verify IPv4/IPv6 TCP/UDP packets checksum 1248 * csum information provides in psdata[2] word: 1249 * AM65_CPSW_RX_PSD_CSUM_ERR bit - indicates csum error 1250 * AM65_CPSW_RX_PSD_IPV6_VALID and AM65_CPSW_RX_PSD_IPV4_VALID 1251 * bits - indicates IPv4/IPv6 packet 1252 * AM65_CPSW_RX_PSD_IS_FRAGMENT bit - indicates fragmented packet 1253 * AM65_CPSW_RX_PSD_CSUM_ADD has value 0xFFFF for non fragmented packets 1254 * or csum value for fragmented packets if !AM65_CPSW_RX_PSD_CSUM_ERR 1255 */ 1256 skb_checksum_none_assert(skb); 1257 1258 if (unlikely(!(skb->dev->features & NETIF_F_RXCSUM))) 1259 return; 1260 1261 if ((csum_info & (AM65_CPSW_RX_PSD_IPV6_VALID | 1262 AM65_CPSW_RX_PSD_IPV4_VALID)) && 1263 !(csum_info & AM65_CPSW_RX_PSD_CSUM_ERR)) { 1264 /* csum for fragmented packets is unsupported */ 1265 if (!(csum_info & AM65_CPSW_RX_PSD_IS_FRAGMENT)) 1266 skb->ip_summed = CHECKSUM_UNNECESSARY; 1267 } 1268 } 1269 1270 static int am65_cpsw_nuss_rx_packets(struct am65_cpsw_rx_flow *flow, 1271 int *xdp_state) 1272 { 1273 struct am65_cpsw_rx_chn *rx_chn = &flow->common->rx_chns; 1274 u32 buf_dma_len, pkt_len, port_id = 0, csum_info; 1275 struct am65_cpsw_common *common = flow->common; 1276 struct am65_cpsw_ndev_priv *ndev_priv; 1277 struct cppi5_host_desc_t *desc_rx; 1278 struct device *dev = common->dev; 1279 struct am65_cpsw_swdata *swdata; 1280 struct page *page, *new_page; 1281 dma_addr_t desc_dma, buf_dma; 1282 struct am65_cpsw_port *port; 1283 struct net_device *ndev; 1284 u32 flow_idx = flow->id; 1285 struct sk_buff *skb; 1286 struct xdp_buff xdp; 1287 int headroom, ret; 1288 void *page_addr; 1289 u32 *psdata; 1290 1291 *xdp_state = AM65_CPSW_XDP_PASS; 1292 ret = k3_udma_glue_pop_rx_chn(rx_chn->rx_chn, flow_idx, &desc_dma); 1293 if (ret) { 1294 if (ret != -ENODATA) 1295 dev_err(dev, "RX: pop chn fail %d\n", ret); 1296 return ret; 1297 } 1298 1299 if (cppi5_desc_is_tdcm(desc_dma)) { 1300 dev_dbg(dev, "%s RX tdown flow: %u\n", __func__, flow_idx); 1301 if (common->pdata.quirks & AM64_CPSW_QUIRK_DMA_RX_TDOWN_IRQ) 1302 complete(&common->tdown_complete); 1303 return 0; 1304 } 1305 1306 desc_rx = k3_cppi_desc_pool_dma2virt(rx_chn->desc_pool, desc_dma); 1307 dev_dbg(dev, "%s flow_idx: %u desc %pad\n", 1308 __func__, flow_idx, &desc_dma); 1309 1310 swdata = cppi5_hdesc_get_swdata(desc_rx); 1311 page = swdata->page; 1312 page_addr = page_address(page); 1313 cppi5_hdesc_get_obuf(desc_rx, &buf_dma, &buf_dma_len); 1314 k3_udma_glue_rx_cppi5_to_dma_addr(rx_chn->rx_chn, &buf_dma); 1315 pkt_len = cppi5_hdesc_get_pktlen(desc_rx); 1316 cppi5_desc_get_tags_ids(&desc_rx->hdr, &port_id, NULL); 1317 dev_dbg(dev, "%s rx port_id:%d\n", __func__, port_id); 1318 port = am65_common_get_port(common, port_id); 1319 ndev = port->ndev; 1320 psdata = cppi5_hdesc_get_psdata(desc_rx); 1321 csum_info = psdata[2]; 1322 dev_dbg(dev, "%s rx csum_info:%#x\n", __func__, csum_info); 1323 1324 dma_unmap_single(rx_chn->dma_dev, buf_dma, buf_dma_len, DMA_FROM_DEVICE); 1325 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx); 1326 1327 if (port->xdp_prog) { 1328 xdp_init_buff(&xdp, PAGE_SIZE, &port->xdp_rxq[flow->id]); 1329 xdp_prepare_buff(&xdp, page_addr, AM65_CPSW_HEADROOM, 1330 pkt_len, false); 1331 *xdp_state = am65_cpsw_run_xdp(flow, port, &xdp, &pkt_len); 1332 if (*xdp_state == AM65_CPSW_XDP_CONSUMED) { 1333 page = virt_to_head_page(xdp.data); 1334 am65_cpsw_put_page(flow, page, true); 1335 goto allocate; 1336 } 1337 1338 if (*xdp_state != AM65_CPSW_XDP_PASS) 1339 goto allocate; 1340 1341 headroom = xdp.data - xdp.data_hard_start; 1342 } else { 1343 headroom = AM65_CPSW_HEADROOM; 1344 } 1345 1346 skb = am65_cpsw_build_skb(page_addr, ndev, 1347 AM65_CPSW_MAX_PACKET_SIZE, headroom); 1348 if (unlikely(!skb)) { 1349 new_page = page; 1350 goto requeue; 1351 } 1352 1353 ndev_priv = netdev_priv(ndev); 1354 am65_cpsw_nuss_set_offload_fwd_mark(skb, ndev_priv->offload_fwd_mark); 1355 skb_put(skb, pkt_len); 1356 if (port->rx_ts_enabled) 1357 am65_cpts_rx_timestamp(common->cpts, skb); 1358 skb_mark_for_recycle(skb); 1359 skb->protocol = eth_type_trans(skb, ndev); 1360 am65_cpsw_nuss_rx_csum(skb, csum_info); 1361 napi_gro_receive(&flow->napi_rx, skb); 1362 1363 dev_sw_netstats_rx_add(ndev, pkt_len); 1364 1365 allocate: 1366 new_page = page_pool_dev_alloc_pages(flow->page_pool); 1367 if (unlikely(!new_page)) { 1368 dev_err(dev, "page alloc failed\n"); 1369 return -ENOMEM; 1370 } 1371 1372 if (netif_dormant(ndev)) { 1373 am65_cpsw_put_page(flow, new_page, true); 1374 ndev->stats.rx_dropped++; 1375 return 0; 1376 } 1377 1378 requeue: 1379 ret = am65_cpsw_nuss_rx_push(common, new_page, flow_idx); 1380 if (WARN_ON(ret < 0)) { 1381 am65_cpsw_put_page(flow, new_page, true); 1382 ndev->stats.rx_errors++; 1383 ndev->stats.rx_dropped++; 1384 } 1385 1386 return ret; 1387 } 1388 1389 static enum hrtimer_restart am65_cpsw_nuss_rx_timer_callback(struct hrtimer *timer) 1390 { 1391 struct am65_cpsw_rx_flow *flow = container_of(timer, 1392 struct am65_cpsw_rx_flow, 1393 rx_hrtimer); 1394 1395 enable_irq(flow->irq); 1396 return HRTIMER_NORESTART; 1397 } 1398 1399 static int am65_cpsw_nuss_rx_poll(struct napi_struct *napi_rx, int budget) 1400 { 1401 struct am65_cpsw_rx_flow *flow = am65_cpsw_napi_to_rx_flow(napi_rx); 1402 struct am65_cpsw_common *common = flow->common; 1403 int xdp_state_or = 0; 1404 int cur_budget, ret; 1405 int xdp_state; 1406 int num_rx = 0; 1407 1408 /* process only this flow */ 1409 cur_budget = budget; 1410 while (cur_budget--) { 1411 ret = am65_cpsw_nuss_rx_packets(flow, &xdp_state); 1412 xdp_state_or |= xdp_state; 1413 if (ret) 1414 break; 1415 num_rx++; 1416 } 1417 1418 if (xdp_state_or & AM65_CPSW_XDP_REDIRECT) 1419 xdp_do_flush(); 1420 1421 dev_dbg(common->dev, "%s num_rx:%d %d\n", __func__, num_rx, budget); 1422 1423 if (num_rx < budget && napi_complete_done(napi_rx, num_rx)) { 1424 if (flow->irq_disabled) { 1425 flow->irq_disabled = false; 1426 if (unlikely(flow->rx_pace_timeout)) { 1427 hrtimer_start(&flow->rx_hrtimer, 1428 ns_to_ktime(flow->rx_pace_timeout), 1429 HRTIMER_MODE_REL_PINNED); 1430 } else { 1431 enable_irq(flow->irq); 1432 } 1433 } 1434 } 1435 1436 return num_rx; 1437 } 1438 1439 static void am65_cpsw_nuss_tx_wake(struct am65_cpsw_tx_chn *tx_chn, struct net_device *ndev, 1440 struct netdev_queue *netif_txq) 1441 { 1442 if (netif_tx_queue_stopped(netif_txq)) { 1443 /* Check whether the queue is stopped due to stalled 1444 * tx dma, if the queue is stopped then wake the queue 1445 * as we have free desc for tx 1446 */ 1447 __netif_tx_lock(netif_txq, smp_processor_id()); 1448 if (netif_running(ndev) && 1449 (k3_cppi_desc_pool_avail(tx_chn->desc_pool) >= MAX_SKB_FRAGS)) 1450 netif_tx_wake_queue(netif_txq); 1451 1452 __netif_tx_unlock(netif_txq); 1453 } 1454 } 1455 1456 static int am65_cpsw_nuss_tx_compl_packets(struct am65_cpsw_common *common, 1457 int chn, unsigned int budget, bool *tdown) 1458 { 1459 bool single_port = AM65_CPSW_IS_CPSW2G(common); 1460 enum am65_cpsw_tx_buf_type buf_type; 1461 struct am65_cpsw_tx_swdata *swdata; 1462 struct cppi5_host_desc_t *desc_tx; 1463 struct device *dev = common->dev; 1464 struct am65_cpsw_tx_chn *tx_chn; 1465 struct netdev_queue *netif_txq; 1466 unsigned int total_bytes = 0; 1467 struct net_device *ndev; 1468 struct xdp_frame *xdpf; 1469 unsigned int pkt_len; 1470 struct sk_buff *skb; 1471 dma_addr_t desc_dma; 1472 int res, num_tx = 0; 1473 1474 tx_chn = &common->tx_chns[chn]; 1475 1476 while (true) { 1477 if (!single_port) 1478 spin_lock(&tx_chn->lock); 1479 res = k3_udma_glue_pop_tx_chn(tx_chn->tx_chn, &desc_dma); 1480 if (!single_port) 1481 spin_unlock(&tx_chn->lock); 1482 1483 if (res == -ENODATA) 1484 break; 1485 1486 if (cppi5_desc_is_tdcm(desc_dma)) { 1487 if (atomic_dec_and_test(&common->tdown_cnt)) 1488 complete(&common->tdown_complete); 1489 *tdown = true; 1490 break; 1491 } 1492 1493 desc_tx = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, 1494 desc_dma); 1495 swdata = cppi5_hdesc_get_swdata(desc_tx); 1496 ndev = swdata->ndev; 1497 buf_type = am65_cpsw_nuss_buf_type(tx_chn, desc_dma); 1498 if (buf_type == AM65_CPSW_TX_BUF_TYPE_SKB) { 1499 skb = swdata->skb; 1500 am65_cpts_tx_timestamp(tx_chn->common->cpts, skb); 1501 pkt_len = skb->len; 1502 napi_consume_skb(skb, budget); 1503 } else { 1504 xdpf = swdata->xdpf; 1505 pkt_len = xdpf->len; 1506 if (buf_type == AM65_CPSW_TX_BUF_TYPE_XDP_TX) 1507 xdp_return_frame_rx_napi(xdpf); 1508 else 1509 xdp_return_frame(xdpf); 1510 } 1511 1512 total_bytes += pkt_len; 1513 num_tx++; 1514 am65_cpsw_nuss_xmit_free(tx_chn, desc_tx); 1515 dev_sw_netstats_tx_add(ndev, 1, pkt_len); 1516 if (!single_port) { 1517 /* as packets from multi ports can be interleaved 1518 * on the same channel, we have to figure out the 1519 * port/queue at every packet and report it/wake queue. 1520 */ 1521 netif_txq = netdev_get_tx_queue(ndev, chn); 1522 netdev_tx_completed_queue(netif_txq, 1, pkt_len); 1523 am65_cpsw_nuss_tx_wake(tx_chn, ndev, netif_txq); 1524 } 1525 } 1526 1527 if (single_port) { 1528 netif_txq = netdev_get_tx_queue(ndev, chn); 1529 netdev_tx_completed_queue(netif_txq, num_tx, total_bytes); 1530 am65_cpsw_nuss_tx_wake(tx_chn, ndev, netif_txq); 1531 } 1532 1533 dev_dbg(dev, "%s:%u pkt:%d\n", __func__, chn, num_tx); 1534 1535 return num_tx; 1536 } 1537 1538 static enum hrtimer_restart am65_cpsw_nuss_tx_timer_callback(struct hrtimer *timer) 1539 { 1540 struct am65_cpsw_tx_chn *tx_chns = 1541 container_of(timer, struct am65_cpsw_tx_chn, tx_hrtimer); 1542 1543 enable_irq(tx_chns->irq); 1544 return HRTIMER_NORESTART; 1545 } 1546 1547 static int am65_cpsw_nuss_tx_poll(struct napi_struct *napi_tx, int budget) 1548 { 1549 struct am65_cpsw_tx_chn *tx_chn = am65_cpsw_napi_to_tx_chn(napi_tx); 1550 bool tdown = false; 1551 int num_tx; 1552 1553 num_tx = am65_cpsw_nuss_tx_compl_packets(tx_chn->common, 1554 tx_chn->id, budget, &tdown); 1555 if (num_tx >= budget) 1556 return budget; 1557 1558 if (napi_complete_done(napi_tx, num_tx)) { 1559 if (unlikely(tx_chn->tx_pace_timeout && !tdown)) { 1560 hrtimer_start(&tx_chn->tx_hrtimer, 1561 ns_to_ktime(tx_chn->tx_pace_timeout), 1562 HRTIMER_MODE_REL_PINNED); 1563 } else { 1564 enable_irq(tx_chn->irq); 1565 } 1566 } 1567 1568 return 0; 1569 } 1570 1571 static irqreturn_t am65_cpsw_nuss_rx_irq(int irq, void *dev_id) 1572 { 1573 struct am65_cpsw_rx_flow *flow = dev_id; 1574 1575 flow->irq_disabled = true; 1576 disable_irq_nosync(irq); 1577 napi_schedule(&flow->napi_rx); 1578 1579 return IRQ_HANDLED; 1580 } 1581 1582 static irqreturn_t am65_cpsw_nuss_tx_irq(int irq, void *dev_id) 1583 { 1584 struct am65_cpsw_tx_chn *tx_chn = dev_id; 1585 1586 disable_irq_nosync(irq); 1587 napi_schedule(&tx_chn->napi_tx); 1588 1589 return IRQ_HANDLED; 1590 } 1591 1592 static netdev_tx_t am65_cpsw_nuss_ndo_slave_xmit(struct sk_buff *skb, 1593 struct net_device *ndev) 1594 { 1595 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 1596 struct cppi5_host_desc_t *first_desc, *next_desc, *cur_desc; 1597 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1598 struct am65_cpsw_tx_swdata *swdata; 1599 struct device *dev = common->dev; 1600 struct am65_cpsw_tx_chn *tx_chn; 1601 struct netdev_queue *netif_txq; 1602 dma_addr_t desc_dma, buf_dma; 1603 int ret, q_idx, i; 1604 u32 *psdata; 1605 u32 pkt_len; 1606 1607 /* padding enabled in hw */ 1608 pkt_len = skb_headlen(skb); 1609 1610 /* SKB TX timestamp */ 1611 if (port->tx_ts_enabled) 1612 am65_cpts_prep_tx_timestamp(common->cpts, skb); 1613 1614 q_idx = skb_get_queue_mapping(skb); 1615 dev_dbg(dev, "%s skb_queue:%d\n", __func__, q_idx); 1616 1617 tx_chn = &common->tx_chns[q_idx]; 1618 netif_txq = netdev_get_tx_queue(ndev, q_idx); 1619 1620 /* Map the linear buffer */ 1621 buf_dma = dma_map_single(tx_chn->dma_dev, skb->data, pkt_len, 1622 DMA_TO_DEVICE); 1623 if (unlikely(dma_mapping_error(tx_chn->dma_dev, buf_dma))) { 1624 dev_err(dev, "Failed to map tx skb buffer\n"); 1625 ndev->stats.tx_errors++; 1626 goto err_free_skb; 1627 } 1628 1629 first_desc = k3_cppi_desc_pool_alloc(tx_chn->desc_pool); 1630 if (!first_desc) { 1631 dev_dbg(dev, "Failed to allocate descriptor\n"); 1632 dma_unmap_single(tx_chn->dma_dev, buf_dma, pkt_len, 1633 DMA_TO_DEVICE); 1634 goto busy_stop_q; 1635 } 1636 1637 am65_cpsw_nuss_set_buf_type(tx_chn, first_desc, 1638 AM65_CPSW_TX_BUF_TYPE_SKB); 1639 1640 cppi5_hdesc_init(first_desc, CPPI5_INFO0_HDESC_EPIB_PRESENT, 1641 AM65_CPSW_NAV_PS_DATA_SIZE); 1642 cppi5_desc_set_pktids(&first_desc->hdr, 0, AM65_CPSW_CPPI_TX_FLOW_ID); 1643 cppi5_hdesc_set_pkttype(first_desc, AM65_CPSW_CPPI_TX_PKT_TYPE); 1644 cppi5_desc_set_tags_ids(&first_desc->hdr, 0, port->port_id); 1645 1646 k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &buf_dma); 1647 cppi5_hdesc_attach_buf(first_desc, buf_dma, pkt_len, buf_dma, pkt_len); 1648 swdata = cppi5_hdesc_get_swdata(first_desc); 1649 swdata->ndev = ndev; 1650 swdata->skb = skb; 1651 psdata = cppi5_hdesc_get_psdata(first_desc); 1652 1653 /* HW csum offload if enabled */ 1654 psdata[2] = 0; 1655 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) { 1656 unsigned int cs_start, cs_offset; 1657 1658 cs_start = skb_transport_offset(skb); 1659 cs_offset = cs_start + skb->csum_offset; 1660 /* HW numerates bytes starting from 1 */ 1661 psdata[2] = ((cs_offset + 1) << 24) | 1662 ((cs_start + 1) << 16) | (skb->len - cs_start); 1663 dev_dbg(dev, "%s tx psdata:%#x\n", __func__, psdata[2]); 1664 } 1665 1666 if (!skb_is_nonlinear(skb)) 1667 goto done_tx; 1668 1669 dev_dbg(dev, "fragmented SKB\n"); 1670 1671 /* Handle the case where skb is fragmented in pages */ 1672 cur_desc = first_desc; 1673 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1674 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1675 u32 frag_size = skb_frag_size(frag); 1676 1677 next_desc = k3_cppi_desc_pool_alloc(tx_chn->desc_pool); 1678 if (!next_desc) { 1679 dev_err(dev, "Failed to allocate descriptor\n"); 1680 goto busy_free_descs; 1681 } 1682 1683 am65_cpsw_nuss_set_buf_type(tx_chn, next_desc, 1684 AM65_CPSW_TX_BUF_TYPE_SKB); 1685 1686 buf_dma = skb_frag_dma_map(tx_chn->dma_dev, frag, 0, frag_size, 1687 DMA_TO_DEVICE); 1688 if (unlikely(dma_mapping_error(tx_chn->dma_dev, buf_dma))) { 1689 dev_err(dev, "Failed to map tx skb page\n"); 1690 k3_cppi_desc_pool_free(tx_chn->desc_pool, next_desc); 1691 ndev->stats.tx_errors++; 1692 goto err_free_descs; 1693 } 1694 1695 cppi5_hdesc_reset_hbdesc(next_desc); 1696 k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &buf_dma); 1697 cppi5_hdesc_attach_buf(next_desc, 1698 buf_dma, frag_size, buf_dma, frag_size); 1699 1700 desc_dma = k3_cppi_desc_pool_virt2dma(tx_chn->desc_pool, 1701 next_desc); 1702 k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &desc_dma); 1703 cppi5_hdesc_link_hbdesc(cur_desc, desc_dma); 1704 1705 pkt_len += frag_size; 1706 cur_desc = next_desc; 1707 } 1708 WARN_ON(pkt_len != skb->len); 1709 1710 done_tx: 1711 skb_tx_timestamp(skb); 1712 1713 /* report bql before sending packet */ 1714 netdev_tx_sent_queue(netif_txq, pkt_len); 1715 1716 cppi5_hdesc_set_pktlen(first_desc, pkt_len); 1717 desc_dma = k3_cppi_desc_pool_virt2dma(tx_chn->desc_pool, first_desc); 1718 if (AM65_CPSW_IS_CPSW2G(common)) { 1719 ret = k3_udma_glue_push_tx_chn(tx_chn->tx_chn, first_desc, desc_dma); 1720 } else { 1721 spin_lock_bh(&tx_chn->lock); 1722 ret = k3_udma_glue_push_tx_chn(tx_chn->tx_chn, first_desc, desc_dma); 1723 spin_unlock_bh(&tx_chn->lock); 1724 } 1725 if (ret) { 1726 dev_err(dev, "can't push desc %d\n", ret); 1727 /* inform bql */ 1728 netdev_tx_completed_queue(netif_txq, 1, pkt_len); 1729 ndev->stats.tx_errors++; 1730 goto err_free_descs; 1731 } 1732 1733 if (k3_cppi_desc_pool_avail(tx_chn->desc_pool) < MAX_SKB_FRAGS) { 1734 netif_tx_stop_queue(netif_txq); 1735 /* Barrier, so that stop_queue visible to other cpus */ 1736 smp_mb__after_atomic(); 1737 dev_dbg(dev, "netif_tx_stop_queue %d\n", q_idx); 1738 1739 /* re-check for smp */ 1740 if (k3_cppi_desc_pool_avail(tx_chn->desc_pool) >= 1741 MAX_SKB_FRAGS) { 1742 netif_tx_wake_queue(netif_txq); 1743 dev_dbg(dev, "netif_tx_wake_queue %d\n", q_idx); 1744 } 1745 } 1746 1747 return NETDEV_TX_OK; 1748 1749 err_free_descs: 1750 am65_cpsw_nuss_xmit_free(tx_chn, first_desc); 1751 err_free_skb: 1752 ndev->stats.tx_dropped++; 1753 dev_kfree_skb_any(skb); 1754 return NETDEV_TX_OK; 1755 1756 busy_free_descs: 1757 am65_cpsw_nuss_xmit_free(tx_chn, first_desc); 1758 busy_stop_q: 1759 netif_tx_stop_queue(netif_txq); 1760 return NETDEV_TX_BUSY; 1761 } 1762 1763 static int am65_cpsw_nuss_ndo_slave_set_mac_address(struct net_device *ndev, 1764 void *addr) 1765 { 1766 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 1767 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1768 struct sockaddr *sockaddr = (struct sockaddr *)addr; 1769 int ret; 1770 1771 ret = eth_prepare_mac_addr_change(ndev, addr); 1772 if (ret < 0) 1773 return ret; 1774 1775 ret = pm_runtime_resume_and_get(common->dev); 1776 if (ret < 0) 1777 return ret; 1778 1779 cpsw_ale_del_ucast(common->ale, ndev->dev_addr, 1780 HOST_PORT_NUM, 0, 0); 1781 cpsw_ale_add_ucast(common->ale, sockaddr->sa_data, 1782 HOST_PORT_NUM, ALE_SECURE, 0); 1783 1784 am65_cpsw_port_set_sl_mac(port, addr); 1785 eth_commit_mac_addr_change(ndev, sockaddr); 1786 1787 pm_runtime_put(common->dev); 1788 1789 return 0; 1790 } 1791 1792 static int am65_cpsw_nuss_hwtstamp_set(struct net_device *ndev, 1793 struct ifreq *ifr) 1794 { 1795 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1796 u32 ts_ctrl, seq_id, ts_ctrl_ltype2, ts_vlan_ltype; 1797 struct hwtstamp_config cfg; 1798 1799 if (!IS_ENABLED(CONFIG_TI_K3_AM65_CPTS)) 1800 return -EOPNOTSUPP; 1801 1802 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 1803 return -EFAULT; 1804 1805 /* TX HW timestamp */ 1806 switch (cfg.tx_type) { 1807 case HWTSTAMP_TX_OFF: 1808 case HWTSTAMP_TX_ON: 1809 break; 1810 default: 1811 return -ERANGE; 1812 } 1813 1814 switch (cfg.rx_filter) { 1815 case HWTSTAMP_FILTER_NONE: 1816 port->rx_ts_enabled = false; 1817 break; 1818 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 1819 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 1820 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 1821 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1822 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 1823 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 1824 case HWTSTAMP_FILTER_PTP_V2_EVENT: 1825 case HWTSTAMP_FILTER_PTP_V2_SYNC: 1826 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 1827 port->rx_ts_enabled = true; 1828 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 1829 break; 1830 case HWTSTAMP_FILTER_ALL: 1831 case HWTSTAMP_FILTER_SOME: 1832 case HWTSTAMP_FILTER_NTP_ALL: 1833 return -EOPNOTSUPP; 1834 default: 1835 return -ERANGE; 1836 } 1837 1838 port->tx_ts_enabled = (cfg.tx_type == HWTSTAMP_TX_ON); 1839 1840 /* cfg TX timestamp */ 1841 seq_id = (AM65_CPSW_TS_SEQ_ID_OFFSET << 1842 AM65_CPSW_PN_TS_SEQ_ID_OFFSET_SHIFT) | ETH_P_1588; 1843 1844 ts_vlan_ltype = ETH_P_8021Q; 1845 1846 ts_ctrl_ltype2 = ETH_P_1588 | 1847 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_107 | 1848 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_129 | 1849 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_130 | 1850 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_131 | 1851 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_132 | 1852 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_319 | 1853 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_320 | 1854 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_TTL_NONZERO; 1855 1856 ts_ctrl = AM65_CPSW_TS_EVENT_MSG_TYPE_BITS << 1857 AM65_CPSW_PN_TS_CTL_MSG_TYPE_EN_SHIFT; 1858 1859 if (port->tx_ts_enabled) 1860 ts_ctrl |= AM65_CPSW_TS_TX_ANX_ALL_EN | 1861 AM65_CPSW_PN_TS_CTL_TX_VLAN_LT1_EN; 1862 1863 if (port->rx_ts_enabled) 1864 ts_ctrl |= AM65_CPSW_TS_RX_ANX_ALL_EN | 1865 AM65_CPSW_PN_TS_CTL_RX_VLAN_LT1_EN; 1866 1867 writel(seq_id, port->port_base + AM65_CPSW_PORTN_REG_TS_SEQ_LTYPE_REG); 1868 writel(ts_vlan_ltype, port->port_base + 1869 AM65_CPSW_PORTN_REG_TS_VLAN_LTYPE_REG); 1870 writel(ts_ctrl_ltype2, port->port_base + 1871 AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2); 1872 writel(ts_ctrl, port->port_base + AM65_CPSW_PORTN_REG_TS_CTL); 1873 1874 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 1875 } 1876 1877 static int am65_cpsw_nuss_hwtstamp_get(struct net_device *ndev, 1878 struct ifreq *ifr) 1879 { 1880 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1881 struct hwtstamp_config cfg; 1882 1883 if (!IS_ENABLED(CONFIG_TI_K3_AM65_CPTS)) 1884 return -EOPNOTSUPP; 1885 1886 cfg.flags = 0; 1887 cfg.tx_type = port->tx_ts_enabled ? 1888 HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF; 1889 cfg.rx_filter = port->rx_ts_enabled ? 1890 HWTSTAMP_FILTER_PTP_V2_EVENT : HWTSTAMP_FILTER_NONE; 1891 1892 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 1893 } 1894 1895 static int am65_cpsw_nuss_ndo_slave_ioctl(struct net_device *ndev, 1896 struct ifreq *req, int cmd) 1897 { 1898 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1899 1900 if (!netif_running(ndev)) 1901 return -EINVAL; 1902 1903 switch (cmd) { 1904 case SIOCSHWTSTAMP: 1905 return am65_cpsw_nuss_hwtstamp_set(ndev, req); 1906 case SIOCGHWTSTAMP: 1907 return am65_cpsw_nuss_hwtstamp_get(ndev, req); 1908 } 1909 1910 return phylink_mii_ioctl(port->slave.phylink, req, cmd); 1911 } 1912 1913 static void am65_cpsw_nuss_ndo_get_stats(struct net_device *dev, 1914 struct rtnl_link_stats64 *stats) 1915 { 1916 dev_fetch_sw_netstats(stats, dev->tstats); 1917 1918 stats->rx_errors = dev->stats.rx_errors; 1919 stats->rx_dropped = dev->stats.rx_dropped; 1920 stats->tx_dropped = dev->stats.tx_dropped; 1921 } 1922 1923 static int am65_cpsw_xdp_prog_setup(struct net_device *ndev, 1924 struct bpf_prog *prog) 1925 { 1926 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1927 bool running = netif_running(ndev); 1928 struct bpf_prog *old_prog; 1929 1930 if (running) 1931 am65_cpsw_nuss_ndo_slave_stop(ndev); 1932 1933 old_prog = xchg(&port->xdp_prog, prog); 1934 if (old_prog) 1935 bpf_prog_put(old_prog); 1936 1937 if (running) 1938 return am65_cpsw_nuss_ndo_slave_open(ndev); 1939 1940 return 0; 1941 } 1942 1943 static int am65_cpsw_ndo_bpf(struct net_device *ndev, struct netdev_bpf *bpf) 1944 { 1945 switch (bpf->command) { 1946 case XDP_SETUP_PROG: 1947 return am65_cpsw_xdp_prog_setup(ndev, bpf->prog); 1948 default: 1949 return -EINVAL; 1950 } 1951 } 1952 1953 static int am65_cpsw_ndo_xdp_xmit(struct net_device *ndev, int n, 1954 struct xdp_frame **frames, u32 flags) 1955 { 1956 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 1957 struct am65_cpsw_tx_chn *tx_chn; 1958 struct netdev_queue *netif_txq; 1959 int cpu = smp_processor_id(); 1960 int i, nxmit = 0; 1961 1962 tx_chn = &common->tx_chns[cpu % common->tx_ch_num]; 1963 netif_txq = netdev_get_tx_queue(ndev, tx_chn->id); 1964 1965 __netif_tx_lock(netif_txq, cpu); 1966 for (i = 0; i < n; i++) { 1967 if (am65_cpsw_xdp_tx_frame(ndev, tx_chn, frames[i], 1968 AM65_CPSW_TX_BUF_TYPE_XDP_NDO)) 1969 break; 1970 nxmit++; 1971 } 1972 __netif_tx_unlock(netif_txq); 1973 1974 return nxmit; 1975 } 1976 1977 static const struct net_device_ops am65_cpsw_nuss_netdev_ops = { 1978 .ndo_open = am65_cpsw_nuss_ndo_slave_open, 1979 .ndo_stop = am65_cpsw_nuss_ndo_slave_stop, 1980 .ndo_start_xmit = am65_cpsw_nuss_ndo_slave_xmit, 1981 .ndo_set_rx_mode = am65_cpsw_nuss_ndo_slave_set_rx_mode, 1982 .ndo_get_stats64 = am65_cpsw_nuss_ndo_get_stats, 1983 .ndo_validate_addr = eth_validate_addr, 1984 .ndo_set_mac_address = am65_cpsw_nuss_ndo_slave_set_mac_address, 1985 .ndo_tx_timeout = am65_cpsw_nuss_ndo_host_tx_timeout, 1986 .ndo_vlan_rx_add_vid = am65_cpsw_nuss_ndo_slave_add_vid, 1987 .ndo_vlan_rx_kill_vid = am65_cpsw_nuss_ndo_slave_kill_vid, 1988 .ndo_eth_ioctl = am65_cpsw_nuss_ndo_slave_ioctl, 1989 .ndo_setup_tc = am65_cpsw_qos_ndo_setup_tc, 1990 .ndo_set_tx_maxrate = am65_cpsw_qos_ndo_tx_p0_set_maxrate, 1991 .ndo_bpf = am65_cpsw_ndo_bpf, 1992 .ndo_xdp_xmit = am65_cpsw_ndo_xdp_xmit, 1993 }; 1994 1995 static void am65_cpsw_disable_phy(struct phy *phy) 1996 { 1997 phy_power_off(phy); 1998 phy_exit(phy); 1999 } 2000 2001 static int am65_cpsw_enable_phy(struct phy *phy) 2002 { 2003 int ret; 2004 2005 ret = phy_init(phy); 2006 if (ret < 0) 2007 return ret; 2008 2009 ret = phy_power_on(phy); 2010 if (ret < 0) { 2011 phy_exit(phy); 2012 return ret; 2013 } 2014 2015 return 0; 2016 } 2017 2018 static void am65_cpsw_disable_serdes_phy(struct am65_cpsw_common *common) 2019 { 2020 struct am65_cpsw_port *port; 2021 struct phy *phy; 2022 int i; 2023 2024 for (i = 0; i < common->port_num; i++) { 2025 port = &common->ports[i]; 2026 phy = port->slave.serdes_phy; 2027 if (phy) 2028 am65_cpsw_disable_phy(phy); 2029 } 2030 } 2031 2032 static int am65_cpsw_init_serdes_phy(struct device *dev, struct device_node *port_np, 2033 struct am65_cpsw_port *port) 2034 { 2035 const char *name = "serdes"; 2036 struct phy *phy; 2037 int ret; 2038 2039 phy = devm_of_phy_optional_get(dev, port_np, name); 2040 if (IS_ERR_OR_NULL(phy)) 2041 return PTR_ERR_OR_ZERO(phy); 2042 2043 /* Serdes PHY exists. Store it. */ 2044 port->slave.serdes_phy = phy; 2045 2046 ret = am65_cpsw_enable_phy(phy); 2047 if (ret < 0) 2048 goto err_phy; 2049 2050 return 0; 2051 2052 err_phy: 2053 devm_phy_put(dev, phy); 2054 return ret; 2055 } 2056 2057 static void am65_cpsw_nuss_mac_config(struct phylink_config *config, unsigned int mode, 2058 const struct phylink_link_state *state) 2059 { 2060 struct am65_cpsw_slave_data *slave = container_of(config, struct am65_cpsw_slave_data, 2061 phylink_config); 2062 struct am65_cpsw_port *port = container_of(slave, struct am65_cpsw_port, slave); 2063 struct am65_cpsw_common *common = port->common; 2064 2065 if (common->pdata.extra_modes & BIT(state->interface)) { 2066 if (state->interface == PHY_INTERFACE_MODE_SGMII) { 2067 writel(ADVERTISE_SGMII, 2068 port->sgmii_base + AM65_CPSW_SGMII_MR_ADV_ABILITY_REG); 2069 cpsw_sl_ctl_set(port->slave.mac_sl, CPSW_SL_CTL_EXT_EN); 2070 } else { 2071 cpsw_sl_ctl_clr(port->slave.mac_sl, CPSW_SL_CTL_EXT_EN); 2072 } 2073 2074 if (state->interface == PHY_INTERFACE_MODE_USXGMII) { 2075 cpsw_sl_ctl_set(port->slave.mac_sl, 2076 CPSW_SL_CTL_XGIG | CPSW_SL_CTL_XGMII_EN); 2077 } else { 2078 cpsw_sl_ctl_clr(port->slave.mac_sl, 2079 CPSW_SL_CTL_XGIG | CPSW_SL_CTL_XGMII_EN); 2080 } 2081 2082 writel(AM65_CPSW_SGMII_CONTROL_MR_AN_ENABLE, 2083 port->sgmii_base + AM65_CPSW_SGMII_CONTROL_REG); 2084 } 2085 } 2086 2087 static void am65_cpsw_nuss_mac_link_down(struct phylink_config *config, unsigned int mode, 2088 phy_interface_t interface) 2089 { 2090 struct am65_cpsw_slave_data *slave = container_of(config, struct am65_cpsw_slave_data, 2091 phylink_config); 2092 struct am65_cpsw_port *port = container_of(slave, struct am65_cpsw_port, slave); 2093 struct am65_cpsw_common *common = port->common; 2094 struct net_device *ndev = port->ndev; 2095 u32 mac_control; 2096 int tmo; 2097 2098 /* disable forwarding */ 2099 cpsw_ale_control_set(common->ale, port->port_id, ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 2100 2101 cpsw_sl_ctl_set(port->slave.mac_sl, CPSW_SL_CTL_CMD_IDLE); 2102 2103 tmo = cpsw_sl_wait_for_idle(port->slave.mac_sl, 100); 2104 dev_dbg(common->dev, "down msc_sl %08x tmo %d\n", 2105 cpsw_sl_reg_read(port->slave.mac_sl, CPSW_SL_MACSTATUS), tmo); 2106 2107 /* All the bits that am65_cpsw_nuss_mac_link_up() can possibly set */ 2108 mac_control = CPSW_SL_CTL_GMII_EN | CPSW_SL_CTL_GIG | CPSW_SL_CTL_IFCTL_A | 2109 CPSW_SL_CTL_FULLDUPLEX | CPSW_SL_CTL_RX_FLOW_EN | CPSW_SL_CTL_TX_FLOW_EN; 2110 /* If interface mode is RGMII, CPSW_SL_CTL_EXT_EN might have been set for 10 Mbps */ 2111 if (phy_interface_mode_is_rgmii(interface)) 2112 mac_control |= CPSW_SL_CTL_EXT_EN; 2113 /* Only clear those bits that can be set by am65_cpsw_nuss_mac_link_up() */ 2114 cpsw_sl_ctl_clr(port->slave.mac_sl, mac_control); 2115 2116 am65_cpsw_qos_link_down(ndev); 2117 netif_tx_stop_all_queues(ndev); 2118 } 2119 2120 static void am65_cpsw_nuss_mac_link_up(struct phylink_config *config, struct phy_device *phy, 2121 unsigned int mode, phy_interface_t interface, int speed, 2122 int duplex, bool tx_pause, bool rx_pause) 2123 { 2124 struct am65_cpsw_slave_data *slave = container_of(config, struct am65_cpsw_slave_data, 2125 phylink_config); 2126 struct am65_cpsw_port *port = container_of(slave, struct am65_cpsw_port, slave); 2127 struct am65_cpsw_common *common = port->common; 2128 u32 mac_control = CPSW_SL_CTL_GMII_EN; 2129 struct net_device *ndev = port->ndev; 2130 2131 /* Bring the port out of idle state */ 2132 cpsw_sl_ctl_clr(port->slave.mac_sl, CPSW_SL_CTL_CMD_IDLE); 2133 2134 if (speed == SPEED_1000) 2135 mac_control |= CPSW_SL_CTL_GIG; 2136 /* TODO: Verify whether in-band is necessary for 10 Mbps RGMII */ 2137 if (speed == SPEED_10 && phy_interface_mode_is_rgmii(interface)) 2138 /* Can be used with in band mode only */ 2139 mac_control |= CPSW_SL_CTL_EXT_EN; 2140 if (speed == SPEED_100 && interface == PHY_INTERFACE_MODE_RMII) 2141 mac_control |= CPSW_SL_CTL_IFCTL_A; 2142 if (duplex) 2143 mac_control |= CPSW_SL_CTL_FULLDUPLEX; 2144 2145 /* rx_pause/tx_pause */ 2146 if (rx_pause) 2147 mac_control |= CPSW_SL_CTL_TX_FLOW_EN; 2148 2149 if (tx_pause) 2150 mac_control |= CPSW_SL_CTL_RX_FLOW_EN; 2151 2152 cpsw_sl_ctl_set(port->slave.mac_sl, mac_control); 2153 2154 /* enable forwarding */ 2155 cpsw_ale_control_set(common->ale, port->port_id, ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 2156 2157 am65_cpsw_qos_link_up(ndev, speed); 2158 netif_tx_wake_all_queues(ndev); 2159 } 2160 2161 static const struct phylink_mac_ops am65_cpsw_phylink_mac_ops = { 2162 .mac_config = am65_cpsw_nuss_mac_config, 2163 .mac_link_down = am65_cpsw_nuss_mac_link_down, 2164 .mac_link_up = am65_cpsw_nuss_mac_link_up, 2165 }; 2166 2167 static void am65_cpsw_nuss_slave_disable_unused(struct am65_cpsw_port *port) 2168 { 2169 struct am65_cpsw_common *common = port->common; 2170 2171 if (!port->disabled) 2172 return; 2173 2174 cpsw_ale_control_set(common->ale, port->port_id, 2175 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 2176 2177 cpsw_sl_reset(port->slave.mac_sl, 100); 2178 cpsw_sl_ctl_reset(port->slave.mac_sl); 2179 } 2180 2181 static void am65_cpsw_nuss_free_tx_chns(void *data) 2182 { 2183 struct am65_cpsw_common *common = data; 2184 int i; 2185 2186 for (i = 0; i < common->tx_ch_num; i++) { 2187 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i]; 2188 2189 if (!IS_ERR_OR_NULL(tx_chn->desc_pool)) 2190 k3_cppi_desc_pool_destroy(tx_chn->desc_pool); 2191 2192 if (!IS_ERR_OR_NULL(tx_chn->tx_chn)) 2193 k3_udma_glue_release_tx_chn(tx_chn->tx_chn); 2194 2195 memset(tx_chn, 0, sizeof(*tx_chn)); 2196 } 2197 } 2198 2199 static void am65_cpsw_nuss_remove_tx_chns(struct am65_cpsw_common *common) 2200 { 2201 struct device *dev = common->dev; 2202 int i; 2203 2204 common->tx_ch_rate_msk = 0; 2205 for (i = 0; i < common->tx_ch_num; i++) { 2206 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i]; 2207 2208 if (tx_chn->irq > 0) 2209 devm_free_irq(dev, tx_chn->irq, tx_chn); 2210 2211 netif_napi_del(&tx_chn->napi_tx); 2212 } 2213 2214 am65_cpsw_nuss_free_tx_chns(common); 2215 } 2216 2217 static int am65_cpsw_nuss_ndev_add_tx_napi(struct am65_cpsw_common *common) 2218 { 2219 struct device *dev = common->dev; 2220 struct am65_cpsw_tx_chn *tx_chn; 2221 int i, ret = 0; 2222 2223 for (i = 0; i < common->tx_ch_num; i++) { 2224 tx_chn = &common->tx_chns[i]; 2225 2226 hrtimer_setup(&tx_chn->tx_hrtimer, &am65_cpsw_nuss_tx_timer_callback, 2227 CLOCK_MONOTONIC, HRTIMER_MODE_REL_PINNED); 2228 2229 netif_napi_add_tx(common->dma_ndev, &tx_chn->napi_tx, 2230 am65_cpsw_nuss_tx_poll); 2231 2232 ret = devm_request_irq(dev, tx_chn->irq, 2233 am65_cpsw_nuss_tx_irq, 2234 IRQF_TRIGGER_HIGH, 2235 tx_chn->tx_chn_name, tx_chn); 2236 if (ret) { 2237 dev_err(dev, "failure requesting tx%u irq %u, %d\n", 2238 tx_chn->id, tx_chn->irq, ret); 2239 goto err; 2240 } 2241 } 2242 2243 return 0; 2244 2245 err: 2246 netif_napi_del(&tx_chn->napi_tx); 2247 for (--i; i >= 0; i--) { 2248 tx_chn = &common->tx_chns[i]; 2249 devm_free_irq(dev, tx_chn->irq, tx_chn); 2250 netif_napi_del(&tx_chn->napi_tx); 2251 } 2252 2253 return ret; 2254 } 2255 2256 static int am65_cpsw_nuss_init_tx_chns(struct am65_cpsw_common *common) 2257 { 2258 u32 max_desc_num = ALIGN(AM65_CPSW_MAX_TX_DESC, MAX_SKB_FRAGS); 2259 struct k3_udma_glue_tx_channel_cfg tx_cfg = { 0 }; 2260 struct device *dev = common->dev; 2261 struct k3_ring_cfg ring_cfg = { 2262 .elm_size = K3_RINGACC_RING_ELSIZE_8, 2263 .mode = K3_RINGACC_RING_MODE_RING, 2264 .flags = 0 2265 }; 2266 u32 hdesc_size, hdesc_size_out; 2267 int i, ret = 0; 2268 2269 hdesc_size = cppi5_hdesc_calc_size(true, AM65_CPSW_NAV_PS_DATA_SIZE, 2270 AM65_CPSW_NAV_SW_DATA_SIZE); 2271 2272 tx_cfg.swdata_size = AM65_CPSW_NAV_SW_DATA_SIZE; 2273 tx_cfg.tx_cfg = ring_cfg; 2274 tx_cfg.txcq_cfg = ring_cfg; 2275 tx_cfg.tx_cfg.size = max_desc_num; 2276 tx_cfg.txcq_cfg.size = max_desc_num; 2277 2278 for (i = 0; i < common->tx_ch_num; i++) { 2279 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i]; 2280 2281 snprintf(tx_chn->tx_chn_name, 2282 sizeof(tx_chn->tx_chn_name), "tx%d", i); 2283 2284 spin_lock_init(&tx_chn->lock); 2285 tx_chn->common = common; 2286 tx_chn->id = i; 2287 tx_chn->descs_num = max_desc_num; 2288 2289 tx_chn->tx_chn = 2290 k3_udma_glue_request_tx_chn(dev, 2291 tx_chn->tx_chn_name, 2292 &tx_cfg); 2293 if (IS_ERR(tx_chn->tx_chn)) { 2294 ret = dev_err_probe(dev, PTR_ERR(tx_chn->tx_chn), 2295 "Failed to request tx dma channel\n"); 2296 goto err; 2297 } 2298 tx_chn->dma_dev = k3_udma_glue_tx_get_dma_device(tx_chn->tx_chn); 2299 2300 tx_chn->desc_pool = k3_cppi_desc_pool_create_name(tx_chn->dma_dev, 2301 tx_chn->descs_num, 2302 hdesc_size, 2303 tx_chn->tx_chn_name); 2304 if (IS_ERR(tx_chn->desc_pool)) { 2305 ret = PTR_ERR(tx_chn->desc_pool); 2306 dev_err(dev, "Failed to create poll %d\n", ret); 2307 goto err; 2308 } 2309 2310 hdesc_size_out = k3_cppi_desc_pool_desc_size(tx_chn->desc_pool); 2311 tx_chn->dsize_log2 = __fls(hdesc_size_out); 2312 WARN_ON(hdesc_size_out != (1 << tx_chn->dsize_log2)); 2313 2314 tx_chn->irq = k3_udma_glue_tx_get_irq(tx_chn->tx_chn); 2315 if (tx_chn->irq < 0) { 2316 dev_err(dev, "Failed to get tx dma irq %d\n", 2317 tx_chn->irq); 2318 ret = tx_chn->irq; 2319 goto err; 2320 } 2321 2322 snprintf(tx_chn->tx_chn_name, 2323 sizeof(tx_chn->tx_chn_name), "%s-tx%d", 2324 dev_name(dev), tx_chn->id); 2325 } 2326 2327 ret = am65_cpsw_nuss_ndev_add_tx_napi(common); 2328 if (ret) { 2329 dev_err(dev, "Failed to add tx NAPI %d\n", ret); 2330 goto err; 2331 } 2332 2333 return 0; 2334 2335 err: 2336 am65_cpsw_nuss_free_tx_chns(common); 2337 2338 return ret; 2339 } 2340 2341 static void am65_cpsw_nuss_free_rx_chns(void *data) 2342 { 2343 struct am65_cpsw_common *common = data; 2344 struct am65_cpsw_rx_chn *rx_chn; 2345 2346 rx_chn = &common->rx_chns; 2347 2348 if (!IS_ERR_OR_NULL(rx_chn->desc_pool)) 2349 k3_cppi_desc_pool_destroy(rx_chn->desc_pool); 2350 2351 if (!IS_ERR_OR_NULL(rx_chn->rx_chn)) 2352 k3_udma_glue_release_rx_chn(rx_chn->rx_chn); 2353 } 2354 2355 static void am65_cpsw_nuss_remove_rx_chns(struct am65_cpsw_common *common) 2356 { 2357 struct device *dev = common->dev; 2358 struct am65_cpsw_rx_chn *rx_chn; 2359 struct am65_cpsw_rx_flow *flows; 2360 int i; 2361 2362 rx_chn = &common->rx_chns; 2363 flows = rx_chn->flows; 2364 2365 for (i = 0; i < common->rx_ch_num_flows; i++) { 2366 if (!(flows[i].irq < 0)) 2367 devm_free_irq(dev, flows[i].irq, &flows[i]); 2368 netif_napi_del(&flows[i].napi_rx); 2369 } 2370 2371 am65_cpsw_nuss_free_rx_chns(common); 2372 2373 common->rx_flow_id_base = -1; 2374 } 2375 2376 static int am65_cpsw_nuss_init_rx_chns(struct am65_cpsw_common *common) 2377 { 2378 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; 2379 struct k3_udma_glue_rx_channel_cfg rx_cfg = { 0 }; 2380 u32 max_desc_num = AM65_CPSW_MAX_RX_DESC; 2381 struct device *dev = common->dev; 2382 struct am65_cpsw_rx_flow *flow; 2383 u32 hdesc_size, hdesc_size_out; 2384 u32 fdqring_id; 2385 int i, ret = 0; 2386 2387 hdesc_size = cppi5_hdesc_calc_size(true, AM65_CPSW_NAV_PS_DATA_SIZE, 2388 AM65_CPSW_NAV_SW_DATA_SIZE); 2389 2390 rx_cfg.swdata_size = AM65_CPSW_NAV_SW_DATA_SIZE; 2391 rx_cfg.flow_id_num = common->rx_ch_num_flows; 2392 rx_cfg.flow_id_base = common->rx_flow_id_base; 2393 2394 /* init all flows */ 2395 rx_chn->dev = dev; 2396 rx_chn->descs_num = max_desc_num * rx_cfg.flow_id_num; 2397 2398 for (i = 0; i < common->rx_ch_num_flows; i++) { 2399 flow = &rx_chn->flows[i]; 2400 flow->page_pool = NULL; 2401 } 2402 2403 rx_chn->rx_chn = k3_udma_glue_request_rx_chn(dev, "rx", &rx_cfg); 2404 if (IS_ERR(rx_chn->rx_chn)) { 2405 ret = dev_err_probe(dev, PTR_ERR(rx_chn->rx_chn), 2406 "Failed to request rx dma channel\n"); 2407 goto err; 2408 } 2409 rx_chn->dma_dev = k3_udma_glue_rx_get_dma_device(rx_chn->rx_chn); 2410 2411 rx_chn->desc_pool = k3_cppi_desc_pool_create_name(rx_chn->dma_dev, 2412 rx_chn->descs_num, 2413 hdesc_size, "rx"); 2414 if (IS_ERR(rx_chn->desc_pool)) { 2415 ret = PTR_ERR(rx_chn->desc_pool); 2416 dev_err(dev, "Failed to create rx poll %d\n", ret); 2417 goto err; 2418 } 2419 2420 hdesc_size_out = k3_cppi_desc_pool_desc_size(rx_chn->desc_pool); 2421 rx_chn->dsize_log2 = __fls(hdesc_size_out); 2422 WARN_ON(hdesc_size_out != (1 << rx_chn->dsize_log2)); 2423 2424 common->rx_flow_id_base = 2425 k3_udma_glue_rx_get_flow_id_base(rx_chn->rx_chn); 2426 dev_info(dev, "set new flow-id-base %u\n", common->rx_flow_id_base); 2427 2428 fdqring_id = K3_RINGACC_RING_ID_ANY; 2429 for (i = 0; i < rx_cfg.flow_id_num; i++) { 2430 struct k3_ring_cfg rxring_cfg = { 2431 .elm_size = K3_RINGACC_RING_ELSIZE_8, 2432 .mode = K3_RINGACC_RING_MODE_RING, 2433 .flags = 0, 2434 }; 2435 struct k3_ring_cfg fdqring_cfg = { 2436 .elm_size = K3_RINGACC_RING_ELSIZE_8, 2437 .flags = K3_RINGACC_RING_SHARED, 2438 }; 2439 struct k3_udma_glue_rx_flow_cfg rx_flow_cfg = { 2440 .rx_cfg = rxring_cfg, 2441 .rxfdq_cfg = fdqring_cfg, 2442 .ring_rxq_id = K3_RINGACC_RING_ID_ANY, 2443 .src_tag_lo_sel = 2444 K3_UDMA_GLUE_SRC_TAG_LO_USE_REMOTE_SRC_TAG, 2445 }; 2446 2447 flow = &rx_chn->flows[i]; 2448 flow->id = i; 2449 flow->common = common; 2450 flow->irq = -EINVAL; 2451 2452 rx_flow_cfg.ring_rxfdq0_id = fdqring_id; 2453 rx_flow_cfg.rx_cfg.size = max_desc_num; 2454 /* share same FDQ for all flows */ 2455 rx_flow_cfg.rxfdq_cfg.size = max_desc_num * rx_cfg.flow_id_num; 2456 rx_flow_cfg.rxfdq_cfg.mode = common->pdata.fdqring_mode; 2457 2458 ret = k3_udma_glue_rx_flow_init(rx_chn->rx_chn, 2459 i, &rx_flow_cfg); 2460 if (ret) { 2461 dev_err(dev, "Failed to init rx flow%d %d\n", i, ret); 2462 goto err_flow; 2463 } 2464 if (!i) 2465 fdqring_id = 2466 k3_udma_glue_rx_flow_get_fdq_id(rx_chn->rx_chn, 2467 i); 2468 2469 flow->irq = k3_udma_glue_rx_get_irq(rx_chn->rx_chn, i); 2470 if (flow->irq <= 0) { 2471 dev_err(dev, "Failed to get rx dma irq %d\n", 2472 flow->irq); 2473 ret = flow->irq; 2474 goto err_flow; 2475 } 2476 2477 snprintf(flow->name, 2478 sizeof(flow->name), "%s-rx%d", 2479 dev_name(dev), i); 2480 hrtimer_setup(&flow->rx_hrtimer, &am65_cpsw_nuss_rx_timer_callback, CLOCK_MONOTONIC, 2481 HRTIMER_MODE_REL_PINNED); 2482 2483 netif_napi_add(common->dma_ndev, &flow->napi_rx, 2484 am65_cpsw_nuss_rx_poll); 2485 2486 ret = devm_request_irq(dev, flow->irq, 2487 am65_cpsw_nuss_rx_irq, 2488 IRQF_TRIGGER_HIGH, 2489 flow->name, flow); 2490 if (ret) { 2491 dev_err(dev, "failure requesting rx %d irq %u, %d\n", 2492 i, flow->irq, ret); 2493 flow->irq = -EINVAL; 2494 goto err_request_irq; 2495 } 2496 } 2497 2498 /* setup classifier to route priorities to flows */ 2499 cpsw_ale_classifier_setup_default(common->ale, common->rx_ch_num_flows); 2500 2501 return 0; 2502 2503 err_request_irq: 2504 netif_napi_del(&flow->napi_rx); 2505 2506 err_flow: 2507 for (--i; i >= 0; i--) { 2508 flow = &rx_chn->flows[i]; 2509 devm_free_irq(dev, flow->irq, flow); 2510 netif_napi_del(&flow->napi_rx); 2511 } 2512 2513 err: 2514 am65_cpsw_nuss_free_rx_chns(common); 2515 2516 return ret; 2517 } 2518 2519 static int am65_cpsw_nuss_init_host_p(struct am65_cpsw_common *common) 2520 { 2521 struct am65_cpsw_host *host_p = am65_common_get_host(common); 2522 2523 host_p->common = common; 2524 host_p->port_base = common->cpsw_base + AM65_CPSW_NU_PORTS_BASE; 2525 host_p->stat_base = common->cpsw_base + AM65_CPSW_NU_STATS_BASE; 2526 2527 return 0; 2528 } 2529 2530 static int am65_cpsw_am654_get_efuse_macid(struct device_node *of_node, 2531 int slave, u8 *mac_addr) 2532 { 2533 u32 mac_lo, mac_hi, offset; 2534 struct regmap *syscon; 2535 2536 syscon = syscon_regmap_lookup_by_phandle_args(of_node, "ti,syscon-efuse", 2537 1, &offset); 2538 if (IS_ERR(syscon)) { 2539 if (PTR_ERR(syscon) == -ENODEV) 2540 return 0; 2541 return PTR_ERR(syscon); 2542 } 2543 2544 regmap_read(syscon, offset, &mac_lo); 2545 regmap_read(syscon, offset + 4, &mac_hi); 2546 2547 mac_addr[0] = (mac_hi >> 8) & 0xff; 2548 mac_addr[1] = mac_hi & 0xff; 2549 mac_addr[2] = (mac_lo >> 24) & 0xff; 2550 mac_addr[3] = (mac_lo >> 16) & 0xff; 2551 mac_addr[4] = (mac_lo >> 8) & 0xff; 2552 mac_addr[5] = mac_lo & 0xff; 2553 2554 return 0; 2555 } 2556 2557 static int am65_cpsw_init_cpts(struct am65_cpsw_common *common) 2558 { 2559 struct device *dev = common->dev; 2560 struct device_node *node; 2561 struct am65_cpts *cpts; 2562 void __iomem *reg_base; 2563 2564 if (!IS_ENABLED(CONFIG_TI_K3_AM65_CPTS)) 2565 return 0; 2566 2567 node = of_get_child_by_name(dev->of_node, "cpts"); 2568 if (!node) { 2569 dev_err(dev, "%s cpts not found\n", __func__); 2570 return -ENOENT; 2571 } 2572 2573 reg_base = common->cpsw_base + AM65_CPSW_NU_CPTS_BASE; 2574 cpts = am65_cpts_create(dev, reg_base, node); 2575 if (IS_ERR(cpts)) { 2576 int ret = PTR_ERR(cpts); 2577 2578 of_node_put(node); 2579 dev_err(dev, "cpts create err %d\n", ret); 2580 return ret; 2581 } 2582 common->cpts = cpts; 2583 /* Forbid PM runtime if CPTS is running. 2584 * K3 CPSWxG modules may completely lose context during ON->OFF 2585 * transitions depending on integration. 2586 * AM65x/J721E MCU CPSW2G: false 2587 * J721E MAIN_CPSW9G: true 2588 */ 2589 pm_runtime_forbid(dev); 2590 2591 return 0; 2592 } 2593 2594 static int am65_cpsw_nuss_init_slave_ports(struct am65_cpsw_common *common) 2595 { 2596 struct device_node *node, *port_np; 2597 struct device *dev = common->dev; 2598 int ret; 2599 2600 node = of_get_child_by_name(dev->of_node, "ethernet-ports"); 2601 if (!node) 2602 return -ENOENT; 2603 2604 for_each_child_of_node(node, port_np) { 2605 struct am65_cpsw_port *port; 2606 u32 port_id; 2607 2608 /* it is not a slave port node, continue */ 2609 if (strcmp(port_np->name, "port")) 2610 continue; 2611 2612 ret = of_property_read_u32(port_np, "reg", &port_id); 2613 if (ret < 0) { 2614 dev_err(dev, "%pOF error reading port_id %d\n", 2615 port_np, ret); 2616 goto of_node_put; 2617 } 2618 2619 if (!port_id || port_id > common->port_num) { 2620 dev_err(dev, "%pOF has invalid port_id %u %s\n", 2621 port_np, port_id, port_np->name); 2622 ret = -EINVAL; 2623 goto of_node_put; 2624 } 2625 2626 port = am65_common_get_port(common, port_id); 2627 port->port_id = port_id; 2628 port->common = common; 2629 port->port_base = common->cpsw_base + AM65_CPSW_NU_PORTS_BASE + 2630 AM65_CPSW_NU_PORTS_OFFSET * (port_id); 2631 if (common->pdata.extra_modes) 2632 port->sgmii_base = common->ss_base + AM65_CPSW_SGMII_BASE * (port_id); 2633 port->stat_base = common->cpsw_base + AM65_CPSW_NU_STATS_BASE + 2634 (AM65_CPSW_NU_STATS_PORT_OFFSET * port_id); 2635 port->name = of_get_property(port_np, "label", NULL); 2636 port->fetch_ram_base = 2637 common->cpsw_base + AM65_CPSW_NU_FRAM_BASE + 2638 (AM65_CPSW_NU_FRAM_PORT_OFFSET * (port_id - 1)); 2639 2640 port->slave.mac_sl = cpsw_sl_get("am65", dev, port->port_base); 2641 if (IS_ERR(port->slave.mac_sl)) { 2642 ret = PTR_ERR(port->slave.mac_sl); 2643 goto of_node_put; 2644 } 2645 2646 port->disabled = !of_device_is_available(port_np); 2647 if (port->disabled) { 2648 common->disabled_ports_mask |= BIT(port->port_id); 2649 continue; 2650 } 2651 2652 port->slave.ifphy = devm_of_phy_get(dev, port_np, NULL); 2653 if (IS_ERR(port->slave.ifphy)) { 2654 ret = PTR_ERR(port->slave.ifphy); 2655 dev_err(dev, "%pOF error retrieving port phy: %d\n", 2656 port_np, ret); 2657 goto of_node_put; 2658 } 2659 2660 /* Initialize the Serdes PHY for the port */ 2661 ret = am65_cpsw_init_serdes_phy(dev, port_np, port); 2662 if (ret) 2663 goto of_node_put; 2664 2665 port->slave.mac_only = 2666 of_property_read_bool(port_np, "ti,mac-only"); 2667 2668 /* get phy/link info */ 2669 port->slave.port_np = of_node_get(port_np); 2670 ret = of_get_phy_mode(port_np, &port->slave.phy_if); 2671 if (ret) { 2672 dev_err(dev, "%pOF read phy-mode err %d\n", 2673 port_np, ret); 2674 goto of_node_put; 2675 } 2676 2677 ret = phy_set_mode_ext(port->slave.ifphy, PHY_MODE_ETHERNET, port->slave.phy_if); 2678 if (ret) 2679 goto of_node_put; 2680 2681 ret = of_get_mac_address(port_np, port->slave.mac_addr); 2682 if (ret == -EPROBE_DEFER) { 2683 goto of_node_put; 2684 } else if (ret) { 2685 am65_cpsw_am654_get_efuse_macid(port_np, 2686 port->port_id, 2687 port->slave.mac_addr); 2688 if (!is_valid_ether_addr(port->slave.mac_addr)) { 2689 eth_random_addr(port->slave.mac_addr); 2690 dev_info(dev, "Use random MAC address\n"); 2691 } 2692 } 2693 2694 /* Reset all Queue priorities to 0 */ 2695 writel(0, port->port_base + AM65_CPSW_PN_REG_TX_PRI_MAP); 2696 } 2697 of_node_put(node); 2698 2699 /* is there at least one ext.port */ 2700 if (!(~common->disabled_ports_mask & GENMASK(common->port_num, 1))) { 2701 dev_err(dev, "No Ext. port are available\n"); 2702 return -ENODEV; 2703 } 2704 2705 return 0; 2706 2707 of_node_put: 2708 of_node_put(port_np); 2709 of_node_put(node); 2710 return ret; 2711 } 2712 2713 static void am65_cpsw_nuss_phylink_cleanup(struct am65_cpsw_common *common) 2714 { 2715 struct am65_cpsw_port *port; 2716 int i; 2717 2718 for (i = 0; i < common->port_num; i++) { 2719 port = &common->ports[i]; 2720 if (port->slave.phylink) 2721 phylink_destroy(port->slave.phylink); 2722 } 2723 } 2724 2725 static void am65_cpsw_remove_dt(struct am65_cpsw_common *common) 2726 { 2727 struct am65_cpsw_port *port; 2728 int i; 2729 2730 for (i = 0; i < common->port_num; i++) { 2731 port = &common->ports[i]; 2732 of_node_put(port->slave.port_np); 2733 } 2734 } 2735 2736 static int 2737 am65_cpsw_nuss_init_port_ndev(struct am65_cpsw_common *common, u32 port_idx) 2738 { 2739 struct am65_cpsw_ndev_priv *ndev_priv; 2740 struct device *dev = common->dev; 2741 struct am65_cpsw_port *port; 2742 struct phylink *phylink; 2743 2744 port = &common->ports[port_idx]; 2745 2746 if (port->disabled) 2747 return 0; 2748 2749 /* alloc netdev */ 2750 port->ndev = alloc_etherdev_mqs(sizeof(struct am65_cpsw_ndev_priv), 2751 AM65_CPSW_MAX_QUEUES, 2752 AM65_CPSW_MAX_QUEUES); 2753 if (!port->ndev) { 2754 dev_err(dev, "error allocating slave net_device %u\n", 2755 port->port_id); 2756 return -ENOMEM; 2757 } 2758 2759 ndev_priv = netdev_priv(port->ndev); 2760 ndev_priv->port = port; 2761 ndev_priv->msg_enable = AM65_CPSW_DEBUG; 2762 mutex_init(&ndev_priv->mm_lock); 2763 port->qos.link_speed = SPEED_UNKNOWN; 2764 SET_NETDEV_DEV(port->ndev, dev); 2765 device_set_node(&port->ndev->dev, of_fwnode_handle(port->slave.port_np)); 2766 2767 eth_hw_addr_set(port->ndev, port->slave.mac_addr); 2768 2769 port->ndev->min_mtu = AM65_CPSW_MIN_PACKET_SIZE; 2770 port->ndev->max_mtu = AM65_CPSW_MAX_PACKET_SIZE - 2771 (VLAN_ETH_HLEN + ETH_FCS_LEN); 2772 port->ndev->hw_features = NETIF_F_SG | 2773 NETIF_F_RXCSUM | 2774 NETIF_F_HW_CSUM | 2775 NETIF_F_HW_TC; 2776 port->ndev->features = port->ndev->hw_features | 2777 NETIF_F_HW_VLAN_CTAG_FILTER; 2778 port->ndev->xdp_features = NETDEV_XDP_ACT_BASIC | 2779 NETDEV_XDP_ACT_REDIRECT | 2780 NETDEV_XDP_ACT_NDO_XMIT; 2781 port->ndev->vlan_features |= NETIF_F_SG; 2782 port->ndev->netdev_ops = &am65_cpsw_nuss_netdev_ops; 2783 port->ndev->ethtool_ops = &am65_cpsw_ethtool_ops_slave; 2784 2785 /* Configuring Phylink */ 2786 port->slave.phylink_config.dev = &port->ndev->dev; 2787 port->slave.phylink_config.type = PHYLINK_NETDEV; 2788 port->slave.phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 2789 MAC_1000FD | MAC_5000FD; 2790 port->slave.phylink_config.mac_managed_pm = true; /* MAC does PM */ 2791 2792 switch (port->slave.phy_if) { 2793 case PHY_INTERFACE_MODE_RGMII: 2794 case PHY_INTERFACE_MODE_RGMII_ID: 2795 case PHY_INTERFACE_MODE_RGMII_RXID: 2796 case PHY_INTERFACE_MODE_RGMII_TXID: 2797 phy_interface_set_rgmii(port->slave.phylink_config.supported_interfaces); 2798 break; 2799 2800 case PHY_INTERFACE_MODE_RMII: 2801 __set_bit(PHY_INTERFACE_MODE_RMII, 2802 port->slave.phylink_config.supported_interfaces); 2803 break; 2804 2805 case PHY_INTERFACE_MODE_QSGMII: 2806 case PHY_INTERFACE_MODE_SGMII: 2807 case PHY_INTERFACE_MODE_USXGMII: 2808 if (common->pdata.extra_modes & BIT(port->slave.phy_if)) { 2809 __set_bit(port->slave.phy_if, 2810 port->slave.phylink_config.supported_interfaces); 2811 } else { 2812 dev_err(dev, "selected phy-mode is not supported\n"); 2813 return -EOPNOTSUPP; 2814 } 2815 break; 2816 2817 default: 2818 dev_err(dev, "selected phy-mode is not supported\n"); 2819 return -EOPNOTSUPP; 2820 } 2821 2822 phylink = phylink_create(&port->slave.phylink_config, 2823 of_fwnode_handle(port->slave.port_np), 2824 port->slave.phy_if, 2825 &am65_cpsw_phylink_mac_ops); 2826 if (IS_ERR(phylink)) 2827 return PTR_ERR(phylink); 2828 2829 port->slave.phylink = phylink; 2830 2831 /* Disable TX checksum offload by default due to HW bug */ 2832 if (common->pdata.quirks & AM65_CPSW_QUIRK_I2027_NO_TX_CSUM) 2833 port->ndev->features &= ~NETIF_F_HW_CSUM; 2834 2835 port->ndev->pcpu_stat_type = NETDEV_PCPU_STAT_TSTATS; 2836 port->xdp_prog = NULL; 2837 2838 if (!common->dma_ndev) 2839 common->dma_ndev = port->ndev; 2840 2841 return 0; 2842 } 2843 2844 static int am65_cpsw_nuss_init_ndevs(struct am65_cpsw_common *common) 2845 { 2846 int ret; 2847 int i; 2848 2849 for (i = 0; i < common->port_num; i++) { 2850 ret = am65_cpsw_nuss_init_port_ndev(common, i); 2851 if (ret) 2852 return ret; 2853 } 2854 2855 return ret; 2856 } 2857 2858 static void am65_cpsw_nuss_cleanup_ndev(struct am65_cpsw_common *common) 2859 { 2860 struct am65_cpsw_port *port; 2861 int i; 2862 2863 for (i = 0; i < common->port_num; i++) { 2864 port = &common->ports[i]; 2865 if (!port->ndev) 2866 continue; 2867 if (port->ndev->reg_state == NETREG_REGISTERED) 2868 unregister_netdev(port->ndev); 2869 free_netdev(port->ndev); 2870 port->ndev = NULL; 2871 } 2872 } 2873 2874 static void am65_cpsw_port_offload_fwd_mark_update(struct am65_cpsw_common *common) 2875 { 2876 int set_val = 0; 2877 int i; 2878 2879 if (common->br_members == (GENMASK(common->port_num, 1) & ~common->disabled_ports_mask)) 2880 set_val = 1; 2881 2882 dev_dbg(common->dev, "set offload_fwd_mark %d\n", set_val); 2883 2884 for (i = 1; i <= common->port_num; i++) { 2885 struct am65_cpsw_port *port = am65_common_get_port(common, i); 2886 struct am65_cpsw_ndev_priv *priv; 2887 2888 if (!port->ndev) 2889 continue; 2890 2891 priv = am65_ndev_to_priv(port->ndev); 2892 priv->offload_fwd_mark = set_val; 2893 } 2894 } 2895 2896 bool am65_cpsw_port_dev_check(const struct net_device *ndev) 2897 { 2898 if (ndev->netdev_ops == &am65_cpsw_nuss_netdev_ops) { 2899 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 2900 2901 return !common->is_emac_mode; 2902 } 2903 2904 return false; 2905 } 2906 2907 static int am65_cpsw_netdevice_port_link(struct net_device *ndev, 2908 struct net_device *br_ndev, 2909 struct netlink_ext_ack *extack) 2910 { 2911 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 2912 struct am65_cpsw_ndev_priv *priv = am65_ndev_to_priv(ndev); 2913 int err; 2914 2915 if (!common->br_members) { 2916 common->hw_bridge_dev = br_ndev; 2917 } else { 2918 /* This is adding the port to a second bridge, this is 2919 * unsupported 2920 */ 2921 if (common->hw_bridge_dev != br_ndev) 2922 return -EOPNOTSUPP; 2923 } 2924 2925 err = switchdev_bridge_port_offload(ndev, ndev, NULL, NULL, NULL, 2926 false, extack); 2927 if (err) 2928 return err; 2929 2930 common->br_members |= BIT(priv->port->port_id); 2931 2932 am65_cpsw_port_offload_fwd_mark_update(common); 2933 2934 return NOTIFY_DONE; 2935 } 2936 2937 static void am65_cpsw_netdevice_port_unlink(struct net_device *ndev) 2938 { 2939 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 2940 struct am65_cpsw_ndev_priv *priv = am65_ndev_to_priv(ndev); 2941 2942 switchdev_bridge_port_unoffload(ndev, NULL, NULL, NULL); 2943 2944 common->br_members &= ~BIT(priv->port->port_id); 2945 2946 am65_cpsw_port_offload_fwd_mark_update(common); 2947 2948 if (!common->br_members) 2949 common->hw_bridge_dev = NULL; 2950 } 2951 2952 /* netdev notifier */ 2953 static int am65_cpsw_netdevice_event(struct notifier_block *unused, 2954 unsigned long event, void *ptr) 2955 { 2956 struct netlink_ext_ack *extack = netdev_notifier_info_to_extack(ptr); 2957 struct net_device *ndev = netdev_notifier_info_to_dev(ptr); 2958 struct netdev_notifier_changeupper_info *info; 2959 int ret = NOTIFY_DONE; 2960 2961 if (!am65_cpsw_port_dev_check(ndev)) 2962 return NOTIFY_DONE; 2963 2964 switch (event) { 2965 case NETDEV_CHANGEUPPER: 2966 info = ptr; 2967 2968 if (netif_is_bridge_master(info->upper_dev)) { 2969 if (info->linking) 2970 ret = am65_cpsw_netdevice_port_link(ndev, 2971 info->upper_dev, 2972 extack); 2973 else 2974 am65_cpsw_netdevice_port_unlink(ndev); 2975 } 2976 break; 2977 default: 2978 return NOTIFY_DONE; 2979 } 2980 2981 return notifier_from_errno(ret); 2982 } 2983 2984 static int am65_cpsw_register_notifiers(struct am65_cpsw_common *cpsw) 2985 { 2986 int ret = 0; 2987 2988 if (AM65_CPSW_IS_CPSW2G(cpsw) || 2989 !IS_REACHABLE(CONFIG_TI_K3_AM65_CPSW_SWITCHDEV)) 2990 return 0; 2991 2992 cpsw->am65_cpsw_netdevice_nb.notifier_call = &am65_cpsw_netdevice_event; 2993 ret = register_netdevice_notifier(&cpsw->am65_cpsw_netdevice_nb); 2994 if (ret) { 2995 dev_err(cpsw->dev, "can't register netdevice notifier\n"); 2996 return ret; 2997 } 2998 2999 ret = am65_cpsw_switchdev_register_notifiers(cpsw); 3000 if (ret) 3001 unregister_netdevice_notifier(&cpsw->am65_cpsw_netdevice_nb); 3002 3003 return ret; 3004 } 3005 3006 static void am65_cpsw_unregister_notifiers(struct am65_cpsw_common *cpsw) 3007 { 3008 if (AM65_CPSW_IS_CPSW2G(cpsw) || 3009 !IS_REACHABLE(CONFIG_TI_K3_AM65_CPSW_SWITCHDEV)) 3010 return; 3011 3012 am65_cpsw_switchdev_unregister_notifiers(cpsw); 3013 unregister_netdevice_notifier(&cpsw->am65_cpsw_netdevice_nb); 3014 } 3015 3016 static const struct devlink_ops am65_cpsw_devlink_ops = {}; 3017 3018 static void am65_cpsw_init_stp_ale_entry(struct am65_cpsw_common *cpsw) 3019 { 3020 cpsw_ale_add_mcast(cpsw->ale, eth_stp_addr, ALE_PORT_HOST, ALE_SUPER, 0, 3021 ALE_MCAST_BLOCK_LEARN_FWD); 3022 } 3023 3024 static void am65_cpsw_init_host_port_switch(struct am65_cpsw_common *common) 3025 { 3026 struct am65_cpsw_host *host = am65_common_get_host(common); 3027 3028 writel(common->default_vlan, host->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 3029 3030 am65_cpsw_init_stp_ale_entry(common); 3031 3032 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_P0_UNI_FLOOD, 1); 3033 dev_dbg(common->dev, "Set P0_UNI_FLOOD\n"); 3034 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_PORT_NOLEARN, 0); 3035 } 3036 3037 static void am65_cpsw_init_host_port_emac(struct am65_cpsw_common *common) 3038 { 3039 struct am65_cpsw_host *host = am65_common_get_host(common); 3040 3041 writel(0, host->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 3042 3043 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_P0_UNI_FLOOD, 0); 3044 dev_dbg(common->dev, "unset P0_UNI_FLOOD\n"); 3045 3046 /* learning make no sense in multi-mac mode */ 3047 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_PORT_NOLEARN, 1); 3048 } 3049 3050 static int am65_cpsw_dl_switch_mode_get(struct devlink *dl, u32 id, 3051 struct devlink_param_gset_ctx *ctx) 3052 { 3053 struct am65_cpsw_devlink *dl_priv = devlink_priv(dl); 3054 struct am65_cpsw_common *common = dl_priv->common; 3055 3056 dev_dbg(common->dev, "%s id:%u\n", __func__, id); 3057 3058 if (id != AM65_CPSW_DL_PARAM_SWITCH_MODE) 3059 return -EOPNOTSUPP; 3060 3061 ctx->val.vbool = !common->is_emac_mode; 3062 3063 return 0; 3064 } 3065 3066 static void am65_cpsw_init_port_emac_ale(struct am65_cpsw_port *port) 3067 { 3068 struct am65_cpsw_slave_data *slave = &port->slave; 3069 struct am65_cpsw_common *common = port->common; 3070 u32 port_mask; 3071 3072 writel(slave->port_vlan, port->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 3073 3074 if (slave->mac_only) 3075 /* enable mac-only mode on port */ 3076 cpsw_ale_control_set(common->ale, port->port_id, 3077 ALE_PORT_MACONLY, 1); 3078 3079 cpsw_ale_control_set(common->ale, port->port_id, ALE_PORT_NOLEARN, 1); 3080 3081 port_mask = BIT(port->port_id) | ALE_PORT_HOST; 3082 3083 cpsw_ale_add_ucast(common->ale, port->ndev->dev_addr, 3084 HOST_PORT_NUM, ALE_SECURE, slave->port_vlan); 3085 cpsw_ale_add_mcast(common->ale, port->ndev->broadcast, 3086 port_mask, ALE_VLAN, slave->port_vlan, ALE_MCAST_FWD_2); 3087 } 3088 3089 static void am65_cpsw_init_port_switch_ale(struct am65_cpsw_port *port) 3090 { 3091 struct am65_cpsw_slave_data *slave = &port->slave; 3092 struct am65_cpsw_common *cpsw = port->common; 3093 u32 port_mask; 3094 3095 cpsw_ale_control_set(cpsw->ale, port->port_id, 3096 ALE_PORT_NOLEARN, 0); 3097 3098 cpsw_ale_add_ucast(cpsw->ale, port->ndev->dev_addr, 3099 HOST_PORT_NUM, ALE_SECURE | ALE_BLOCKED | ALE_VLAN, 3100 slave->port_vlan); 3101 3102 port_mask = BIT(port->port_id) | ALE_PORT_HOST; 3103 3104 cpsw_ale_add_mcast(cpsw->ale, port->ndev->broadcast, 3105 port_mask, ALE_VLAN, slave->port_vlan, 3106 ALE_MCAST_FWD_2); 3107 3108 writel(slave->port_vlan, port->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 3109 3110 cpsw_ale_control_set(cpsw->ale, port->port_id, 3111 ALE_PORT_MACONLY, 0); 3112 } 3113 3114 static int am65_cpsw_dl_switch_mode_set(struct devlink *dl, u32 id, 3115 struct devlink_param_gset_ctx *ctx, 3116 struct netlink_ext_ack *extack) 3117 { 3118 struct am65_cpsw_devlink *dl_priv = devlink_priv(dl); 3119 struct am65_cpsw_common *cpsw = dl_priv->common; 3120 bool switch_en = ctx->val.vbool; 3121 bool if_running = false; 3122 int i; 3123 3124 dev_dbg(cpsw->dev, "%s id:%u\n", __func__, id); 3125 3126 if (id != AM65_CPSW_DL_PARAM_SWITCH_MODE) 3127 return -EOPNOTSUPP; 3128 3129 if (switch_en == !cpsw->is_emac_mode) 3130 return 0; 3131 3132 if (!switch_en && cpsw->br_members) { 3133 dev_err(cpsw->dev, "Remove ports from bridge before disabling switch mode\n"); 3134 return -EINVAL; 3135 } 3136 3137 rtnl_lock(); 3138 3139 cpsw->is_emac_mode = !switch_en; 3140 3141 for (i = 0; i < cpsw->port_num; i++) { 3142 struct net_device *sl_ndev = cpsw->ports[i].ndev; 3143 3144 if (!sl_ndev || !netif_running(sl_ndev)) 3145 continue; 3146 3147 if_running = true; 3148 } 3149 3150 if (!if_running) { 3151 /* all ndevs are down */ 3152 for (i = 0; i < cpsw->port_num; i++) { 3153 struct net_device *sl_ndev = cpsw->ports[i].ndev; 3154 struct am65_cpsw_slave_data *slave; 3155 3156 if (!sl_ndev) 3157 continue; 3158 3159 slave = am65_ndev_to_slave(sl_ndev); 3160 if (switch_en) 3161 slave->port_vlan = cpsw->default_vlan; 3162 else 3163 slave->port_vlan = 0; 3164 } 3165 3166 goto exit; 3167 } 3168 3169 cpsw_ale_control_set(cpsw->ale, 0, ALE_BYPASS, 1); 3170 /* clean up ALE table */ 3171 cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM, ALE_CLEAR, 1); 3172 cpsw_ale_control_get(cpsw->ale, HOST_PORT_NUM, ALE_AGEOUT); 3173 3174 if (switch_en) { 3175 dev_info(cpsw->dev, "Enable switch mode\n"); 3176 3177 am65_cpsw_init_host_port_switch(cpsw); 3178 3179 for (i = 0; i < cpsw->port_num; i++) { 3180 struct net_device *sl_ndev = cpsw->ports[i].ndev; 3181 struct am65_cpsw_slave_data *slave; 3182 struct am65_cpsw_port *port; 3183 3184 if (!sl_ndev) 3185 continue; 3186 3187 port = am65_ndev_to_port(sl_ndev); 3188 slave = am65_ndev_to_slave(sl_ndev); 3189 slave->port_vlan = cpsw->default_vlan; 3190 3191 if (netif_running(sl_ndev)) 3192 am65_cpsw_init_port_switch_ale(port); 3193 } 3194 3195 } else { 3196 dev_info(cpsw->dev, "Disable switch mode\n"); 3197 3198 am65_cpsw_init_host_port_emac(cpsw); 3199 3200 for (i = 0; i < cpsw->port_num; i++) { 3201 struct net_device *sl_ndev = cpsw->ports[i].ndev; 3202 struct am65_cpsw_port *port; 3203 3204 if (!sl_ndev) 3205 continue; 3206 3207 port = am65_ndev_to_port(sl_ndev); 3208 port->slave.port_vlan = 0; 3209 if (netif_running(sl_ndev)) 3210 am65_cpsw_init_port_emac_ale(port); 3211 } 3212 } 3213 cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM, ALE_BYPASS, 0); 3214 exit: 3215 rtnl_unlock(); 3216 3217 return 0; 3218 } 3219 3220 static const struct devlink_param am65_cpsw_devlink_params[] = { 3221 DEVLINK_PARAM_DRIVER(AM65_CPSW_DL_PARAM_SWITCH_MODE, "switch_mode", 3222 DEVLINK_PARAM_TYPE_BOOL, 3223 BIT(DEVLINK_PARAM_CMODE_RUNTIME), 3224 am65_cpsw_dl_switch_mode_get, 3225 am65_cpsw_dl_switch_mode_set, NULL), 3226 }; 3227 3228 static int am65_cpsw_nuss_register_devlink(struct am65_cpsw_common *common) 3229 { 3230 struct devlink_port_attrs attrs = {}; 3231 struct am65_cpsw_devlink *dl_priv; 3232 struct device *dev = common->dev; 3233 struct devlink_port *dl_port; 3234 struct am65_cpsw_port *port; 3235 int ret = 0; 3236 int i; 3237 3238 common->devlink = 3239 devlink_alloc(&am65_cpsw_devlink_ops, sizeof(*dl_priv), dev); 3240 if (!common->devlink) 3241 return -ENOMEM; 3242 3243 dl_priv = devlink_priv(common->devlink); 3244 dl_priv->common = common; 3245 3246 /* Provide devlink hook to switch mode when multiple external ports 3247 * are present NUSS switchdev driver is enabled. 3248 */ 3249 if (!AM65_CPSW_IS_CPSW2G(common) && 3250 IS_ENABLED(CONFIG_TI_K3_AM65_CPSW_SWITCHDEV)) { 3251 ret = devlink_params_register(common->devlink, 3252 am65_cpsw_devlink_params, 3253 ARRAY_SIZE(am65_cpsw_devlink_params)); 3254 if (ret) { 3255 dev_err(dev, "devlink params reg fail ret:%d\n", ret); 3256 goto dl_unreg; 3257 } 3258 } 3259 3260 for (i = 1; i <= common->port_num; i++) { 3261 port = am65_common_get_port(common, i); 3262 dl_port = &port->devlink_port; 3263 3264 if (port->ndev) 3265 attrs.flavour = DEVLINK_PORT_FLAVOUR_PHYSICAL; 3266 else 3267 attrs.flavour = DEVLINK_PORT_FLAVOUR_UNUSED; 3268 attrs.phys.port_number = port->port_id; 3269 attrs.switch_id.id_len = sizeof(resource_size_t); 3270 memcpy(attrs.switch_id.id, common->switch_id, attrs.switch_id.id_len); 3271 devlink_port_attrs_set(dl_port, &attrs); 3272 3273 ret = devlink_port_register(common->devlink, dl_port, port->port_id); 3274 if (ret) { 3275 dev_err(dev, "devlink_port reg fail for port %d, ret:%d\n", 3276 port->port_id, ret); 3277 goto dl_port_unreg; 3278 } 3279 } 3280 devlink_register(common->devlink); 3281 return ret; 3282 3283 dl_port_unreg: 3284 for (i = i - 1; i >= 1; i--) { 3285 port = am65_common_get_port(common, i); 3286 dl_port = &port->devlink_port; 3287 3288 devlink_port_unregister(dl_port); 3289 } 3290 dl_unreg: 3291 devlink_free(common->devlink); 3292 return ret; 3293 } 3294 3295 static void am65_cpsw_unregister_devlink(struct am65_cpsw_common *common) 3296 { 3297 struct devlink_port *dl_port; 3298 struct am65_cpsw_port *port; 3299 int i; 3300 3301 devlink_unregister(common->devlink); 3302 3303 for (i = 1; i <= common->port_num; i++) { 3304 port = am65_common_get_port(common, i); 3305 dl_port = &port->devlink_port; 3306 3307 devlink_port_unregister(dl_port); 3308 } 3309 3310 if (!AM65_CPSW_IS_CPSW2G(common) && 3311 IS_ENABLED(CONFIG_TI_K3_AM65_CPSW_SWITCHDEV)) 3312 devlink_params_unregister(common->devlink, 3313 am65_cpsw_devlink_params, 3314 ARRAY_SIZE(am65_cpsw_devlink_params)); 3315 3316 devlink_free(common->devlink); 3317 } 3318 3319 static int am65_cpsw_nuss_register_ndevs(struct am65_cpsw_common *common) 3320 { 3321 struct am65_cpsw_rx_chn *rx_chan = &common->rx_chns; 3322 struct am65_cpsw_tx_chn *tx_chan = common->tx_chns; 3323 struct device *dev = common->dev; 3324 struct am65_cpsw_port *port; 3325 int ret = 0, i; 3326 3327 /* init tx channels */ 3328 ret = am65_cpsw_nuss_init_tx_chns(common); 3329 if (ret) 3330 return ret; 3331 ret = am65_cpsw_nuss_init_rx_chns(common); 3332 if (ret) 3333 goto err_remove_tx; 3334 3335 /* The DMA Channels are not guaranteed to be in a clean state. 3336 * Reset and disable them to ensure that they are back to the 3337 * clean state and ready to be used. 3338 */ 3339 for (i = 0; i < common->tx_ch_num; i++) { 3340 k3_udma_glue_reset_tx_chn(tx_chan[i].tx_chn, &tx_chan[i], 3341 am65_cpsw_nuss_tx_cleanup); 3342 k3_udma_glue_disable_tx_chn(tx_chan[i].tx_chn); 3343 } 3344 3345 for (i = 0; i < common->rx_ch_num_flows; i++) 3346 k3_udma_glue_reset_rx_chn(rx_chan->rx_chn, i, 3347 rx_chan, 3348 am65_cpsw_nuss_rx_cleanup); 3349 3350 k3_udma_glue_disable_rx_chn(rx_chan->rx_chn); 3351 3352 ret = am65_cpsw_nuss_register_devlink(common); 3353 if (ret) 3354 goto err_remove_rx; 3355 3356 for (i = 0; i < common->port_num; i++) { 3357 port = &common->ports[i]; 3358 3359 if (!port->ndev) 3360 continue; 3361 3362 SET_NETDEV_DEVLINK_PORT(port->ndev, &port->devlink_port); 3363 3364 ret = register_netdev(port->ndev); 3365 if (ret) { 3366 dev_err(dev, "error registering slave net device%i %d\n", 3367 i, ret); 3368 goto err_cleanup_ndev; 3369 } 3370 } 3371 3372 ret = am65_cpsw_register_notifiers(common); 3373 if (ret) 3374 goto err_cleanup_ndev; 3375 3376 /* can't auto unregister ndev using devm_add_action() due to 3377 * devres release sequence in DD core for DMA 3378 */ 3379 3380 return 0; 3381 3382 err_cleanup_ndev: 3383 am65_cpsw_nuss_cleanup_ndev(common); 3384 am65_cpsw_unregister_devlink(common); 3385 err_remove_rx: 3386 am65_cpsw_nuss_remove_rx_chns(common); 3387 err_remove_tx: 3388 am65_cpsw_nuss_remove_tx_chns(common); 3389 3390 return ret; 3391 } 3392 3393 int am65_cpsw_nuss_update_tx_rx_chns(struct am65_cpsw_common *common, 3394 int num_tx, int num_rx) 3395 { 3396 int ret; 3397 3398 am65_cpsw_nuss_remove_tx_chns(common); 3399 am65_cpsw_nuss_remove_rx_chns(common); 3400 3401 common->tx_ch_num = num_tx; 3402 common->rx_ch_num_flows = num_rx; 3403 ret = am65_cpsw_nuss_init_tx_chns(common); 3404 if (ret) 3405 return ret; 3406 3407 ret = am65_cpsw_nuss_init_rx_chns(common); 3408 if (ret) 3409 am65_cpsw_nuss_remove_tx_chns(common); 3410 3411 return ret; 3412 } 3413 3414 struct am65_cpsw_soc_pdata { 3415 u32 quirks_dis; 3416 }; 3417 3418 static const struct am65_cpsw_soc_pdata am65x_soc_sr2_0 = { 3419 .quirks_dis = AM65_CPSW_QUIRK_I2027_NO_TX_CSUM, 3420 }; 3421 3422 static const struct soc_device_attribute am65_cpsw_socinfo[] = { 3423 { .family = "AM65X", 3424 .revision = "SR2.0", 3425 .data = &am65x_soc_sr2_0 3426 }, 3427 {/* sentinel */} 3428 }; 3429 3430 static const struct am65_cpsw_pdata am65x_sr1_0 = { 3431 .quirks = AM65_CPSW_QUIRK_I2027_NO_TX_CSUM, 3432 .ale_dev_id = "am65x-cpsw2g", 3433 .fdqring_mode = K3_RINGACC_RING_MODE_MESSAGE, 3434 }; 3435 3436 static const struct am65_cpsw_pdata j721e_pdata = { 3437 .quirks = 0, 3438 .ale_dev_id = "am65x-cpsw2g", 3439 .fdqring_mode = K3_RINGACC_RING_MODE_MESSAGE, 3440 }; 3441 3442 static const struct am65_cpsw_pdata am64x_cpswxg_pdata = { 3443 .quirks = AM64_CPSW_QUIRK_DMA_RX_TDOWN_IRQ, 3444 .ale_dev_id = "am64-cpswxg", 3445 .fdqring_mode = K3_RINGACC_RING_MODE_RING, 3446 }; 3447 3448 static const struct am65_cpsw_pdata j7200_cpswxg_pdata = { 3449 .quirks = 0, 3450 .ale_dev_id = "am64-cpswxg", 3451 .fdqring_mode = K3_RINGACC_RING_MODE_RING, 3452 .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII) | 3453 BIT(PHY_INTERFACE_MODE_USXGMII), 3454 }; 3455 3456 static const struct am65_cpsw_pdata j721e_cpswxg_pdata = { 3457 .quirks = 0, 3458 .ale_dev_id = "am64-cpswxg", 3459 .fdqring_mode = K3_RINGACC_RING_MODE_MESSAGE, 3460 .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII), 3461 }; 3462 3463 static const struct am65_cpsw_pdata j784s4_cpswxg_pdata = { 3464 .quirks = 0, 3465 .ale_dev_id = "am64-cpswxg", 3466 .fdqring_mode = K3_RINGACC_RING_MODE_MESSAGE, 3467 .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII) | 3468 BIT(PHY_INTERFACE_MODE_USXGMII), 3469 }; 3470 3471 static const struct of_device_id am65_cpsw_nuss_of_mtable[] = { 3472 { .compatible = "ti,am654-cpsw-nuss", .data = &am65x_sr1_0}, 3473 { .compatible = "ti,j721e-cpsw-nuss", .data = &j721e_pdata}, 3474 { .compatible = "ti,am642-cpsw-nuss", .data = &am64x_cpswxg_pdata}, 3475 { .compatible = "ti,j7200-cpswxg-nuss", .data = &j7200_cpswxg_pdata}, 3476 { .compatible = "ti,j721e-cpswxg-nuss", .data = &j721e_cpswxg_pdata}, 3477 { .compatible = "ti,j784s4-cpswxg-nuss", .data = &j784s4_cpswxg_pdata}, 3478 { /* sentinel */ }, 3479 }; 3480 MODULE_DEVICE_TABLE(of, am65_cpsw_nuss_of_mtable); 3481 3482 static void am65_cpsw_nuss_apply_socinfo(struct am65_cpsw_common *common) 3483 { 3484 const struct soc_device_attribute *soc; 3485 3486 soc = soc_device_match(am65_cpsw_socinfo); 3487 if (soc && soc->data) { 3488 const struct am65_cpsw_soc_pdata *socdata = soc->data; 3489 3490 /* disable quirks */ 3491 common->pdata.quirks &= ~socdata->quirks_dis; 3492 } 3493 } 3494 3495 static int am65_cpsw_nuss_probe(struct platform_device *pdev) 3496 { 3497 struct cpsw_ale_params ale_params = { 0 }; 3498 const struct of_device_id *of_id; 3499 struct device *dev = &pdev->dev; 3500 struct am65_cpsw_common *common; 3501 struct device_node *node; 3502 struct resource *res; 3503 struct clk *clk; 3504 int ale_entries; 3505 __be64 id_temp; 3506 int ret, i; 3507 3508 BUILD_BUG_ON_MSG(sizeof(struct am65_cpsw_tx_swdata) > AM65_CPSW_NAV_SW_DATA_SIZE, 3509 "TX SW_DATA size exceeds AM65_CPSW_NAV_SW_DATA_SIZE"); 3510 BUILD_BUG_ON_MSG(sizeof(struct am65_cpsw_swdata) > AM65_CPSW_NAV_SW_DATA_SIZE, 3511 "SW_DATA size exceeds AM65_CPSW_NAV_SW_DATA_SIZE"); 3512 common = devm_kzalloc(dev, sizeof(struct am65_cpsw_common), GFP_KERNEL); 3513 if (!common) 3514 return -ENOMEM; 3515 common->dev = dev; 3516 3517 of_id = of_match_device(am65_cpsw_nuss_of_mtable, dev); 3518 if (!of_id) 3519 return -EINVAL; 3520 common->pdata = *(const struct am65_cpsw_pdata *)of_id->data; 3521 3522 am65_cpsw_nuss_apply_socinfo(common); 3523 3524 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cpsw_nuss"); 3525 common->ss_base = devm_ioremap_resource(&pdev->dev, res); 3526 if (IS_ERR(common->ss_base)) 3527 return PTR_ERR(common->ss_base); 3528 common->cpsw_base = common->ss_base + AM65_CPSW_CPSW_NU_BASE; 3529 /* Use device's physical base address as switch id */ 3530 id_temp = cpu_to_be64(res->start); 3531 memcpy(common->switch_id, &id_temp, sizeof(res->start)); 3532 3533 node = of_get_child_by_name(dev->of_node, "ethernet-ports"); 3534 if (!node) 3535 return -ENOENT; 3536 common->port_num = of_get_child_count(node); 3537 of_node_put(node); 3538 if (common->port_num < 1 || common->port_num > AM65_CPSW_MAX_PORTS) 3539 return -ENOENT; 3540 3541 common->rx_flow_id_base = -1; 3542 init_completion(&common->tdown_complete); 3543 common->tx_ch_num = AM65_CPSW_DEFAULT_TX_CHNS; 3544 common->rx_ch_num_flows = AM65_CPSW_DEFAULT_RX_CHN_FLOWS; 3545 common->pf_p0_rx_ptype_rrobin = true; 3546 common->default_vlan = 1; 3547 3548 common->ports = devm_kcalloc(dev, common->port_num, 3549 sizeof(*common->ports), 3550 GFP_KERNEL); 3551 if (!common->ports) 3552 return -ENOMEM; 3553 3554 clk = devm_clk_get(dev, "fck"); 3555 if (IS_ERR(clk)) 3556 return dev_err_probe(dev, PTR_ERR(clk), "getting fck clock\n"); 3557 common->bus_freq = clk_get_rate(clk); 3558 3559 pm_runtime_enable(dev); 3560 ret = pm_runtime_resume_and_get(dev); 3561 if (ret < 0) { 3562 pm_runtime_disable(dev); 3563 return ret; 3564 } 3565 3566 am65_cpsw_nuss_get_ver(common); 3567 3568 ret = am65_cpsw_nuss_init_host_p(common); 3569 if (ret) 3570 goto err_pm_clear; 3571 3572 ret = am65_cpsw_nuss_init_slave_ports(common); 3573 if (ret) 3574 goto err_pm_clear; 3575 3576 node = of_get_child_by_name(dev->of_node, "mdio"); 3577 if (!node) { 3578 dev_warn(dev, "MDIO node not found\n"); 3579 } else if (of_device_is_available(node)) { 3580 struct platform_device *mdio_pdev; 3581 3582 mdio_pdev = of_platform_device_create(node, NULL, dev); 3583 if (!mdio_pdev) { 3584 ret = -ENODEV; 3585 goto err_pm_clear; 3586 } 3587 3588 common->mdio_dev = &mdio_pdev->dev; 3589 } 3590 of_node_put(node); 3591 3592 /* init common data */ 3593 ale_params.dev = dev; 3594 ale_params.ale_ageout = AM65_CPSW_ALE_AGEOUT_DEFAULT; 3595 ale_params.ale_ports = common->port_num + 1; 3596 ale_params.ale_regs = common->cpsw_base + AM65_CPSW_NU_ALE_BASE; 3597 ale_params.dev_id = common->pdata.ale_dev_id; 3598 ale_params.bus_freq = common->bus_freq; 3599 3600 common->ale = cpsw_ale_create(&ale_params); 3601 if (IS_ERR(common->ale)) { 3602 dev_err(dev, "error initializing ale engine\n"); 3603 ret = PTR_ERR(common->ale); 3604 goto err_of_clear; 3605 } 3606 3607 ale_entries = common->ale->params.ale_entries; 3608 common->ale_context = devm_kzalloc(dev, 3609 ale_entries * ALE_ENTRY_WORDS * sizeof(u32), 3610 GFP_KERNEL); 3611 ret = am65_cpsw_init_cpts(common); 3612 if (ret) 3613 goto err_of_clear; 3614 3615 /* init ports */ 3616 for (i = 0; i < common->port_num; i++) 3617 am65_cpsw_nuss_slave_disable_unused(&common->ports[i]); 3618 3619 dev_set_drvdata(dev, common); 3620 3621 common->is_emac_mode = true; 3622 3623 ret = am65_cpsw_nuss_init_ndevs(common); 3624 if (ret) 3625 goto err_ndevs_clear; 3626 3627 ret = am65_cpsw_nuss_register_ndevs(common); 3628 if (ret) 3629 goto err_ndevs_clear; 3630 3631 pm_runtime_put(dev); 3632 return 0; 3633 3634 err_ndevs_clear: 3635 am65_cpsw_nuss_cleanup_ndev(common); 3636 am65_cpsw_nuss_phylink_cleanup(common); 3637 am65_cpts_release(common->cpts); 3638 am65_cpsw_remove_dt(common); 3639 err_of_clear: 3640 if (common->mdio_dev) 3641 of_platform_device_destroy(common->mdio_dev, NULL); 3642 err_pm_clear: 3643 pm_runtime_put_sync(dev); 3644 pm_runtime_disable(dev); 3645 return ret; 3646 } 3647 3648 static void am65_cpsw_nuss_remove(struct platform_device *pdev) 3649 { 3650 struct device *dev = &pdev->dev; 3651 struct am65_cpsw_common *common; 3652 int ret; 3653 3654 common = dev_get_drvdata(dev); 3655 3656 ret = pm_runtime_resume_and_get(&pdev->dev); 3657 if (ret < 0) { 3658 /* Note, if this error path is taken, we're leaking some 3659 * resources. 3660 */ 3661 dev_err(&pdev->dev, "Failed to resume device (%pe)\n", 3662 ERR_PTR(ret)); 3663 return; 3664 } 3665 3666 am65_cpsw_unregister_notifiers(common); 3667 3668 /* must unregister ndevs here because DD release_driver routine calls 3669 * dma_deconfigure(dev) before devres_release_all(dev) 3670 */ 3671 am65_cpsw_nuss_cleanup_ndev(common); 3672 am65_cpsw_unregister_devlink(common); 3673 am65_cpsw_nuss_remove_rx_chns(common); 3674 am65_cpsw_nuss_remove_tx_chns(common); 3675 am65_cpsw_nuss_phylink_cleanup(common); 3676 am65_cpts_release(common->cpts); 3677 am65_cpsw_disable_serdes_phy(common); 3678 am65_cpsw_remove_dt(common); 3679 3680 if (common->mdio_dev) 3681 of_platform_device_destroy(common->mdio_dev, NULL); 3682 3683 pm_runtime_put_sync(&pdev->dev); 3684 pm_runtime_disable(&pdev->dev); 3685 } 3686 3687 static int am65_cpsw_nuss_suspend(struct device *dev) 3688 { 3689 struct am65_cpsw_common *common = dev_get_drvdata(dev); 3690 struct am65_cpsw_host *host_p = am65_common_get_host(common); 3691 struct am65_cpsw_port *port; 3692 struct net_device *ndev; 3693 int i, ret; 3694 3695 cpsw_ale_dump(common->ale, common->ale_context); 3696 host_p->vid_context = readl(host_p->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 3697 for (i = 0; i < common->port_num; i++) { 3698 port = &common->ports[i]; 3699 ndev = port->ndev; 3700 3701 if (!ndev) 3702 continue; 3703 3704 port->vid_context = readl(port->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 3705 netif_device_detach(ndev); 3706 if (netif_running(ndev)) { 3707 rtnl_lock(); 3708 ret = am65_cpsw_nuss_ndo_slave_stop(ndev); 3709 rtnl_unlock(); 3710 if (ret < 0) { 3711 netdev_err(ndev, "failed to stop: %d", ret); 3712 return ret; 3713 } 3714 } 3715 } 3716 3717 am65_cpts_suspend(common->cpts); 3718 3719 am65_cpsw_nuss_remove_rx_chns(common); 3720 am65_cpsw_nuss_remove_tx_chns(common); 3721 3722 return 0; 3723 } 3724 3725 static int am65_cpsw_nuss_resume(struct device *dev) 3726 { 3727 struct am65_cpsw_common *common = dev_get_drvdata(dev); 3728 struct am65_cpsw_host *host_p = am65_common_get_host(common); 3729 struct am65_cpsw_port *port; 3730 struct net_device *ndev; 3731 int i, ret; 3732 3733 ret = am65_cpsw_nuss_init_tx_chns(common); 3734 if (ret) 3735 return ret; 3736 ret = am65_cpsw_nuss_init_rx_chns(common); 3737 if (ret) { 3738 am65_cpsw_nuss_remove_tx_chns(common); 3739 return ret; 3740 } 3741 3742 /* If RX IRQ was disabled before suspend, keep it disabled */ 3743 for (i = 0; i < common->rx_ch_num_flows; i++) { 3744 if (common->rx_chns.flows[i].irq_disabled) 3745 disable_irq(common->rx_chns.flows[i].irq); 3746 } 3747 3748 am65_cpts_resume(common->cpts); 3749 3750 for (i = 0; i < common->port_num; i++) { 3751 port = &common->ports[i]; 3752 ndev = port->ndev; 3753 3754 if (!ndev) 3755 continue; 3756 3757 if (netif_running(ndev)) { 3758 rtnl_lock(); 3759 ret = am65_cpsw_nuss_ndo_slave_open(ndev); 3760 rtnl_unlock(); 3761 if (ret < 0) { 3762 netdev_err(ndev, "failed to start: %d", ret); 3763 return ret; 3764 } 3765 } 3766 3767 netif_device_attach(ndev); 3768 writel(port->vid_context, port->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 3769 } 3770 3771 writel(host_p->vid_context, host_p->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 3772 cpsw_ale_restore(common->ale, common->ale_context); 3773 3774 return 0; 3775 } 3776 3777 static const struct dev_pm_ops am65_cpsw_nuss_dev_pm_ops = { 3778 SYSTEM_SLEEP_PM_OPS(am65_cpsw_nuss_suspend, am65_cpsw_nuss_resume) 3779 }; 3780 3781 static struct platform_driver am65_cpsw_nuss_driver = { 3782 .driver = { 3783 .name = AM65_CPSW_DRV_NAME, 3784 .of_match_table = am65_cpsw_nuss_of_mtable, 3785 .pm = &am65_cpsw_nuss_dev_pm_ops, 3786 }, 3787 .probe = am65_cpsw_nuss_probe, 3788 .remove = am65_cpsw_nuss_remove, 3789 }; 3790 3791 module_platform_driver(am65_cpsw_nuss_driver); 3792 3793 MODULE_LICENSE("GPL v2"); 3794 MODULE_AUTHOR("Grygorii Strashko <grygorii.strashko@ti.com>"); 3795 MODULE_DESCRIPTION("TI AM65 CPSW Ethernet driver"); 3796