1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * r8169.c: RealTek 8169/8168/8101 ethernet driver. 4 * 5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> 6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> 7 * Copyright (c) a lot of people too. Please respect their work. 8 * 9 * See MAINTAINERS file for support contact information. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/pci.h> 14 #include <linux/netdevice.h> 15 #include <linux/etherdevice.h> 16 #include <linux/clk.h> 17 #include <linux/delay.h> 18 #include <linux/ethtool.h> 19 #include <linux/phy.h> 20 #include <linux/if_vlan.h> 21 #include <linux/in.h> 22 #include <linux/io.h> 23 #include <linux/ip.h> 24 #include <linux/tcp.h> 25 #include <linux/interrupt.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/bitfield.h> 29 #include <linux/prefetch.h> 30 #include <linux/ipv6.h> 31 #include <linux/unaligned.h> 32 #include <net/ip6_checksum.h> 33 #include <net/netdev_queues.h> 34 35 #include "r8169.h" 36 #include "r8169_firmware.h" 37 38 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw" 39 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw" 40 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw" 41 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw" 42 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw" 43 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw" 44 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw" 45 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw" 46 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw" 47 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw" 48 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw" 49 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw" 50 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw" 51 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw" 52 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw" 53 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw" 54 #define FIRMWARE_8168FP_3 "rtl_nic/rtl8168fp-3.fw" 55 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw" 56 #define FIRMWARE_8125A_3 "rtl_nic/rtl8125a-3.fw" 57 #define FIRMWARE_8125B_2 "rtl_nic/rtl8125b-2.fw" 58 #define FIRMWARE_8125D_1 "rtl_nic/rtl8125d-1.fw" 59 #define FIRMWARE_8125D_2 "rtl_nic/rtl8125d-2.fw" 60 #define FIRMWARE_8125BP_2 "rtl_nic/rtl8125bp-2.fw" 61 #define FIRMWARE_8126A_2 "rtl_nic/rtl8126a-2.fw" 62 #define FIRMWARE_8126A_3 "rtl_nic/rtl8126a-3.fw" 63 #define FIRMWARE_8127A_1 "rtl_nic/rtl8127a-1.fw" 64 65 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */ 66 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ 67 68 #define R8169_REGS_SIZE 256 69 #define R8169_RX_BUF_SIZE (SZ_16K - 1) 70 #define NUM_TX_DESC 256 /* Number of Tx descriptor registers */ 71 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */ 72 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) 73 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) 74 #define R8169_TX_STOP_THRS (MAX_SKB_FRAGS + 1) 75 #define R8169_TX_START_THRS (2 * R8169_TX_STOP_THRS) 76 77 #define OCP_STD_PHY_BASE 0xa400 78 79 #define RTL_CFG_NO_GBIT 1 80 81 /* write/read MMIO register */ 82 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg)) 83 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg)) 84 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg)) 85 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg)) 86 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg)) 87 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg)) 88 89 #define JUMBO_4K (4 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 90 #define JUMBO_6K (6 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 91 #define JUMBO_7K (7 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 92 #define JUMBO_9K (9 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 93 #define JUMBO_16K (SZ_16K - VLAN_ETH_HLEN - ETH_FCS_LEN) 94 95 static const struct rtl_chip_info { 96 u16 mask; 97 u16 val; 98 enum mac_version mac_version; 99 const char *name; 100 const char *fw_name; 101 } rtl_chip_infos[] = { 102 /* 8127A family. */ 103 { 0x7cf, 0x6c9, RTL_GIGA_MAC_VER_80, "RTL8127A", FIRMWARE_8127A_1 }, 104 105 /* 8126A family. */ 106 { 0x7cf, 0x64a, RTL_GIGA_MAC_VER_70, "RTL8126A", FIRMWARE_8126A_3 }, 107 { 0x7cf, 0x649, RTL_GIGA_MAC_VER_70, "RTL8126A", FIRMWARE_8126A_2 }, 108 109 /* 8125BP family. */ 110 { 0x7cf, 0x681, RTL_GIGA_MAC_VER_66, "RTL8125BP", FIRMWARE_8125BP_2 }, 111 112 /* 8125D family. */ 113 { 0x7cf, 0x689, RTL_GIGA_MAC_VER_64, "RTL8125D", FIRMWARE_8125D_2 }, 114 { 0x7cf, 0x688, RTL_GIGA_MAC_VER_64, "RTL8125D", FIRMWARE_8125D_1 }, 115 116 /* 8125B family. */ 117 { 0x7cf, 0x641, RTL_GIGA_MAC_VER_63, "RTL8125B", FIRMWARE_8125B_2 }, 118 119 /* 8125A family. */ 120 { 0x7cf, 0x609, RTL_GIGA_MAC_VER_61, "RTL8125A", FIRMWARE_8125A_3 }, 121 122 /* RTL8117 */ 123 { 0x7cf, 0x54b, RTL_GIGA_MAC_VER_52, "RTL8168fp/RTL8117" }, 124 { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52, "RTL8168fp/RTL8117", 125 FIRMWARE_8168FP_3 }, 126 127 /* 8168EP family. */ 128 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51, "RTL8168ep/8111ep" }, 129 130 /* 8168H family. */ 131 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46, "RTL8168h/8111h", 132 FIRMWARE_8168H_2 }, 133 /* Realtek calls it RTL8168M, but it's handled like RTL8168H */ 134 { 0x7cf, 0x6c0, RTL_GIGA_MAC_VER_46, "RTL8168M", FIRMWARE_8168H_2 }, 135 136 /* 8168G family. */ 137 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44, "RTL8411b", FIRMWARE_8411_2 }, 138 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42, "RTL8168gu/8111gu", 139 FIRMWARE_8168G_3 }, 140 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40, "RTL8168g/8111g", 141 FIRMWARE_8168G_2 }, 142 143 /* 8168F family. */ 144 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38, "RTL8411", FIRMWARE_8411_1 }, 145 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36, "RTL8168f/8111f", 146 FIRMWARE_8168F_2 }, 147 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35, "RTL8168f/8111f", 148 FIRMWARE_8168F_1 }, 149 150 /* 8168E family. */ 151 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34, "RTL8168evl/8111evl", 152 FIRMWARE_8168E_3 }, 153 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32, "RTL8168e/8111e", 154 FIRMWARE_8168E_1 }, 155 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33, "RTL8168e/8111e", 156 FIRMWARE_8168E_2 }, 157 158 /* 8168D family. */ 159 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25, "RTL8168d/8111d", 160 FIRMWARE_8168D_1 }, 161 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26, "RTL8168d/8111d", 162 FIRMWARE_8168D_2 }, 163 164 /* 8168DP family. */ 165 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28, "RTL8168dp/8111dp" }, 166 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31, "RTL8168dp/8111dp" }, 167 168 /* 8168C family. */ 169 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23, "RTL8168cp/8111cp" }, 170 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18, "RTL8168cp/8111cp" }, 171 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24, "RTL8168cp/8111cp" }, 172 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19, "RTL8168c/8111c" }, 173 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20, "RTL8168c/8111c" }, 174 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21, "RTL8168c/8111c" }, 175 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22, "RTL8168c/8111c" }, 176 177 /* 8168B family. */ 178 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17, "RTL8168b/8111b" }, 179 /* This one is very old and rare, support has been removed. 180 * { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11, "RTL8168b/8111b" }, 181 */ 182 183 /* 8101 family. */ 184 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39, "RTL8106e", FIRMWARE_8106E_1 }, 185 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37, "RTL8402", FIRMWARE_8402_1 }, 186 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29, "RTL8105e", FIRMWARE_8105E_1 }, 187 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30, "RTL8105e", FIRMWARE_8105E_1 }, 188 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08, "RTL8102e" }, 189 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08, "RTL8102e" }, 190 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07, "RTL8102e" }, 191 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07, "RTL8102e" }, 192 { 0x7cf, 0x240, RTL_GIGA_MAC_VER_14, "RTL8401" }, 193 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09, "RTL8102e/RTL8103e" }, 194 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09, "RTL8102e/RTL8103e" }, 195 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_10, "RTL8101e/RTL8100e" }, 196 197 /* 8110 family. */ 198 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06, "RTL8169sc/8110sc" }, 199 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05, "RTL8169sc/8110sc" }, 200 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04, "RTL8169sb/8110sb" }, 201 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03, "RTL8110s" }, 202 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02, "RTL8169s" }, 203 204 /* Catch-all */ 205 { 0x000, 0x000, RTL_GIGA_MAC_NONE } 206 }; 207 208 static const struct pci_device_id rtl8169_pci_tbl[] = { 209 { PCI_VDEVICE(REALTEK, 0x2502) }, 210 { PCI_VDEVICE(REALTEK, 0x2600) }, 211 { PCI_VDEVICE(REALTEK, 0x8129) }, 212 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT }, 213 { PCI_VDEVICE(REALTEK, 0x8161) }, 214 { PCI_VDEVICE(REALTEK, 0x8162) }, 215 { PCI_VDEVICE(REALTEK, 0x8167) }, 216 { PCI_VDEVICE(REALTEK, 0x8168) }, 217 { PCI_VDEVICE(NCUBE, 0x8168) }, 218 { PCI_VDEVICE(REALTEK, 0x8169) }, 219 { PCI_VENDOR_ID_DLINK, 0x4300, 220 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 }, 221 { PCI_VDEVICE(DLINK, 0x4300) }, 222 { PCI_VDEVICE(DLINK, 0x4302) }, 223 { PCI_VDEVICE(AT, 0xc107) }, 224 { PCI_VDEVICE(USR, 0x0116) }, 225 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 }, 226 { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 }, 227 { PCI_VDEVICE(REALTEK, 0x8125) }, 228 { PCI_VDEVICE(REALTEK, 0x8126) }, 229 { PCI_VDEVICE(REALTEK, 0x8127) }, 230 { PCI_VDEVICE(REALTEK, 0x3000) }, 231 { PCI_VDEVICE(REALTEK, 0x5000) }, 232 { PCI_VDEVICE(REALTEK, 0x0e10) }, 233 {} 234 }; 235 236 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl); 237 238 enum rtl_registers { 239 MAC0 = 0, /* Ethernet hardware address. */ 240 MAC4 = 4, 241 MAR0 = 8, /* Multicast filter. */ 242 CounterAddrLow = 0x10, 243 CounterAddrHigh = 0x14, 244 TxDescStartAddrLow = 0x20, 245 TxDescStartAddrHigh = 0x24, 246 TxHDescStartAddrLow = 0x28, 247 TxHDescStartAddrHigh = 0x2c, 248 FLASH = 0x30, 249 ERSR = 0x36, 250 ChipCmd = 0x37, 251 TxPoll = 0x38, 252 IntrMask = 0x3c, 253 IntrStatus = 0x3e, 254 255 TxConfig = 0x40, 256 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */ 257 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */ 258 259 RxConfig = 0x44, 260 #define RX128_INT_EN (1 << 15) /* 8111c and later */ 261 #define RX_MULTI_EN (1 << 14) /* 8111c only */ 262 #define RXCFG_FIFO_SHIFT 13 263 /* No threshold before first PCI xfer */ 264 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT) 265 #define RX_EARLY_OFF (1 << 11) 266 #define RX_PAUSE_SLOT_ON (1 << 11) /* 8125b and later */ 267 #define RXCFG_DMA_SHIFT 8 268 /* Unlimited maximum PCI burst. */ 269 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT) 270 271 Cfg9346 = 0x50, 272 Config0 = 0x51, 273 Config1 = 0x52, 274 Config2 = 0x53, 275 #define PME_SIGNAL (1 << 5) /* 8168c and later */ 276 277 Config3 = 0x54, 278 Config4 = 0x55, 279 Config5 = 0x56, 280 PHYAR = 0x60, 281 PHYstatus = 0x6c, 282 RxMaxSize = 0xda, 283 CPlusCmd = 0xe0, 284 IntrMitigate = 0xe2, 285 286 #define RTL_COALESCE_TX_USECS GENMASK(15, 12) 287 #define RTL_COALESCE_TX_FRAMES GENMASK(11, 8) 288 #define RTL_COALESCE_RX_USECS GENMASK(7, 4) 289 #define RTL_COALESCE_RX_FRAMES GENMASK(3, 0) 290 291 #define RTL_COALESCE_T_MAX 0x0fU 292 #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_T_MAX * 4) 293 294 RxDescAddrLow = 0xe4, 295 RxDescAddrHigh = 0xe8, 296 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */ 297 298 #define NoEarlyTx 0x3f /* Max value : no early transmit. */ 299 300 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */ 301 302 #define TxPacketMax (8064 >> 7) 303 #define EarlySize 0x27 304 305 FuncEvent = 0xf0, 306 FuncEventMask = 0xf4, 307 FuncPresetState = 0xf8, 308 IBCR0 = 0xf8, 309 IBCR2 = 0xf9, 310 IBIMR0 = 0xfa, 311 IBISR0 = 0xfb, 312 FuncForceEvent = 0xfc, 313 }; 314 315 enum rtl8168_8101_registers { 316 CSIDR = 0x64, 317 CSIAR = 0x68, 318 #define CSIAR_FLAG 0x80000000 319 #define CSIAR_WRITE_CMD 0x80000000 320 #define CSIAR_BYTE_ENABLE 0x0000f000 321 #define CSIAR_ADDR_MASK 0x00000fff 322 PMCH = 0x6f, 323 #define D3COLD_NO_PLL_DOWN BIT(7) 324 #define D3HOT_NO_PLL_DOWN BIT(6) 325 #define D3_NO_PLL_DOWN (BIT(7) | BIT(6)) 326 EPHYAR = 0x80, 327 #define EPHYAR_FLAG 0x80000000 328 #define EPHYAR_WRITE_CMD 0x80000000 329 #define EPHYAR_REG_MASK 0x1f 330 #define EPHYAR_REG_SHIFT 16 331 #define EPHYAR_DATA_MASK 0xffff 332 DLLPR = 0xd0, 333 #define PFM_EN (1 << 6) 334 #define TX_10M_PS_EN (1 << 7) 335 DBG_REG = 0xd1, 336 #define FIX_NAK_1 (1 << 4) 337 #define FIX_NAK_2 (1 << 3) 338 TWSI = 0xd2, 339 MCU = 0xd3, 340 #define NOW_IS_OOB (1 << 7) 341 #define TX_EMPTY (1 << 5) 342 #define RX_EMPTY (1 << 4) 343 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY) 344 #define EN_NDP (1 << 3) 345 #define EN_OOB_RESET (1 << 2) 346 #define LINK_LIST_RDY (1 << 1) 347 EFUSEAR = 0xdc, 348 #define EFUSEAR_FLAG 0x80000000 349 #define EFUSEAR_WRITE_CMD 0x80000000 350 #define EFUSEAR_READ_CMD 0x00000000 351 #define EFUSEAR_REG_MASK 0x03ff 352 #define EFUSEAR_REG_SHIFT 8 353 #define EFUSEAR_DATA_MASK 0xff 354 MISC_1 = 0xf2, 355 #define PFM_D3COLD_EN (1 << 6) 356 }; 357 358 enum rtl8168_registers { 359 LED_CTRL = 0x18, 360 LED_FREQ = 0x1a, 361 EEE_LED = 0x1b, 362 ERIDR = 0x70, 363 ERIAR = 0x74, 364 #define ERIAR_FLAG 0x80000000 365 #define ERIAR_WRITE_CMD 0x80000000 366 #define ERIAR_READ_CMD 0x00000000 367 #define ERIAR_ADDR_BYTE_ALIGN 4 368 #define ERIAR_TYPE_SHIFT 16 369 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT) 370 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT) 371 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT) 372 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT) 373 #define ERIAR_MASK_SHIFT 12 374 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT) 375 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT) 376 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT) 377 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT) 378 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT) 379 EPHY_RXER_NUM = 0x7c, 380 OCPDR = 0xb0, /* OCP GPHY access */ 381 #define OCPDR_WRITE_CMD 0x80000000 382 #define OCPDR_READ_CMD 0x00000000 383 #define OCPDR_REG_MASK 0x7f 384 #define OCPDR_GPHY_REG_SHIFT 16 385 #define OCPDR_DATA_MASK 0xffff 386 OCPAR = 0xb4, 387 #define OCPAR_FLAG 0x80000000 388 #define OCPAR_GPHY_WRITE_CMD 0x8000f060 389 #define OCPAR_GPHY_READ_CMD 0x0000f060 390 GPHY_OCP = 0xb8, 391 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */ 392 MISC = 0xf0, /* 8168e only. */ 393 #define TXPLA_RST (1 << 29) 394 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */ 395 #define PWM_EN (1 << 22) 396 #define RXDV_GATED_EN (1 << 19) 397 #define EARLY_TALLY_EN (1 << 16) 398 }; 399 400 enum rtl8125_registers { 401 LEDSEL0 = 0x18, 402 INT_CFG0_8125 = 0x34, 403 #define INT_CFG0_ENABLE_8125 BIT(0) 404 #define INT_CFG0_CLKREQEN BIT(3) 405 IntrMask_8125 = 0x38, 406 IntrStatus_8125 = 0x3c, 407 INT_CFG1_8125 = 0x7a, 408 LEDSEL2 = 0x84, 409 LEDSEL1 = 0x86, 410 TxPoll_8125 = 0x90, 411 LEDSEL3 = 0x96, 412 MAC0_BKP = 0x19e0, 413 RSS_CTRL_8125 = 0x4500, 414 Q_NUM_CTRL_8125 = 0x4800, 415 EEE_TXIDLE_TIMER_8125 = 0x6048, 416 }; 417 418 #define LEDSEL_MASK_8125 0x23f 419 420 #define RX_VLAN_INNER_8125 BIT(22) 421 #define RX_VLAN_OUTER_8125 BIT(23) 422 #define RX_VLAN_8125 (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125) 423 424 #define RX_FETCH_DFLT_8125 (8 << 27) 425 426 enum rtl_register_content { 427 /* InterruptStatusBits */ 428 SYSErr = 0x8000, 429 PCSTimeout = 0x4000, 430 SWInt = 0x0100, 431 TxDescUnavail = 0x0080, 432 RxFIFOOver = 0x0040, 433 LinkChg = 0x0020, 434 RxOverflow = 0x0010, 435 TxErr = 0x0008, 436 TxOK = 0x0004, 437 RxErr = 0x0002, 438 RxOK = 0x0001, 439 440 /* RxStatusDesc */ 441 RxRWT = (1 << 22), 442 RxRES = (1 << 21), 443 RxRUNT = (1 << 20), 444 RxCRC = (1 << 19), 445 446 /* ChipCmdBits */ 447 StopReq = 0x80, 448 CmdReset = 0x10, 449 CmdRxEnb = 0x08, 450 CmdTxEnb = 0x04, 451 RxBufEmpty = 0x01, 452 453 /* TXPoll register p.5 */ 454 HPQ = 0x80, /* Poll cmd on the high prio queue */ 455 NPQ = 0x40, /* Poll cmd on the low prio queue */ 456 FSWInt = 0x01, /* Forced software interrupt */ 457 458 /* Cfg9346Bits */ 459 Cfg9346_Lock = 0x00, 460 Cfg9346_Unlock = 0xc0, 461 462 /* rx_mode_bits */ 463 AcceptErr = 0x20, 464 AcceptRunt = 0x10, 465 #define RX_CONFIG_ACCEPT_ERR_MASK 0x30 466 AcceptBroadcast = 0x08, 467 AcceptMulticast = 0x04, 468 AcceptMyPhys = 0x02, 469 AcceptAllPhys = 0x01, 470 #define RX_CONFIG_ACCEPT_OK_MASK 0x0f 471 #define RX_CONFIG_ACCEPT_MASK 0x3f 472 473 /* TxConfigBits */ 474 TxInterFrameGapShift = 24, 475 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ 476 477 /* Config1 register p.24 */ 478 LEDS1 = (1 << 7), 479 LEDS0 = (1 << 6), 480 Speed_down = (1 << 4), 481 MEMMAP = (1 << 3), 482 IOMAP = (1 << 2), 483 VPD = (1 << 1), 484 PMEnable = (1 << 0), /* Power Management Enable */ 485 486 /* Config2 register p. 25 */ 487 ClkReqEn = (1 << 7), /* Clock Request Enable */ 488 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */ 489 PCI_Clock_66MHz = 0x01, 490 PCI_Clock_33MHz = 0x00, 491 492 /* Config3 register p.25 */ 493 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ 494 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ 495 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */ 496 Rdy_to_L23 = (1 << 1), /* L23 Enable */ 497 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */ 498 499 /* Config4 register */ 500 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */ 501 502 /* Config5 register p.27 */ 503 BWF = (1 << 6), /* Accept Broadcast wakeup frame */ 504 MWF = (1 << 5), /* Accept Multicast wakeup frame */ 505 UWF = (1 << 4), /* Accept Unicast wakeup frame */ 506 Spi_en = (1 << 3), 507 LanWake = (1 << 1), /* LanWake enable/disable */ 508 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ 509 ASPM_en = (1 << 0), /* ASPM enable */ 510 511 /* CPlusCmd p.31 */ 512 EnableBist = (1 << 15), // 8168 8101 513 Mac_dbgo_oe = (1 << 14), // 8168 8101 514 EnAnaPLL = (1 << 14), // 8169 515 Normal_mode = (1 << 13), // unused 516 Force_half_dup = (1 << 12), // 8168 8101 517 Force_rxflow_en = (1 << 11), // 8168 8101 518 Force_txflow_en = (1 << 10), // 8168 8101 519 Cxpl_dbg_sel = (1 << 9), // 8168 8101 520 ASF = (1 << 8), // 8168 8101 521 PktCntrDisable = (1 << 7), // 8168 8101 522 Mac_dbgo_sel = 0x001c, // 8168 523 RxVlan = (1 << 6), 524 RxChkSum = (1 << 5), 525 PCIDAC = (1 << 4), 526 PCIMulRW = (1 << 3), 527 #define INTT_MASK GENMASK(1, 0) 528 #define CPCMD_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK) 529 530 /* rtl8169_PHYstatus */ 531 TBI_Enable = 0x80, 532 TxFlowCtrl = 0x40, 533 RxFlowCtrl = 0x20, 534 _1000bpsF = 0x10, 535 _100bps = 0x08, 536 _10bps = 0x04, 537 LinkStatus = 0x02, 538 FullDup = 0x01, 539 540 /* ResetCounterCommand */ 541 CounterReset = 0x1, 542 543 /* DumpCounterCommand */ 544 CounterDump = 0x8, 545 546 /* magic enable v2 */ 547 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */ 548 }; 549 550 enum rtl_desc_bit { 551 /* First doubleword. */ 552 DescOwn = (1 << 31), /* Descriptor is owned by NIC */ 553 RingEnd = (1 << 30), /* End of descriptor ring */ 554 FirstFrag = (1 << 29), /* First segment of a packet */ 555 LastFrag = (1 << 28), /* Final segment of a packet */ 556 }; 557 558 /* Generic case. */ 559 enum rtl_tx_desc_bit { 560 /* First doubleword. */ 561 TD_LSO = (1 << 27), /* Large Send Offload */ 562 #define TD_MSS_MAX 0x07ffu /* MSS value */ 563 564 /* Second doubleword. */ 565 TxVlanTag = (1 << 17), /* Add VLAN tag */ 566 }; 567 568 /* 8169, 8168b and 810x except 8102e. */ 569 enum rtl_tx_desc_bit_0 { 570 /* First doubleword. */ 571 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */ 572 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */ 573 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */ 574 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */ 575 }; 576 577 /* 8102e, 8168c and beyond. */ 578 enum rtl_tx_desc_bit_1 { 579 /* First doubleword. */ 580 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */ 581 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */ 582 #define GTTCPHO_SHIFT 18 583 #define GTTCPHO_MAX 0x7f 584 585 /* Second doubleword. */ 586 #define TCPHO_SHIFT 18 587 #define TCPHO_MAX 0x3ff 588 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */ 589 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */ 590 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */ 591 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */ 592 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */ 593 }; 594 595 enum rtl_rx_desc_bit { 596 /* Rx private */ 597 PID1 = (1 << 18), /* Protocol ID bit 1/2 */ 598 PID0 = (1 << 17), /* Protocol ID bit 0/2 */ 599 600 #define RxProtoUDP (PID1) 601 #define RxProtoTCP (PID0) 602 #define RxProtoIP (PID1 | PID0) 603 #define RxProtoMask RxProtoIP 604 605 IPFail = (1 << 16), /* IP checksum failed */ 606 UDPFail = (1 << 15), /* UDP/IP checksum failed */ 607 TCPFail = (1 << 14), /* TCP/IP checksum failed */ 608 609 #define RxCSFailMask (IPFail | UDPFail | TCPFail) 610 611 RxVlanTag = (1 << 16), /* VLAN tag available */ 612 }; 613 614 #define RTL_GSO_MAX_SIZE_V1 32000 615 #define RTL_GSO_MAX_SEGS_V1 24 616 #define RTL_GSO_MAX_SIZE_V2 64000 617 #define RTL_GSO_MAX_SEGS_V2 64 618 619 struct TxDesc { 620 __le32 opts1; 621 __le32 opts2; 622 __le64 addr; 623 }; 624 625 struct RxDesc { 626 __le32 opts1; 627 __le32 opts2; 628 __le64 addr; 629 }; 630 631 struct ring_info { 632 struct sk_buff *skb; 633 u32 len; 634 }; 635 636 struct rtl8169_counters { 637 __le64 tx_packets; 638 __le64 rx_packets; 639 __le64 tx_errors; 640 __le32 rx_errors; 641 __le16 rx_missed; 642 __le16 align_errors; 643 __le32 tx_one_collision; 644 __le32 tx_multi_collision; 645 __le64 rx_unicast; 646 __le64 rx_broadcast; 647 __le32 rx_multicast; 648 __le16 tx_aborted; 649 __le16 tx_underrun; 650 /* new since RTL8125 */ 651 __le64 tx_octets; 652 __le64 rx_octets; 653 __le64 rx_multicast64; 654 __le64 tx_unicast64; 655 __le64 tx_broadcast64; 656 __le64 tx_multicast64; 657 __le32 tx_pause_on; 658 __le32 tx_pause_off; 659 __le32 tx_pause_all; 660 __le32 tx_deferred; 661 __le32 tx_late_collision; 662 __le32 tx_all_collision; 663 __le32 tx_aborted32; 664 __le32 align_errors32; 665 __le32 rx_frame_too_long; 666 __le32 rx_runt; 667 __le32 rx_pause_on; 668 __le32 rx_pause_off; 669 __le32 rx_pause_all; 670 __le32 rx_unknown_opcode; 671 __le32 rx_mac_error; 672 __le32 tx_underrun32; 673 __le32 rx_mac_missed; 674 __le32 rx_tcam_dropped; 675 __le32 tdu; 676 __le32 rdu; 677 }; 678 679 struct rtl8169_tc_offsets { 680 bool inited; 681 __le64 tx_errors; 682 __le32 tx_multi_collision; 683 __le16 tx_aborted; 684 __le16 rx_missed; 685 }; 686 687 enum rtl_flag { 688 RTL_FLAG_TASK_RESET_PENDING, 689 RTL_FLAG_TASK_TX_TIMEOUT, 690 RTL_FLAG_MAX 691 }; 692 693 enum rtl_dash_type { 694 RTL_DASH_NONE, 695 RTL_DASH_DP, 696 RTL_DASH_EP, 697 RTL_DASH_25_BP, 698 }; 699 700 struct rtl8169_private { 701 void __iomem *mmio_addr; /* memory map physical address */ 702 struct pci_dev *pci_dev; 703 struct net_device *dev; 704 struct phy_device *phydev; 705 struct napi_struct napi; 706 enum mac_version mac_version; 707 enum rtl_dash_type dash_type; 708 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ 709 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ 710 u32 dirty_tx; 711 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */ 712 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ 713 dma_addr_t TxPhyAddr; 714 dma_addr_t RxPhyAddr; 715 struct page *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */ 716 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ 717 u16 cp_cmd; 718 u16 tx_lpi_timer; 719 u32 irq_mask; 720 int irq; 721 struct clk *clk; 722 723 struct { 724 DECLARE_BITMAP(flags, RTL_FLAG_MAX); 725 struct work_struct work; 726 } wk; 727 728 raw_spinlock_t mac_ocp_lock; 729 struct mutex led_lock; /* serialize LED ctrl RMW access */ 730 731 unsigned supports_gmii:1; 732 unsigned aspm_manageable:1; 733 unsigned dash_enabled:1; 734 dma_addr_t counters_phys_addr; 735 struct rtl8169_counters *counters; 736 struct rtl8169_tc_offsets tc_offset; 737 u32 saved_wolopts; 738 739 const char *fw_name; 740 struct rtl_fw *rtl_fw; 741 742 struct r8169_led_classdev *leds; 743 744 u32 ocp_base; 745 }; 746 747 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp); 748 749 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>"); 750 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver"); 751 MODULE_SOFTDEP("pre: realtek"); 752 MODULE_LICENSE("GPL"); 753 MODULE_FIRMWARE(FIRMWARE_8168D_1); 754 MODULE_FIRMWARE(FIRMWARE_8168D_2); 755 MODULE_FIRMWARE(FIRMWARE_8168E_1); 756 MODULE_FIRMWARE(FIRMWARE_8168E_2); 757 MODULE_FIRMWARE(FIRMWARE_8168E_3); 758 MODULE_FIRMWARE(FIRMWARE_8105E_1); 759 MODULE_FIRMWARE(FIRMWARE_8168F_1); 760 MODULE_FIRMWARE(FIRMWARE_8168F_2); 761 MODULE_FIRMWARE(FIRMWARE_8402_1); 762 MODULE_FIRMWARE(FIRMWARE_8411_1); 763 MODULE_FIRMWARE(FIRMWARE_8411_2); 764 MODULE_FIRMWARE(FIRMWARE_8106E_1); 765 MODULE_FIRMWARE(FIRMWARE_8106E_2); 766 MODULE_FIRMWARE(FIRMWARE_8168G_2); 767 MODULE_FIRMWARE(FIRMWARE_8168G_3); 768 MODULE_FIRMWARE(FIRMWARE_8168H_2); 769 MODULE_FIRMWARE(FIRMWARE_8168FP_3); 770 MODULE_FIRMWARE(FIRMWARE_8107E_2); 771 MODULE_FIRMWARE(FIRMWARE_8125A_3); 772 MODULE_FIRMWARE(FIRMWARE_8125B_2); 773 MODULE_FIRMWARE(FIRMWARE_8125D_1); 774 MODULE_FIRMWARE(FIRMWARE_8125D_2); 775 MODULE_FIRMWARE(FIRMWARE_8125BP_2); 776 MODULE_FIRMWARE(FIRMWARE_8126A_2); 777 MODULE_FIRMWARE(FIRMWARE_8126A_3); 778 MODULE_FIRMWARE(FIRMWARE_8127A_1); 779 780 static inline struct device *tp_to_dev(struct rtl8169_private *tp) 781 { 782 return &tp->pci_dev->dev; 783 } 784 785 static void rtl_lock_config_regs(struct rtl8169_private *tp) 786 { 787 RTL_W8(tp, Cfg9346, Cfg9346_Lock); 788 } 789 790 static void rtl_unlock_config_regs(struct rtl8169_private *tp) 791 { 792 RTL_W8(tp, Cfg9346, Cfg9346_Unlock); 793 } 794 795 static void rtl_pci_commit(struct rtl8169_private *tp) 796 { 797 /* Read an arbitrary register to commit a preceding PCI write */ 798 RTL_R8(tp, ChipCmd); 799 } 800 801 static void rtl_mod_config2(struct rtl8169_private *tp, u8 clear, u8 set) 802 { 803 u8 val; 804 805 val = RTL_R8(tp, Config2); 806 RTL_W8(tp, Config2, (val & ~clear) | set); 807 } 808 809 static void rtl_mod_config5(struct rtl8169_private *tp, u8 clear, u8 set) 810 { 811 u8 val; 812 813 val = RTL_R8(tp, Config5); 814 RTL_W8(tp, Config5, (val & ~clear) | set); 815 } 816 817 static void r8169_mod_reg8_cond(struct rtl8169_private *tp, int reg, 818 u8 bits, bool cond) 819 { 820 u8 val, old_val; 821 822 old_val = RTL_R8(tp, reg); 823 if (cond) 824 val = old_val | bits; 825 else 826 val = old_val & ~bits; 827 if (val != old_val) 828 RTL_W8(tp, reg, val); 829 } 830 831 static bool rtl_is_8125(struct rtl8169_private *tp) 832 { 833 return tp->mac_version >= RTL_GIGA_MAC_VER_61; 834 } 835 836 static bool rtl_is_8168evl_up(struct rtl8169_private *tp) 837 { 838 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 839 tp->mac_version != RTL_GIGA_MAC_VER_39 && 840 tp->mac_version <= RTL_GIGA_MAC_VER_52; 841 } 842 843 static bool rtl_supports_eee(struct rtl8169_private *tp) 844 { 845 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 846 tp->mac_version != RTL_GIGA_MAC_VER_37 && 847 tp->mac_version != RTL_GIGA_MAC_VER_39; 848 } 849 850 static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg) 851 { 852 int i; 853 854 for (i = 0; i < ETH_ALEN; i++) 855 mac[i] = RTL_R8(tp, reg + i); 856 } 857 858 struct rtl_cond { 859 bool (*check)(struct rtl8169_private *); 860 const char *msg; 861 }; 862 863 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c, 864 unsigned long usecs, int n, bool high) 865 { 866 int i; 867 868 for (i = 0; i < n; i++) { 869 if (c->check(tp) == high) 870 return true; 871 fsleep(usecs); 872 } 873 874 if (net_ratelimit()) 875 netdev_err(tp->dev, "%s == %d (loop: %d, delay: %lu).\n", 876 c->msg, !high, n, usecs); 877 return false; 878 } 879 880 static bool rtl_loop_wait_high(struct rtl8169_private *tp, 881 const struct rtl_cond *c, 882 unsigned long d, int n) 883 { 884 return rtl_loop_wait(tp, c, d, n, true); 885 } 886 887 static bool rtl_loop_wait_low(struct rtl8169_private *tp, 888 const struct rtl_cond *c, 889 unsigned long d, int n) 890 { 891 return rtl_loop_wait(tp, c, d, n, false); 892 } 893 894 #define DECLARE_RTL_COND(name) \ 895 static bool name ## _check(struct rtl8169_private *); \ 896 \ 897 static const struct rtl_cond name = { \ 898 .check = name ## _check, \ 899 .msg = #name \ 900 }; \ 901 \ 902 static bool name ## _check(struct rtl8169_private *tp) 903 904 int rtl8168_led_mod_ctrl(struct rtl8169_private *tp, u16 mask, u16 val) 905 { 906 struct device *dev = tp_to_dev(tp); 907 int ret; 908 909 ret = pm_runtime_resume_and_get(dev); 910 if (ret < 0) 911 return ret; 912 913 mutex_lock(&tp->led_lock); 914 RTL_W16(tp, LED_CTRL, (RTL_R16(tp, LED_CTRL) & ~mask) | val); 915 mutex_unlock(&tp->led_lock); 916 917 pm_runtime_put_sync(dev); 918 919 return 0; 920 } 921 922 int rtl8168_get_led_mode(struct rtl8169_private *tp) 923 { 924 struct device *dev = tp_to_dev(tp); 925 int ret; 926 927 ret = pm_runtime_resume_and_get(dev); 928 if (ret < 0) 929 return ret; 930 931 ret = RTL_R16(tp, LED_CTRL); 932 933 pm_runtime_put_sync(dev); 934 935 return ret; 936 } 937 938 static int rtl8125_get_led_reg(int index) 939 { 940 static const int led_regs[] = { LEDSEL0, LEDSEL1, LEDSEL2, LEDSEL3 }; 941 942 return led_regs[index]; 943 } 944 945 int rtl8125_set_led_mode(struct rtl8169_private *tp, int index, u16 mode) 946 { 947 int reg = rtl8125_get_led_reg(index); 948 struct device *dev = tp_to_dev(tp); 949 int ret; 950 u16 val; 951 952 ret = pm_runtime_resume_and_get(dev); 953 if (ret < 0) 954 return ret; 955 956 mutex_lock(&tp->led_lock); 957 val = RTL_R16(tp, reg) & ~LEDSEL_MASK_8125; 958 RTL_W16(tp, reg, val | mode); 959 mutex_unlock(&tp->led_lock); 960 961 pm_runtime_put_sync(dev); 962 963 return 0; 964 } 965 966 int rtl8125_get_led_mode(struct rtl8169_private *tp, int index) 967 { 968 int reg = rtl8125_get_led_reg(index); 969 struct device *dev = tp_to_dev(tp); 970 int ret; 971 972 ret = pm_runtime_resume_and_get(dev); 973 if (ret < 0) 974 return ret; 975 976 ret = RTL_R16(tp, reg); 977 978 pm_runtime_put_sync(dev); 979 980 return ret; 981 } 982 983 void r8169_get_led_name(struct rtl8169_private *tp, int idx, 984 char *buf, int buf_len) 985 { 986 struct pci_dev *pdev = tp->pci_dev; 987 char pdom[8], pfun[8]; 988 int domain; 989 990 domain = pci_domain_nr(pdev->bus); 991 if (domain) 992 snprintf(pdom, sizeof(pdom), "P%d", domain); 993 else 994 pdom[0] = '\0'; 995 996 if (pdev->multifunction) 997 snprintf(pfun, sizeof(pfun), "f%d", PCI_FUNC(pdev->devfn)); 998 else 999 pfun[0] = '\0'; 1000 1001 snprintf(buf, buf_len, "en%sp%ds%d%s-%d::lan", pdom, pdev->bus->number, 1002 PCI_SLOT(pdev->devfn), pfun, idx); 1003 } 1004 1005 static void r8168fp_adjust_ocp_cmd(struct rtl8169_private *tp, u32 *cmd, int type) 1006 { 1007 /* based on RTL8168FP_OOBMAC_BASE in vendor driver */ 1008 if (type == ERIAR_OOB && tp->mac_version == RTL_GIGA_MAC_VER_52) 1009 *cmd |= 0xf70 << 18; 1010 } 1011 1012 DECLARE_RTL_COND(rtl_eriar_cond) 1013 { 1014 return RTL_R32(tp, ERIAR) & ERIAR_FLAG; 1015 } 1016 1017 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 1018 u32 val, int type) 1019 { 1020 u32 cmd = ERIAR_WRITE_CMD | type | mask | addr; 1021 1022 if (WARN(addr & 3 || !mask, "addr: 0x%x, mask: 0x%08x\n", addr, mask)) 1023 return; 1024 1025 RTL_W32(tp, ERIDR, val); 1026 r8168fp_adjust_ocp_cmd(tp, &cmd, type); 1027 RTL_W32(tp, ERIAR, cmd); 1028 1029 rtl_loop_wait_low(tp, &rtl_eriar_cond, 100, 100); 1030 } 1031 1032 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 1033 u32 val) 1034 { 1035 _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC); 1036 } 1037 1038 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type) 1039 { 1040 u32 cmd = ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr; 1041 1042 r8168fp_adjust_ocp_cmd(tp, &cmd, type); 1043 RTL_W32(tp, ERIAR, cmd); 1044 1045 return rtl_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ? 1046 RTL_R32(tp, ERIDR) : ~0; 1047 } 1048 1049 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr) 1050 { 1051 return _rtl_eri_read(tp, addr, ERIAR_EXGMAC); 1052 } 1053 1054 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 p, u32 m) 1055 { 1056 u32 val = rtl_eri_read(tp, addr); 1057 1058 rtl_eri_write(tp, addr, ERIAR_MASK_1111, (val & ~m) | p); 1059 } 1060 1061 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 p) 1062 { 1063 rtl_w0w1_eri(tp, addr, p, 0); 1064 } 1065 1066 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 m) 1067 { 1068 rtl_w0w1_eri(tp, addr, 0, m); 1069 } 1070 1071 static bool rtl_ocp_reg_failure(u32 reg) 1072 { 1073 return WARN_ONCE(reg & 0xffff0001, "Invalid ocp reg %x!\n", reg); 1074 } 1075 1076 DECLARE_RTL_COND(rtl_ocp_gphy_cond) 1077 { 1078 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG; 1079 } 1080 1081 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 1082 { 1083 if (rtl_ocp_reg_failure(reg)) 1084 return; 1085 1086 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data); 1087 1088 rtl_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10); 1089 } 1090 1091 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg) 1092 { 1093 if (rtl_ocp_reg_failure(reg)) 1094 return 0; 1095 1096 RTL_W32(tp, GPHY_OCP, reg << 15); 1097 1098 return rtl_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ? 1099 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT; 1100 } 1101 1102 static void __r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 1103 { 1104 if (rtl_ocp_reg_failure(reg)) 1105 return; 1106 1107 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data); 1108 } 1109 1110 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 1111 { 1112 unsigned long flags; 1113 1114 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 1115 __r8168_mac_ocp_write(tp, reg, data); 1116 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 1117 } 1118 1119 static u16 __r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) 1120 { 1121 if (rtl_ocp_reg_failure(reg)) 1122 return 0; 1123 1124 RTL_W32(tp, OCPDR, reg << 15); 1125 1126 return RTL_R32(tp, OCPDR); 1127 } 1128 1129 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) 1130 { 1131 unsigned long flags; 1132 u16 val; 1133 1134 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 1135 val = __r8168_mac_ocp_read(tp, reg); 1136 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 1137 1138 return val; 1139 } 1140 1141 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask, 1142 u16 set) 1143 { 1144 unsigned long flags; 1145 u16 data; 1146 1147 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 1148 data = __r8168_mac_ocp_read(tp, reg); 1149 __r8168_mac_ocp_write(tp, reg, (data & ~mask) | set); 1150 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 1151 } 1152 1153 /* Work around a hw issue with RTL8168g PHY, the quirk disables 1154 * PHY MCU interrupts before PHY power-down. 1155 */ 1156 static void rtl8168g_phy_suspend_quirk(struct rtl8169_private *tp, int value) 1157 { 1158 switch (tp->mac_version) { 1159 case RTL_GIGA_MAC_VER_40: 1160 if (value & BMCR_RESET || !(value & BMCR_PDOWN)) 1161 rtl_eri_set_bits(tp, 0x1a8, 0xfc000000); 1162 else 1163 rtl_eri_clear_bits(tp, 0x1a8, 0xfc000000); 1164 break; 1165 default: 1166 break; 1167 } 1168 }; 1169 1170 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value) 1171 { 1172 if (reg == 0x1f) { 1173 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE; 1174 return; 1175 } 1176 1177 if (tp->ocp_base != OCP_STD_PHY_BASE) 1178 reg -= 0x10; 1179 1180 if (tp->ocp_base == OCP_STD_PHY_BASE && reg == MII_BMCR) 1181 rtl8168g_phy_suspend_quirk(tp, value); 1182 1183 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value); 1184 } 1185 1186 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg) 1187 { 1188 if (reg == 0x1f) 1189 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4; 1190 1191 if (tp->ocp_base != OCP_STD_PHY_BASE) 1192 reg -= 0x10; 1193 1194 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2); 1195 } 1196 1197 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value) 1198 { 1199 if (reg == 0x1f) { 1200 tp->ocp_base = value << 4; 1201 return; 1202 } 1203 1204 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value); 1205 } 1206 1207 static int mac_mcu_read(struct rtl8169_private *tp, int reg) 1208 { 1209 return r8168_mac_ocp_read(tp, tp->ocp_base + reg); 1210 } 1211 1212 DECLARE_RTL_COND(rtl_phyar_cond) 1213 { 1214 return RTL_R32(tp, PHYAR) & 0x80000000; 1215 } 1216 1217 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value) 1218 { 1219 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff)); 1220 1221 rtl_loop_wait_low(tp, &rtl_phyar_cond, 25, 20); 1222 /* 1223 * According to hardware specs a 20us delay is required after write 1224 * complete indication, but before sending next command. 1225 */ 1226 udelay(20); 1227 } 1228 1229 static int r8169_mdio_read(struct rtl8169_private *tp, int reg) 1230 { 1231 int value; 1232 1233 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16); 1234 1235 value = rtl_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ? 1236 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT; 1237 1238 /* 1239 * According to hardware specs a 20us delay is required after read 1240 * complete indication, but before sending next command. 1241 */ 1242 udelay(20); 1243 1244 return value; 1245 } 1246 1247 DECLARE_RTL_COND(rtl_ocpar_cond) 1248 { 1249 return RTL_R32(tp, OCPAR) & OCPAR_FLAG; 1250 } 1251 1252 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000 1253 1254 static void r8168dp_2_mdio_start(struct rtl8169_private *tp) 1255 { 1256 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT); 1257 } 1258 1259 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp) 1260 { 1261 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT); 1262 } 1263 1264 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value) 1265 { 1266 r8168dp_2_mdio_start(tp); 1267 1268 r8169_mdio_write(tp, reg, value); 1269 1270 r8168dp_2_mdio_stop(tp); 1271 } 1272 1273 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg) 1274 { 1275 int value; 1276 1277 /* Work around issue with chip reporting wrong PHY ID */ 1278 if (reg == MII_PHYSID2) 1279 return 0xc912; 1280 1281 r8168dp_2_mdio_start(tp); 1282 1283 value = r8169_mdio_read(tp, reg); 1284 1285 r8168dp_2_mdio_stop(tp); 1286 1287 return value; 1288 } 1289 1290 static void rtl_writephy(struct rtl8169_private *tp, int location, int val) 1291 { 1292 switch (tp->mac_version) { 1293 case RTL_GIGA_MAC_VER_28: 1294 case RTL_GIGA_MAC_VER_31: 1295 r8168dp_2_mdio_write(tp, location, val); 1296 break; 1297 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_LAST: 1298 r8168g_mdio_write(tp, location, val); 1299 break; 1300 default: 1301 r8169_mdio_write(tp, location, val); 1302 break; 1303 } 1304 } 1305 1306 static int rtl_readphy(struct rtl8169_private *tp, int location) 1307 { 1308 switch (tp->mac_version) { 1309 case RTL_GIGA_MAC_VER_28: 1310 case RTL_GIGA_MAC_VER_31: 1311 return r8168dp_2_mdio_read(tp, location); 1312 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_LAST: 1313 return r8168g_mdio_read(tp, location); 1314 default: 1315 return r8169_mdio_read(tp, location); 1316 } 1317 } 1318 1319 DECLARE_RTL_COND(rtl_ephyar_cond) 1320 { 1321 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG; 1322 } 1323 1324 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value) 1325 { 1326 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) | 1327 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1328 1329 rtl_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100); 1330 1331 udelay(10); 1332 } 1333 1334 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr) 1335 { 1336 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1337 1338 return rtl_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ? 1339 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0; 1340 } 1341 1342 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u16 reg) 1343 { 1344 RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff)); 1345 return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ? 1346 RTL_R32(tp, OCPDR) : ~0; 1347 } 1348 1349 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u16 reg) 1350 { 1351 return _rtl_eri_read(tp, reg, ERIAR_OOB); 1352 } 1353 1354 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1355 u32 data) 1356 { 1357 RTL_W32(tp, OCPDR, data); 1358 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); 1359 rtl_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20); 1360 } 1361 1362 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1363 u32 data) 1364 { 1365 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT, 1366 data, ERIAR_OOB); 1367 } 1368 1369 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd) 1370 { 1371 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd); 1372 1373 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001); 1374 } 1375 1376 #define OOB_CMD_RESET 0x00 1377 #define OOB_CMD_DRIVER_START 0x05 1378 #define OOB_CMD_DRIVER_STOP 0x06 1379 1380 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp) 1381 { 1382 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10; 1383 } 1384 1385 DECLARE_RTL_COND(rtl_dp_ocp_read_cond) 1386 { 1387 u16 reg; 1388 1389 reg = rtl8168_get_ocp_reg(tp); 1390 1391 return r8168dp_ocp_read(tp, reg) & 0x00000800; 1392 } 1393 1394 DECLARE_RTL_COND(rtl_ep_ocp_read_cond) 1395 { 1396 return r8168ep_ocp_read(tp, 0x124) & 0x00000001; 1397 } 1398 1399 DECLARE_RTL_COND(rtl_ocp_tx_cond) 1400 { 1401 return RTL_R8(tp, IBISR0) & 0x20; 1402 } 1403 1404 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp) 1405 { 1406 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01); 1407 rtl_loop_wait_high(tp, &rtl_ocp_tx_cond, 50000, 2000); 1408 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20); 1409 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01); 1410 } 1411 1412 static void rtl8168dp_driver_start(struct rtl8169_private *tp) 1413 { 1414 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START); 1415 if (tp->dash_enabled) 1416 rtl_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10000, 10); 1417 } 1418 1419 static void rtl8168ep_driver_start(struct rtl8169_private *tp) 1420 { 1421 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START); 1422 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); 1423 if (tp->dash_enabled) 1424 rtl_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10000, 30); 1425 } 1426 1427 static void rtl8125bp_driver_start(struct rtl8169_private *tp) 1428 { 1429 r8168ep_ocp_write(tp, 0x01, 0x14, OOB_CMD_DRIVER_START); 1430 r8168ep_ocp_write(tp, 0x01, 0x18, 0x00); 1431 r8168ep_ocp_write(tp, 0x01, 0x10, 0x01); 1432 } 1433 1434 static void rtl8168_driver_start(struct rtl8169_private *tp) 1435 { 1436 if (tp->dash_type == RTL_DASH_DP) 1437 rtl8168dp_driver_start(tp); 1438 else if (tp->dash_type == RTL_DASH_25_BP) 1439 rtl8125bp_driver_start(tp); 1440 else 1441 rtl8168ep_driver_start(tp); 1442 } 1443 1444 static void rtl8168dp_driver_stop(struct rtl8169_private *tp) 1445 { 1446 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP); 1447 if (tp->dash_enabled) 1448 rtl_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10000, 10); 1449 } 1450 1451 static void rtl8168ep_driver_stop(struct rtl8169_private *tp) 1452 { 1453 rtl8168ep_stop_cmac(tp); 1454 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP); 1455 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); 1456 if (tp->dash_enabled) 1457 rtl_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10000, 10); 1458 } 1459 1460 static void rtl8125bp_driver_stop(struct rtl8169_private *tp) 1461 { 1462 r8168ep_ocp_write(tp, 0x01, 0x14, OOB_CMD_DRIVER_STOP); 1463 r8168ep_ocp_write(tp, 0x01, 0x18, 0x00); 1464 r8168ep_ocp_write(tp, 0x01, 0x10, 0x01); 1465 } 1466 1467 static void rtl8168_driver_stop(struct rtl8169_private *tp) 1468 { 1469 if (tp->dash_type == RTL_DASH_DP) 1470 rtl8168dp_driver_stop(tp); 1471 else if (tp->dash_type == RTL_DASH_25_BP) 1472 rtl8125bp_driver_stop(tp); 1473 else 1474 rtl8168ep_driver_stop(tp); 1475 } 1476 1477 static bool r8168dp_check_dash(struct rtl8169_private *tp) 1478 { 1479 u16 reg = rtl8168_get_ocp_reg(tp); 1480 1481 return r8168dp_ocp_read(tp, reg) & BIT(15); 1482 } 1483 1484 static bool r8168ep_check_dash(struct rtl8169_private *tp) 1485 { 1486 return r8168ep_ocp_read(tp, 0x128) & BIT(0); 1487 } 1488 1489 static bool rtl_dash_is_enabled(struct rtl8169_private *tp) 1490 { 1491 switch (tp->dash_type) { 1492 case RTL_DASH_DP: 1493 return r8168dp_check_dash(tp); 1494 case RTL_DASH_EP: 1495 case RTL_DASH_25_BP: 1496 return r8168ep_check_dash(tp); 1497 default: 1498 return false; 1499 } 1500 } 1501 1502 static enum rtl_dash_type rtl_get_dash_type(struct rtl8169_private *tp) 1503 { 1504 switch (tp->mac_version) { 1505 case RTL_GIGA_MAC_VER_28: 1506 case RTL_GIGA_MAC_VER_31: 1507 return RTL_DASH_DP; 1508 case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_52: 1509 return RTL_DASH_EP; 1510 case RTL_GIGA_MAC_VER_66: 1511 return RTL_DASH_25_BP; 1512 default: 1513 return RTL_DASH_NONE; 1514 } 1515 } 1516 1517 static void rtl_set_d3_pll_down(struct rtl8169_private *tp, bool enable) 1518 { 1519 if (tp->mac_version >= RTL_GIGA_MAC_VER_25 && 1520 tp->mac_version != RTL_GIGA_MAC_VER_28 && 1521 tp->mac_version != RTL_GIGA_MAC_VER_31 && 1522 tp->mac_version != RTL_GIGA_MAC_VER_38) 1523 r8169_mod_reg8_cond(tp, PMCH, D3_NO_PLL_DOWN, !enable); 1524 } 1525 1526 static void rtl_reset_packet_filter(struct rtl8169_private *tp) 1527 { 1528 rtl_eri_clear_bits(tp, 0xdc, BIT(0)); 1529 rtl_eri_set_bits(tp, 0xdc, BIT(0)); 1530 } 1531 1532 DECLARE_RTL_COND(rtl_efusear_cond) 1533 { 1534 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG; 1535 } 1536 1537 u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr) 1538 { 1539 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT); 1540 1541 return rtl_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ? 1542 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0; 1543 } 1544 1545 static u32 rtl_get_events(struct rtl8169_private *tp) 1546 { 1547 if (rtl_is_8125(tp)) 1548 return RTL_R32(tp, IntrStatus_8125); 1549 else 1550 return RTL_R16(tp, IntrStatus); 1551 } 1552 1553 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits) 1554 { 1555 if (rtl_is_8125(tp)) 1556 RTL_W32(tp, IntrStatus_8125, bits); 1557 else 1558 RTL_W16(tp, IntrStatus, bits); 1559 } 1560 1561 static void rtl_irq_disable(struct rtl8169_private *tp) 1562 { 1563 if (rtl_is_8125(tp)) 1564 RTL_W32(tp, IntrMask_8125, 0); 1565 else 1566 RTL_W16(tp, IntrMask, 0); 1567 } 1568 1569 static void rtl_irq_enable(struct rtl8169_private *tp) 1570 { 1571 if (rtl_is_8125(tp)) 1572 RTL_W32(tp, IntrMask_8125, tp->irq_mask); 1573 else 1574 RTL_W16(tp, IntrMask, tp->irq_mask); 1575 } 1576 1577 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp) 1578 { 1579 rtl_irq_disable(tp); 1580 rtl_ack_events(tp, 0xffffffff); 1581 rtl_pci_commit(tp); 1582 } 1583 1584 static void rtl_link_chg_patch(struct rtl8169_private *tp) 1585 { 1586 struct phy_device *phydev = tp->phydev; 1587 1588 if (tp->mac_version == RTL_GIGA_MAC_VER_34 || 1589 tp->mac_version == RTL_GIGA_MAC_VER_38) { 1590 if (phydev->speed == SPEED_1000) { 1591 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1592 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1593 } else if (phydev->speed == SPEED_100) { 1594 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1595 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1596 } else { 1597 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1598 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1599 } 1600 rtl_reset_packet_filter(tp); 1601 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 || 1602 tp->mac_version == RTL_GIGA_MAC_VER_36) { 1603 if (phydev->speed == SPEED_1000) { 1604 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1605 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1606 } else { 1607 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1608 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1609 } 1610 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) { 1611 if (phydev->speed == SPEED_10) { 1612 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02); 1613 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a); 1614 } else { 1615 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 1616 } 1617 } 1618 } 1619 1620 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) 1621 1622 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1623 { 1624 struct rtl8169_private *tp = netdev_priv(dev); 1625 1626 wol->supported = WAKE_ANY; 1627 wol->wolopts = tp->saved_wolopts; 1628 } 1629 1630 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts) 1631 { 1632 rtl_unlock_config_regs(tp); 1633 1634 if (rtl_is_8168evl_up(tp)) { 1635 if (wolopts & WAKE_MAGIC) 1636 rtl_eri_set_bits(tp, 0x0dc, MagicPacket_v2); 1637 else 1638 rtl_eri_clear_bits(tp, 0x0dc, MagicPacket_v2); 1639 } else if (rtl_is_8125(tp)) { 1640 if (wolopts & WAKE_MAGIC) 1641 r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0)); 1642 else 1643 r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0); 1644 } else { 1645 r8169_mod_reg8_cond(tp, Config3, MagicPacket, 1646 wolopts & WAKE_MAGIC); 1647 } 1648 1649 r8169_mod_reg8_cond(tp, Config3, LinkUp, wolopts & WAKE_PHY); 1650 if (rtl_is_8125(tp)) 1651 r8168_mac_ocp_modify(tp, 0xe0c6, 0x3f, 1652 wolopts & WAKE_PHY ? 0x13 : 0); 1653 r8169_mod_reg8_cond(tp, Config5, UWF, wolopts & WAKE_UCAST); 1654 r8169_mod_reg8_cond(tp, Config5, BWF, wolopts & WAKE_BCAST); 1655 r8169_mod_reg8_cond(tp, Config5, MWF, wolopts & WAKE_MCAST); 1656 r8169_mod_reg8_cond(tp, Config5, LanWake, wolopts); 1657 1658 switch (tp->mac_version) { 1659 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 1660 r8169_mod_reg8_cond(tp, Config1, PMEnable, wolopts); 1661 break; 1662 case RTL_GIGA_MAC_VER_34: 1663 case RTL_GIGA_MAC_VER_37: 1664 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_LAST: 1665 r8169_mod_reg8_cond(tp, Config2, PME_SIGNAL, wolopts); 1666 break; 1667 default: 1668 break; 1669 } 1670 1671 rtl_lock_config_regs(tp); 1672 1673 device_set_wakeup_enable(tp_to_dev(tp), wolopts); 1674 1675 if (!tp->dash_enabled) { 1676 rtl_set_d3_pll_down(tp, !wolopts); 1677 tp->dev->ethtool->wol_enabled = wolopts ? 1 : 0; 1678 } 1679 } 1680 1681 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1682 { 1683 struct rtl8169_private *tp = netdev_priv(dev); 1684 1685 if (wol->wolopts & ~WAKE_ANY) 1686 return -EINVAL; 1687 1688 tp->saved_wolopts = wol->wolopts; 1689 __rtl8169_set_wol(tp, tp->saved_wolopts); 1690 1691 return 0; 1692 } 1693 1694 static void rtl8169_get_drvinfo(struct net_device *dev, 1695 struct ethtool_drvinfo *info) 1696 { 1697 struct rtl8169_private *tp = netdev_priv(dev); 1698 struct rtl_fw *rtl_fw = tp->rtl_fw; 1699 1700 strscpy(info->driver, KBUILD_MODNAME, sizeof(info->driver)); 1701 strscpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info)); 1702 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version)); 1703 if (rtl_fw) 1704 strscpy(info->fw_version, rtl_fw->version, 1705 sizeof(info->fw_version)); 1706 } 1707 1708 static int rtl8169_get_regs_len(struct net_device *dev) 1709 { 1710 return R8169_REGS_SIZE; 1711 } 1712 1713 static netdev_features_t rtl8169_fix_features(struct net_device *dev, 1714 netdev_features_t features) 1715 { 1716 struct rtl8169_private *tp = netdev_priv(dev); 1717 1718 if (dev->mtu > TD_MSS_MAX) 1719 features &= ~NETIF_F_ALL_TSO; 1720 1721 if (dev->mtu > ETH_DATA_LEN && 1722 tp->mac_version > RTL_GIGA_MAC_VER_06) 1723 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_ALL_TSO); 1724 1725 return features; 1726 } 1727 1728 static void rtl_set_rx_config_features(struct rtl8169_private *tp, 1729 netdev_features_t features) 1730 { 1731 u32 rx_config = RTL_R32(tp, RxConfig); 1732 1733 if (features & NETIF_F_RXALL) 1734 rx_config |= RX_CONFIG_ACCEPT_ERR_MASK; 1735 else 1736 rx_config &= ~RX_CONFIG_ACCEPT_ERR_MASK; 1737 1738 if (rtl_is_8125(tp)) { 1739 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1740 rx_config |= RX_VLAN_8125; 1741 else 1742 rx_config &= ~RX_VLAN_8125; 1743 } 1744 1745 RTL_W32(tp, RxConfig, rx_config); 1746 } 1747 1748 static int rtl8169_set_features(struct net_device *dev, 1749 netdev_features_t features) 1750 { 1751 struct rtl8169_private *tp = netdev_priv(dev); 1752 1753 rtl_set_rx_config_features(tp, features); 1754 1755 if (features & NETIF_F_RXCSUM) 1756 tp->cp_cmd |= RxChkSum; 1757 else 1758 tp->cp_cmd &= ~RxChkSum; 1759 1760 if (!rtl_is_8125(tp)) { 1761 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1762 tp->cp_cmd |= RxVlan; 1763 else 1764 tp->cp_cmd &= ~RxVlan; 1765 } 1766 1767 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 1768 rtl_pci_commit(tp); 1769 1770 return 0; 1771 } 1772 1773 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb) 1774 { 1775 return (skb_vlan_tag_present(skb)) ? 1776 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00; 1777 } 1778 1779 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb) 1780 { 1781 u32 opts2 = le32_to_cpu(desc->opts2); 1782 1783 if (opts2 & RxVlanTag) 1784 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff)); 1785 } 1786 1787 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs, 1788 void *p) 1789 { 1790 struct rtl8169_private *tp = netdev_priv(dev); 1791 u32 __iomem *data = tp->mmio_addr; 1792 u32 *dw = p; 1793 int i; 1794 1795 for (i = 0; i < R8169_REGS_SIZE; i += 4) 1796 memcpy_fromio(dw++, data++, 4); 1797 } 1798 1799 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = { 1800 "tx_packets", 1801 "rx_packets", 1802 "tx_errors", 1803 "rx_errors", 1804 "rx_missed", 1805 "align_errors", 1806 "tx_single_collisions", 1807 "tx_multi_collisions", 1808 "unicast", 1809 "broadcast", 1810 "multicast", 1811 "tx_aborted", 1812 "tx_underrun", 1813 }; 1814 1815 static int rtl8169_get_sset_count(struct net_device *dev, int sset) 1816 { 1817 switch (sset) { 1818 case ETH_SS_STATS: 1819 return ARRAY_SIZE(rtl8169_gstrings); 1820 default: 1821 return -EOPNOTSUPP; 1822 } 1823 } 1824 1825 DECLARE_RTL_COND(rtl_counters_cond) 1826 { 1827 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump); 1828 } 1829 1830 static void rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd) 1831 { 1832 u32 cmd = lower_32_bits(tp->counters_phys_addr); 1833 1834 RTL_W32(tp, CounterAddrHigh, upper_32_bits(tp->counters_phys_addr)); 1835 rtl_pci_commit(tp); 1836 RTL_W32(tp, CounterAddrLow, cmd); 1837 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd); 1838 1839 rtl_loop_wait_low(tp, &rtl_counters_cond, 10, 1000); 1840 } 1841 1842 static void rtl8169_update_counters(struct rtl8169_private *tp) 1843 { 1844 u8 val = RTL_R8(tp, ChipCmd); 1845 1846 /* 1847 * Some chips are unable to dump tally counters when the receiver 1848 * is disabled. If 0xff chip may be in a PCI power-save state. 1849 */ 1850 if (val & CmdRxEnb && val != 0xff) 1851 rtl8169_do_counters(tp, CounterDump); 1852 } 1853 1854 static void rtl8169_init_counter_offsets(struct rtl8169_private *tp) 1855 { 1856 struct rtl8169_counters *counters = tp->counters; 1857 1858 /* 1859 * rtl8169_init_counter_offsets is called from rtl_open. On chip 1860 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only 1861 * reset by a power cycle, while the counter values collected by the 1862 * driver are reset at every driver unload/load cycle. 1863 * 1864 * To make sure the HW values returned by @get_stats64 match the SW 1865 * values, we collect the initial values at first open(*) and use them 1866 * as offsets to normalize the values returned by @get_stats64. 1867 * 1868 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one 1869 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only 1870 * set at open time by rtl_hw_start. 1871 */ 1872 1873 if (tp->tc_offset.inited) 1874 return; 1875 1876 if (tp->mac_version >= RTL_GIGA_MAC_VER_19) { 1877 rtl8169_do_counters(tp, CounterReset); 1878 } else { 1879 rtl8169_update_counters(tp); 1880 tp->tc_offset.tx_errors = counters->tx_errors; 1881 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision; 1882 tp->tc_offset.tx_aborted = counters->tx_aborted; 1883 tp->tc_offset.rx_missed = counters->rx_missed; 1884 } 1885 1886 tp->tc_offset.inited = true; 1887 } 1888 1889 static void rtl8169_get_ethtool_stats(struct net_device *dev, 1890 struct ethtool_stats *stats, u64 *data) 1891 { 1892 struct rtl8169_private *tp = netdev_priv(dev); 1893 struct rtl8169_counters *counters; 1894 1895 counters = tp->counters; 1896 rtl8169_update_counters(tp); 1897 1898 data[0] = le64_to_cpu(counters->tx_packets); 1899 data[1] = le64_to_cpu(counters->rx_packets); 1900 data[2] = le64_to_cpu(counters->tx_errors); 1901 data[3] = le32_to_cpu(counters->rx_errors); 1902 data[4] = le16_to_cpu(counters->rx_missed); 1903 data[5] = le16_to_cpu(counters->align_errors); 1904 data[6] = le32_to_cpu(counters->tx_one_collision); 1905 data[7] = le32_to_cpu(counters->tx_multi_collision); 1906 data[8] = le64_to_cpu(counters->rx_unicast); 1907 data[9] = le64_to_cpu(counters->rx_broadcast); 1908 data[10] = le32_to_cpu(counters->rx_multicast); 1909 data[11] = le16_to_cpu(counters->tx_aborted); 1910 data[12] = le16_to_cpu(counters->tx_underrun); 1911 } 1912 1913 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data) 1914 { 1915 switch(stringset) { 1916 case ETH_SS_STATS: 1917 memcpy(data, rtl8169_gstrings, sizeof(rtl8169_gstrings)); 1918 break; 1919 } 1920 } 1921 1922 /* 1923 * Interrupt coalescing 1924 * 1925 * > 1 - the availability of the IntrMitigate (0xe2) register through the 1926 * > 8169, 8168 and 810x line of chipsets 1927 * 1928 * 8169, 8168, and 8136(810x) serial chipsets support it. 1929 * 1930 * > 2 - the Tx timer unit at gigabit speed 1931 * 1932 * The unit of the timer depends on both the speed and the setting of CPlusCmd 1933 * (0xe0) bit 1 and bit 0. 1934 * 1935 * For 8169 1936 * bit[1:0] \ speed 1000M 100M 10M 1937 * 0 0 320ns 2.56us 40.96us 1938 * 0 1 2.56us 20.48us 327.7us 1939 * 1 0 5.12us 40.96us 655.4us 1940 * 1 1 10.24us 81.92us 1.31ms 1941 * 1942 * For the other 1943 * bit[1:0] \ speed 1000M 100M 10M 1944 * 0 0 5us 2.56us 40.96us 1945 * 0 1 40us 20.48us 327.7us 1946 * 1 0 80us 40.96us 655.4us 1947 * 1 1 160us 81.92us 1.31ms 1948 */ 1949 1950 /* rx/tx scale factors for all CPlusCmd[0:1] cases */ 1951 struct rtl_coalesce_info { 1952 u32 speed; 1953 u32 scale_nsecs[4]; 1954 }; 1955 1956 /* produce array with base delay *1, *8, *8*2, *8*2*2 */ 1957 #define COALESCE_DELAY(d) { (d), 8 * (d), 16 * (d), 32 * (d) } 1958 1959 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = { 1960 { SPEED_1000, COALESCE_DELAY(320) }, 1961 { SPEED_100, COALESCE_DELAY(2560) }, 1962 { SPEED_10, COALESCE_DELAY(40960) }, 1963 { 0 }, 1964 }; 1965 1966 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = { 1967 { SPEED_1000, COALESCE_DELAY(5000) }, 1968 { SPEED_100, COALESCE_DELAY(2560) }, 1969 { SPEED_10, COALESCE_DELAY(40960) }, 1970 { 0 }, 1971 }; 1972 #undef COALESCE_DELAY 1973 1974 /* get rx/tx scale vector corresponding to current speed */ 1975 static const struct rtl_coalesce_info * 1976 rtl_coalesce_info(struct rtl8169_private *tp) 1977 { 1978 const struct rtl_coalesce_info *ci; 1979 1980 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 1981 ci = rtl_coalesce_info_8169; 1982 else 1983 ci = rtl_coalesce_info_8168_8136; 1984 1985 /* if speed is unknown assume highest one */ 1986 if (tp->phydev->speed == SPEED_UNKNOWN) 1987 return ci; 1988 1989 for (; ci->speed; ci++) { 1990 if (tp->phydev->speed == ci->speed) 1991 return ci; 1992 } 1993 1994 return ERR_PTR(-ELNRNG); 1995 } 1996 1997 static int rtl_get_coalesce(struct net_device *dev, 1998 struct ethtool_coalesce *ec, 1999 struct kernel_ethtool_coalesce *kernel_coal, 2000 struct netlink_ext_ack *extack) 2001 { 2002 struct rtl8169_private *tp = netdev_priv(dev); 2003 const struct rtl_coalesce_info *ci; 2004 u32 scale, c_us, c_fr; 2005 u16 intrmit; 2006 2007 if (rtl_is_8125(tp)) 2008 return -EOPNOTSUPP; 2009 2010 memset(ec, 0, sizeof(*ec)); 2011 2012 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */ 2013 ci = rtl_coalesce_info(tp); 2014 if (IS_ERR(ci)) 2015 return PTR_ERR(ci); 2016 2017 scale = ci->scale_nsecs[tp->cp_cmd & INTT_MASK]; 2018 2019 intrmit = RTL_R16(tp, IntrMitigate); 2020 2021 c_us = FIELD_GET(RTL_COALESCE_TX_USECS, intrmit); 2022 ec->tx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); 2023 2024 c_fr = FIELD_GET(RTL_COALESCE_TX_FRAMES, intrmit); 2025 /* ethtool_coalesce states usecs and max_frames must not both be 0 */ 2026 ec->tx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; 2027 2028 c_us = FIELD_GET(RTL_COALESCE_RX_USECS, intrmit); 2029 ec->rx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); 2030 2031 c_fr = FIELD_GET(RTL_COALESCE_RX_FRAMES, intrmit); 2032 ec->rx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; 2033 2034 return 0; 2035 } 2036 2037 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, usec) */ 2038 static int rtl_coalesce_choose_scale(struct rtl8169_private *tp, u32 usec, 2039 u16 *cp01) 2040 { 2041 const struct rtl_coalesce_info *ci; 2042 u16 i; 2043 2044 ci = rtl_coalesce_info(tp); 2045 if (IS_ERR(ci)) 2046 return PTR_ERR(ci); 2047 2048 for (i = 0; i < 4; i++) { 2049 if (usec <= ci->scale_nsecs[i] * RTL_COALESCE_T_MAX / 1000U) { 2050 *cp01 = i; 2051 return ci->scale_nsecs[i]; 2052 } 2053 } 2054 2055 return -ERANGE; 2056 } 2057 2058 static int rtl_set_coalesce(struct net_device *dev, 2059 struct ethtool_coalesce *ec, 2060 struct kernel_ethtool_coalesce *kernel_coal, 2061 struct netlink_ext_ack *extack) 2062 { 2063 struct rtl8169_private *tp = netdev_priv(dev); 2064 u32 tx_fr = ec->tx_max_coalesced_frames; 2065 u32 rx_fr = ec->rx_max_coalesced_frames; 2066 u32 coal_usec_max, units; 2067 u16 w = 0, cp01 = 0; 2068 int scale; 2069 2070 if (rtl_is_8125(tp)) 2071 return -EOPNOTSUPP; 2072 2073 if (rx_fr > RTL_COALESCE_FRAME_MAX || tx_fr > RTL_COALESCE_FRAME_MAX) 2074 return -ERANGE; 2075 2076 coal_usec_max = max(ec->rx_coalesce_usecs, ec->tx_coalesce_usecs); 2077 scale = rtl_coalesce_choose_scale(tp, coal_usec_max, &cp01); 2078 if (scale < 0) 2079 return scale; 2080 2081 /* Accept max_frames=1 we returned in rtl_get_coalesce. Accept it 2082 * not only when usecs=0 because of e.g. the following scenario: 2083 * 2084 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX) 2085 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1 2086 * - then user does `ethtool -C eth0 rx-usecs 100` 2087 * 2088 * Since ethtool sends to kernel whole ethtool_coalesce settings, 2089 * if we want to ignore rx_frames then it has to be set to 0. 2090 */ 2091 if (rx_fr == 1) 2092 rx_fr = 0; 2093 if (tx_fr == 1) 2094 tx_fr = 0; 2095 2096 /* HW requires time limit to be set if frame limit is set */ 2097 if ((tx_fr && !ec->tx_coalesce_usecs) || 2098 (rx_fr && !ec->rx_coalesce_usecs)) 2099 return -EINVAL; 2100 2101 w |= FIELD_PREP(RTL_COALESCE_TX_FRAMES, DIV_ROUND_UP(tx_fr, 4)); 2102 w |= FIELD_PREP(RTL_COALESCE_RX_FRAMES, DIV_ROUND_UP(rx_fr, 4)); 2103 2104 units = DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000U, scale); 2105 w |= FIELD_PREP(RTL_COALESCE_TX_USECS, units); 2106 units = DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000U, scale); 2107 w |= FIELD_PREP(RTL_COALESCE_RX_USECS, units); 2108 2109 RTL_W16(tp, IntrMitigate, w); 2110 2111 /* Meaning of PktCntrDisable bit changed from RTL8168e-vl */ 2112 if (rtl_is_8168evl_up(tp)) { 2113 if (!rx_fr && !tx_fr) 2114 /* disable packet counter */ 2115 tp->cp_cmd |= PktCntrDisable; 2116 else 2117 tp->cp_cmd &= ~PktCntrDisable; 2118 } 2119 2120 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01; 2121 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 2122 rtl_pci_commit(tp); 2123 2124 return 0; 2125 } 2126 2127 static void rtl_set_eee_txidle_timer(struct rtl8169_private *tp) 2128 { 2129 unsigned int timer_val = READ_ONCE(tp->dev->mtu) + ETH_HLEN + 0x20; 2130 2131 switch (tp->mac_version) { 2132 case RTL_GIGA_MAC_VER_46: 2133 case RTL_GIGA_MAC_VER_48: 2134 tp->tx_lpi_timer = timer_val; 2135 r8168_mac_ocp_write(tp, 0xe048, timer_val); 2136 break; 2137 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_LAST: 2138 tp->tx_lpi_timer = timer_val; 2139 RTL_W16(tp, EEE_TXIDLE_TIMER_8125, timer_val); 2140 break; 2141 default: 2142 break; 2143 } 2144 } 2145 2146 static unsigned int r8169_get_tx_lpi_timer_us(struct rtl8169_private *tp) 2147 { 2148 unsigned int speed = tp->phydev->speed; 2149 unsigned int timer = tp->tx_lpi_timer; 2150 2151 if (!timer || speed == SPEED_UNKNOWN) 2152 return 0; 2153 2154 /* tx_lpi_timer value is in bytes */ 2155 return DIV_ROUND_CLOSEST(timer * BITS_PER_BYTE, speed); 2156 } 2157 2158 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_keee *data) 2159 { 2160 struct rtl8169_private *tp = netdev_priv(dev); 2161 int ret; 2162 2163 if (!rtl_supports_eee(tp)) 2164 return -EOPNOTSUPP; 2165 2166 ret = phy_ethtool_get_eee(tp->phydev, data); 2167 if (ret) 2168 return ret; 2169 2170 data->tx_lpi_timer = r8169_get_tx_lpi_timer_us(tp); 2171 2172 return 0; 2173 } 2174 2175 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_keee *data) 2176 { 2177 struct rtl8169_private *tp = netdev_priv(dev); 2178 2179 if (!rtl_supports_eee(tp)) 2180 return -EOPNOTSUPP; 2181 2182 return phy_ethtool_set_eee(tp->phydev, data); 2183 } 2184 2185 static void rtl8169_get_ringparam(struct net_device *dev, 2186 struct ethtool_ringparam *data, 2187 struct kernel_ethtool_ringparam *kernel_data, 2188 struct netlink_ext_ack *extack) 2189 { 2190 data->rx_max_pending = NUM_RX_DESC; 2191 data->rx_pending = NUM_RX_DESC; 2192 data->tx_max_pending = NUM_TX_DESC; 2193 data->tx_pending = NUM_TX_DESC; 2194 } 2195 2196 static void rtl8169_get_pause_stats(struct net_device *dev, 2197 struct ethtool_pause_stats *pause_stats) 2198 { 2199 struct rtl8169_private *tp = netdev_priv(dev); 2200 2201 if (!rtl_is_8125(tp)) 2202 return; 2203 2204 rtl8169_update_counters(tp); 2205 pause_stats->tx_pause_frames = le32_to_cpu(tp->counters->tx_pause_on); 2206 pause_stats->rx_pause_frames = le32_to_cpu(tp->counters->rx_pause_on); 2207 } 2208 2209 static void rtl8169_get_pauseparam(struct net_device *dev, 2210 struct ethtool_pauseparam *data) 2211 { 2212 struct rtl8169_private *tp = netdev_priv(dev); 2213 bool tx_pause, rx_pause; 2214 2215 phy_get_pause(tp->phydev, &tx_pause, &rx_pause); 2216 2217 data->autoneg = tp->phydev->autoneg; 2218 data->tx_pause = tx_pause ? 1 : 0; 2219 data->rx_pause = rx_pause ? 1 : 0; 2220 } 2221 2222 static int rtl8169_set_pauseparam(struct net_device *dev, 2223 struct ethtool_pauseparam *data) 2224 { 2225 struct rtl8169_private *tp = netdev_priv(dev); 2226 2227 if (dev->mtu > ETH_DATA_LEN) 2228 return -EOPNOTSUPP; 2229 2230 phy_set_asym_pause(tp->phydev, data->rx_pause, data->tx_pause); 2231 2232 return 0; 2233 } 2234 2235 static void rtl8169_get_eth_mac_stats(struct net_device *dev, 2236 struct ethtool_eth_mac_stats *mac_stats) 2237 { 2238 struct rtl8169_private *tp = netdev_priv(dev); 2239 2240 rtl8169_update_counters(tp); 2241 2242 mac_stats->FramesTransmittedOK = 2243 le64_to_cpu(tp->counters->tx_packets); 2244 mac_stats->SingleCollisionFrames = 2245 le32_to_cpu(tp->counters->tx_one_collision); 2246 mac_stats->MultipleCollisionFrames = 2247 le32_to_cpu(tp->counters->tx_multi_collision); 2248 mac_stats->FramesReceivedOK = 2249 le64_to_cpu(tp->counters->rx_packets); 2250 mac_stats->AlignmentErrors = 2251 le16_to_cpu(tp->counters->align_errors); 2252 mac_stats->FramesLostDueToIntMACXmitError = 2253 le64_to_cpu(tp->counters->tx_errors); 2254 mac_stats->BroadcastFramesReceivedOK = 2255 le64_to_cpu(tp->counters->rx_broadcast); 2256 mac_stats->MulticastFramesReceivedOK = 2257 le32_to_cpu(tp->counters->rx_multicast); 2258 2259 if (!rtl_is_8125(tp)) 2260 return; 2261 2262 mac_stats->AlignmentErrors = 2263 le32_to_cpu(tp->counters->align_errors32); 2264 mac_stats->OctetsTransmittedOK = 2265 le64_to_cpu(tp->counters->tx_octets); 2266 mac_stats->LateCollisions = 2267 le32_to_cpu(tp->counters->tx_late_collision); 2268 mac_stats->FramesAbortedDueToXSColls = 2269 le32_to_cpu(tp->counters->tx_aborted32); 2270 mac_stats->OctetsReceivedOK = 2271 le64_to_cpu(tp->counters->rx_octets); 2272 mac_stats->FramesLostDueToIntMACRcvError = 2273 le32_to_cpu(tp->counters->rx_mac_error); 2274 mac_stats->MulticastFramesXmittedOK = 2275 le64_to_cpu(tp->counters->tx_multicast64); 2276 mac_stats->BroadcastFramesXmittedOK = 2277 le64_to_cpu(tp->counters->tx_broadcast64); 2278 mac_stats->MulticastFramesReceivedOK = 2279 le64_to_cpu(tp->counters->rx_multicast64); 2280 mac_stats->FrameTooLongErrors = 2281 le32_to_cpu(tp->counters->rx_frame_too_long); 2282 } 2283 2284 static void rtl8169_get_eth_ctrl_stats(struct net_device *dev, 2285 struct ethtool_eth_ctrl_stats *ctrl_stats) 2286 { 2287 struct rtl8169_private *tp = netdev_priv(dev); 2288 2289 if (!rtl_is_8125(tp)) 2290 return; 2291 2292 rtl8169_update_counters(tp); 2293 2294 ctrl_stats->UnsupportedOpcodesReceived = 2295 le32_to_cpu(tp->counters->rx_unknown_opcode); 2296 } 2297 2298 static const struct ethtool_ops rtl8169_ethtool_ops = { 2299 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 2300 ETHTOOL_COALESCE_MAX_FRAMES, 2301 .get_drvinfo = rtl8169_get_drvinfo, 2302 .get_regs_len = rtl8169_get_regs_len, 2303 .get_link = ethtool_op_get_link, 2304 .get_coalesce = rtl_get_coalesce, 2305 .set_coalesce = rtl_set_coalesce, 2306 .get_regs = rtl8169_get_regs, 2307 .get_wol = rtl8169_get_wol, 2308 .set_wol = rtl8169_set_wol, 2309 .get_strings = rtl8169_get_strings, 2310 .get_sset_count = rtl8169_get_sset_count, 2311 .get_ethtool_stats = rtl8169_get_ethtool_stats, 2312 .get_ts_info = ethtool_op_get_ts_info, 2313 .nway_reset = phy_ethtool_nway_reset, 2314 .get_eee = rtl8169_get_eee, 2315 .set_eee = rtl8169_set_eee, 2316 .get_link_ksettings = phy_ethtool_get_link_ksettings, 2317 .set_link_ksettings = phy_ethtool_set_link_ksettings, 2318 .get_ringparam = rtl8169_get_ringparam, 2319 .get_pause_stats = rtl8169_get_pause_stats, 2320 .get_pauseparam = rtl8169_get_pauseparam, 2321 .set_pauseparam = rtl8169_set_pauseparam, 2322 .get_eth_mac_stats = rtl8169_get_eth_mac_stats, 2323 .get_eth_ctrl_stats = rtl8169_get_eth_ctrl_stats, 2324 }; 2325 2326 static const struct rtl_chip_info *rtl8169_get_chip_version(u16 xid, bool gmii) 2327 { 2328 /* Chips combining a 1Gbps MAC with a 100Mbps PHY */ 2329 static const struct rtl_chip_info rtl8106eus_info = { 2330 .mac_version = RTL_GIGA_MAC_VER_43, 2331 .name = "RTL8106eus", 2332 .fw_name = FIRMWARE_8106E_2, 2333 }; 2334 static const struct rtl_chip_info rtl8107e_info = { 2335 .mac_version = RTL_GIGA_MAC_VER_48, 2336 .name = "RTL8107e", 2337 .fw_name = FIRMWARE_8107E_2, 2338 }; 2339 const struct rtl_chip_info *p = rtl_chip_infos; 2340 2341 while ((xid & p->mask) != p->val) 2342 p++; 2343 2344 if (p->mac_version == RTL_GIGA_MAC_VER_42 && !gmii) 2345 return &rtl8106eus_info; 2346 if (p->mac_version == RTL_GIGA_MAC_VER_46 && !gmii) 2347 return &rtl8107e_info; 2348 2349 return p; 2350 } 2351 2352 static void rtl_release_firmware(struct rtl8169_private *tp) 2353 { 2354 if (tp->rtl_fw) { 2355 rtl_fw_release_firmware(tp->rtl_fw); 2356 kfree(tp->rtl_fw); 2357 tp->rtl_fw = NULL; 2358 } 2359 } 2360 2361 void r8169_apply_firmware(struct rtl8169_private *tp) 2362 { 2363 int val; 2364 2365 /* TODO: release firmware if rtl_fw_write_firmware signals failure. */ 2366 if (tp->rtl_fw) { 2367 rtl_fw_write_firmware(tp, tp->rtl_fw); 2368 /* At least one firmware doesn't reset tp->ocp_base. */ 2369 tp->ocp_base = OCP_STD_PHY_BASE; 2370 2371 /* PHY soft reset may still be in progress */ 2372 phy_read_poll_timeout(tp->phydev, MII_BMCR, val, 2373 !(val & BMCR_RESET), 2374 50000, 600000, true); 2375 } 2376 } 2377 2378 static void rtl8168_config_eee_mac(struct rtl8169_private *tp) 2379 { 2380 /* Adjust EEE LED frequency */ 2381 if (tp->mac_version != RTL_GIGA_MAC_VER_38) 2382 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07); 2383 2384 rtl_eri_set_bits(tp, 0x1b0, 0x0003); 2385 } 2386 2387 static void rtl8125a_config_eee_mac(struct rtl8169_private *tp) 2388 { 2389 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); 2390 r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1)); 2391 } 2392 2393 static void rtl8125b_config_eee_mac(struct rtl8169_private *tp) 2394 { 2395 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); 2396 } 2397 2398 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, const u8 *addr) 2399 { 2400 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, get_unaligned_le32(addr)); 2401 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, get_unaligned_le16(addr + 4)); 2402 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, get_unaligned_le16(addr) << 16); 2403 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, get_unaligned_le32(addr + 2)); 2404 } 2405 2406 u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp) 2407 { 2408 u16 data1, data2, ioffset; 2409 2410 r8168_mac_ocp_write(tp, 0xdd02, 0x807d); 2411 data1 = r8168_mac_ocp_read(tp, 0xdd02); 2412 data2 = r8168_mac_ocp_read(tp, 0xdd00); 2413 2414 ioffset = (data2 >> 1) & 0x7ff8; 2415 ioffset |= data2 & 0x0007; 2416 if (data1 & BIT(7)) 2417 ioffset |= BIT(15); 2418 2419 return ioffset; 2420 } 2421 2422 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag) 2423 { 2424 set_bit(flag, tp->wk.flags); 2425 if (!schedule_work(&tp->wk.work)) 2426 clear_bit(flag, tp->wk.flags); 2427 } 2428 2429 static void rtl8169_init_phy(struct rtl8169_private *tp) 2430 { 2431 r8169_hw_phy_config(tp, tp->phydev, tp->mac_version); 2432 2433 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) { 2434 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); 2435 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); 2436 /* set undocumented MAC Reg C+CR Offset 0x82h */ 2437 RTL_W8(tp, 0x82, 0x01); 2438 } 2439 2440 if (tp->mac_version == RTL_GIGA_MAC_VER_05 && 2441 tp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_GIGABYTE && 2442 tp->pci_dev->subsystem_device == 0xe000) 2443 phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b); 2444 2445 /* We may have called phy_speed_down before */ 2446 phy_speed_up(tp->phydev); 2447 2448 genphy_soft_reset(tp->phydev); 2449 } 2450 2451 static void rtl_rar_set(struct rtl8169_private *tp, const u8 *addr) 2452 { 2453 rtl_unlock_config_regs(tp); 2454 2455 RTL_W32(tp, MAC4, get_unaligned_le16(addr + 4)); 2456 rtl_pci_commit(tp); 2457 2458 RTL_W32(tp, MAC0, get_unaligned_le32(addr)); 2459 rtl_pci_commit(tp); 2460 2461 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 2462 rtl_rar_exgmac_set(tp, addr); 2463 2464 rtl_lock_config_regs(tp); 2465 } 2466 2467 static int rtl_set_mac_address(struct net_device *dev, void *p) 2468 { 2469 struct rtl8169_private *tp = netdev_priv(dev); 2470 int ret; 2471 2472 ret = eth_mac_addr(dev, p); 2473 if (ret) 2474 return ret; 2475 2476 rtl_rar_set(tp, dev->dev_addr); 2477 2478 return 0; 2479 } 2480 2481 static void rtl_init_rxcfg(struct rtl8169_private *tp) 2482 { 2483 switch (tp->mac_version) { 2484 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 2485 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 2486 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST); 2487 break; 2488 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 2489 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36: 2490 case RTL_GIGA_MAC_VER_38: 2491 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST); 2492 break; 2493 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_52: 2494 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF); 2495 break; 2496 case RTL_GIGA_MAC_VER_61: 2497 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST); 2498 break; 2499 case RTL_GIGA_MAC_VER_63 ... RTL_GIGA_MAC_VER_LAST: 2500 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST | 2501 RX_PAUSE_SLOT_ON); 2502 break; 2503 default: 2504 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST); 2505 break; 2506 } 2507 } 2508 2509 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp) 2510 { 2511 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0; 2512 } 2513 2514 static void rtl_jumbo_config(struct rtl8169_private *tp) 2515 { 2516 bool jumbo = tp->dev->mtu > ETH_DATA_LEN; 2517 int readrq = 4096; 2518 2519 if (jumbo && tp->mac_version >= RTL_GIGA_MAC_VER_17 && 2520 tp->mac_version <= RTL_GIGA_MAC_VER_26) 2521 readrq = 512; 2522 2523 rtl_unlock_config_regs(tp); 2524 switch (tp->mac_version) { 2525 case RTL_GIGA_MAC_VER_17: 2526 r8169_mod_reg8_cond(tp, Config4, BIT(0), jumbo); 2527 break; 2528 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26: 2529 r8169_mod_reg8_cond(tp, Config3, Jumbo_En0, jumbo); 2530 r8169_mod_reg8_cond(tp, Config4, Jumbo_En1, jumbo); 2531 break; 2532 case RTL_GIGA_MAC_VER_28: 2533 r8169_mod_reg8_cond(tp, Config3, Jumbo_En0, jumbo); 2534 break; 2535 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33: 2536 RTL_W8(tp, MaxTxPacketSize, jumbo ? 0x24 : 0x3f); 2537 r8169_mod_reg8_cond(tp, Config3, Jumbo_En0, jumbo); 2538 r8169_mod_reg8_cond(tp, Config4, BIT(0), jumbo); 2539 break; 2540 default: 2541 break; 2542 } 2543 rtl_lock_config_regs(tp); 2544 2545 if (pci_is_pcie(tp->pci_dev) && tp->supports_gmii) 2546 pcie_set_readrq(tp->pci_dev, readrq); 2547 2548 /* Chip doesn't support pause in jumbo mode */ 2549 if (jumbo) { 2550 linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT, 2551 tp->phydev->advertising); 2552 linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, 2553 tp->phydev->advertising); 2554 phy_start_aneg(tp->phydev); 2555 } 2556 } 2557 2558 DECLARE_RTL_COND(rtl_chipcmd_cond) 2559 { 2560 return RTL_R8(tp, ChipCmd) & CmdReset; 2561 } 2562 2563 static void rtl_hw_reset(struct rtl8169_private *tp) 2564 { 2565 RTL_W8(tp, ChipCmd, CmdReset); 2566 2567 rtl_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100); 2568 } 2569 2570 static void rtl_request_firmware(struct rtl8169_private *tp) 2571 { 2572 struct rtl_fw *rtl_fw; 2573 2574 /* firmware loaded already or no firmware available */ 2575 if (tp->rtl_fw || !tp->fw_name) 2576 return; 2577 2578 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL); 2579 if (!rtl_fw) 2580 return; 2581 2582 rtl_fw->phy_write = rtl_writephy; 2583 rtl_fw->phy_read = rtl_readphy; 2584 rtl_fw->mac_mcu_write = mac_mcu_write; 2585 rtl_fw->mac_mcu_read = mac_mcu_read; 2586 rtl_fw->fw_name = tp->fw_name; 2587 rtl_fw->dev = tp_to_dev(tp); 2588 2589 if (rtl_fw_request_firmware(rtl_fw)) 2590 kfree(rtl_fw); 2591 else 2592 tp->rtl_fw = rtl_fw; 2593 } 2594 2595 static void rtl_rx_close(struct rtl8169_private *tp) 2596 { 2597 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK); 2598 } 2599 2600 DECLARE_RTL_COND(rtl_npq_cond) 2601 { 2602 return RTL_R8(tp, TxPoll) & NPQ; 2603 } 2604 2605 DECLARE_RTL_COND(rtl_txcfg_empty_cond) 2606 { 2607 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY; 2608 } 2609 2610 DECLARE_RTL_COND(rtl_rxtx_empty_cond) 2611 { 2612 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY; 2613 } 2614 2615 DECLARE_RTL_COND(rtl_rxtx_empty_cond_2) 2616 { 2617 /* IntrMitigate has new functionality on RTL8125 */ 2618 return (RTL_R16(tp, IntrMitigate) & 0x0103) == 0x0103; 2619 } 2620 2621 static void rtl_wait_txrx_fifo_empty(struct rtl8169_private *tp) 2622 { 2623 switch (tp->mac_version) { 2624 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_52: 2625 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42); 2626 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2627 break; 2628 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_61: 2629 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2630 break; 2631 case RTL_GIGA_MAC_VER_63 ... RTL_GIGA_MAC_VER_LAST: 2632 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 2633 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2634 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond_2, 100, 42); 2635 break; 2636 default: 2637 break; 2638 } 2639 } 2640 2641 static void rtl_disable_rxdvgate(struct rtl8169_private *tp) 2642 { 2643 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 2644 } 2645 2646 static void rtl_enable_rxdvgate(struct rtl8169_private *tp) 2647 { 2648 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN); 2649 fsleep(2000); 2650 rtl_wait_txrx_fifo_empty(tp); 2651 } 2652 2653 static void rtl_wol_enable_rx(struct rtl8169_private *tp) 2654 { 2655 if (tp->mac_version >= RTL_GIGA_MAC_VER_25) 2656 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) | 2657 AcceptBroadcast | AcceptMulticast | AcceptMyPhys); 2658 2659 if (tp->mac_version >= RTL_GIGA_MAC_VER_40) 2660 rtl_disable_rxdvgate(tp); 2661 } 2662 2663 static void rtl_prepare_power_down(struct rtl8169_private *tp) 2664 { 2665 if (tp->dash_enabled) 2666 return; 2667 2668 if (tp->mac_version == RTL_GIGA_MAC_VER_32 || 2669 tp->mac_version == RTL_GIGA_MAC_VER_33) 2670 rtl_ephy_write(tp, 0x19, 0xff64); 2671 2672 if (device_may_wakeup(tp_to_dev(tp))) { 2673 phy_speed_down(tp->phydev, false); 2674 rtl_wol_enable_rx(tp); 2675 } 2676 } 2677 2678 static void rtl_set_tx_config_registers(struct rtl8169_private *tp) 2679 { 2680 u32 val = TX_DMA_BURST << TxDMAShift | 2681 InterFrameGap << TxInterFrameGapShift; 2682 2683 if (rtl_is_8168evl_up(tp)) 2684 val |= TXCFG_AUTO_FIFO; 2685 2686 RTL_W32(tp, TxConfig, val); 2687 } 2688 2689 static void rtl_set_rx_max_size(struct rtl8169_private *tp) 2690 { 2691 /* Low hurts. Let's disable the filtering. */ 2692 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1); 2693 } 2694 2695 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp) 2696 { 2697 /* 2698 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh 2699 * register to be written before TxDescAddrLow to work. 2700 * Switching from MMIO to I/O access fixes the issue as well. 2701 */ 2702 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32); 2703 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32)); 2704 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32); 2705 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32)); 2706 } 2707 2708 static void rtl8169_set_magic_reg(struct rtl8169_private *tp) 2709 { 2710 u32 val; 2711 2712 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 2713 val = 0x000fff00; 2714 else if (tp->mac_version == RTL_GIGA_MAC_VER_06) 2715 val = 0x00ffff00; 2716 else 2717 return; 2718 2719 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz) 2720 val |= 0xff; 2721 2722 RTL_W32(tp, 0x7c, val); 2723 } 2724 2725 static void rtl_set_rx_mode(struct net_device *dev) 2726 { 2727 u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast; 2728 /* Multicast hash filter */ 2729 u32 mc_filter[2] = { 0xffffffff, 0xffffffff }; 2730 struct rtl8169_private *tp = netdev_priv(dev); 2731 u32 tmp; 2732 2733 if (dev->flags & IFF_PROMISC) { 2734 rx_mode |= AcceptAllPhys; 2735 } else if (!(dev->flags & IFF_MULTICAST)) { 2736 rx_mode &= ~AcceptMulticast; 2737 } else if (dev->flags & IFF_ALLMULTI || 2738 tp->mac_version == RTL_GIGA_MAC_VER_35) { 2739 /* accept all multicasts */ 2740 } else if (netdev_mc_empty(dev)) { 2741 rx_mode &= ~AcceptMulticast; 2742 } else { 2743 struct netdev_hw_addr *ha; 2744 2745 mc_filter[1] = mc_filter[0] = 0; 2746 netdev_for_each_mc_addr(ha, dev) { 2747 u32 bit_nr = eth_hw_addr_crc(ha) >> 26; 2748 mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31); 2749 } 2750 2751 if (tp->mac_version > RTL_GIGA_MAC_VER_06) { 2752 tmp = mc_filter[0]; 2753 mc_filter[0] = swab32(mc_filter[1]); 2754 mc_filter[1] = swab32(tmp); 2755 } 2756 } 2757 2758 RTL_W32(tp, MAR0 + 4, mc_filter[1]); 2759 RTL_W32(tp, MAR0 + 0, mc_filter[0]); 2760 2761 tmp = RTL_R32(tp, RxConfig); 2762 RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode); 2763 } 2764 2765 DECLARE_RTL_COND(rtl_csiar_cond) 2766 { 2767 return RTL_R32(tp, CSIAR) & CSIAR_FLAG; 2768 } 2769 2770 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value) 2771 { 2772 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2773 2774 RTL_W32(tp, CSIDR, value); 2775 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | 2776 CSIAR_BYTE_ENABLE | func << 16); 2777 2778 rtl_loop_wait_low(tp, &rtl_csiar_cond, 10, 100); 2779 } 2780 2781 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr) 2782 { 2783 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2784 2785 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 | 2786 CSIAR_BYTE_ENABLE); 2787 2788 return rtl_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ? 2789 RTL_R32(tp, CSIDR) : ~0; 2790 } 2791 2792 static void rtl_csi_mod(struct rtl8169_private *tp, int addr, 2793 u32 mask, u32 set) 2794 { 2795 u32 val; 2796 2797 WARN(addr % 4, "Invalid CSI address %#x\n", addr); 2798 2799 netdev_notice_once(tp->dev, 2800 "No native access to PCI extended config space, falling back to CSI\n"); 2801 2802 val = rtl_csi_read(tp, addr); 2803 rtl_csi_write(tp, addr, (val & ~mask) | set); 2804 } 2805 2806 static void rtl_disable_zrxdc_timeout(struct rtl8169_private *tp) 2807 { 2808 struct pci_dev *pdev = tp->pci_dev; 2809 int rc; 2810 u8 val; 2811 2812 #define RTL_GEN3_RELATED_OFF 0x0890 2813 #define RTL_GEN3_ZRXDC_NONCOMPL 0x1 2814 if (pdev->cfg_size > RTL_GEN3_RELATED_OFF) { 2815 rc = pci_read_config_byte(pdev, RTL_GEN3_RELATED_OFF, &val); 2816 if (rc == PCIBIOS_SUCCESSFUL) { 2817 val &= ~RTL_GEN3_ZRXDC_NONCOMPL; 2818 rc = pci_write_config_byte(pdev, RTL_GEN3_RELATED_OFF, 2819 val); 2820 if (rc == PCIBIOS_SUCCESSFUL) 2821 return; 2822 } 2823 } 2824 2825 rtl_csi_mod(tp, RTL_GEN3_RELATED_OFF, RTL_GEN3_ZRXDC_NONCOMPL, 0); 2826 } 2827 2828 static void rtl_set_aspm_entry_latency(struct rtl8169_private *tp, u8 val) 2829 { 2830 struct pci_dev *pdev = tp->pci_dev; 2831 2832 /* According to Realtek the value at config space address 0x070f 2833 * controls the L0s/L1 entrance latency. We try standard ECAM access 2834 * first and if it fails fall back to CSI. 2835 * bit 0..2: L0: 0 = 1us, 1 = 2us .. 6 = 7us, 7 = 7us (no typo) 2836 * bit 3..5: L1: 0 = 1us, 1 = 2us .. 6 = 64us, 7 = 64us 2837 */ 2838 if (pdev->cfg_size > 0x070f && 2839 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL) 2840 return; 2841 2842 rtl_csi_mod(tp, 0x070c, 0xff000000, val << 24); 2843 } 2844 2845 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp) 2846 { 2847 /* L0 7us, L1 16us */ 2848 rtl_set_aspm_entry_latency(tp, 0x27); 2849 } 2850 2851 struct ephy_info { 2852 unsigned int offset; 2853 u16 mask; 2854 u16 bits; 2855 }; 2856 2857 static void __rtl_ephy_init(struct rtl8169_private *tp, 2858 const struct ephy_info *e, int len) 2859 { 2860 u16 w; 2861 2862 while (len-- > 0) { 2863 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits; 2864 rtl_ephy_write(tp, e->offset, w); 2865 e++; 2866 } 2867 } 2868 2869 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a)) 2870 2871 static void rtl_disable_clock_request(struct rtl8169_private *tp) 2872 { 2873 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL, 2874 PCI_EXP_LNKCTL_CLKREQ_EN); 2875 } 2876 2877 static void rtl_enable_clock_request(struct rtl8169_private *tp) 2878 { 2879 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL, 2880 PCI_EXP_LNKCTL_CLKREQ_EN); 2881 } 2882 2883 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp) 2884 { 2885 /* work around an issue when PCI reset occurs during L2/L3 state */ 2886 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23); 2887 } 2888 2889 static void rtl_enable_exit_l1(struct rtl8169_private *tp) 2890 { 2891 /* Bits control which events trigger ASPM L1 exit: 2892 * Bit 12: rxdv 2893 * Bit 11: ltr_msg 2894 * Bit 10: txdma_poll 2895 * Bit 9: xadm 2896 * Bit 8: pktavi 2897 * Bit 7: txpla 2898 */ 2899 switch (tp->mac_version) { 2900 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36: 2901 rtl_eri_set_bits(tp, 0xd4, 0x1f00); 2902 break; 2903 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_38: 2904 rtl_eri_set_bits(tp, 0xd4, 0x0c00); 2905 break; 2906 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_LAST: 2907 r8168_mac_ocp_modify(tp, 0xc0ac, 0, 0x1f80); 2908 break; 2909 default: 2910 break; 2911 } 2912 } 2913 2914 static void rtl_disable_exit_l1(struct rtl8169_private *tp) 2915 { 2916 switch (tp->mac_version) { 2917 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: 2918 rtl_eri_clear_bits(tp, 0xd4, 0x1f00); 2919 break; 2920 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_LAST: 2921 r8168_mac_ocp_modify(tp, 0xc0ac, 0x1f80, 0); 2922 break; 2923 default: 2924 break; 2925 } 2926 } 2927 2928 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable) 2929 { 2930 u8 val8; 2931 2932 if (tp->mac_version < RTL_GIGA_MAC_VER_32) 2933 return; 2934 2935 /* Don't enable ASPM in the chip if OS can't control ASPM */ 2936 if (enable && tp->aspm_manageable) { 2937 /* On these chip versions ASPM can even harm 2938 * bus communication of other PCI devices. 2939 */ 2940 if (tp->mac_version == RTL_GIGA_MAC_VER_42 || 2941 tp->mac_version == RTL_GIGA_MAC_VER_43) 2942 return; 2943 2944 rtl_mod_config5(tp, 0, ASPM_en); 2945 switch (tp->mac_version) { 2946 case RTL_GIGA_MAC_VER_70: 2947 case RTL_GIGA_MAC_VER_80: 2948 val8 = RTL_R8(tp, INT_CFG0_8125) | INT_CFG0_CLKREQEN; 2949 RTL_W8(tp, INT_CFG0_8125, val8); 2950 break; 2951 default: 2952 rtl_mod_config2(tp, 0, ClkReqEn); 2953 break; 2954 } 2955 2956 switch (tp->mac_version) { 2957 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: 2958 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_LAST: 2959 /* reset ephy tx/rx disable timer */ 2960 r8168_mac_ocp_modify(tp, 0xe094, 0xff00, 0); 2961 /* chip can trigger L1.2 */ 2962 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, BIT(2)); 2963 break; 2964 default: 2965 break; 2966 } 2967 } else { 2968 switch (tp->mac_version) { 2969 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: 2970 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_LAST: 2971 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, 0); 2972 break; 2973 default: 2974 break; 2975 } 2976 2977 switch (tp->mac_version) { 2978 case RTL_GIGA_MAC_VER_70: 2979 case RTL_GIGA_MAC_VER_80: 2980 val8 = RTL_R8(tp, INT_CFG0_8125) & ~INT_CFG0_CLKREQEN; 2981 RTL_W8(tp, INT_CFG0_8125, val8); 2982 break; 2983 default: 2984 rtl_mod_config2(tp, ClkReqEn, 0); 2985 break; 2986 } 2987 rtl_mod_config5(tp, ASPM_en, 0); 2988 } 2989 } 2990 2991 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat, 2992 u16 tx_stat, u16 rx_dyn, u16 tx_dyn) 2993 { 2994 /* Usage of dynamic vs. static FIFO is controlled by bit 2995 * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known. 2996 */ 2997 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn); 2998 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn); 2999 } 3000 3001 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp, 3002 u8 low, u8 high) 3003 { 3004 /* FIFO thresholds for pause flow control */ 3005 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low); 3006 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high); 3007 } 3008 3009 static void rtl_hw_start_8168b(struct rtl8169_private *tp) 3010 { 3011 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3012 } 3013 3014 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp) 3015 { 3016 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down); 3017 3018 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3019 3020 rtl_disable_clock_request(tp); 3021 } 3022 3023 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp) 3024 { 3025 static const struct ephy_info e_info_8168cp[] = { 3026 { 0x01, 0, 0x0001 }, 3027 { 0x02, 0x0800, 0x1000 }, 3028 { 0x03, 0, 0x0042 }, 3029 { 0x06, 0x0080, 0x0000 }, 3030 { 0x07, 0, 0x2000 } 3031 }; 3032 3033 rtl_set_def_aspm_entry_latency(tp); 3034 3035 rtl_ephy_init(tp, e_info_8168cp); 3036 3037 __rtl_hw_start_8168cp(tp); 3038 } 3039 3040 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp) 3041 { 3042 rtl_set_def_aspm_entry_latency(tp); 3043 3044 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3045 } 3046 3047 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp) 3048 { 3049 rtl_set_def_aspm_entry_latency(tp); 3050 3051 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3052 3053 /* Magic. */ 3054 RTL_W8(tp, DBG_REG, 0x20); 3055 } 3056 3057 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp) 3058 { 3059 static const struct ephy_info e_info_8168c_1[] = { 3060 { 0x02, 0x0800, 0x1000 }, 3061 { 0x03, 0, 0x0002 }, 3062 { 0x06, 0x0080, 0x0000 } 3063 }; 3064 3065 rtl_set_def_aspm_entry_latency(tp); 3066 3067 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); 3068 3069 rtl_ephy_init(tp, e_info_8168c_1); 3070 3071 __rtl_hw_start_8168cp(tp); 3072 } 3073 3074 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp) 3075 { 3076 static const struct ephy_info e_info_8168c_2[] = { 3077 { 0x01, 0, 0x0001 }, 3078 { 0x03, 0x0400, 0x0020 } 3079 }; 3080 3081 rtl_set_def_aspm_entry_latency(tp); 3082 3083 rtl_ephy_init(tp, e_info_8168c_2); 3084 3085 __rtl_hw_start_8168cp(tp); 3086 } 3087 3088 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp) 3089 { 3090 rtl_set_def_aspm_entry_latency(tp); 3091 3092 __rtl_hw_start_8168cp(tp); 3093 } 3094 3095 static void rtl_hw_start_8168d(struct rtl8169_private *tp) 3096 { 3097 rtl_set_def_aspm_entry_latency(tp); 3098 3099 rtl_disable_clock_request(tp); 3100 } 3101 3102 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp) 3103 { 3104 static const struct ephy_info e_info_8168d_4[] = { 3105 { 0x0b, 0x0000, 0x0048 }, 3106 { 0x19, 0x0020, 0x0050 }, 3107 { 0x0c, 0x0100, 0x0020 }, 3108 { 0x10, 0x0004, 0x0000 }, 3109 }; 3110 3111 rtl_set_def_aspm_entry_latency(tp); 3112 3113 rtl_ephy_init(tp, e_info_8168d_4); 3114 3115 rtl_enable_clock_request(tp); 3116 } 3117 3118 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp) 3119 { 3120 static const struct ephy_info e_info_8168e_1[] = { 3121 { 0x00, 0x0200, 0x0100 }, 3122 { 0x00, 0x0000, 0x0004 }, 3123 { 0x06, 0x0002, 0x0001 }, 3124 { 0x06, 0x0000, 0x0030 }, 3125 { 0x07, 0x0000, 0x2000 }, 3126 { 0x00, 0x0000, 0x0020 }, 3127 { 0x03, 0x5800, 0x2000 }, 3128 { 0x03, 0x0000, 0x0001 }, 3129 { 0x01, 0x0800, 0x1000 }, 3130 { 0x07, 0x0000, 0x4000 }, 3131 { 0x1e, 0x0000, 0x2000 }, 3132 { 0x19, 0xffff, 0xfe6c }, 3133 { 0x0a, 0x0000, 0x0040 } 3134 }; 3135 3136 rtl_set_def_aspm_entry_latency(tp); 3137 3138 rtl_ephy_init(tp, e_info_8168e_1); 3139 3140 rtl_disable_clock_request(tp); 3141 3142 /* Reset tx FIFO pointer */ 3143 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST); 3144 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST); 3145 3146 rtl_mod_config5(tp, Spi_en, 0); 3147 } 3148 3149 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp) 3150 { 3151 static const struct ephy_info e_info_8168e_2[] = { 3152 { 0x09, 0x0000, 0x0080 }, 3153 { 0x19, 0x0000, 0x0224 }, 3154 { 0x00, 0x0000, 0x0004 }, 3155 { 0x0c, 0x3df0, 0x0200 }, 3156 }; 3157 3158 rtl_set_def_aspm_entry_latency(tp); 3159 3160 rtl_ephy_init(tp, e_info_8168e_2); 3161 3162 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3163 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); 3164 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 3165 rtl_eri_set_bits(tp, 0x1d0, BIT(1)); 3166 rtl_reset_packet_filter(tp); 3167 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); 3168 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 3169 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060); 3170 3171 rtl_disable_clock_request(tp); 3172 3173 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3174 3175 rtl8168_config_eee_mac(tp); 3176 3177 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3178 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 3179 rtl_mod_config5(tp, Spi_en, 0); 3180 } 3181 3182 static void rtl_hw_start_8168f(struct rtl8169_private *tp) 3183 { 3184 rtl_set_def_aspm_entry_latency(tp); 3185 3186 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3187 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); 3188 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 3189 rtl_reset_packet_filter(tp); 3190 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); 3191 rtl_eri_set_bits(tp, 0x1d0, BIT(4) | BIT(1)); 3192 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 3193 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060); 3194 3195 rtl_disable_clock_request(tp); 3196 3197 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3198 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3199 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 3200 rtl_mod_config5(tp, Spi_en, 0); 3201 3202 rtl8168_config_eee_mac(tp); 3203 } 3204 3205 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp) 3206 { 3207 static const struct ephy_info e_info_8168f_1[] = { 3208 { 0x06, 0x00c0, 0x0020 }, 3209 { 0x08, 0x0001, 0x0002 }, 3210 { 0x09, 0x0000, 0x0080 }, 3211 { 0x19, 0x0000, 0x0224 }, 3212 { 0x00, 0x0000, 0x0008 }, 3213 { 0x0c, 0x3df0, 0x0200 }, 3214 }; 3215 3216 rtl_hw_start_8168f(tp); 3217 3218 rtl_ephy_init(tp, e_info_8168f_1); 3219 } 3220 3221 static void rtl_hw_start_8411(struct rtl8169_private *tp) 3222 { 3223 static const struct ephy_info e_info_8168f_1[] = { 3224 { 0x06, 0x00c0, 0x0020 }, 3225 { 0x0f, 0xffff, 0x5200 }, 3226 { 0x19, 0x0000, 0x0224 }, 3227 { 0x00, 0x0000, 0x0008 }, 3228 { 0x0c, 0x3df0, 0x0200 }, 3229 }; 3230 3231 rtl_hw_start_8168f(tp); 3232 rtl_pcie_state_l2l3_disable(tp); 3233 3234 rtl_ephy_init(tp, e_info_8168f_1); 3235 } 3236 3237 static void rtl_hw_start_8168g(struct rtl8169_private *tp) 3238 { 3239 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3240 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 3241 3242 rtl_set_def_aspm_entry_latency(tp); 3243 3244 rtl_reset_packet_filter(tp); 3245 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f); 3246 3247 rtl_disable_rxdvgate(tp); 3248 3249 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3250 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3251 3252 rtl8168_config_eee_mac(tp); 3253 3254 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); 3255 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3256 3257 rtl_pcie_state_l2l3_disable(tp); 3258 } 3259 3260 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp) 3261 { 3262 static const struct ephy_info e_info_8168g_1[] = { 3263 { 0x00, 0x0008, 0x0000 }, 3264 { 0x0c, 0x3ff0, 0x0820 }, 3265 { 0x1e, 0x0000, 0x0001 }, 3266 { 0x19, 0x8000, 0x0000 } 3267 }; 3268 3269 rtl_hw_start_8168g(tp); 3270 rtl_ephy_init(tp, e_info_8168g_1); 3271 } 3272 3273 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp) 3274 { 3275 static const struct ephy_info e_info_8168g_2[] = { 3276 { 0x00, 0x0008, 0x0000 }, 3277 { 0x0c, 0x3ff0, 0x0820 }, 3278 { 0x19, 0xffff, 0x7c00 }, 3279 { 0x1e, 0xffff, 0x20eb }, 3280 { 0x0d, 0xffff, 0x1666 }, 3281 { 0x00, 0xffff, 0x10a3 }, 3282 { 0x06, 0xffff, 0xf050 }, 3283 { 0x04, 0x0000, 0x0010 }, 3284 { 0x1d, 0x4000, 0x0000 }, 3285 }; 3286 3287 rtl_hw_start_8168g(tp); 3288 rtl_ephy_init(tp, e_info_8168g_2); 3289 } 3290 3291 static void rtl8411b_fix_phy_down(struct rtl8169_private *tp) 3292 { 3293 static const u16 fix_data[] = { 3294 /* 0xf800 */ 0xe008, 0xe00a, 0xe00c, 0xe00e, 0xe027, 0xe04f, 0xe05e, 0xe065, 3295 /* 0xf810 */ 0xc602, 0xbe00, 0x0000, 0xc502, 0xbd00, 0x074c, 0xc302, 0xbb00, 3296 /* 0xf820 */ 0x080a, 0x6420, 0x48c2, 0x8c20, 0xc516, 0x64a4, 0x49c0, 0xf009, 3297 /* 0xf830 */ 0x74a2, 0x8ca5, 0x74a0, 0xc50e, 0x9ca2, 0x1c11, 0x9ca0, 0xe006, 3298 /* 0xf840 */ 0x74f8, 0x48c4, 0x8cf8, 0xc404, 0xbc00, 0xc403, 0xbc00, 0x0bf2, 3299 /* 0xf850 */ 0x0c0a, 0xe434, 0xd3c0, 0x49d9, 0xf01f, 0xc526, 0x64a5, 0x1400, 3300 /* 0xf860 */ 0xf007, 0x0c01, 0x8ca5, 0x1c15, 0xc51b, 0x9ca0, 0xe013, 0xc519, 3301 /* 0xf870 */ 0x74a0, 0x48c4, 0x8ca0, 0xc516, 0x74a4, 0x48c8, 0x48ca, 0x9ca4, 3302 /* 0xf880 */ 0xc512, 0x1b00, 0x9ba0, 0x1b1c, 0x483f, 0x9ba2, 0x1b04, 0xc508, 3303 /* 0xf890 */ 0x9ba0, 0xc505, 0xbd00, 0xc502, 0xbd00, 0x0300, 0x051e, 0xe434, 3304 /* 0xf8a0 */ 0xe018, 0xe092, 0xde20, 0xd3c0, 0xc50f, 0x76a4, 0x49e3, 0xf007, 3305 /* 0xf8b0 */ 0x49c0, 0xf103, 0xc607, 0xbe00, 0xc606, 0xbe00, 0xc602, 0xbe00, 3306 /* 0xf8c0 */ 0x0c4c, 0x0c28, 0x0c2c, 0xdc00, 0xc707, 0x1d00, 0x8de2, 0x48c1, 3307 /* 0xf8d0 */ 0xc502, 0xbd00, 0x00aa, 0xe0c0, 0xc502, 0xbd00, 0x0132 3308 }; 3309 unsigned long flags; 3310 int i; 3311 3312 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 3313 for (i = 0; i < ARRAY_SIZE(fix_data); i++) 3314 __r8168_mac_ocp_write(tp, 0xf800 + 2 * i, fix_data[i]); 3315 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 3316 } 3317 3318 static void rtl_hw_start_8411_2(struct rtl8169_private *tp) 3319 { 3320 static const struct ephy_info e_info_8411_2[] = { 3321 { 0x00, 0x0008, 0x0000 }, 3322 { 0x0c, 0x37d0, 0x0820 }, 3323 { 0x1e, 0x0000, 0x0001 }, 3324 { 0x19, 0x8021, 0x0000 }, 3325 { 0x1e, 0x0000, 0x2000 }, 3326 { 0x0d, 0x0100, 0x0200 }, 3327 { 0x00, 0x0000, 0x0080 }, 3328 { 0x06, 0x0000, 0x0010 }, 3329 { 0x04, 0x0000, 0x0010 }, 3330 { 0x1d, 0x0000, 0x4000 }, 3331 }; 3332 3333 rtl_hw_start_8168g(tp); 3334 3335 rtl_ephy_init(tp, e_info_8411_2); 3336 3337 /* The following Realtek-provided magic fixes an issue with the RX unit 3338 * getting confused after the PHY having been powered-down. 3339 */ 3340 r8168_mac_ocp_write(tp, 0xFC28, 0x0000); 3341 r8168_mac_ocp_write(tp, 0xFC2A, 0x0000); 3342 r8168_mac_ocp_write(tp, 0xFC2C, 0x0000); 3343 r8168_mac_ocp_write(tp, 0xFC2E, 0x0000); 3344 r8168_mac_ocp_write(tp, 0xFC30, 0x0000); 3345 r8168_mac_ocp_write(tp, 0xFC32, 0x0000); 3346 r8168_mac_ocp_write(tp, 0xFC34, 0x0000); 3347 r8168_mac_ocp_write(tp, 0xFC36, 0x0000); 3348 mdelay(3); 3349 r8168_mac_ocp_write(tp, 0xFC26, 0x0000); 3350 3351 rtl8411b_fix_phy_down(tp); 3352 3353 r8168_mac_ocp_write(tp, 0xFC26, 0x8000); 3354 3355 r8168_mac_ocp_write(tp, 0xFC2A, 0x0743); 3356 r8168_mac_ocp_write(tp, 0xFC2C, 0x0801); 3357 r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9); 3358 r8168_mac_ocp_write(tp, 0xFC30, 0x02FD); 3359 r8168_mac_ocp_write(tp, 0xFC32, 0x0C25); 3360 r8168_mac_ocp_write(tp, 0xFC34, 0x00A9); 3361 r8168_mac_ocp_write(tp, 0xFC36, 0x012D); 3362 } 3363 3364 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp) 3365 { 3366 static const struct ephy_info e_info_8168h_1[] = { 3367 { 0x1e, 0x0800, 0x0001 }, 3368 { 0x1d, 0x0000, 0x0800 }, 3369 { 0x05, 0xffff, 0x2089 }, 3370 { 0x06, 0xffff, 0x5881 }, 3371 { 0x04, 0xffff, 0x854a }, 3372 { 0x01, 0xffff, 0x068b } 3373 }; 3374 int rg_saw_cnt; 3375 3376 rtl_ephy_init(tp, e_info_8168h_1); 3377 3378 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3379 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 3380 3381 rtl_set_def_aspm_entry_latency(tp); 3382 3383 rtl_reset_packet_filter(tp); 3384 3385 rtl_eri_set_bits(tp, 0xdc, 0x001c); 3386 3387 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3388 3389 rtl_disable_rxdvgate(tp); 3390 3391 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3392 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3393 3394 rtl8168_config_eee_mac(tp); 3395 3396 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3397 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3398 3399 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3400 3401 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3402 3403 rtl_pcie_state_l2l3_disable(tp); 3404 3405 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3406 if (rg_saw_cnt > 0) { 3407 u16 sw_cnt_1ms_ini; 3408 3409 sw_cnt_1ms_ini = 16000000/rg_saw_cnt; 3410 sw_cnt_1ms_ini &= 0x0fff; 3411 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3412 } 3413 3414 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3415 r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008); 3416 r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f); 3417 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3418 3419 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3420 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3421 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3422 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3423 } 3424 3425 static void rtl_hw_start_8168ep(struct rtl8169_private *tp) 3426 { 3427 rtl8168ep_stop_cmac(tp); 3428 3429 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3430 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3431 3432 rtl_set_def_aspm_entry_latency(tp); 3433 3434 rtl_reset_packet_filter(tp); 3435 3436 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3437 3438 rtl_disable_rxdvgate(tp); 3439 3440 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3441 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3442 3443 rtl8168_config_eee_mac(tp); 3444 3445 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); 3446 3447 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3448 3449 rtl_pcie_state_l2l3_disable(tp); 3450 } 3451 3452 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp) 3453 { 3454 static const struct ephy_info e_info_8168ep_3[] = { 3455 { 0x00, 0x0000, 0x0080 }, 3456 { 0x0d, 0x0100, 0x0200 }, 3457 { 0x19, 0x8021, 0x0000 }, 3458 { 0x1e, 0x0000, 0x2000 }, 3459 }; 3460 3461 rtl_ephy_init(tp, e_info_8168ep_3); 3462 3463 rtl_hw_start_8168ep(tp); 3464 3465 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3466 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3467 3468 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271); 3469 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3470 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3471 } 3472 3473 static void rtl_hw_start_8117(struct rtl8169_private *tp) 3474 { 3475 static const struct ephy_info e_info_8117[] = { 3476 { 0x19, 0x0040, 0x1100 }, 3477 { 0x59, 0x0040, 0x1100 }, 3478 }; 3479 int rg_saw_cnt; 3480 3481 rtl8168ep_stop_cmac(tp); 3482 rtl_ephy_init(tp, e_info_8117); 3483 3484 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3485 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3486 3487 rtl_set_def_aspm_entry_latency(tp); 3488 3489 rtl_reset_packet_filter(tp); 3490 3491 rtl_eri_set_bits(tp, 0xd4, 0x0010); 3492 3493 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3494 3495 rtl_disable_rxdvgate(tp); 3496 3497 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3498 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3499 3500 rtl8168_config_eee_mac(tp); 3501 3502 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3503 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3504 3505 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3506 3507 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3508 3509 rtl_pcie_state_l2l3_disable(tp); 3510 3511 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3512 if (rg_saw_cnt > 0) { 3513 u16 sw_cnt_1ms_ini; 3514 3515 sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff; 3516 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3517 } 3518 3519 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3520 r8168_mac_ocp_write(tp, 0xea80, 0x0003); 3521 r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009); 3522 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3523 3524 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3525 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3526 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3527 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3528 3529 /* firmware is for MAC only */ 3530 r8169_apply_firmware(tp); 3531 } 3532 3533 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp) 3534 { 3535 static const struct ephy_info e_info_8102e_1[] = { 3536 { 0x01, 0, 0x6e65 }, 3537 { 0x02, 0, 0x091f }, 3538 { 0x03, 0, 0xc2f9 }, 3539 { 0x06, 0, 0xafb5 }, 3540 { 0x07, 0, 0x0e00 }, 3541 { 0x19, 0, 0xec80 }, 3542 { 0x01, 0, 0x2e65 }, 3543 { 0x01, 0, 0x6e65 } 3544 }; 3545 u8 cfg1; 3546 3547 rtl_set_def_aspm_entry_latency(tp); 3548 3549 RTL_W8(tp, DBG_REG, FIX_NAK_1); 3550 3551 RTL_W8(tp, Config1, 3552 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable); 3553 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3554 3555 cfg1 = RTL_R8(tp, Config1); 3556 if ((cfg1 & LEDS0) && (cfg1 & LEDS1)) 3557 RTL_W8(tp, Config1, cfg1 & ~LEDS0); 3558 3559 rtl_ephy_init(tp, e_info_8102e_1); 3560 } 3561 3562 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp) 3563 { 3564 rtl_set_def_aspm_entry_latency(tp); 3565 3566 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable); 3567 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3568 } 3569 3570 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp) 3571 { 3572 rtl_hw_start_8102e_2(tp); 3573 3574 rtl_ephy_write(tp, 0x03, 0xc2f9); 3575 } 3576 3577 static void rtl_hw_start_8401(struct rtl8169_private *tp) 3578 { 3579 static const struct ephy_info e_info_8401[] = { 3580 { 0x01, 0xffff, 0x6fe5 }, 3581 { 0x03, 0xffff, 0x0599 }, 3582 { 0x06, 0xffff, 0xaf25 }, 3583 { 0x07, 0xffff, 0x8e68 }, 3584 }; 3585 3586 rtl_ephy_init(tp, e_info_8401); 3587 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3588 } 3589 3590 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp) 3591 { 3592 static const struct ephy_info e_info_8105e_1[] = { 3593 { 0x07, 0, 0x4000 }, 3594 { 0x19, 0, 0x0200 }, 3595 { 0x19, 0, 0x0020 }, 3596 { 0x1e, 0, 0x2000 }, 3597 { 0x03, 0, 0x0001 }, 3598 { 0x19, 0, 0x0100 }, 3599 { 0x19, 0, 0x0004 }, 3600 { 0x0a, 0, 0x0020 } 3601 }; 3602 3603 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3604 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3605 3606 /* Disable Early Tally Counter */ 3607 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000); 3608 3609 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3610 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3611 3612 rtl_ephy_init(tp, e_info_8105e_1); 3613 3614 rtl_pcie_state_l2l3_disable(tp); 3615 } 3616 3617 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp) 3618 { 3619 rtl_hw_start_8105e_1(tp); 3620 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000); 3621 } 3622 3623 static void rtl_hw_start_8402(struct rtl8169_private *tp) 3624 { 3625 static const struct ephy_info e_info_8402[] = { 3626 { 0x19, 0xffff, 0xff64 }, 3627 { 0x1e, 0, 0x4000 } 3628 }; 3629 3630 rtl_set_def_aspm_entry_latency(tp); 3631 3632 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3633 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3634 3635 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3636 3637 rtl_ephy_init(tp, e_info_8402); 3638 3639 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06); 3640 rtl_reset_packet_filter(tp); 3641 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3642 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3643 rtl_w0w1_eri(tp, 0x0d4, 0x0e00, 0xff00); 3644 3645 /* disable EEE */ 3646 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3647 3648 rtl_pcie_state_l2l3_disable(tp); 3649 } 3650 3651 static void rtl_hw_start_8106(struct rtl8169_private *tp) 3652 { 3653 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3654 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3655 3656 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN); 3657 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3658 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3659 3660 /* L0 7us, L1 32us - needed to avoid issues with link-up detection */ 3661 rtl_set_aspm_entry_latency(tp, 0x2f); 3662 3663 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 3664 3665 /* disable EEE */ 3666 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3667 3668 rtl_pcie_state_l2l3_disable(tp); 3669 } 3670 3671 DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond) 3672 { 3673 return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13); 3674 } 3675 3676 static void rtl_hw_start_8125_common(struct rtl8169_private *tp) 3677 { 3678 rtl_pcie_state_l2l3_disable(tp); 3679 3680 RTL_W16(tp, 0x382, 0x221b); 3681 RTL_W32(tp, RSS_CTRL_8125, 0); 3682 RTL_W16(tp, Q_NUM_CTRL_8125, 0); 3683 3684 /* disable UPS */ 3685 r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000); 3686 3687 RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10); 3688 3689 r8168_mac_ocp_write(tp, 0xc140, 0xffff); 3690 r8168_mac_ocp_write(tp, 0xc142, 0xffff); 3691 3692 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9); 3693 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3694 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3695 3696 /* disable new tx descriptor format */ 3697 r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000); 3698 3699 if (tp->mac_version == RTL_GIGA_MAC_VER_70 || 3700 tp->mac_version == RTL_GIGA_MAC_VER_80) 3701 RTL_W8(tp, 0xD8, RTL_R8(tp, 0xD8) & ~0x02); 3702 3703 if (tp->mac_version == RTL_GIGA_MAC_VER_80) 3704 r8168_mac_ocp_modify(tp, 0xe614, 0x0f00, 0x0f00); 3705 else if (tp->mac_version == RTL_GIGA_MAC_VER_70) 3706 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400); 3707 else if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3708 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200); 3709 else 3710 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0300); 3711 3712 if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3713 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0000); 3714 else 3715 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020); 3716 3717 r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c); 3718 r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033); 3719 r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040); 3720 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030); 3721 r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000); 3722 r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001); 3723 if (tp->mac_version == RTL_GIGA_MAC_VER_70 || 3724 tp->mac_version == RTL_GIGA_MAC_VER_80) 3725 r8168_mac_ocp_modify(tp, 0xea1c, 0x0300, 0x0000); 3726 else 3727 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000); 3728 r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403); 3729 r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0068); 3730 r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f); 3731 3732 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000); 3733 r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001); 3734 udelay(1); 3735 r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000); 3736 RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030); 3737 3738 r8168_mac_ocp_write(tp, 0xe098, 0xc302); 3739 3740 rtl_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10); 3741 3742 if (tp->mac_version == RTL_GIGA_MAC_VER_61) 3743 rtl8125a_config_eee_mac(tp); 3744 else 3745 rtl8125b_config_eee_mac(tp); 3746 3747 rtl_disable_rxdvgate(tp); 3748 } 3749 3750 static void rtl_hw_start_8125a_2(struct rtl8169_private *tp) 3751 { 3752 static const struct ephy_info e_info_8125a_2[] = { 3753 { 0x04, 0xffff, 0xd000 }, 3754 { 0x0a, 0xffff, 0x8653 }, 3755 { 0x23, 0xffff, 0xab66 }, 3756 { 0x20, 0xffff, 0x9455 }, 3757 { 0x21, 0xffff, 0x99ff }, 3758 { 0x29, 0xffff, 0xfe04 }, 3759 3760 { 0x44, 0xffff, 0xd000 }, 3761 { 0x4a, 0xffff, 0x8653 }, 3762 { 0x63, 0xffff, 0xab66 }, 3763 { 0x60, 0xffff, 0x9455 }, 3764 { 0x61, 0xffff, 0x99ff }, 3765 { 0x69, 0xffff, 0xfe04 }, 3766 }; 3767 3768 rtl_set_def_aspm_entry_latency(tp); 3769 rtl_ephy_init(tp, e_info_8125a_2); 3770 rtl_hw_start_8125_common(tp); 3771 } 3772 3773 static void rtl_hw_start_8125b(struct rtl8169_private *tp) 3774 { 3775 static const struct ephy_info e_info_8125b[] = { 3776 { 0x0b, 0xffff, 0xa908 }, 3777 { 0x1e, 0xffff, 0x20eb }, 3778 { 0x4b, 0xffff, 0xa908 }, 3779 { 0x5e, 0xffff, 0x20eb }, 3780 { 0x22, 0x0030, 0x0020 }, 3781 { 0x62, 0x0030, 0x0020 }, 3782 }; 3783 3784 rtl_set_def_aspm_entry_latency(tp); 3785 rtl_ephy_init(tp, e_info_8125b); 3786 rtl_hw_start_8125_common(tp); 3787 } 3788 3789 static void rtl_hw_start_8125d(struct rtl8169_private *tp) 3790 { 3791 rtl_set_def_aspm_entry_latency(tp); 3792 rtl_hw_start_8125_common(tp); 3793 } 3794 3795 static void rtl_hw_start_8126a(struct rtl8169_private *tp) 3796 { 3797 rtl_disable_zrxdc_timeout(tp); 3798 rtl_set_def_aspm_entry_latency(tp); 3799 rtl_hw_start_8125_common(tp); 3800 } 3801 3802 static void rtl_hw_start_8127a(struct rtl8169_private *tp) 3803 { 3804 rtl_set_def_aspm_entry_latency(tp); 3805 rtl_hw_start_8125_common(tp); 3806 } 3807 3808 static void rtl_hw_config(struct rtl8169_private *tp) 3809 { 3810 static const rtl_generic_fct hw_configs[] = { 3811 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1, 3812 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3, 3813 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2, 3814 [RTL_GIGA_MAC_VER_10] = NULL, 3815 [RTL_GIGA_MAC_VER_14] = rtl_hw_start_8401, 3816 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168b, 3817 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1, 3818 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1, 3819 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2, 3820 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_2, 3821 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4, 3822 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2, 3823 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3, 3824 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d, 3825 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d, 3826 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4, 3827 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1, 3828 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2, 3829 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168d, 3830 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1, 3831 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1, 3832 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2, 3833 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1, 3834 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1, 3835 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402, 3836 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411, 3837 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106, 3838 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1, 3839 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2, 3840 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2, 3841 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2, 3842 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1, 3843 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1, 3844 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3, 3845 [RTL_GIGA_MAC_VER_52] = rtl_hw_start_8117, 3846 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125a_2, 3847 [RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b, 3848 [RTL_GIGA_MAC_VER_64] = rtl_hw_start_8125d, 3849 [RTL_GIGA_MAC_VER_66] = rtl_hw_start_8125d, 3850 [RTL_GIGA_MAC_VER_70] = rtl_hw_start_8126a, 3851 [RTL_GIGA_MAC_VER_80] = rtl_hw_start_8127a, 3852 }; 3853 3854 if (hw_configs[tp->mac_version]) 3855 hw_configs[tp->mac_version](tp); 3856 } 3857 3858 static void rtl_hw_start_8125(struct rtl8169_private *tp) 3859 { 3860 int i; 3861 3862 RTL_W8(tp, INT_CFG0_8125, 0x00); 3863 3864 /* disable interrupt coalescing */ 3865 switch (tp->mac_version) { 3866 case RTL_GIGA_MAC_VER_61: 3867 case RTL_GIGA_MAC_VER_64: 3868 case RTL_GIGA_MAC_VER_66: 3869 case RTL_GIGA_MAC_VER_80: 3870 for (i = 0xa00; i < 0xb00; i += 4) 3871 RTL_W32(tp, i, 0); 3872 if (tp->mac_version == RTL_GIGA_MAC_VER_80) 3873 RTL_W16(tp, INT_CFG1_8125, 0x0000); 3874 break; 3875 case RTL_GIGA_MAC_VER_63: 3876 case RTL_GIGA_MAC_VER_70: 3877 for (i = 0xa00; i < 0xa80; i += 4) 3878 RTL_W32(tp, i, 0); 3879 RTL_W16(tp, INT_CFG1_8125, 0x0000); 3880 break; 3881 default: 3882 break; 3883 } 3884 3885 /* enable extended tally counter */ 3886 r8168_mac_ocp_modify(tp, 0xea84, 0, BIT(1) | BIT(0)); 3887 3888 rtl_hw_config(tp); 3889 } 3890 3891 static void rtl_hw_start_8168(struct rtl8169_private *tp) 3892 { 3893 if (rtl_is_8168evl_up(tp)) 3894 RTL_W8(tp, MaxTxPacketSize, EarlySize); 3895 else 3896 RTL_W8(tp, MaxTxPacketSize, TxPacketMax); 3897 3898 rtl_hw_config(tp); 3899 3900 /* disable interrupt coalescing */ 3901 RTL_W16(tp, IntrMitigate, 0x0000); 3902 } 3903 3904 static void rtl_hw_start_8169(struct rtl8169_private *tp) 3905 { 3906 RTL_W8(tp, EarlyTxThres, NoEarlyTx); 3907 3908 tp->cp_cmd |= PCIMulRW; 3909 3910 if (tp->mac_version == RTL_GIGA_MAC_VER_02 || 3911 tp->mac_version == RTL_GIGA_MAC_VER_03) 3912 tp->cp_cmd |= EnAnaPLL; 3913 3914 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 3915 3916 rtl8169_set_magic_reg(tp); 3917 3918 /* disable interrupt coalescing */ 3919 RTL_W16(tp, IntrMitigate, 0x0000); 3920 } 3921 3922 static void rtl_hw_start(struct rtl8169_private *tp) 3923 { 3924 rtl_unlock_config_regs(tp); 3925 /* disable aspm and clock request before ephy access */ 3926 rtl_hw_aspm_clkreq_enable(tp, false); 3927 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 3928 3929 rtl_set_eee_txidle_timer(tp); 3930 3931 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 3932 rtl_hw_start_8169(tp); 3933 else if (rtl_is_8125(tp)) 3934 rtl_hw_start_8125(tp); 3935 else 3936 rtl_hw_start_8168(tp); 3937 3938 rtl_enable_exit_l1(tp); 3939 rtl_hw_aspm_clkreq_enable(tp, true); 3940 rtl_set_rx_max_size(tp); 3941 rtl_set_rx_tx_desc_registers(tp); 3942 rtl_lock_config_regs(tp); 3943 3944 rtl_jumbo_config(tp); 3945 3946 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */ 3947 rtl_pci_commit(tp); 3948 3949 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb); 3950 rtl_init_rxcfg(tp); 3951 rtl_set_tx_config_registers(tp); 3952 rtl_set_rx_config_features(tp, tp->dev->features); 3953 rtl_set_rx_mode(tp->dev); 3954 rtl_irq_enable(tp); 3955 } 3956 3957 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu) 3958 { 3959 struct rtl8169_private *tp = netdev_priv(dev); 3960 3961 WRITE_ONCE(dev->mtu, new_mtu); 3962 netdev_update_features(dev); 3963 rtl_jumbo_config(tp); 3964 rtl_set_eee_txidle_timer(tp); 3965 3966 return 0; 3967 } 3968 3969 static void rtl8169_mark_to_asic(struct RxDesc *desc) 3970 { 3971 u32 eor = le32_to_cpu(desc->opts1) & RingEnd; 3972 3973 desc->opts2 = 0; 3974 /* Force memory writes to complete before releasing descriptor */ 3975 dma_wmb(); 3976 WRITE_ONCE(desc->opts1, cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE)); 3977 } 3978 3979 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp, 3980 struct RxDesc *desc) 3981 { 3982 struct device *d = tp_to_dev(tp); 3983 int node = dev_to_node(d); 3984 dma_addr_t mapping; 3985 struct page *data; 3986 3987 data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE)); 3988 if (!data) 3989 return NULL; 3990 3991 mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 3992 if (unlikely(dma_mapping_error(d, mapping))) { 3993 netdev_err(tp->dev, "Failed to map RX DMA!\n"); 3994 __free_pages(data, get_order(R8169_RX_BUF_SIZE)); 3995 return NULL; 3996 } 3997 3998 desc->addr = cpu_to_le64(mapping); 3999 rtl8169_mark_to_asic(desc); 4000 4001 return data; 4002 } 4003 4004 static void rtl8169_rx_clear(struct rtl8169_private *tp) 4005 { 4006 int i; 4007 4008 for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) { 4009 dma_unmap_page(tp_to_dev(tp), 4010 le64_to_cpu(tp->RxDescArray[i].addr), 4011 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 4012 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE)); 4013 tp->Rx_databuff[i] = NULL; 4014 tp->RxDescArray[i].addr = 0; 4015 tp->RxDescArray[i].opts1 = 0; 4016 } 4017 } 4018 4019 static int rtl8169_rx_fill(struct rtl8169_private *tp) 4020 { 4021 int i; 4022 4023 for (i = 0; i < NUM_RX_DESC; i++) { 4024 struct page *data; 4025 4026 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i); 4027 if (!data) { 4028 rtl8169_rx_clear(tp); 4029 return -ENOMEM; 4030 } 4031 tp->Rx_databuff[i] = data; 4032 } 4033 4034 /* mark as last descriptor in the ring */ 4035 tp->RxDescArray[NUM_RX_DESC - 1].opts1 |= cpu_to_le32(RingEnd); 4036 4037 return 0; 4038 } 4039 4040 static int rtl8169_init_ring(struct rtl8169_private *tp) 4041 { 4042 rtl8169_init_ring_indexes(tp); 4043 4044 memset(tp->tx_skb, 0, sizeof(tp->tx_skb)); 4045 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff)); 4046 4047 return rtl8169_rx_fill(tp); 4048 } 4049 4050 static void rtl8169_unmap_tx_skb(struct rtl8169_private *tp, unsigned int entry) 4051 { 4052 struct ring_info *tx_skb = tp->tx_skb + entry; 4053 struct TxDesc *desc = tp->TxDescArray + entry; 4054 4055 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr), tx_skb->len, 4056 DMA_TO_DEVICE); 4057 memset(desc, 0, sizeof(*desc)); 4058 memset(tx_skb, 0, sizeof(*tx_skb)); 4059 } 4060 4061 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start, 4062 unsigned int n) 4063 { 4064 unsigned int i; 4065 4066 for (i = 0; i < n; i++) { 4067 unsigned int entry = (start + i) % NUM_TX_DESC; 4068 struct ring_info *tx_skb = tp->tx_skb + entry; 4069 unsigned int len = tx_skb->len; 4070 4071 if (len) { 4072 struct sk_buff *skb = tx_skb->skb; 4073 4074 rtl8169_unmap_tx_skb(tp, entry); 4075 if (skb) 4076 dev_consume_skb_any(skb); 4077 } 4078 } 4079 } 4080 4081 static void rtl8169_tx_clear(struct rtl8169_private *tp) 4082 { 4083 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC); 4084 netdev_reset_queue(tp->dev); 4085 } 4086 4087 static void rtl8169_cleanup(struct rtl8169_private *tp) 4088 { 4089 napi_disable(&tp->napi); 4090 4091 /* Give a racing hard_start_xmit a few cycles to complete. */ 4092 synchronize_net(); 4093 4094 /* Disable interrupts */ 4095 rtl8169_irq_mask_and_ack(tp); 4096 4097 rtl_rx_close(tp); 4098 4099 switch (tp->mac_version) { 4100 case RTL_GIGA_MAC_VER_28: 4101 case RTL_GIGA_MAC_VER_31: 4102 rtl_loop_wait_low(tp, &rtl_npq_cond, 20, 2000); 4103 break; 4104 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: 4105 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 4106 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666); 4107 break; 4108 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_LAST: 4109 rtl_enable_rxdvgate(tp); 4110 fsleep(2000); 4111 break; 4112 default: 4113 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 4114 fsleep(100); 4115 break; 4116 } 4117 4118 rtl_hw_reset(tp); 4119 4120 rtl8169_tx_clear(tp); 4121 rtl8169_init_ring_indexes(tp); 4122 } 4123 4124 static void rtl_reset_work(struct rtl8169_private *tp) 4125 { 4126 int i; 4127 4128 netif_stop_queue(tp->dev); 4129 4130 rtl8169_cleanup(tp); 4131 4132 for (i = 0; i < NUM_RX_DESC; i++) 4133 rtl8169_mark_to_asic(tp->RxDescArray + i); 4134 4135 napi_enable(&tp->napi); 4136 rtl_hw_start(tp); 4137 } 4138 4139 static void rtl8169_tx_timeout(struct net_device *dev, unsigned int txqueue) 4140 { 4141 struct rtl8169_private *tp = netdev_priv(dev); 4142 4143 rtl_schedule_task(tp, RTL_FLAG_TASK_TX_TIMEOUT); 4144 } 4145 4146 static int rtl8169_tx_map(struct rtl8169_private *tp, const u32 *opts, u32 len, 4147 void *addr, unsigned int entry, bool desc_own) 4148 { 4149 struct TxDesc *txd = tp->TxDescArray + entry; 4150 struct device *d = tp_to_dev(tp); 4151 dma_addr_t mapping; 4152 u32 opts1; 4153 int ret; 4154 4155 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE); 4156 ret = dma_mapping_error(d, mapping); 4157 if (unlikely(ret)) { 4158 if (net_ratelimit()) 4159 netdev_err(tp->dev, "Failed to map TX data!\n"); 4160 return ret; 4161 } 4162 4163 txd->addr = cpu_to_le64(mapping); 4164 txd->opts2 = cpu_to_le32(opts[1]); 4165 4166 opts1 = opts[0] | len; 4167 if (entry == NUM_TX_DESC - 1) 4168 opts1 |= RingEnd; 4169 if (desc_own) 4170 opts1 |= DescOwn; 4171 txd->opts1 = cpu_to_le32(opts1); 4172 4173 tp->tx_skb[entry].len = len; 4174 4175 return 0; 4176 } 4177 4178 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb, 4179 const u32 *opts, unsigned int entry) 4180 { 4181 struct skb_shared_info *info = skb_shinfo(skb); 4182 unsigned int cur_frag; 4183 4184 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { 4185 const skb_frag_t *frag = info->frags + cur_frag; 4186 void *addr = skb_frag_address(frag); 4187 u32 len = skb_frag_size(frag); 4188 4189 entry = (entry + 1) % NUM_TX_DESC; 4190 4191 if (unlikely(rtl8169_tx_map(tp, opts, len, addr, entry, true))) 4192 goto err_out; 4193 } 4194 4195 return 0; 4196 4197 err_out: 4198 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag); 4199 return -EIO; 4200 } 4201 4202 static bool rtl_skb_is_udp(struct sk_buff *skb) 4203 { 4204 int no = skb_network_offset(skb); 4205 struct ipv6hdr *i6h, _i6h; 4206 struct iphdr *ih, _ih; 4207 4208 switch (vlan_get_protocol(skb)) { 4209 case htons(ETH_P_IP): 4210 ih = skb_header_pointer(skb, no, sizeof(_ih), &_ih); 4211 return ih && ih->protocol == IPPROTO_UDP; 4212 case htons(ETH_P_IPV6): 4213 i6h = skb_header_pointer(skb, no, sizeof(_i6h), &_i6h); 4214 return i6h && i6h->nexthdr == IPPROTO_UDP; 4215 default: 4216 return false; 4217 } 4218 } 4219 4220 #define RTL_MIN_PATCH_LEN 47 4221 4222 /* see rtl8125_get_patch_pad_len() in r8125 vendor driver */ 4223 static unsigned int rtl8125_quirk_udp_padto(struct rtl8169_private *tp, 4224 struct sk_buff *skb) 4225 { 4226 unsigned int padto = 0, len = skb->len; 4227 4228 if (len < 128 + RTL_MIN_PATCH_LEN && rtl_skb_is_udp(skb) && 4229 skb_transport_header_was_set(skb)) { 4230 unsigned int trans_data_len = skb_tail_pointer(skb) - 4231 skb_transport_header(skb); 4232 4233 if (trans_data_len >= offsetof(struct udphdr, len) && 4234 trans_data_len < RTL_MIN_PATCH_LEN) { 4235 u16 dest = ntohs(udp_hdr(skb)->dest); 4236 4237 /* dest is a standard PTP port */ 4238 if (dest == 319 || dest == 320) 4239 padto = len + RTL_MIN_PATCH_LEN - trans_data_len; 4240 } 4241 4242 if (trans_data_len < sizeof(struct udphdr)) 4243 padto = max_t(unsigned int, padto, 4244 len + sizeof(struct udphdr) - trans_data_len); 4245 } 4246 4247 return padto; 4248 } 4249 4250 static unsigned int rtl_quirk_packet_padto(struct rtl8169_private *tp, 4251 struct sk_buff *skb) 4252 { 4253 unsigned int padto = 0; 4254 4255 switch (tp->mac_version) { 4256 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63: 4257 padto = rtl8125_quirk_udp_padto(tp, skb); 4258 break; 4259 default: 4260 break; 4261 } 4262 4263 switch (tp->mac_version) { 4264 case RTL_GIGA_MAC_VER_34: 4265 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_LAST: 4266 padto = max_t(unsigned int, padto, ETH_ZLEN); 4267 break; 4268 default: 4269 break; 4270 } 4271 4272 return padto; 4273 } 4274 4275 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts) 4276 { 4277 u32 mss = skb_shinfo(skb)->gso_size; 4278 4279 if (mss) { 4280 opts[0] |= TD_LSO; 4281 opts[0] |= mss << TD0_MSS_SHIFT; 4282 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4283 const struct iphdr *ip = ip_hdr(skb); 4284 4285 if (ip->protocol == IPPROTO_TCP) 4286 opts[0] |= TD0_IP_CS | TD0_TCP_CS; 4287 else if (ip->protocol == IPPROTO_UDP) 4288 opts[0] |= TD0_IP_CS | TD0_UDP_CS; 4289 else 4290 WARN_ON_ONCE(1); 4291 } 4292 } 4293 4294 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp, 4295 struct sk_buff *skb, u32 *opts) 4296 { 4297 struct skb_shared_info *shinfo = skb_shinfo(skb); 4298 u32 mss = shinfo->gso_size; 4299 4300 if (mss) { 4301 if (shinfo->gso_type & SKB_GSO_TCPV4) { 4302 opts[0] |= TD1_GTSENV4; 4303 } else if (shinfo->gso_type & SKB_GSO_TCPV6) { 4304 if (skb_cow_head(skb, 0)) 4305 return false; 4306 4307 tcp_v6_gso_csum_prep(skb); 4308 opts[0] |= TD1_GTSENV6; 4309 } else { 4310 WARN_ON_ONCE(1); 4311 } 4312 4313 opts[0] |= skb_transport_offset(skb) << GTTCPHO_SHIFT; 4314 opts[1] |= mss << TD1_MSS_SHIFT; 4315 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4316 u8 ip_protocol; 4317 4318 switch (vlan_get_protocol(skb)) { 4319 case htons(ETH_P_IP): 4320 opts[1] |= TD1_IPv4_CS; 4321 ip_protocol = ip_hdr(skb)->protocol; 4322 break; 4323 4324 case htons(ETH_P_IPV6): 4325 opts[1] |= TD1_IPv6_CS; 4326 ip_protocol = ipv6_hdr(skb)->nexthdr; 4327 break; 4328 4329 default: 4330 ip_protocol = IPPROTO_RAW; 4331 break; 4332 } 4333 4334 if (ip_protocol == IPPROTO_TCP) 4335 opts[1] |= TD1_TCP_CS; 4336 else if (ip_protocol == IPPROTO_UDP) 4337 opts[1] |= TD1_UDP_CS; 4338 else 4339 WARN_ON_ONCE(1); 4340 4341 opts[1] |= skb_transport_offset(skb) << TCPHO_SHIFT; 4342 } else { 4343 unsigned int padto = rtl_quirk_packet_padto(tp, skb); 4344 4345 /* skb_padto would free the skb on error */ 4346 return !__skb_put_padto(skb, padto, false); 4347 } 4348 4349 return true; 4350 } 4351 4352 static unsigned int rtl_tx_slots_avail(struct rtl8169_private *tp) 4353 { 4354 return READ_ONCE(tp->dirty_tx) + NUM_TX_DESC - READ_ONCE(tp->cur_tx); 4355 } 4356 4357 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */ 4358 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp) 4359 { 4360 switch (tp->mac_version) { 4361 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 4362 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 4363 return false; 4364 default: 4365 return true; 4366 } 4367 } 4368 4369 static void rtl8169_doorbell(struct rtl8169_private *tp) 4370 { 4371 if (rtl_is_8125(tp)) 4372 RTL_W16(tp, TxPoll_8125, BIT(0)); 4373 else 4374 RTL_W8(tp, TxPoll, NPQ); 4375 } 4376 4377 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, 4378 struct net_device *dev) 4379 { 4380 struct rtl8169_private *tp = netdev_priv(dev); 4381 unsigned int entry = tp->cur_tx % NUM_TX_DESC; 4382 struct TxDesc *txd_first, *txd_last; 4383 bool stop_queue, door_bell; 4384 unsigned int frags; 4385 u32 opts[2]; 4386 4387 if (unlikely(!rtl_tx_slots_avail(tp))) { 4388 if (net_ratelimit()) 4389 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n"); 4390 netif_stop_queue(dev); 4391 return NETDEV_TX_BUSY; 4392 } 4393 4394 opts[1] = rtl8169_tx_vlan_tag(skb); 4395 opts[0] = 0; 4396 4397 if (!rtl_chip_supports_csum_v2(tp)) 4398 rtl8169_tso_csum_v1(skb, opts); 4399 else if (!rtl8169_tso_csum_v2(tp, skb, opts)) 4400 goto err_dma_0; 4401 4402 if (unlikely(rtl8169_tx_map(tp, opts, skb_headlen(skb), skb->data, 4403 entry, false))) 4404 goto err_dma_0; 4405 4406 txd_first = tp->TxDescArray + entry; 4407 4408 frags = skb_shinfo(skb)->nr_frags; 4409 if (frags) { 4410 if (rtl8169_xmit_frags(tp, skb, opts, entry)) 4411 goto err_dma_1; 4412 entry = (entry + frags) % NUM_TX_DESC; 4413 } 4414 4415 txd_last = tp->TxDescArray + entry; 4416 txd_last->opts1 |= cpu_to_le32(LastFrag); 4417 tp->tx_skb[entry].skb = skb; 4418 4419 skb_tx_timestamp(skb); 4420 4421 /* Force memory writes to complete before releasing descriptor */ 4422 dma_wmb(); 4423 4424 door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more()); 4425 4426 txd_first->opts1 |= cpu_to_le32(DescOwn | FirstFrag); 4427 4428 /* rtl_tx needs to see descriptor changes before updated tp->cur_tx */ 4429 smp_wmb(); 4430 4431 WRITE_ONCE(tp->cur_tx, tp->cur_tx + frags + 1); 4432 4433 stop_queue = !netif_subqueue_maybe_stop(dev, 0, rtl_tx_slots_avail(tp), 4434 R8169_TX_STOP_THRS, 4435 R8169_TX_START_THRS); 4436 if (door_bell || stop_queue) 4437 rtl8169_doorbell(tp); 4438 4439 return NETDEV_TX_OK; 4440 4441 err_dma_1: 4442 rtl8169_unmap_tx_skb(tp, entry); 4443 err_dma_0: 4444 dev_kfree_skb_any(skb); 4445 dev->stats.tx_dropped++; 4446 return NETDEV_TX_OK; 4447 } 4448 4449 static unsigned int rtl_last_frag_len(struct sk_buff *skb) 4450 { 4451 struct skb_shared_info *info = skb_shinfo(skb); 4452 unsigned int nr_frags = info->nr_frags; 4453 4454 if (!nr_frags) 4455 return UINT_MAX; 4456 4457 return skb_frag_size(info->frags + nr_frags - 1); 4458 } 4459 4460 /* Workaround for hw issues with TSO on RTL8168evl */ 4461 static netdev_features_t rtl8168evl_fix_tso(struct sk_buff *skb, 4462 netdev_features_t features) 4463 { 4464 /* IPv4 header has options field */ 4465 if (vlan_get_protocol(skb) == htons(ETH_P_IP) && 4466 ip_hdrlen(skb) > sizeof(struct iphdr)) 4467 features &= ~NETIF_F_ALL_TSO; 4468 4469 /* IPv4 TCP header has options field */ 4470 else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4 && 4471 tcp_hdrlen(skb) > sizeof(struct tcphdr)) 4472 features &= ~NETIF_F_ALL_TSO; 4473 4474 else if (rtl_last_frag_len(skb) <= 6) 4475 features &= ~NETIF_F_ALL_TSO; 4476 4477 return features; 4478 } 4479 4480 static netdev_features_t rtl8169_features_check(struct sk_buff *skb, 4481 struct net_device *dev, 4482 netdev_features_t features) 4483 { 4484 struct rtl8169_private *tp = netdev_priv(dev); 4485 4486 if (skb_is_gso(skb)) { 4487 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 4488 features = rtl8168evl_fix_tso(skb, features); 4489 4490 if (skb_transport_offset(skb) > GTTCPHO_MAX && 4491 rtl_chip_supports_csum_v2(tp)) 4492 features &= ~NETIF_F_ALL_TSO; 4493 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4494 /* work around hw bug on some chip versions */ 4495 if (skb->len < ETH_ZLEN) 4496 features &= ~NETIF_F_CSUM_MASK; 4497 4498 if (rtl_quirk_packet_padto(tp, skb)) 4499 features &= ~NETIF_F_CSUM_MASK; 4500 4501 if (skb_transport_offset(skb) > TCPHO_MAX && 4502 rtl_chip_supports_csum_v2(tp)) 4503 features &= ~NETIF_F_CSUM_MASK; 4504 } 4505 4506 return vlan_features_check(skb, features); 4507 } 4508 4509 static void rtl8169_pcierr_interrupt(struct net_device *dev) 4510 { 4511 struct rtl8169_private *tp = netdev_priv(dev); 4512 struct pci_dev *pdev = tp->pci_dev; 4513 int pci_status_errs; 4514 u16 pci_cmd; 4515 4516 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 4517 4518 pci_status_errs = pci_status_get_and_clear_errors(pdev); 4519 4520 if (net_ratelimit()) 4521 netdev_err(dev, "PCI error (cmd = 0x%04x, status_errs = 0x%04x)\n", 4522 pci_cmd, pci_status_errs); 4523 4524 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4525 } 4526 4527 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp, 4528 int budget) 4529 { 4530 unsigned int dirty_tx, bytes_compl = 0, pkts_compl = 0; 4531 struct sk_buff *skb; 4532 4533 dirty_tx = tp->dirty_tx; 4534 4535 while (READ_ONCE(tp->cur_tx) != dirty_tx) { 4536 unsigned int entry = dirty_tx % NUM_TX_DESC; 4537 u32 status; 4538 4539 status = le32_to_cpu(READ_ONCE(tp->TxDescArray[entry].opts1)); 4540 if (status & DescOwn) 4541 break; 4542 4543 skb = tp->tx_skb[entry].skb; 4544 rtl8169_unmap_tx_skb(tp, entry); 4545 4546 if (skb) { 4547 pkts_compl++; 4548 bytes_compl += skb->len; 4549 napi_consume_skb(skb, budget); 4550 } 4551 dirty_tx++; 4552 } 4553 4554 if (tp->dirty_tx != dirty_tx) { 4555 dev_sw_netstats_tx_add(dev, pkts_compl, bytes_compl); 4556 WRITE_ONCE(tp->dirty_tx, dirty_tx); 4557 4558 netif_subqueue_completed_wake(dev, 0, pkts_compl, bytes_compl, 4559 rtl_tx_slots_avail(tp), 4560 R8169_TX_START_THRS); 4561 /* 4562 * 8168 hack: TxPoll requests are lost when the Tx packets are 4563 * too close. Let's kick an extra TxPoll request when a burst 4564 * of start_xmit activity is detected (if it is not detected, 4565 * it is slow enough). -- FR 4566 * If skb is NULL then we come here again once a tx irq is 4567 * triggered after the last fragment is marked transmitted. 4568 */ 4569 if (READ_ONCE(tp->cur_tx) != dirty_tx && skb) 4570 rtl8169_doorbell(tp); 4571 } 4572 } 4573 4574 static inline int rtl8169_fragmented_frame(u32 status) 4575 { 4576 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag); 4577 } 4578 4579 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1) 4580 { 4581 u32 status = opts1 & (RxProtoMask | RxCSFailMask); 4582 4583 if (status == RxProtoTCP || status == RxProtoUDP) 4584 skb->ip_summed = CHECKSUM_UNNECESSARY; 4585 else 4586 skb_checksum_none_assert(skb); 4587 } 4588 4589 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, int budget) 4590 { 4591 struct device *d = tp_to_dev(tp); 4592 int count; 4593 4594 for (count = 0; count < budget; count++, tp->cur_rx++) { 4595 unsigned int pkt_size, entry = tp->cur_rx % NUM_RX_DESC; 4596 struct RxDesc *desc = tp->RxDescArray + entry; 4597 struct sk_buff *skb; 4598 const void *rx_buf; 4599 dma_addr_t addr; 4600 u32 status; 4601 4602 status = le32_to_cpu(READ_ONCE(desc->opts1)); 4603 if (status & DescOwn) 4604 break; 4605 4606 /* This barrier is needed to keep us from reading 4607 * any other fields out of the Rx descriptor until 4608 * we know the status of DescOwn 4609 */ 4610 dma_rmb(); 4611 4612 if (unlikely(status & RxRES)) { 4613 if (net_ratelimit()) 4614 netdev_warn(dev, "Rx ERROR. status = %08x\n", 4615 status); 4616 dev->stats.rx_errors++; 4617 if (status & (RxRWT | RxRUNT)) 4618 dev->stats.rx_length_errors++; 4619 if (status & RxCRC) 4620 dev->stats.rx_crc_errors++; 4621 4622 if (!(dev->features & NETIF_F_RXALL)) 4623 goto release_descriptor; 4624 else if (status & RxRWT || !(status & (RxRUNT | RxCRC))) 4625 goto release_descriptor; 4626 } 4627 4628 pkt_size = status & GENMASK(13, 0); 4629 if (likely(!(dev->features & NETIF_F_RXFCS))) 4630 pkt_size -= ETH_FCS_LEN; 4631 4632 /* The driver does not support incoming fragmented frames. 4633 * They are seen as a symptom of over-mtu sized frames. 4634 */ 4635 if (unlikely(rtl8169_fragmented_frame(status))) { 4636 dev->stats.rx_dropped++; 4637 dev->stats.rx_length_errors++; 4638 goto release_descriptor; 4639 } 4640 4641 skb = napi_alloc_skb(&tp->napi, pkt_size); 4642 if (unlikely(!skb)) { 4643 dev->stats.rx_dropped++; 4644 goto release_descriptor; 4645 } 4646 4647 addr = le64_to_cpu(desc->addr); 4648 rx_buf = page_address(tp->Rx_databuff[entry]); 4649 4650 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE); 4651 prefetch(rx_buf); 4652 skb_copy_to_linear_data(skb, rx_buf, pkt_size); 4653 skb->tail += pkt_size; 4654 skb->len = pkt_size; 4655 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE); 4656 4657 rtl8169_rx_csum(skb, status); 4658 skb->protocol = eth_type_trans(skb, dev); 4659 4660 rtl8169_rx_vlan_tag(desc, skb); 4661 4662 if (skb->pkt_type == PACKET_MULTICAST) 4663 dev->stats.multicast++; 4664 4665 napi_gro_receive(&tp->napi, skb); 4666 4667 dev_sw_netstats_rx_add(dev, pkt_size); 4668 release_descriptor: 4669 rtl8169_mark_to_asic(desc); 4670 } 4671 4672 return count; 4673 } 4674 4675 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance) 4676 { 4677 struct rtl8169_private *tp = dev_instance; 4678 u32 status = rtl_get_events(tp); 4679 4680 if ((status & 0xffff) == 0xffff || !(status & tp->irq_mask)) 4681 return IRQ_NONE; 4682 4683 /* At least RTL8168fp may unexpectedly set the SYSErr bit */ 4684 if (unlikely(status & SYSErr && 4685 tp->mac_version <= RTL_GIGA_MAC_VER_06)) { 4686 rtl8169_pcierr_interrupt(tp->dev); 4687 goto out; 4688 } 4689 4690 if (status & LinkChg) 4691 phy_mac_interrupt(tp->phydev); 4692 4693 rtl_irq_disable(tp); 4694 napi_schedule(&tp->napi); 4695 out: 4696 rtl_ack_events(tp, status); 4697 4698 return IRQ_HANDLED; 4699 } 4700 4701 static void rtl_task(struct work_struct *work) 4702 { 4703 struct rtl8169_private *tp = 4704 container_of(work, struct rtl8169_private, wk.work); 4705 int ret; 4706 4707 if (test_and_clear_bit(RTL_FLAG_TASK_TX_TIMEOUT, tp->wk.flags)) { 4708 /* if chip isn't accessible, reset bus to revive it */ 4709 if (RTL_R32(tp, TxConfig) == ~0) { 4710 ret = pci_reset_bus(tp->pci_dev); 4711 if (ret < 0) { 4712 netdev_err(tp->dev, "Can't reset secondary PCI bus, detach NIC\n"); 4713 netif_device_detach(tp->dev); 4714 return; 4715 } 4716 } 4717 4718 /* ASPM compatibility issues are a typical reason for tx timeouts */ 4719 ret = pci_disable_link_state(tp->pci_dev, PCIE_LINK_STATE_L1 | 4720 PCIE_LINK_STATE_L0S); 4721 if (!ret) 4722 netdev_warn_once(tp->dev, "ASPM disabled on Tx timeout\n"); 4723 goto reset; 4724 } 4725 4726 if (test_and_clear_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags)) { 4727 reset: 4728 rtl_reset_work(tp); 4729 netif_wake_queue(tp->dev); 4730 } 4731 } 4732 4733 static int rtl8169_poll(struct napi_struct *napi, int budget) 4734 { 4735 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi); 4736 struct net_device *dev = tp->dev; 4737 int work_done; 4738 4739 rtl_tx(dev, tp, budget); 4740 4741 work_done = rtl_rx(dev, tp, budget); 4742 4743 if (work_done < budget && napi_complete_done(napi, work_done)) 4744 rtl_irq_enable(tp); 4745 4746 return work_done; 4747 } 4748 4749 static void r8169_phylink_handler(struct net_device *ndev) 4750 { 4751 struct rtl8169_private *tp = netdev_priv(ndev); 4752 struct device *d = tp_to_dev(tp); 4753 4754 if (netif_carrier_ok(ndev)) { 4755 rtl_link_chg_patch(tp); 4756 pm_request_resume(d); 4757 } else { 4758 pm_runtime_idle(d); 4759 } 4760 4761 phy_print_status(tp->phydev); 4762 } 4763 4764 static int r8169_phy_connect(struct rtl8169_private *tp) 4765 { 4766 struct phy_device *phydev = tp->phydev; 4767 phy_interface_t phy_mode; 4768 int ret; 4769 4770 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII : 4771 PHY_INTERFACE_MODE_MII; 4772 4773 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler, 4774 phy_mode); 4775 if (ret) 4776 return ret; 4777 4778 if (!tp->supports_gmii) 4779 phy_set_max_speed(phydev, SPEED_100); 4780 4781 phy_attached_info(phydev); 4782 4783 return 0; 4784 } 4785 4786 static void rtl8169_down(struct rtl8169_private *tp) 4787 { 4788 disable_work_sync(&tp->wk.work); 4789 /* Clear all task flags */ 4790 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX); 4791 4792 phy_stop(tp->phydev); 4793 4794 rtl8169_update_counters(tp); 4795 4796 pci_clear_master(tp->pci_dev); 4797 rtl_pci_commit(tp); 4798 4799 rtl8169_cleanup(tp); 4800 rtl_disable_exit_l1(tp); 4801 rtl_prepare_power_down(tp); 4802 4803 if (tp->dash_type != RTL_DASH_NONE) 4804 rtl8168_driver_stop(tp); 4805 } 4806 4807 static void rtl8169_up(struct rtl8169_private *tp) 4808 { 4809 if (tp->dash_type != RTL_DASH_NONE) 4810 rtl8168_driver_start(tp); 4811 4812 pci_set_master(tp->pci_dev); 4813 phy_init_hw(tp->phydev); 4814 phy_resume(tp->phydev); 4815 rtl8169_init_phy(tp); 4816 napi_enable(&tp->napi); 4817 enable_work(&tp->wk.work); 4818 rtl_reset_work(tp); 4819 4820 phy_start(tp->phydev); 4821 } 4822 4823 static int rtl8169_close(struct net_device *dev) 4824 { 4825 struct rtl8169_private *tp = netdev_priv(dev); 4826 struct pci_dev *pdev = tp->pci_dev; 4827 4828 pm_runtime_get_sync(&pdev->dev); 4829 4830 netif_stop_queue(dev); 4831 rtl8169_down(tp); 4832 rtl8169_rx_clear(tp); 4833 4834 free_irq(tp->irq, tp); 4835 4836 phy_disconnect(tp->phydev); 4837 4838 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4839 tp->RxPhyAddr); 4840 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 4841 tp->TxPhyAddr); 4842 tp->TxDescArray = NULL; 4843 tp->RxDescArray = NULL; 4844 4845 pm_runtime_put_sync(&pdev->dev); 4846 4847 return 0; 4848 } 4849 4850 #ifdef CONFIG_NET_POLL_CONTROLLER 4851 static void rtl8169_netpoll(struct net_device *dev) 4852 { 4853 struct rtl8169_private *tp = netdev_priv(dev); 4854 4855 rtl8169_interrupt(tp->irq, tp); 4856 } 4857 #endif 4858 4859 static int rtl_open(struct net_device *dev) 4860 { 4861 struct rtl8169_private *tp = netdev_priv(dev); 4862 struct pci_dev *pdev = tp->pci_dev; 4863 unsigned long irqflags; 4864 int retval = -ENOMEM; 4865 4866 pm_runtime_get_sync(&pdev->dev); 4867 4868 /* 4869 * Rx and Tx descriptors needs 256 bytes alignment. 4870 * dma_alloc_coherent provides more. 4871 */ 4872 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES, 4873 &tp->TxPhyAddr, GFP_KERNEL); 4874 if (!tp->TxDescArray) 4875 goto out; 4876 4877 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES, 4878 &tp->RxPhyAddr, GFP_KERNEL); 4879 if (!tp->RxDescArray) 4880 goto err_free_tx_0; 4881 4882 retval = rtl8169_init_ring(tp); 4883 if (retval < 0) 4884 goto err_free_rx_1; 4885 4886 rtl_request_firmware(tp); 4887 4888 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_NO_THREAD : IRQF_SHARED; 4889 retval = request_irq(tp->irq, rtl8169_interrupt, irqflags, dev->name, tp); 4890 if (retval < 0) 4891 goto err_release_fw_2; 4892 4893 retval = r8169_phy_connect(tp); 4894 if (retval) 4895 goto err_free_irq; 4896 4897 rtl8169_up(tp); 4898 rtl8169_init_counter_offsets(tp); 4899 netif_start_queue(dev); 4900 out: 4901 pm_runtime_put_sync(&pdev->dev); 4902 4903 return retval; 4904 4905 err_free_irq: 4906 free_irq(tp->irq, tp); 4907 err_release_fw_2: 4908 rtl_release_firmware(tp); 4909 rtl8169_rx_clear(tp); 4910 err_free_rx_1: 4911 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4912 tp->RxPhyAddr); 4913 tp->RxDescArray = NULL; 4914 err_free_tx_0: 4915 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 4916 tp->TxPhyAddr); 4917 tp->TxDescArray = NULL; 4918 goto out; 4919 } 4920 4921 static void 4922 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 4923 { 4924 struct rtl8169_private *tp = netdev_priv(dev); 4925 struct pci_dev *pdev = tp->pci_dev; 4926 struct rtl8169_counters *counters = tp->counters; 4927 4928 pm_runtime_get_noresume(&pdev->dev); 4929 4930 netdev_stats_to_stats64(stats, &dev->stats); 4931 dev_fetch_sw_netstats(stats, dev->tstats); 4932 4933 /* 4934 * Fetch additional counter values missing in stats collected by driver 4935 * from tally counters. 4936 */ 4937 if (pm_runtime_active(&pdev->dev)) 4938 rtl8169_update_counters(tp); 4939 4940 /* 4941 * Subtract values fetched during initalization. 4942 * See rtl8169_init_counter_offsets for a description why we do that. 4943 */ 4944 stats->tx_errors = le64_to_cpu(counters->tx_errors) - 4945 le64_to_cpu(tp->tc_offset.tx_errors); 4946 stats->collisions = le32_to_cpu(counters->tx_multi_collision) - 4947 le32_to_cpu(tp->tc_offset.tx_multi_collision); 4948 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) - 4949 le16_to_cpu(tp->tc_offset.tx_aborted); 4950 stats->rx_missed_errors = le16_to_cpu(counters->rx_missed) - 4951 le16_to_cpu(tp->tc_offset.rx_missed); 4952 4953 pm_runtime_put_noidle(&pdev->dev); 4954 } 4955 4956 static void rtl8169_net_suspend(struct rtl8169_private *tp) 4957 { 4958 netif_device_detach(tp->dev); 4959 4960 if (netif_running(tp->dev)) 4961 rtl8169_down(tp); 4962 } 4963 4964 static int rtl8169_runtime_resume(struct device *dev) 4965 { 4966 struct rtl8169_private *tp = dev_get_drvdata(dev); 4967 4968 rtl_rar_set(tp, tp->dev->dev_addr); 4969 __rtl8169_set_wol(tp, tp->saved_wolopts); 4970 4971 if (tp->TxDescArray) 4972 rtl8169_up(tp); 4973 4974 netif_device_attach(tp->dev); 4975 4976 return 0; 4977 } 4978 4979 static int rtl8169_suspend(struct device *device) 4980 { 4981 struct rtl8169_private *tp = dev_get_drvdata(device); 4982 4983 rtnl_lock(); 4984 rtl8169_net_suspend(tp); 4985 if (!device_may_wakeup(tp_to_dev(tp))) 4986 clk_disable_unprepare(tp->clk); 4987 rtnl_unlock(); 4988 4989 return 0; 4990 } 4991 4992 static int rtl8169_resume(struct device *device) 4993 { 4994 struct rtl8169_private *tp = dev_get_drvdata(device); 4995 4996 if (!device_may_wakeup(tp_to_dev(tp))) 4997 clk_prepare_enable(tp->clk); 4998 4999 /* Reportedly at least Asus X453MA truncates packets otherwise */ 5000 if (tp->mac_version == RTL_GIGA_MAC_VER_37) 5001 rtl_init_rxcfg(tp); 5002 5003 return rtl8169_runtime_resume(device); 5004 } 5005 5006 static int rtl8169_runtime_suspend(struct device *device) 5007 { 5008 struct rtl8169_private *tp = dev_get_drvdata(device); 5009 5010 if (!tp->TxDescArray) { 5011 netif_device_detach(tp->dev); 5012 return 0; 5013 } 5014 5015 rtnl_lock(); 5016 __rtl8169_set_wol(tp, WAKE_PHY); 5017 rtl8169_net_suspend(tp); 5018 rtnl_unlock(); 5019 5020 return 0; 5021 } 5022 5023 static int rtl8169_runtime_idle(struct device *device) 5024 { 5025 struct rtl8169_private *tp = dev_get_drvdata(device); 5026 5027 if (tp->dash_enabled) 5028 return -EBUSY; 5029 5030 if (!netif_running(tp->dev) || !netif_carrier_ok(tp->dev)) 5031 pm_schedule_suspend(device, 10000); 5032 5033 return -EBUSY; 5034 } 5035 5036 static const struct dev_pm_ops rtl8169_pm_ops = { 5037 SYSTEM_SLEEP_PM_OPS(rtl8169_suspend, rtl8169_resume) 5038 RUNTIME_PM_OPS(rtl8169_runtime_suspend, rtl8169_runtime_resume, 5039 rtl8169_runtime_idle) 5040 }; 5041 5042 static void rtl_shutdown(struct pci_dev *pdev) 5043 { 5044 struct rtl8169_private *tp = pci_get_drvdata(pdev); 5045 5046 rtnl_lock(); 5047 rtl8169_net_suspend(tp); 5048 rtnl_unlock(); 5049 5050 /* Restore original MAC address */ 5051 rtl_rar_set(tp, tp->dev->perm_addr); 5052 5053 if (system_state == SYSTEM_POWER_OFF && !tp->dash_enabled) 5054 pci_prepare_to_sleep(pdev); 5055 } 5056 5057 static void rtl_remove_one(struct pci_dev *pdev) 5058 { 5059 struct rtl8169_private *tp = pci_get_drvdata(pdev); 5060 5061 if (pci_dev_run_wake(pdev)) 5062 pm_runtime_get_noresume(&pdev->dev); 5063 5064 disable_work_sync(&tp->wk.work); 5065 5066 if (IS_ENABLED(CONFIG_R8169_LEDS)) 5067 r8169_remove_leds(tp->leds); 5068 5069 unregister_netdev(tp->dev); 5070 5071 if (tp->dash_type != RTL_DASH_NONE) 5072 rtl8168_driver_stop(tp); 5073 5074 rtl_release_firmware(tp); 5075 5076 /* restore original MAC address */ 5077 rtl_rar_set(tp, tp->dev->perm_addr); 5078 } 5079 5080 static const struct net_device_ops rtl_netdev_ops = { 5081 .ndo_open = rtl_open, 5082 .ndo_stop = rtl8169_close, 5083 .ndo_get_stats64 = rtl8169_get_stats64, 5084 .ndo_start_xmit = rtl8169_start_xmit, 5085 .ndo_features_check = rtl8169_features_check, 5086 .ndo_tx_timeout = rtl8169_tx_timeout, 5087 .ndo_validate_addr = eth_validate_addr, 5088 .ndo_change_mtu = rtl8169_change_mtu, 5089 .ndo_fix_features = rtl8169_fix_features, 5090 .ndo_set_features = rtl8169_set_features, 5091 .ndo_set_mac_address = rtl_set_mac_address, 5092 .ndo_eth_ioctl = phy_do_ioctl_running, 5093 .ndo_set_rx_mode = rtl_set_rx_mode, 5094 #ifdef CONFIG_NET_POLL_CONTROLLER 5095 .ndo_poll_controller = rtl8169_netpoll, 5096 #endif 5097 5098 }; 5099 5100 static void rtl_set_irq_mask(struct rtl8169_private *tp) 5101 { 5102 tp->irq_mask = RxOK | RxErr | TxOK | TxErr | LinkChg; 5103 5104 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 5105 tp->irq_mask |= SYSErr | RxFIFOOver; 5106 } 5107 5108 static int rtl_alloc_irq(struct rtl8169_private *tp) 5109 { 5110 unsigned int flags; 5111 5112 switch (tp->mac_version) { 5113 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 5114 rtl_unlock_config_regs(tp); 5115 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable); 5116 rtl_lock_config_regs(tp); 5117 fallthrough; 5118 case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_17: 5119 flags = PCI_IRQ_INTX; 5120 break; 5121 default: 5122 flags = PCI_IRQ_ALL_TYPES; 5123 break; 5124 } 5125 5126 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags); 5127 } 5128 5129 static void rtl_read_mac_address(struct rtl8169_private *tp, 5130 u8 mac_addr[ETH_ALEN]) 5131 { 5132 /* Get MAC address */ 5133 if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) { 5134 u32 value; 5135 5136 value = rtl_eri_read(tp, 0xe0); 5137 put_unaligned_le32(value, mac_addr); 5138 value = rtl_eri_read(tp, 0xe4); 5139 put_unaligned_le16(value, mac_addr + 4); 5140 } else if (rtl_is_8125(tp)) { 5141 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP); 5142 } 5143 } 5144 5145 DECLARE_RTL_COND(rtl_link_list_ready_cond) 5146 { 5147 return RTL_R8(tp, MCU) & LINK_LIST_RDY; 5148 } 5149 5150 static void r8168g_wait_ll_share_fifo_ready(struct rtl8169_private *tp) 5151 { 5152 rtl_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42); 5153 } 5154 5155 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg) 5156 { 5157 struct rtl8169_private *tp = mii_bus->priv; 5158 5159 if (phyaddr > 0) 5160 return -ENODEV; 5161 5162 return rtl_readphy(tp, phyreg); 5163 } 5164 5165 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr, 5166 int phyreg, u16 val) 5167 { 5168 struct rtl8169_private *tp = mii_bus->priv; 5169 5170 if (phyaddr > 0) 5171 return -ENODEV; 5172 5173 rtl_writephy(tp, phyreg, val); 5174 5175 return 0; 5176 } 5177 5178 static int r8169_mdio_read_reg_c45(struct mii_bus *mii_bus, int addr, 5179 int devnum, int regnum) 5180 { 5181 struct rtl8169_private *tp = mii_bus->priv; 5182 5183 if (addr > 0) 5184 return -ENODEV; 5185 5186 if (devnum == MDIO_MMD_VEND2 && regnum > MDIO_STAT2) 5187 return r8168_phy_ocp_read(tp, regnum); 5188 5189 return 0; 5190 } 5191 5192 static int r8169_mdio_write_reg_c45(struct mii_bus *mii_bus, int addr, 5193 int devnum, int regnum, u16 val) 5194 { 5195 struct rtl8169_private *tp = mii_bus->priv; 5196 5197 if (addr > 0 || devnum != MDIO_MMD_VEND2 || regnum <= MDIO_STAT2) 5198 return -ENODEV; 5199 5200 r8168_phy_ocp_write(tp, regnum, val); 5201 5202 return 0; 5203 } 5204 5205 static int r8169_mdio_register(struct rtl8169_private *tp) 5206 { 5207 struct pci_dev *pdev = tp->pci_dev; 5208 struct mii_bus *new_bus; 5209 int ret; 5210 5211 /* On some boards with this chip version the BIOS is buggy and misses 5212 * to reset the PHY page selector. This results in the PHY ID read 5213 * accessing registers on a different page, returning a more or 5214 * less random value. Fix this by resetting the page selector first. 5215 */ 5216 if (tp->mac_version == RTL_GIGA_MAC_VER_25 || 5217 tp->mac_version == RTL_GIGA_MAC_VER_26) 5218 r8169_mdio_write(tp, 0x1f, 0); 5219 5220 new_bus = devm_mdiobus_alloc(&pdev->dev); 5221 if (!new_bus) 5222 return -ENOMEM; 5223 5224 new_bus->name = "r8169"; 5225 new_bus->priv = tp; 5226 new_bus->parent = &pdev->dev; 5227 new_bus->irq[0] = PHY_MAC_INTERRUPT; 5228 new_bus->phy_mask = GENMASK(31, 1); 5229 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x-%x", 5230 pci_domain_nr(pdev->bus), pci_dev_id(pdev)); 5231 5232 new_bus->read = r8169_mdio_read_reg; 5233 new_bus->write = r8169_mdio_write_reg; 5234 5235 if (tp->mac_version >= RTL_GIGA_MAC_VER_40) { 5236 new_bus->read_c45 = r8169_mdio_read_reg_c45; 5237 new_bus->write_c45 = r8169_mdio_write_reg_c45; 5238 } 5239 5240 ret = devm_mdiobus_register(&pdev->dev, new_bus); 5241 if (ret) 5242 return ret; 5243 5244 tp->phydev = mdiobus_get_phy(new_bus, 0); 5245 if (!tp->phydev) { 5246 return -ENODEV; 5247 } else if (!tp->phydev->drv) { 5248 /* Most chip versions fail with the genphy driver. 5249 * Therefore ensure that the dedicated PHY driver is loaded. 5250 */ 5251 dev_err(&pdev->dev, "no dedicated PHY driver found for PHY ID 0x%08x, maybe realtek.ko needs to be added to initramfs?\n", 5252 tp->phydev->phy_id); 5253 return -EUNATCH; 5254 } 5255 5256 tp->phydev->mac_managed_pm = true; 5257 if (rtl_supports_eee(tp)) 5258 phy_support_eee(tp->phydev); 5259 phy_support_asym_pause(tp->phydev); 5260 5261 /* mimic behavior of r8125/r8126 vendor drivers */ 5262 if (tp->mac_version == RTL_GIGA_MAC_VER_61) 5263 phy_disable_eee_mode(tp->phydev, 5264 ETHTOOL_LINK_MODE_2500baseT_Full_BIT); 5265 phy_disable_eee_mode(tp->phydev, ETHTOOL_LINK_MODE_5000baseT_Full_BIT); 5266 5267 /* PHY will be woken up in rtl_open() */ 5268 phy_suspend(tp->phydev); 5269 5270 return 0; 5271 } 5272 5273 static void rtl_hw_init_8168g(struct rtl8169_private *tp) 5274 { 5275 rtl_enable_rxdvgate(tp); 5276 5277 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5278 msleep(1); 5279 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5280 5281 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5282 r8168g_wait_ll_share_fifo_ready(tp); 5283 5284 r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15)); 5285 r8168g_wait_ll_share_fifo_ready(tp); 5286 } 5287 5288 static void rtl_hw_init_8125(struct rtl8169_private *tp) 5289 { 5290 rtl_enable_rxdvgate(tp); 5291 5292 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5293 msleep(1); 5294 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5295 5296 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5297 r8168g_wait_ll_share_fifo_ready(tp); 5298 5299 r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0); 5300 r8168_mac_ocp_write(tp, 0xc0a6, 0x0150); 5301 r8168_mac_ocp_write(tp, 0xc01e, 0x5555); 5302 r8168g_wait_ll_share_fifo_ready(tp); 5303 } 5304 5305 static void rtl_hw_initialize(struct rtl8169_private *tp) 5306 { 5307 switch (tp->mac_version) { 5308 case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_52: 5309 rtl8168ep_stop_cmac(tp); 5310 fallthrough; 5311 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48: 5312 rtl_hw_init_8168g(tp); 5313 break; 5314 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_LAST: 5315 rtl_hw_init_8125(tp); 5316 break; 5317 default: 5318 break; 5319 } 5320 } 5321 5322 static int rtl_jumbo_max(struct rtl8169_private *tp) 5323 { 5324 /* Non-GBit versions don't support jumbo frames */ 5325 if (!tp->supports_gmii) 5326 return 0; 5327 5328 switch (tp->mac_version) { 5329 /* RTL8169 */ 5330 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 5331 return JUMBO_7K; 5332 /* RTL8168b */ 5333 case RTL_GIGA_MAC_VER_17: 5334 return JUMBO_4K; 5335 /* RTL8168c */ 5336 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 5337 return JUMBO_6K; 5338 /* RTL8125/8126 */ 5339 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_LAST: 5340 return JUMBO_16K; 5341 default: 5342 return JUMBO_9K; 5343 } 5344 } 5345 5346 static void rtl_init_mac_address(struct rtl8169_private *tp) 5347 { 5348 u8 mac_addr[ETH_ALEN] __aligned(2) = {}; 5349 struct net_device *dev = tp->dev; 5350 int rc; 5351 5352 rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr); 5353 if (!rc) 5354 goto done; 5355 5356 rtl_read_mac_address(tp, mac_addr); 5357 if (is_valid_ether_addr(mac_addr)) 5358 goto done; 5359 5360 rtl_read_mac_from_reg(tp, mac_addr, MAC0); 5361 if (is_valid_ether_addr(mac_addr)) 5362 goto done; 5363 5364 eth_random_addr(mac_addr); 5365 dev->addr_assign_type = NET_ADDR_RANDOM; 5366 dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n"); 5367 done: 5368 eth_hw_addr_set(dev, mac_addr); 5369 rtl_rar_set(tp, mac_addr); 5370 } 5371 5372 /* register is set if system vendor successfully tested ASPM 1.2 */ 5373 static bool rtl_aspm_is_safe(struct rtl8169_private *tp) 5374 { 5375 if (tp->mac_version >= RTL_GIGA_MAC_VER_46 && 5376 r8168_mac_ocp_read(tp, 0xc0b2) & 0xf) 5377 return true; 5378 5379 return false; 5380 } 5381 5382 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 5383 { 5384 const struct rtl_chip_info *chip; 5385 struct rtl8169_private *tp; 5386 int jumbo_max, region, rc; 5387 struct net_device *dev; 5388 u32 txconfig; 5389 u16 xid; 5390 5391 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp)); 5392 if (!dev) 5393 return -ENOMEM; 5394 5395 SET_NETDEV_DEV(dev, &pdev->dev); 5396 dev->netdev_ops = &rtl_netdev_ops; 5397 tp = netdev_priv(dev); 5398 tp->dev = dev; 5399 tp->pci_dev = pdev; 5400 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1; 5401 tp->ocp_base = OCP_STD_PHY_BASE; 5402 5403 raw_spin_lock_init(&tp->mac_ocp_lock); 5404 mutex_init(&tp->led_lock); 5405 5406 /* Get the *optional* external "ether_clk" used on some boards */ 5407 tp->clk = devm_clk_get_optional_enabled(&pdev->dev, "ether_clk"); 5408 if (IS_ERR(tp->clk)) 5409 return dev_err_probe(&pdev->dev, PTR_ERR(tp->clk), "failed to get ether_clk\n"); 5410 5411 /* enable device (incl. PCI PM wakeup and hotplug setup) */ 5412 rc = pcim_enable_device(pdev); 5413 if (rc < 0) 5414 return dev_err_probe(&pdev->dev, rc, "enable failure\n"); 5415 5416 if (pcim_set_mwi(pdev) < 0) 5417 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n"); 5418 5419 /* use first MMIO region */ 5420 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1; 5421 if (region < 0) 5422 return dev_err_probe(&pdev->dev, -ENODEV, "no MMIO resource found\n"); 5423 5424 tp->mmio_addr = pcim_iomap_region(pdev, region, KBUILD_MODNAME); 5425 if (IS_ERR(tp->mmio_addr)) 5426 return dev_err_probe(&pdev->dev, PTR_ERR(tp->mmio_addr), 5427 "cannot remap MMIO, aborting\n"); 5428 5429 txconfig = RTL_R32(tp, TxConfig); 5430 if (txconfig == ~0U) 5431 return dev_err_probe(&pdev->dev, -EIO, "PCI read failed\n"); 5432 5433 xid = (txconfig >> 20) & 0xfcf; 5434 5435 /* Identify chip attached to board */ 5436 chip = rtl8169_get_chip_version(xid, tp->supports_gmii); 5437 if (chip->mac_version == RTL_GIGA_MAC_NONE) 5438 return dev_err_probe(&pdev->dev, -ENODEV, 5439 "unknown chip XID %03x, contact r8169 maintainers (see MAINTAINERS file)\n", 5440 xid); 5441 tp->mac_version = chip->mac_version; 5442 tp->fw_name = chip->fw_name; 5443 5444 /* Disable ASPM L1 as that cause random device stop working 5445 * problems as well as full system hangs for some PCIe devices users. 5446 */ 5447 if (rtl_aspm_is_safe(tp)) 5448 rc = 0; 5449 else 5450 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L1); 5451 tp->aspm_manageable = !rc; 5452 5453 tp->dash_type = rtl_get_dash_type(tp); 5454 tp->dash_enabled = rtl_dash_is_enabled(tp); 5455 5456 tp->cp_cmd = RTL_R16(tp, CPlusCmd) & CPCMD_MASK; 5457 5458 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 && 5459 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) 5460 dev->features |= NETIF_F_HIGHDMA; 5461 5462 rtl_init_rxcfg(tp); 5463 5464 rtl8169_irq_mask_and_ack(tp); 5465 5466 rtl_hw_initialize(tp); 5467 5468 rtl_hw_reset(tp); 5469 5470 rc = rtl_alloc_irq(tp); 5471 if (rc < 0) 5472 return dev_err_probe(&pdev->dev, rc, "Can't allocate interrupt\n"); 5473 5474 tp->irq = pci_irq_vector(pdev, 0); 5475 5476 INIT_WORK(&tp->wk.work, rtl_task); 5477 disable_work(&tp->wk.work); 5478 5479 rtl_init_mac_address(tp); 5480 5481 dev->ethtool_ops = &rtl8169_ethtool_ops; 5482 5483 netif_napi_add(dev, &tp->napi, rtl8169_poll); 5484 5485 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM | 5486 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; 5487 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO; 5488 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; 5489 5490 /* 5491 * Pretend we are using VLANs; This bypasses a nasty bug where 5492 * Interrupts stop flowing on high load on 8110SCd controllers. 5493 */ 5494 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 5495 /* Disallow toggling */ 5496 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX; 5497 5498 if (rtl_chip_supports_csum_v2(tp)) 5499 dev->hw_features |= NETIF_F_IPV6_CSUM; 5500 5501 dev->features |= dev->hw_features; 5502 5503 if (rtl_chip_supports_csum_v2(tp)) { 5504 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6; 5505 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V2); 5506 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V2); 5507 } else { 5508 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO; 5509 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V1); 5510 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V1); 5511 } 5512 5513 /* There has been a number of reports that using SG/TSO results in 5514 * tx timeouts. However for a lot of people SG/TSO works fine. 5515 * It's not fully clear which chip versions are affected. Vendor 5516 * drivers enable SG/TSO for certain chip versions per default, 5517 * let's mimic this here. On other chip versions users can 5518 * use ethtool to enable SG/TSO, use at own risk! 5519 */ 5520 if (tp->mac_version >= RTL_GIGA_MAC_VER_46 && 5521 tp->mac_version != RTL_GIGA_MAC_VER_61) 5522 dev->features |= dev->hw_features; 5523 5524 dev->hw_features |= NETIF_F_RXALL; 5525 dev->hw_features |= NETIF_F_RXFCS; 5526 5527 dev->pcpu_stat_type = NETDEV_PCPU_STAT_TSTATS; 5528 5529 netdev_sw_irq_coalesce_default_on(dev); 5530 5531 /* configure chip for default features */ 5532 rtl8169_set_features(dev, dev->features); 5533 5534 if (!tp->dash_enabled) { 5535 rtl_set_d3_pll_down(tp, true); 5536 } else { 5537 rtl_set_d3_pll_down(tp, false); 5538 dev->ethtool->wol_enabled = 1; 5539 } 5540 5541 jumbo_max = rtl_jumbo_max(tp); 5542 if (jumbo_max) 5543 dev->max_mtu = jumbo_max; 5544 5545 rtl_set_irq_mask(tp); 5546 5547 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters), 5548 &tp->counters_phys_addr, 5549 GFP_KERNEL); 5550 if (!tp->counters) 5551 return -ENOMEM; 5552 5553 pci_set_drvdata(pdev, tp); 5554 5555 rc = r8169_mdio_register(tp); 5556 if (rc) 5557 return rc; 5558 5559 rc = register_netdev(dev); 5560 if (rc) 5561 return rc; 5562 5563 if (IS_ENABLED(CONFIG_R8169_LEDS)) { 5564 if (rtl_is_8125(tp)) 5565 tp->leds = rtl8125_init_leds(dev); 5566 else if (tp->mac_version > RTL_GIGA_MAC_VER_06) 5567 tp->leds = rtl8168_init_leds(dev); 5568 } 5569 5570 netdev_info(dev, "%s, %pM, XID %03x, IRQ %d\n", 5571 chip->name, dev->dev_addr, xid, tp->irq); 5572 5573 if (jumbo_max) 5574 netdev_info(dev, "jumbo features [frames: %d bytes, tx checksumming: %s]\n", 5575 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ? 5576 "ok" : "ko"); 5577 5578 if (tp->dash_type != RTL_DASH_NONE) { 5579 netdev_info(dev, "DASH %s\n", 5580 tp->dash_enabled ? "enabled" : "disabled"); 5581 rtl8168_driver_start(tp); 5582 } 5583 5584 if (pci_dev_run_wake(pdev)) 5585 pm_runtime_put_sync(&pdev->dev); 5586 5587 return 0; 5588 } 5589 5590 static struct pci_driver rtl8169_pci_driver = { 5591 .name = KBUILD_MODNAME, 5592 .id_table = rtl8169_pci_tbl, 5593 .probe = rtl_init_one, 5594 .remove = rtl_remove_one, 5595 .shutdown = rtl_shutdown, 5596 .driver.pm = pm_ptr(&rtl8169_pm_ops), 5597 }; 5598 5599 module_pci_driver(rtl8169_pci_driver); 5600