1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright (c) 2021, Microsoft Corporation. */ 3 4 #include <linux/debugfs.h> 5 #include <linux/module.h> 6 #include <linux/pci.h> 7 #include <linux/utsname.h> 8 #include <linux/version.h> 9 #include <linux/export.h> 10 11 #include <net/mana/mana.h> 12 13 struct dentry *mana_debugfs_root; 14 15 static u32 mana_gd_r32(struct gdma_context *g, u64 offset) 16 { 17 return readl(g->bar0_va + offset); 18 } 19 20 static u64 mana_gd_r64(struct gdma_context *g, u64 offset) 21 { 22 return readq(g->bar0_va + offset); 23 } 24 25 static void mana_gd_init_pf_regs(struct pci_dev *pdev) 26 { 27 struct gdma_context *gc = pci_get_drvdata(pdev); 28 void __iomem *sriov_base_va; 29 u64 sriov_base_off; 30 31 gc->db_page_size = mana_gd_r32(gc, GDMA_PF_REG_DB_PAGE_SIZE) & 0xFFFF; 32 gc->db_page_base = gc->bar0_va + 33 mana_gd_r64(gc, GDMA_PF_REG_DB_PAGE_OFF); 34 35 gc->phys_db_page_base = gc->bar0_pa + 36 mana_gd_r64(gc, GDMA_PF_REG_DB_PAGE_OFF); 37 38 sriov_base_off = mana_gd_r64(gc, GDMA_SRIOV_REG_CFG_BASE_OFF); 39 40 sriov_base_va = gc->bar0_va + sriov_base_off; 41 gc->shm_base = sriov_base_va + 42 mana_gd_r64(gc, sriov_base_off + GDMA_PF_REG_SHM_OFF); 43 } 44 45 static void mana_gd_init_vf_regs(struct pci_dev *pdev) 46 { 47 struct gdma_context *gc = pci_get_drvdata(pdev); 48 49 gc->db_page_size = mana_gd_r32(gc, GDMA_REG_DB_PAGE_SIZE) & 0xFFFF; 50 51 gc->db_page_base = gc->bar0_va + 52 mana_gd_r64(gc, GDMA_REG_DB_PAGE_OFFSET); 53 54 gc->phys_db_page_base = gc->bar0_pa + 55 mana_gd_r64(gc, GDMA_REG_DB_PAGE_OFFSET); 56 57 gc->shm_base = gc->bar0_va + mana_gd_r64(gc, GDMA_REG_SHM_OFFSET); 58 } 59 60 static void mana_gd_init_registers(struct pci_dev *pdev) 61 { 62 struct gdma_context *gc = pci_get_drvdata(pdev); 63 64 if (gc->is_pf) 65 mana_gd_init_pf_regs(pdev); 66 else 67 mana_gd_init_vf_regs(pdev); 68 } 69 70 static int mana_gd_query_max_resources(struct pci_dev *pdev) 71 { 72 struct gdma_context *gc = pci_get_drvdata(pdev); 73 struct gdma_query_max_resources_resp resp = {}; 74 struct gdma_general_req req = {}; 75 int err; 76 77 mana_gd_init_req_hdr(&req.hdr, GDMA_QUERY_MAX_RESOURCES, 78 sizeof(req), sizeof(resp)); 79 80 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 81 if (err || resp.hdr.status) { 82 dev_err(gc->dev, "Failed to query resource info: %d, 0x%x\n", 83 err, resp.hdr.status); 84 return err ? err : -EPROTO; 85 } 86 87 if (gc->num_msix_usable > resp.max_msix) 88 gc->num_msix_usable = resp.max_msix; 89 90 if (gc->num_msix_usable <= 1) 91 return -ENOSPC; 92 93 gc->max_num_queues = num_online_cpus(); 94 if (gc->max_num_queues > MANA_MAX_NUM_QUEUES) 95 gc->max_num_queues = MANA_MAX_NUM_QUEUES; 96 97 if (gc->max_num_queues > resp.max_eq) 98 gc->max_num_queues = resp.max_eq; 99 100 if (gc->max_num_queues > resp.max_cq) 101 gc->max_num_queues = resp.max_cq; 102 103 if (gc->max_num_queues > resp.max_sq) 104 gc->max_num_queues = resp.max_sq; 105 106 if (gc->max_num_queues > resp.max_rq) 107 gc->max_num_queues = resp.max_rq; 108 109 /* The Hardware Channel (HWC) used 1 MSI-X */ 110 if (gc->max_num_queues > gc->num_msix_usable - 1) 111 gc->max_num_queues = gc->num_msix_usable - 1; 112 113 return 0; 114 } 115 116 static int mana_gd_query_hwc_timeout(struct pci_dev *pdev, u32 *timeout_val) 117 { 118 struct gdma_context *gc = pci_get_drvdata(pdev); 119 struct gdma_query_hwc_timeout_resp resp = {}; 120 struct gdma_query_hwc_timeout_req req = {}; 121 int err; 122 123 mana_gd_init_req_hdr(&req.hdr, GDMA_QUERY_HWC_TIMEOUT, 124 sizeof(req), sizeof(resp)); 125 req.timeout_ms = *timeout_val; 126 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 127 if (err || resp.hdr.status) 128 return err ? err : -EPROTO; 129 130 *timeout_val = resp.timeout_ms; 131 132 return 0; 133 } 134 135 static int mana_gd_detect_devices(struct pci_dev *pdev) 136 { 137 struct gdma_context *gc = pci_get_drvdata(pdev); 138 struct gdma_list_devices_resp resp = {}; 139 struct gdma_general_req req = {}; 140 struct gdma_dev_id dev; 141 int found_dev = 0; 142 u16 dev_type; 143 int err; 144 u32 i; 145 146 mana_gd_init_req_hdr(&req.hdr, GDMA_LIST_DEVICES, sizeof(req), 147 sizeof(resp)); 148 149 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 150 if (err || resp.hdr.status) { 151 dev_err(gc->dev, "Failed to detect devices: %d, 0x%x\n", err, 152 resp.hdr.status); 153 return err ? err : -EPROTO; 154 } 155 156 for (i = 0; i < GDMA_DEV_LIST_SIZE && 157 found_dev < resp.num_of_devs; i++) { 158 dev = resp.devs[i]; 159 dev_type = dev.type; 160 161 /* Skip empty devices */ 162 if (dev.as_uint32 == 0) 163 continue; 164 165 found_dev++; 166 167 /* HWC is already detected in mana_hwc_create_channel(). */ 168 if (dev_type == GDMA_DEVICE_HWC) 169 continue; 170 171 if (dev_type == GDMA_DEVICE_MANA) { 172 gc->mana.gdma_context = gc; 173 gc->mana.dev_id = dev; 174 } else if (dev_type == GDMA_DEVICE_MANA_IB) { 175 gc->mana_ib.dev_id = dev; 176 gc->mana_ib.gdma_context = gc; 177 } 178 } 179 180 return gc->mana.dev_id.type == 0 ? -ENODEV : 0; 181 } 182 183 int mana_gd_send_request(struct gdma_context *gc, u32 req_len, const void *req, 184 u32 resp_len, void *resp) 185 { 186 struct hw_channel_context *hwc = gc->hwc.driver_data; 187 188 return mana_hwc_send_request(hwc, req_len, req, resp_len, resp); 189 } 190 EXPORT_SYMBOL_NS(mana_gd_send_request, "NET_MANA"); 191 192 int mana_gd_alloc_memory(struct gdma_context *gc, unsigned int length, 193 struct gdma_mem_info *gmi) 194 { 195 dma_addr_t dma_handle; 196 void *buf; 197 198 if (length < MANA_PAGE_SIZE || !is_power_of_2(length)) 199 return -EINVAL; 200 201 gmi->dev = gc->dev; 202 buf = dma_alloc_coherent(gmi->dev, length, &dma_handle, GFP_KERNEL); 203 if (!buf) 204 return -ENOMEM; 205 206 gmi->dma_handle = dma_handle; 207 gmi->virt_addr = buf; 208 gmi->length = length; 209 210 return 0; 211 } 212 213 void mana_gd_free_memory(struct gdma_mem_info *gmi) 214 { 215 dma_free_coherent(gmi->dev, gmi->length, gmi->virt_addr, 216 gmi->dma_handle); 217 } 218 219 static int mana_gd_create_hw_eq(struct gdma_context *gc, 220 struct gdma_queue *queue) 221 { 222 struct gdma_create_queue_resp resp = {}; 223 struct gdma_create_queue_req req = {}; 224 int err; 225 226 if (queue->type != GDMA_EQ) 227 return -EINVAL; 228 229 mana_gd_init_req_hdr(&req.hdr, GDMA_CREATE_QUEUE, 230 sizeof(req), sizeof(resp)); 231 232 req.hdr.dev_id = queue->gdma_dev->dev_id; 233 req.type = queue->type; 234 req.pdid = queue->gdma_dev->pdid; 235 req.doolbell_id = queue->gdma_dev->doorbell; 236 req.gdma_region = queue->mem_info.dma_region_handle; 237 req.queue_size = queue->queue_size; 238 req.log2_throttle_limit = queue->eq.log2_throttle_limit; 239 req.eq_pci_msix_index = queue->eq.msix_index; 240 241 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 242 if (err || resp.hdr.status) { 243 dev_err(gc->dev, "Failed to create queue: %d, 0x%x\n", err, 244 resp.hdr.status); 245 return err ? err : -EPROTO; 246 } 247 248 queue->id = resp.queue_index; 249 queue->eq.disable_needed = true; 250 queue->mem_info.dma_region_handle = GDMA_INVALID_DMA_REGION; 251 return 0; 252 } 253 254 static int mana_gd_disable_queue(struct gdma_queue *queue) 255 { 256 struct gdma_context *gc = queue->gdma_dev->gdma_context; 257 struct gdma_disable_queue_req req = {}; 258 struct gdma_general_resp resp = {}; 259 int err; 260 261 WARN_ON(queue->type != GDMA_EQ); 262 263 mana_gd_init_req_hdr(&req.hdr, GDMA_DISABLE_QUEUE, 264 sizeof(req), sizeof(resp)); 265 266 req.hdr.dev_id = queue->gdma_dev->dev_id; 267 req.type = queue->type; 268 req.queue_index = queue->id; 269 req.alloc_res_id_on_creation = 1; 270 271 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 272 if (err || resp.hdr.status) { 273 dev_err(gc->dev, "Failed to disable queue: %d, 0x%x\n", err, 274 resp.hdr.status); 275 return err ? err : -EPROTO; 276 } 277 278 return 0; 279 } 280 281 #define DOORBELL_OFFSET_SQ 0x0 282 #define DOORBELL_OFFSET_RQ 0x400 283 #define DOORBELL_OFFSET_CQ 0x800 284 #define DOORBELL_OFFSET_EQ 0xFF8 285 286 static void mana_gd_ring_doorbell(struct gdma_context *gc, u32 db_index, 287 enum gdma_queue_type q_type, u32 qid, 288 u32 tail_ptr, u8 num_req) 289 { 290 void __iomem *addr = gc->db_page_base + gc->db_page_size * db_index; 291 union gdma_doorbell_entry e = {}; 292 293 switch (q_type) { 294 case GDMA_EQ: 295 e.eq.id = qid; 296 e.eq.tail_ptr = tail_ptr; 297 e.eq.arm = num_req; 298 299 addr += DOORBELL_OFFSET_EQ; 300 break; 301 302 case GDMA_CQ: 303 e.cq.id = qid; 304 e.cq.tail_ptr = tail_ptr; 305 e.cq.arm = num_req; 306 307 addr += DOORBELL_OFFSET_CQ; 308 break; 309 310 case GDMA_RQ: 311 e.rq.id = qid; 312 e.rq.tail_ptr = tail_ptr; 313 e.rq.wqe_cnt = num_req; 314 315 addr += DOORBELL_OFFSET_RQ; 316 break; 317 318 case GDMA_SQ: 319 e.sq.id = qid; 320 e.sq.tail_ptr = tail_ptr; 321 322 addr += DOORBELL_OFFSET_SQ; 323 break; 324 325 default: 326 WARN_ON(1); 327 return; 328 } 329 330 /* Ensure all writes are done before ring doorbell */ 331 wmb(); 332 333 writeq(e.as_uint64, addr); 334 } 335 336 void mana_gd_wq_ring_doorbell(struct gdma_context *gc, struct gdma_queue *queue) 337 { 338 /* Hardware Spec specifies that software client should set 0 for 339 * wqe_cnt for Receive Queues. This value is not used in Send Queues. 340 */ 341 mana_gd_ring_doorbell(gc, queue->gdma_dev->doorbell, queue->type, 342 queue->id, queue->head * GDMA_WQE_BU_SIZE, 0); 343 } 344 EXPORT_SYMBOL_NS(mana_gd_wq_ring_doorbell, "NET_MANA"); 345 346 void mana_gd_ring_cq(struct gdma_queue *cq, u8 arm_bit) 347 { 348 struct gdma_context *gc = cq->gdma_dev->gdma_context; 349 350 u32 num_cqe = cq->queue_size / GDMA_CQE_SIZE; 351 352 u32 head = cq->head % (num_cqe << GDMA_CQE_OWNER_BITS); 353 354 mana_gd_ring_doorbell(gc, cq->gdma_dev->doorbell, cq->type, cq->id, 355 head, arm_bit); 356 } 357 EXPORT_SYMBOL_NS(mana_gd_ring_cq, "NET_MANA"); 358 359 static void mana_gd_process_eqe(struct gdma_queue *eq) 360 { 361 u32 head = eq->head % (eq->queue_size / GDMA_EQE_SIZE); 362 struct gdma_context *gc = eq->gdma_dev->gdma_context; 363 struct gdma_eqe *eq_eqe_ptr = eq->queue_mem_ptr; 364 union gdma_eqe_info eqe_info; 365 enum gdma_eqe_type type; 366 struct gdma_event event; 367 struct gdma_queue *cq; 368 struct gdma_eqe *eqe; 369 u32 cq_id; 370 371 eqe = &eq_eqe_ptr[head]; 372 eqe_info.as_uint32 = eqe->eqe_info; 373 type = eqe_info.type; 374 375 switch (type) { 376 case GDMA_EQE_COMPLETION: 377 cq_id = eqe->details[0] & 0xFFFFFF; 378 if (WARN_ON_ONCE(cq_id >= gc->max_num_cqs)) 379 break; 380 381 cq = gc->cq_table[cq_id]; 382 if (WARN_ON_ONCE(!cq || cq->type != GDMA_CQ || cq->id != cq_id)) 383 break; 384 385 if (cq->cq.callback) 386 cq->cq.callback(cq->cq.context, cq); 387 388 break; 389 390 case GDMA_EQE_TEST_EVENT: 391 gc->test_event_eq_id = eq->id; 392 complete(&gc->eq_test_event); 393 break; 394 395 case GDMA_EQE_HWC_INIT_EQ_ID_DB: 396 case GDMA_EQE_HWC_INIT_DATA: 397 case GDMA_EQE_HWC_INIT_DONE: 398 case GDMA_EQE_HWC_SOC_SERVICE: 399 case GDMA_EQE_RNIC_QP_FATAL: 400 if (!eq->eq.callback) 401 break; 402 403 event.type = type; 404 memcpy(&event.details, &eqe->details, GDMA_EVENT_DATA_SIZE); 405 eq->eq.callback(eq->eq.context, eq, &event); 406 break; 407 408 default: 409 break; 410 } 411 } 412 413 static void mana_gd_process_eq_events(void *arg) 414 { 415 u32 owner_bits, new_bits, old_bits; 416 union gdma_eqe_info eqe_info; 417 struct gdma_eqe *eq_eqe_ptr; 418 struct gdma_queue *eq = arg; 419 struct gdma_context *gc; 420 struct gdma_eqe *eqe; 421 u32 head, num_eqe; 422 int i; 423 424 gc = eq->gdma_dev->gdma_context; 425 426 num_eqe = eq->queue_size / GDMA_EQE_SIZE; 427 eq_eqe_ptr = eq->queue_mem_ptr; 428 429 /* Process up to 5 EQEs at a time, and update the HW head. */ 430 for (i = 0; i < 5; i++) { 431 eqe = &eq_eqe_ptr[eq->head % num_eqe]; 432 eqe_info.as_uint32 = eqe->eqe_info; 433 owner_bits = eqe_info.owner_bits; 434 435 old_bits = (eq->head / num_eqe - 1) & GDMA_EQE_OWNER_MASK; 436 /* No more entries */ 437 if (owner_bits == old_bits) { 438 /* return here without ringing the doorbell */ 439 if (i == 0) 440 return; 441 break; 442 } 443 444 new_bits = (eq->head / num_eqe) & GDMA_EQE_OWNER_MASK; 445 if (owner_bits != new_bits) { 446 dev_err(gc->dev, "EQ %d: overflow detected\n", eq->id); 447 break; 448 } 449 450 /* Per GDMA spec, rmb is necessary after checking owner_bits, before 451 * reading eqe. 452 */ 453 rmb(); 454 455 mana_gd_process_eqe(eq); 456 457 eq->head++; 458 } 459 460 head = eq->head % (num_eqe << GDMA_EQE_OWNER_BITS); 461 462 mana_gd_ring_doorbell(gc, eq->gdma_dev->doorbell, eq->type, eq->id, 463 head, SET_ARM_BIT); 464 } 465 466 static int mana_gd_register_irq(struct gdma_queue *queue, 467 const struct gdma_queue_spec *spec) 468 { 469 struct gdma_dev *gd = queue->gdma_dev; 470 struct gdma_irq_context *gic; 471 struct gdma_context *gc; 472 unsigned int msi_index; 473 unsigned long flags; 474 struct device *dev; 475 int err = 0; 476 477 gc = gd->gdma_context; 478 dev = gc->dev; 479 msi_index = spec->eq.msix_index; 480 481 if (msi_index >= gc->num_msix_usable) { 482 err = -ENOSPC; 483 dev_err(dev, "Register IRQ err:%d, msi:%u nMSI:%u", 484 err, msi_index, gc->num_msix_usable); 485 486 return err; 487 } 488 489 queue->eq.msix_index = msi_index; 490 gic = &gc->irq_contexts[msi_index]; 491 492 spin_lock_irqsave(&gic->lock, flags); 493 list_add_rcu(&queue->entry, &gic->eq_list); 494 spin_unlock_irqrestore(&gic->lock, flags); 495 496 return 0; 497 } 498 499 static void mana_gd_deregiser_irq(struct gdma_queue *queue) 500 { 501 struct gdma_dev *gd = queue->gdma_dev; 502 struct gdma_irq_context *gic; 503 struct gdma_context *gc; 504 unsigned int msix_index; 505 unsigned long flags; 506 struct gdma_queue *eq; 507 508 gc = gd->gdma_context; 509 510 /* At most num_online_cpus() + 1 interrupts are used. */ 511 msix_index = queue->eq.msix_index; 512 if (WARN_ON(msix_index >= gc->num_msix_usable)) 513 return; 514 515 gic = &gc->irq_contexts[msix_index]; 516 spin_lock_irqsave(&gic->lock, flags); 517 list_for_each_entry_rcu(eq, &gic->eq_list, entry) { 518 if (queue == eq) { 519 list_del_rcu(&eq->entry); 520 break; 521 } 522 } 523 spin_unlock_irqrestore(&gic->lock, flags); 524 525 queue->eq.msix_index = INVALID_PCI_MSIX_INDEX; 526 synchronize_rcu(); 527 } 528 529 int mana_gd_test_eq(struct gdma_context *gc, struct gdma_queue *eq) 530 { 531 struct gdma_generate_test_event_req req = {}; 532 struct gdma_general_resp resp = {}; 533 struct device *dev = gc->dev; 534 int err; 535 536 mutex_lock(&gc->eq_test_event_mutex); 537 538 init_completion(&gc->eq_test_event); 539 gc->test_event_eq_id = INVALID_QUEUE_ID; 540 541 mana_gd_init_req_hdr(&req.hdr, GDMA_GENERATE_TEST_EQE, 542 sizeof(req), sizeof(resp)); 543 544 req.hdr.dev_id = eq->gdma_dev->dev_id; 545 req.queue_index = eq->id; 546 547 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 548 if (err) { 549 dev_err(dev, "test_eq failed: %d\n", err); 550 goto out; 551 } 552 553 err = -EPROTO; 554 555 if (resp.hdr.status) { 556 dev_err(dev, "test_eq failed: 0x%x\n", resp.hdr.status); 557 goto out; 558 } 559 560 if (!wait_for_completion_timeout(&gc->eq_test_event, 30 * HZ)) { 561 dev_err(dev, "test_eq timed out on queue %d\n", eq->id); 562 goto out; 563 } 564 565 if (eq->id != gc->test_event_eq_id) { 566 dev_err(dev, "test_eq got an event on wrong queue %d (%d)\n", 567 gc->test_event_eq_id, eq->id); 568 goto out; 569 } 570 571 err = 0; 572 out: 573 mutex_unlock(&gc->eq_test_event_mutex); 574 return err; 575 } 576 577 static void mana_gd_destroy_eq(struct gdma_context *gc, bool flush_evenets, 578 struct gdma_queue *queue) 579 { 580 int err; 581 582 if (flush_evenets) { 583 err = mana_gd_test_eq(gc, queue); 584 if (err) 585 dev_warn(gc->dev, "Failed to flush EQ: %d\n", err); 586 } 587 588 mana_gd_deregiser_irq(queue); 589 590 if (queue->eq.disable_needed) 591 mana_gd_disable_queue(queue); 592 } 593 594 static int mana_gd_create_eq(struct gdma_dev *gd, 595 const struct gdma_queue_spec *spec, 596 bool create_hwq, struct gdma_queue *queue) 597 { 598 struct gdma_context *gc = gd->gdma_context; 599 struct device *dev = gc->dev; 600 u32 log2_num_entries; 601 int err; 602 603 queue->eq.msix_index = INVALID_PCI_MSIX_INDEX; 604 queue->id = INVALID_QUEUE_ID; 605 606 log2_num_entries = ilog2(queue->queue_size / GDMA_EQE_SIZE); 607 608 if (spec->eq.log2_throttle_limit > log2_num_entries) { 609 dev_err(dev, "EQ throttling limit (%lu) > maximum EQE (%u)\n", 610 spec->eq.log2_throttle_limit, log2_num_entries); 611 return -EINVAL; 612 } 613 614 err = mana_gd_register_irq(queue, spec); 615 if (err) { 616 dev_err(dev, "Failed to register irq: %d\n", err); 617 return err; 618 } 619 620 queue->eq.callback = spec->eq.callback; 621 queue->eq.context = spec->eq.context; 622 queue->head |= INITIALIZED_OWNER_BIT(log2_num_entries); 623 queue->eq.log2_throttle_limit = spec->eq.log2_throttle_limit ?: 1; 624 625 if (create_hwq) { 626 err = mana_gd_create_hw_eq(gc, queue); 627 if (err) 628 goto out; 629 630 err = mana_gd_test_eq(gc, queue); 631 if (err) 632 goto out; 633 } 634 635 return 0; 636 out: 637 dev_err(dev, "Failed to create EQ: %d\n", err); 638 mana_gd_destroy_eq(gc, false, queue); 639 return err; 640 } 641 642 static void mana_gd_create_cq(const struct gdma_queue_spec *spec, 643 struct gdma_queue *queue) 644 { 645 u32 log2_num_entries = ilog2(spec->queue_size / GDMA_CQE_SIZE); 646 647 queue->head |= INITIALIZED_OWNER_BIT(log2_num_entries); 648 queue->cq.parent = spec->cq.parent_eq; 649 queue->cq.context = spec->cq.context; 650 queue->cq.callback = spec->cq.callback; 651 } 652 653 static void mana_gd_destroy_cq(struct gdma_context *gc, 654 struct gdma_queue *queue) 655 { 656 u32 id = queue->id; 657 658 if (id >= gc->max_num_cqs) 659 return; 660 661 if (!gc->cq_table[id]) 662 return; 663 664 gc->cq_table[id] = NULL; 665 } 666 667 int mana_gd_create_hwc_queue(struct gdma_dev *gd, 668 const struct gdma_queue_spec *spec, 669 struct gdma_queue **queue_ptr) 670 { 671 struct gdma_context *gc = gd->gdma_context; 672 struct gdma_mem_info *gmi; 673 struct gdma_queue *queue; 674 int err; 675 676 queue = kzalloc(sizeof(*queue), GFP_KERNEL); 677 if (!queue) 678 return -ENOMEM; 679 680 gmi = &queue->mem_info; 681 err = mana_gd_alloc_memory(gc, spec->queue_size, gmi); 682 if (err) { 683 dev_err(gc->dev, "GDMA queue type: %d, size: %u, gdma memory allocation err: %d\n", 684 spec->type, spec->queue_size, err); 685 goto free_q; 686 } 687 688 queue->head = 0; 689 queue->tail = 0; 690 queue->queue_mem_ptr = gmi->virt_addr; 691 queue->queue_size = spec->queue_size; 692 queue->monitor_avl_buf = spec->monitor_avl_buf; 693 queue->type = spec->type; 694 queue->gdma_dev = gd; 695 696 if (spec->type == GDMA_EQ) 697 err = mana_gd_create_eq(gd, spec, false, queue); 698 else if (spec->type == GDMA_CQ) 699 mana_gd_create_cq(spec, queue); 700 701 if (err) 702 goto out; 703 704 *queue_ptr = queue; 705 return 0; 706 out: 707 dev_err(gc->dev, "Failed to create queue type %d of size %u, err: %d\n", 708 spec->type, spec->queue_size, err); 709 mana_gd_free_memory(gmi); 710 free_q: 711 kfree(queue); 712 return err; 713 } 714 715 int mana_gd_destroy_dma_region(struct gdma_context *gc, u64 dma_region_handle) 716 { 717 struct gdma_destroy_dma_region_req req = {}; 718 struct gdma_general_resp resp = {}; 719 int err; 720 721 if (dma_region_handle == GDMA_INVALID_DMA_REGION) 722 return 0; 723 724 mana_gd_init_req_hdr(&req.hdr, GDMA_DESTROY_DMA_REGION, sizeof(req), 725 sizeof(resp)); 726 req.dma_region_handle = dma_region_handle; 727 728 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 729 if (err || resp.hdr.status) { 730 dev_err(gc->dev, "Failed to destroy DMA region: %d, 0x%x\n", 731 err, resp.hdr.status); 732 return -EPROTO; 733 } 734 735 return 0; 736 } 737 EXPORT_SYMBOL_NS(mana_gd_destroy_dma_region, "NET_MANA"); 738 739 static int mana_gd_create_dma_region(struct gdma_dev *gd, 740 struct gdma_mem_info *gmi) 741 { 742 unsigned int num_page = gmi->length / MANA_PAGE_SIZE; 743 struct gdma_create_dma_region_req *req = NULL; 744 struct gdma_create_dma_region_resp resp = {}; 745 struct gdma_context *gc = gd->gdma_context; 746 struct hw_channel_context *hwc; 747 u32 length = gmi->length; 748 size_t req_msg_size; 749 int err; 750 int i; 751 752 if (length < MANA_PAGE_SIZE || !is_power_of_2(length)) 753 return -EINVAL; 754 755 if (!MANA_PAGE_ALIGNED(gmi->virt_addr)) 756 return -EINVAL; 757 758 hwc = gc->hwc.driver_data; 759 req_msg_size = struct_size(req, page_addr_list, num_page); 760 if (req_msg_size > hwc->max_req_msg_size) 761 return -EINVAL; 762 763 req = kzalloc(req_msg_size, GFP_KERNEL); 764 if (!req) 765 return -ENOMEM; 766 767 mana_gd_init_req_hdr(&req->hdr, GDMA_CREATE_DMA_REGION, 768 req_msg_size, sizeof(resp)); 769 req->length = length; 770 req->offset_in_page = 0; 771 req->gdma_page_type = GDMA_PAGE_TYPE_4K; 772 req->page_count = num_page; 773 req->page_addr_list_len = num_page; 774 775 for (i = 0; i < num_page; i++) 776 req->page_addr_list[i] = gmi->dma_handle + i * MANA_PAGE_SIZE; 777 778 err = mana_gd_send_request(gc, req_msg_size, req, sizeof(resp), &resp); 779 if (err) 780 goto out; 781 782 if (resp.hdr.status || 783 resp.dma_region_handle == GDMA_INVALID_DMA_REGION) { 784 dev_err(gc->dev, "Failed to create DMA region: 0x%x\n", 785 resp.hdr.status); 786 err = -EPROTO; 787 goto out; 788 } 789 790 gmi->dma_region_handle = resp.dma_region_handle; 791 dev_dbg(gc->dev, "Created DMA region handle 0x%llx\n", 792 gmi->dma_region_handle); 793 out: 794 if (err) 795 dev_dbg(gc->dev, 796 "Failed to create DMA region of length: %u, page_type: %d, status: 0x%x, err: %d\n", 797 length, req->gdma_page_type, resp.hdr.status, err); 798 kfree(req); 799 return err; 800 } 801 802 int mana_gd_create_mana_eq(struct gdma_dev *gd, 803 const struct gdma_queue_spec *spec, 804 struct gdma_queue **queue_ptr) 805 { 806 struct gdma_context *gc = gd->gdma_context; 807 struct gdma_mem_info *gmi; 808 struct gdma_queue *queue; 809 int err; 810 811 if (spec->type != GDMA_EQ) 812 return -EINVAL; 813 814 queue = kzalloc(sizeof(*queue), GFP_KERNEL); 815 if (!queue) 816 return -ENOMEM; 817 818 gmi = &queue->mem_info; 819 err = mana_gd_alloc_memory(gc, spec->queue_size, gmi); 820 if (err) { 821 dev_err(gc->dev, "GDMA queue type: %d, size: %u, gdma memory allocation err: %d\n", 822 spec->type, spec->queue_size, err); 823 goto free_q; 824 } 825 826 err = mana_gd_create_dma_region(gd, gmi); 827 if (err) 828 goto out; 829 830 queue->head = 0; 831 queue->tail = 0; 832 queue->queue_mem_ptr = gmi->virt_addr; 833 queue->queue_size = spec->queue_size; 834 queue->monitor_avl_buf = spec->monitor_avl_buf; 835 queue->type = spec->type; 836 queue->gdma_dev = gd; 837 838 err = mana_gd_create_eq(gd, spec, true, queue); 839 if (err) 840 goto out; 841 842 *queue_ptr = queue; 843 return 0; 844 out: 845 dev_err(gc->dev, "Failed to create queue type %d of size: %u, err: %d\n", 846 spec->type, spec->queue_size, err); 847 mana_gd_free_memory(gmi); 848 free_q: 849 kfree(queue); 850 return err; 851 } 852 EXPORT_SYMBOL_NS(mana_gd_create_mana_eq, "NET_MANA"); 853 854 int mana_gd_create_mana_wq_cq(struct gdma_dev *gd, 855 const struct gdma_queue_spec *spec, 856 struct gdma_queue **queue_ptr) 857 { 858 struct gdma_context *gc = gd->gdma_context; 859 struct gdma_mem_info *gmi; 860 struct gdma_queue *queue; 861 int err; 862 863 if (spec->type != GDMA_CQ && spec->type != GDMA_SQ && 864 spec->type != GDMA_RQ) 865 return -EINVAL; 866 867 queue = kzalloc(sizeof(*queue), GFP_KERNEL); 868 if (!queue) 869 return -ENOMEM; 870 871 gmi = &queue->mem_info; 872 err = mana_gd_alloc_memory(gc, spec->queue_size, gmi); 873 if (err) { 874 dev_err(gc->dev, "GDMA queue type: %d, size: %u, memory allocation err: %d\n", 875 spec->type, spec->queue_size, err); 876 goto free_q; 877 } 878 879 err = mana_gd_create_dma_region(gd, gmi); 880 if (err) 881 goto out; 882 883 queue->head = 0; 884 queue->tail = 0; 885 queue->queue_mem_ptr = gmi->virt_addr; 886 queue->queue_size = spec->queue_size; 887 queue->monitor_avl_buf = spec->monitor_avl_buf; 888 queue->type = spec->type; 889 queue->gdma_dev = gd; 890 891 if (spec->type == GDMA_CQ) 892 mana_gd_create_cq(spec, queue); 893 894 *queue_ptr = queue; 895 return 0; 896 out: 897 dev_err(gc->dev, "Failed to create queue type %d of size: %u, err: %d\n", 898 spec->type, spec->queue_size, err); 899 mana_gd_free_memory(gmi); 900 free_q: 901 kfree(queue); 902 return err; 903 } 904 EXPORT_SYMBOL_NS(mana_gd_create_mana_wq_cq, "NET_MANA"); 905 906 void mana_gd_destroy_queue(struct gdma_context *gc, struct gdma_queue *queue) 907 { 908 struct gdma_mem_info *gmi = &queue->mem_info; 909 910 switch (queue->type) { 911 case GDMA_EQ: 912 mana_gd_destroy_eq(gc, queue->eq.disable_needed, queue); 913 break; 914 915 case GDMA_CQ: 916 mana_gd_destroy_cq(gc, queue); 917 break; 918 919 case GDMA_RQ: 920 break; 921 922 case GDMA_SQ: 923 break; 924 925 default: 926 dev_err(gc->dev, "Can't destroy unknown queue: type=%d\n", 927 queue->type); 928 return; 929 } 930 931 mana_gd_destroy_dma_region(gc, gmi->dma_region_handle); 932 mana_gd_free_memory(gmi); 933 kfree(queue); 934 } 935 EXPORT_SYMBOL_NS(mana_gd_destroy_queue, "NET_MANA"); 936 937 int mana_gd_verify_vf_version(struct pci_dev *pdev) 938 { 939 struct gdma_context *gc = pci_get_drvdata(pdev); 940 struct gdma_verify_ver_resp resp = {}; 941 struct gdma_verify_ver_req req = {}; 942 struct hw_channel_context *hwc; 943 int err; 944 945 hwc = gc->hwc.driver_data; 946 mana_gd_init_req_hdr(&req.hdr, GDMA_VERIFY_VF_DRIVER_VERSION, 947 sizeof(req), sizeof(resp)); 948 949 req.protocol_ver_min = GDMA_PROTOCOL_FIRST; 950 req.protocol_ver_max = GDMA_PROTOCOL_LAST; 951 952 req.gd_drv_cap_flags1 = GDMA_DRV_CAP_FLAGS1; 953 req.gd_drv_cap_flags2 = GDMA_DRV_CAP_FLAGS2; 954 req.gd_drv_cap_flags3 = GDMA_DRV_CAP_FLAGS3; 955 req.gd_drv_cap_flags4 = GDMA_DRV_CAP_FLAGS4; 956 957 req.drv_ver = 0; /* Unused*/ 958 req.os_type = 0x10; /* Linux */ 959 req.os_ver_major = LINUX_VERSION_MAJOR; 960 req.os_ver_minor = LINUX_VERSION_PATCHLEVEL; 961 req.os_ver_build = LINUX_VERSION_SUBLEVEL; 962 strscpy(req.os_ver_str1, utsname()->sysname, sizeof(req.os_ver_str1)); 963 strscpy(req.os_ver_str2, utsname()->release, sizeof(req.os_ver_str2)); 964 strscpy(req.os_ver_str3, utsname()->version, sizeof(req.os_ver_str3)); 965 966 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 967 if (err || resp.hdr.status) { 968 dev_err(gc->dev, "VfVerifyVersionOutput: %d, status=0x%x\n", 969 err, resp.hdr.status); 970 return err ? err : -EPROTO; 971 } 972 gc->pf_cap_flags1 = resp.pf_cap_flags1; 973 if (resp.pf_cap_flags1 & GDMA_DRV_CAP_FLAG_1_HWC_TIMEOUT_RECONFIG) { 974 err = mana_gd_query_hwc_timeout(pdev, &hwc->hwc_timeout); 975 if (err) { 976 dev_err(gc->dev, "Failed to set the hwc timeout %d\n", err); 977 return err; 978 } 979 dev_dbg(gc->dev, "set the hwc timeout to %u\n", hwc->hwc_timeout); 980 } 981 return 0; 982 } 983 984 int mana_gd_register_device(struct gdma_dev *gd) 985 { 986 struct gdma_context *gc = gd->gdma_context; 987 struct gdma_register_device_resp resp = {}; 988 struct gdma_general_req req = {}; 989 int err; 990 991 gd->pdid = INVALID_PDID; 992 gd->doorbell = INVALID_DOORBELL; 993 gd->gpa_mkey = INVALID_MEM_KEY; 994 995 mana_gd_init_req_hdr(&req.hdr, GDMA_REGISTER_DEVICE, sizeof(req), 996 sizeof(resp)); 997 998 req.hdr.dev_id = gd->dev_id; 999 1000 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 1001 if (err || resp.hdr.status) { 1002 dev_err(gc->dev, "gdma_register_device_resp failed: %d, 0x%x\n", 1003 err, resp.hdr.status); 1004 return err ? err : -EPROTO; 1005 } 1006 1007 gd->pdid = resp.pdid; 1008 gd->gpa_mkey = resp.gpa_mkey; 1009 gd->doorbell = resp.db_id; 1010 1011 return 0; 1012 } 1013 1014 int mana_gd_deregister_device(struct gdma_dev *gd) 1015 { 1016 struct gdma_context *gc = gd->gdma_context; 1017 struct gdma_general_resp resp = {}; 1018 struct gdma_general_req req = {}; 1019 int err; 1020 1021 if (gd->pdid == INVALID_PDID) 1022 return -EINVAL; 1023 1024 mana_gd_init_req_hdr(&req.hdr, GDMA_DEREGISTER_DEVICE, sizeof(req), 1025 sizeof(resp)); 1026 1027 req.hdr.dev_id = gd->dev_id; 1028 1029 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 1030 if (err || resp.hdr.status) { 1031 dev_err(gc->dev, "Failed to deregister device: %d, 0x%x\n", 1032 err, resp.hdr.status); 1033 if (!err) 1034 err = -EPROTO; 1035 } 1036 1037 gd->pdid = INVALID_PDID; 1038 gd->doorbell = INVALID_DOORBELL; 1039 gd->gpa_mkey = INVALID_MEM_KEY; 1040 1041 return err; 1042 } 1043 1044 u32 mana_gd_wq_avail_space(struct gdma_queue *wq) 1045 { 1046 u32 used_space = (wq->head - wq->tail) * GDMA_WQE_BU_SIZE; 1047 u32 wq_size = wq->queue_size; 1048 1049 WARN_ON_ONCE(used_space > wq_size); 1050 1051 return wq_size - used_space; 1052 } 1053 1054 u8 *mana_gd_get_wqe_ptr(const struct gdma_queue *wq, u32 wqe_offset) 1055 { 1056 u32 offset = (wqe_offset * GDMA_WQE_BU_SIZE) & (wq->queue_size - 1); 1057 1058 WARN_ON_ONCE((offset + GDMA_WQE_BU_SIZE) > wq->queue_size); 1059 1060 return wq->queue_mem_ptr + offset; 1061 } 1062 1063 static u32 mana_gd_write_client_oob(const struct gdma_wqe_request *wqe_req, 1064 enum gdma_queue_type q_type, 1065 u32 client_oob_size, u32 sgl_data_size, 1066 u8 *wqe_ptr) 1067 { 1068 bool oob_in_sgl = !!(wqe_req->flags & GDMA_WR_OOB_IN_SGL); 1069 bool pad_data = !!(wqe_req->flags & GDMA_WR_PAD_BY_SGE0); 1070 struct gdma_wqe *header = (struct gdma_wqe *)wqe_ptr; 1071 u8 *ptr; 1072 1073 memset(header, 0, sizeof(struct gdma_wqe)); 1074 header->num_sge = wqe_req->num_sge; 1075 header->inline_oob_size_div4 = client_oob_size / sizeof(u32); 1076 1077 if (oob_in_sgl) { 1078 WARN_ON_ONCE(wqe_req->num_sge < 2); 1079 1080 header->client_oob_in_sgl = 1; 1081 1082 if (pad_data) 1083 header->last_vbytes = wqe_req->sgl[0].size; 1084 } 1085 1086 if (q_type == GDMA_SQ) 1087 header->client_data_unit = wqe_req->client_data_unit; 1088 1089 /* The size of gdma_wqe + client_oob_size must be less than or equal 1090 * to one Basic Unit (i.e. 32 bytes), so the pointer can't go beyond 1091 * the queue memory buffer boundary. 1092 */ 1093 ptr = wqe_ptr + sizeof(header); 1094 1095 if (wqe_req->inline_oob_data && wqe_req->inline_oob_size > 0) { 1096 memcpy(ptr, wqe_req->inline_oob_data, wqe_req->inline_oob_size); 1097 1098 if (client_oob_size > wqe_req->inline_oob_size) 1099 memset(ptr + wqe_req->inline_oob_size, 0, 1100 client_oob_size - wqe_req->inline_oob_size); 1101 } 1102 1103 return sizeof(header) + client_oob_size; 1104 } 1105 1106 static void mana_gd_write_sgl(struct gdma_queue *wq, u8 *wqe_ptr, 1107 const struct gdma_wqe_request *wqe_req) 1108 { 1109 u32 sgl_size = sizeof(struct gdma_sge) * wqe_req->num_sge; 1110 const u8 *address = (u8 *)wqe_req->sgl; 1111 u8 *base_ptr, *end_ptr; 1112 u32 size_to_end; 1113 1114 base_ptr = wq->queue_mem_ptr; 1115 end_ptr = base_ptr + wq->queue_size; 1116 size_to_end = (u32)(end_ptr - wqe_ptr); 1117 1118 if (size_to_end < sgl_size) { 1119 memcpy(wqe_ptr, address, size_to_end); 1120 1121 wqe_ptr = base_ptr; 1122 address += size_to_end; 1123 sgl_size -= size_to_end; 1124 } 1125 1126 memcpy(wqe_ptr, address, sgl_size); 1127 } 1128 1129 int mana_gd_post_work_request(struct gdma_queue *wq, 1130 const struct gdma_wqe_request *wqe_req, 1131 struct gdma_posted_wqe_info *wqe_info) 1132 { 1133 u32 client_oob_size = wqe_req->inline_oob_size; 1134 struct gdma_context *gc; 1135 u32 sgl_data_size; 1136 u32 max_wqe_size; 1137 u32 wqe_size; 1138 u8 *wqe_ptr; 1139 1140 if (wqe_req->num_sge == 0) 1141 return -EINVAL; 1142 1143 if (wq->type == GDMA_RQ) { 1144 if (client_oob_size != 0) 1145 return -EINVAL; 1146 1147 client_oob_size = INLINE_OOB_SMALL_SIZE; 1148 1149 max_wqe_size = GDMA_MAX_RQE_SIZE; 1150 } else { 1151 if (client_oob_size != INLINE_OOB_SMALL_SIZE && 1152 client_oob_size != INLINE_OOB_LARGE_SIZE) 1153 return -EINVAL; 1154 1155 max_wqe_size = GDMA_MAX_SQE_SIZE; 1156 } 1157 1158 sgl_data_size = sizeof(struct gdma_sge) * wqe_req->num_sge; 1159 wqe_size = ALIGN(sizeof(struct gdma_wqe) + client_oob_size + 1160 sgl_data_size, GDMA_WQE_BU_SIZE); 1161 if (wqe_size > max_wqe_size) 1162 return -EINVAL; 1163 1164 if (wq->monitor_avl_buf && wqe_size > mana_gd_wq_avail_space(wq)) { 1165 gc = wq->gdma_dev->gdma_context; 1166 dev_err(gc->dev, "unsuccessful flow control!\n"); 1167 return -ENOSPC; 1168 } 1169 1170 if (wqe_info) 1171 wqe_info->wqe_size_in_bu = wqe_size / GDMA_WQE_BU_SIZE; 1172 1173 wqe_ptr = mana_gd_get_wqe_ptr(wq, wq->head); 1174 wqe_ptr += mana_gd_write_client_oob(wqe_req, wq->type, client_oob_size, 1175 sgl_data_size, wqe_ptr); 1176 if (wqe_ptr >= (u8 *)wq->queue_mem_ptr + wq->queue_size) 1177 wqe_ptr -= wq->queue_size; 1178 1179 mana_gd_write_sgl(wq, wqe_ptr, wqe_req); 1180 1181 wq->head += wqe_size / GDMA_WQE_BU_SIZE; 1182 1183 return 0; 1184 } 1185 EXPORT_SYMBOL_NS(mana_gd_post_work_request, "NET_MANA"); 1186 1187 int mana_gd_post_and_ring(struct gdma_queue *queue, 1188 const struct gdma_wqe_request *wqe_req, 1189 struct gdma_posted_wqe_info *wqe_info) 1190 { 1191 struct gdma_context *gc = queue->gdma_dev->gdma_context; 1192 int err; 1193 1194 err = mana_gd_post_work_request(queue, wqe_req, wqe_info); 1195 if (err) { 1196 dev_err(gc->dev, "Failed to post work req from queue type %d of size %u (err=%d)\n", 1197 queue->type, queue->queue_size, err); 1198 return err; 1199 } 1200 1201 mana_gd_wq_ring_doorbell(gc, queue); 1202 1203 return 0; 1204 } 1205 1206 static int mana_gd_read_cqe(struct gdma_queue *cq, struct gdma_comp *comp) 1207 { 1208 unsigned int num_cqe = cq->queue_size / sizeof(struct gdma_cqe); 1209 struct gdma_cqe *cq_cqe = cq->queue_mem_ptr; 1210 u32 owner_bits, new_bits, old_bits; 1211 struct gdma_cqe *cqe; 1212 1213 cqe = &cq_cqe[cq->head % num_cqe]; 1214 owner_bits = cqe->cqe_info.owner_bits; 1215 1216 old_bits = (cq->head / num_cqe - 1) & GDMA_CQE_OWNER_MASK; 1217 /* Return 0 if no more entries. */ 1218 if (owner_bits == old_bits) 1219 return 0; 1220 1221 new_bits = (cq->head / num_cqe) & GDMA_CQE_OWNER_MASK; 1222 /* Return -1 if overflow detected. */ 1223 if (WARN_ON_ONCE(owner_bits != new_bits)) 1224 return -1; 1225 1226 /* Per GDMA spec, rmb is necessary after checking owner_bits, before 1227 * reading completion info 1228 */ 1229 rmb(); 1230 1231 comp->wq_num = cqe->cqe_info.wq_num; 1232 comp->is_sq = cqe->cqe_info.is_sq; 1233 memcpy(comp->cqe_data, cqe->cqe_data, GDMA_COMP_DATA_SIZE); 1234 1235 return 1; 1236 } 1237 1238 int mana_gd_poll_cq(struct gdma_queue *cq, struct gdma_comp *comp, int num_cqe) 1239 { 1240 int cqe_idx; 1241 int ret; 1242 1243 for (cqe_idx = 0; cqe_idx < num_cqe; cqe_idx++) { 1244 ret = mana_gd_read_cqe(cq, &comp[cqe_idx]); 1245 1246 if (ret < 0) { 1247 cq->head -= cqe_idx; 1248 return ret; 1249 } 1250 1251 if (ret == 0) 1252 break; 1253 1254 cq->head++; 1255 } 1256 1257 return cqe_idx; 1258 } 1259 EXPORT_SYMBOL_NS(mana_gd_poll_cq, "NET_MANA"); 1260 1261 static irqreturn_t mana_gd_intr(int irq, void *arg) 1262 { 1263 struct gdma_irq_context *gic = arg; 1264 struct list_head *eq_list = &gic->eq_list; 1265 struct gdma_queue *eq; 1266 1267 rcu_read_lock(); 1268 list_for_each_entry_rcu(eq, eq_list, entry) { 1269 gic->handler(eq); 1270 } 1271 rcu_read_unlock(); 1272 1273 return IRQ_HANDLED; 1274 } 1275 1276 int mana_gd_alloc_res_map(u32 res_avail, struct gdma_resource *r) 1277 { 1278 r->map = bitmap_zalloc(res_avail, GFP_KERNEL); 1279 if (!r->map) 1280 return -ENOMEM; 1281 1282 r->size = res_avail; 1283 spin_lock_init(&r->lock); 1284 1285 return 0; 1286 } 1287 1288 void mana_gd_free_res_map(struct gdma_resource *r) 1289 { 1290 bitmap_free(r->map); 1291 r->map = NULL; 1292 r->size = 0; 1293 } 1294 1295 static int irq_setup(unsigned int *irqs, unsigned int len, int node) 1296 { 1297 const struct cpumask *next, *prev = cpu_none_mask; 1298 cpumask_var_t cpus __free(free_cpumask_var); 1299 int cpu, weight; 1300 1301 if (!alloc_cpumask_var(&cpus, GFP_KERNEL)) 1302 return -ENOMEM; 1303 1304 rcu_read_lock(); 1305 for_each_numa_hop_mask(next, node) { 1306 weight = cpumask_weight_andnot(next, prev); 1307 while (weight > 0) { 1308 cpumask_andnot(cpus, next, prev); 1309 for_each_cpu(cpu, cpus) { 1310 if (len-- == 0) 1311 goto done; 1312 irq_set_affinity_and_hint(*irqs++, topology_sibling_cpumask(cpu)); 1313 cpumask_andnot(cpus, cpus, topology_sibling_cpumask(cpu)); 1314 --weight; 1315 } 1316 } 1317 prev = next; 1318 } 1319 done: 1320 rcu_read_unlock(); 1321 return 0; 1322 } 1323 1324 static int mana_gd_setup_irqs(struct pci_dev *pdev) 1325 { 1326 struct gdma_context *gc = pci_get_drvdata(pdev); 1327 unsigned int max_queues_per_port; 1328 struct gdma_irq_context *gic; 1329 unsigned int max_irqs, cpu; 1330 int start_irq_index = 1; 1331 int nvec, *irqs, irq; 1332 int err, i = 0, j; 1333 1334 cpus_read_lock(); 1335 max_queues_per_port = num_online_cpus(); 1336 if (max_queues_per_port > MANA_MAX_NUM_QUEUES) 1337 max_queues_per_port = MANA_MAX_NUM_QUEUES; 1338 1339 /* Need 1 interrupt for the Hardware communication Channel (HWC) */ 1340 max_irqs = max_queues_per_port + 1; 1341 1342 nvec = pci_alloc_irq_vectors(pdev, 2, max_irqs, PCI_IRQ_MSIX); 1343 if (nvec < 0) { 1344 cpus_read_unlock(); 1345 return nvec; 1346 } 1347 if (nvec <= num_online_cpus()) 1348 start_irq_index = 0; 1349 1350 irqs = kmalloc_array((nvec - start_irq_index), sizeof(int), GFP_KERNEL); 1351 if (!irqs) { 1352 err = -ENOMEM; 1353 goto free_irq_vector; 1354 } 1355 1356 gc->irq_contexts = kcalloc(nvec, sizeof(struct gdma_irq_context), 1357 GFP_KERNEL); 1358 if (!gc->irq_contexts) { 1359 err = -ENOMEM; 1360 goto free_irq_array; 1361 } 1362 1363 for (i = 0; i < nvec; i++) { 1364 gic = &gc->irq_contexts[i]; 1365 gic->handler = mana_gd_process_eq_events; 1366 INIT_LIST_HEAD(&gic->eq_list); 1367 spin_lock_init(&gic->lock); 1368 1369 if (!i) 1370 snprintf(gic->name, MANA_IRQ_NAME_SZ, "mana_hwc@pci:%s", 1371 pci_name(pdev)); 1372 else 1373 snprintf(gic->name, MANA_IRQ_NAME_SZ, "mana_q%d@pci:%s", 1374 i - 1, pci_name(pdev)); 1375 1376 irq = pci_irq_vector(pdev, i); 1377 if (irq < 0) { 1378 err = irq; 1379 goto free_irq; 1380 } 1381 1382 if (!i) { 1383 err = request_irq(irq, mana_gd_intr, 0, gic->name, gic); 1384 if (err) 1385 goto free_irq; 1386 1387 /* If number of IRQ is one extra than number of online CPUs, 1388 * then we need to assign IRQ0 (hwc irq) and IRQ1 to 1389 * same CPU. 1390 * Else we will use different CPUs for IRQ0 and IRQ1. 1391 * Also we are using cpumask_local_spread instead of 1392 * cpumask_first for the node, because the node can be 1393 * mem only. 1394 */ 1395 if (start_irq_index) { 1396 cpu = cpumask_local_spread(i, gc->numa_node); 1397 irq_set_affinity_and_hint(irq, cpumask_of(cpu)); 1398 } else { 1399 irqs[start_irq_index] = irq; 1400 } 1401 } else { 1402 irqs[i - start_irq_index] = irq; 1403 err = request_irq(irqs[i - start_irq_index], mana_gd_intr, 0, 1404 gic->name, gic); 1405 if (err) 1406 goto free_irq; 1407 } 1408 } 1409 1410 err = irq_setup(irqs, (nvec - start_irq_index), gc->numa_node); 1411 if (err) 1412 goto free_irq; 1413 1414 gc->max_num_msix = nvec; 1415 gc->num_msix_usable = nvec; 1416 cpus_read_unlock(); 1417 kfree(irqs); 1418 return 0; 1419 1420 free_irq: 1421 for (j = i - 1; j >= 0; j--) { 1422 irq = pci_irq_vector(pdev, j); 1423 gic = &gc->irq_contexts[j]; 1424 1425 irq_update_affinity_hint(irq, NULL); 1426 free_irq(irq, gic); 1427 } 1428 1429 kfree(gc->irq_contexts); 1430 gc->irq_contexts = NULL; 1431 free_irq_array: 1432 kfree(irqs); 1433 free_irq_vector: 1434 cpus_read_unlock(); 1435 pci_free_irq_vectors(pdev); 1436 return err; 1437 } 1438 1439 static void mana_gd_remove_irqs(struct pci_dev *pdev) 1440 { 1441 struct gdma_context *gc = pci_get_drvdata(pdev); 1442 struct gdma_irq_context *gic; 1443 int irq, i; 1444 1445 if (gc->max_num_msix < 1) 1446 return; 1447 1448 for (i = 0; i < gc->max_num_msix; i++) { 1449 irq = pci_irq_vector(pdev, i); 1450 if (irq < 0) 1451 continue; 1452 1453 gic = &gc->irq_contexts[i]; 1454 1455 /* Need to clear the hint before free_irq */ 1456 irq_update_affinity_hint(irq, NULL); 1457 free_irq(irq, gic); 1458 } 1459 1460 pci_free_irq_vectors(pdev); 1461 1462 gc->max_num_msix = 0; 1463 gc->num_msix_usable = 0; 1464 kfree(gc->irq_contexts); 1465 gc->irq_contexts = NULL; 1466 } 1467 1468 static int mana_gd_setup(struct pci_dev *pdev) 1469 { 1470 struct gdma_context *gc = pci_get_drvdata(pdev); 1471 int err; 1472 1473 mana_gd_init_registers(pdev); 1474 mana_smc_init(&gc->shm_channel, gc->dev, gc->shm_base); 1475 1476 gc->service_wq = alloc_ordered_workqueue("gdma_service_wq", 0); 1477 if (!gc->service_wq) 1478 return -ENOMEM; 1479 1480 err = mana_gd_setup_irqs(pdev); 1481 if (err) { 1482 dev_err(gc->dev, "Failed to setup IRQs: %d\n", err); 1483 goto free_workqueue; 1484 } 1485 1486 err = mana_hwc_create_channel(gc); 1487 if (err) 1488 goto remove_irq; 1489 1490 err = mana_gd_verify_vf_version(pdev); 1491 if (err) 1492 goto destroy_hwc; 1493 1494 err = mana_gd_query_max_resources(pdev); 1495 if (err) 1496 goto destroy_hwc; 1497 1498 err = mana_gd_detect_devices(pdev); 1499 if (err) 1500 goto destroy_hwc; 1501 1502 dev_dbg(&pdev->dev, "mana gdma setup successful\n"); 1503 return 0; 1504 1505 destroy_hwc: 1506 mana_hwc_destroy_channel(gc); 1507 remove_irq: 1508 mana_gd_remove_irqs(pdev); 1509 free_workqueue: 1510 destroy_workqueue(gc->service_wq); 1511 dev_err(&pdev->dev, "%s failed (error %d)\n", __func__, err); 1512 return err; 1513 } 1514 1515 static void mana_gd_cleanup(struct pci_dev *pdev) 1516 { 1517 struct gdma_context *gc = pci_get_drvdata(pdev); 1518 1519 mana_hwc_destroy_channel(gc); 1520 1521 mana_gd_remove_irqs(pdev); 1522 1523 destroy_workqueue(gc->service_wq); 1524 dev_dbg(&pdev->dev, "mana gdma cleanup successful\n"); 1525 } 1526 1527 static bool mana_is_pf(unsigned short dev_id) 1528 { 1529 return dev_id == MANA_PF_DEVICE_ID; 1530 } 1531 1532 static int mana_gd_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1533 { 1534 struct gdma_context *gc; 1535 void __iomem *bar0_va; 1536 int bar = 0; 1537 int err; 1538 1539 /* Each port has 2 CQs, each CQ has at most 1 EQE at a time */ 1540 BUILD_BUG_ON(2 * MAX_PORTS_IN_MANA_DEV * GDMA_EQE_SIZE > EQ_SIZE); 1541 1542 err = pci_enable_device(pdev); 1543 if (err) { 1544 dev_err(&pdev->dev, "Failed to enable pci device (err=%d)\n", err); 1545 return -ENXIO; 1546 } 1547 1548 pci_set_master(pdev); 1549 1550 err = pci_request_regions(pdev, "mana"); 1551 if (err) 1552 goto disable_dev; 1553 1554 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 1555 if (err) { 1556 dev_err(&pdev->dev, "DMA set mask failed: %d\n", err); 1557 goto release_region; 1558 } 1559 dma_set_max_seg_size(&pdev->dev, UINT_MAX); 1560 1561 err = -ENOMEM; 1562 gc = vzalloc(sizeof(*gc)); 1563 if (!gc) 1564 goto release_region; 1565 1566 mutex_init(&gc->eq_test_event_mutex); 1567 pci_set_drvdata(pdev, gc); 1568 gc->bar0_pa = pci_resource_start(pdev, 0); 1569 1570 bar0_va = pci_iomap(pdev, bar, 0); 1571 if (!bar0_va) 1572 goto free_gc; 1573 1574 gc->numa_node = dev_to_node(&pdev->dev); 1575 gc->is_pf = mana_is_pf(pdev->device); 1576 gc->bar0_va = bar0_va; 1577 gc->dev = &pdev->dev; 1578 1579 if (gc->is_pf) 1580 gc->mana_pci_debugfs = debugfs_create_dir("0", mana_debugfs_root); 1581 else 1582 gc->mana_pci_debugfs = debugfs_create_dir(pci_slot_name(pdev->slot), 1583 mana_debugfs_root); 1584 1585 err = mana_gd_setup(pdev); 1586 if (err) 1587 goto unmap_bar; 1588 1589 err = mana_probe(&gc->mana, false); 1590 if (err) 1591 goto cleanup_gd; 1592 1593 err = mana_rdma_probe(&gc->mana_ib); 1594 if (err) 1595 goto cleanup_mana; 1596 1597 return 0; 1598 1599 cleanup_mana: 1600 mana_remove(&gc->mana, false); 1601 cleanup_gd: 1602 mana_gd_cleanup(pdev); 1603 unmap_bar: 1604 /* 1605 * at this point we know that the other debugfs child dir/files 1606 * are either not yet created or are already cleaned up. 1607 * The pci debugfs folder clean-up now, will only be cleaning up 1608 * adapter-MTU file and apc->mana_pci_debugfs folder. 1609 */ 1610 debugfs_remove_recursive(gc->mana_pci_debugfs); 1611 gc->mana_pci_debugfs = NULL; 1612 pci_iounmap(pdev, bar0_va); 1613 free_gc: 1614 pci_set_drvdata(pdev, NULL); 1615 vfree(gc); 1616 release_region: 1617 pci_release_regions(pdev); 1618 disable_dev: 1619 pci_disable_device(pdev); 1620 dev_err(&pdev->dev, "gdma probe failed: err = %d\n", err); 1621 return err; 1622 } 1623 1624 static void mana_gd_remove(struct pci_dev *pdev) 1625 { 1626 struct gdma_context *gc = pci_get_drvdata(pdev); 1627 1628 mana_rdma_remove(&gc->mana_ib); 1629 mana_remove(&gc->mana, false); 1630 1631 mana_gd_cleanup(pdev); 1632 1633 debugfs_remove_recursive(gc->mana_pci_debugfs); 1634 1635 gc->mana_pci_debugfs = NULL; 1636 1637 pci_iounmap(pdev, gc->bar0_va); 1638 1639 vfree(gc); 1640 1641 pci_release_regions(pdev); 1642 pci_disable_device(pdev); 1643 1644 dev_dbg(&pdev->dev, "mana gdma remove successful\n"); 1645 } 1646 1647 /* The 'state' parameter is not used. */ 1648 static int mana_gd_suspend(struct pci_dev *pdev, pm_message_t state) 1649 { 1650 struct gdma_context *gc = pci_get_drvdata(pdev); 1651 1652 mana_rdma_remove(&gc->mana_ib); 1653 mana_remove(&gc->mana, true); 1654 1655 mana_gd_cleanup(pdev); 1656 1657 return 0; 1658 } 1659 1660 /* In case the NIC hardware stops working, the suspend and resume callbacks will 1661 * fail -- if this happens, it's safer to just report an error than try to undo 1662 * what has been done. 1663 */ 1664 static int mana_gd_resume(struct pci_dev *pdev) 1665 { 1666 struct gdma_context *gc = pci_get_drvdata(pdev); 1667 int err; 1668 1669 err = mana_gd_setup(pdev); 1670 if (err) 1671 return err; 1672 1673 err = mana_probe(&gc->mana, true); 1674 if (err) 1675 return err; 1676 1677 err = mana_rdma_probe(&gc->mana_ib); 1678 if (err) 1679 return err; 1680 1681 return 0; 1682 } 1683 1684 /* Quiesce the device for kexec. This is also called upon reboot/shutdown. */ 1685 static void mana_gd_shutdown(struct pci_dev *pdev) 1686 { 1687 struct gdma_context *gc = pci_get_drvdata(pdev); 1688 1689 dev_info(&pdev->dev, "Shutdown was called\n"); 1690 1691 mana_rdma_remove(&gc->mana_ib); 1692 mana_remove(&gc->mana, true); 1693 1694 mana_gd_cleanup(pdev); 1695 1696 debugfs_remove_recursive(gc->mana_pci_debugfs); 1697 1698 gc->mana_pci_debugfs = NULL; 1699 1700 pci_disable_device(pdev); 1701 } 1702 1703 static const struct pci_device_id mana_id_table[] = { 1704 { PCI_DEVICE(PCI_VENDOR_ID_MICROSOFT, MANA_PF_DEVICE_ID) }, 1705 { PCI_DEVICE(PCI_VENDOR_ID_MICROSOFT, MANA_VF_DEVICE_ID) }, 1706 { } 1707 }; 1708 1709 static struct pci_driver mana_driver = { 1710 .name = "mana", 1711 .id_table = mana_id_table, 1712 .probe = mana_gd_probe, 1713 .remove = mana_gd_remove, 1714 .suspend = mana_gd_suspend, 1715 .resume = mana_gd_resume, 1716 .shutdown = mana_gd_shutdown, 1717 }; 1718 1719 static int __init mana_driver_init(void) 1720 { 1721 int err; 1722 1723 mana_debugfs_root = debugfs_create_dir("mana", NULL); 1724 1725 err = pci_register_driver(&mana_driver); 1726 if (err) { 1727 debugfs_remove(mana_debugfs_root); 1728 mana_debugfs_root = NULL; 1729 } 1730 1731 return err; 1732 } 1733 1734 static void __exit mana_driver_exit(void) 1735 { 1736 pci_unregister_driver(&mana_driver); 1737 1738 debugfs_remove(mana_debugfs_root); 1739 1740 mana_debugfs_root = NULL; 1741 } 1742 1743 module_init(mana_driver_init); 1744 module_exit(mana_driver_exit); 1745 1746 MODULE_DEVICE_TABLE(pci, mana_id_table); 1747 1748 MODULE_LICENSE("Dual BSD/GPL"); 1749 MODULE_DESCRIPTION("Microsoft Azure Network Adapter driver"); 1750