1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Mediatek MT7530 DSA Switch driver 4 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com> 5 */ 6 #include <linux/etherdevice.h> 7 #include <linux/if_bridge.h> 8 #include <linux/iopoll.h> 9 #include <linux/mdio.h> 10 #include <linux/mfd/syscon.h> 11 #include <linux/module.h> 12 #include <linux/netdevice.h> 13 #include <linux/of_irq.h> 14 #include <linux/of_mdio.h> 15 #include <linux/of_net.h> 16 #include <linux/of_platform.h> 17 #include <linux/phylink.h> 18 #include <linux/regmap.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/reset.h> 21 #include <linux/gpio/consumer.h> 22 #include <linux/gpio/driver.h> 23 #include <net/dsa.h> 24 #include <net/pkt_cls.h> 25 26 #include "mt7530.h" 27 28 static struct mt753x_pcs *pcs_to_mt753x_pcs(struct phylink_pcs *pcs) 29 { 30 return container_of(pcs, struct mt753x_pcs, pcs); 31 } 32 33 /* String, offset, and register size in bytes if different from 4 bytes */ 34 static const struct mt7530_mib_desc mt7530_mib[] = { 35 MIB_DESC(1, MT7530_PORT_MIB_TX_DROP, "TxDrop"), 36 MIB_DESC(1, MT7530_PORT_MIB_TX_CRC_ERR, "TxCrcErr"), 37 MIB_DESC(1, MT7530_PORT_MIB_TX_COLLISION, "TxCollision"), 38 MIB_DESC(1, MT7530_PORT_MIB_RX_DROP, "RxDrop"), 39 MIB_DESC(1, MT7530_PORT_MIB_RX_FILTERING, "RxFiltering"), 40 MIB_DESC(1, MT7530_PORT_MIB_RX_CRC_ERR, "RxCrcErr"), 41 MIB_DESC(1, MT7530_PORT_MIB_RX_CTRL_DROP, "RxCtrlDrop"), 42 MIB_DESC(1, MT7530_PORT_MIB_RX_INGRESS_DROP, "RxIngressDrop"), 43 MIB_DESC(1, MT7530_PORT_MIB_RX_ARL_DROP, "RxArlDrop"), 44 }; 45 46 static void 47 mt7530_mutex_lock(struct mt7530_priv *priv) 48 { 49 if (priv->bus) 50 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); 51 } 52 53 static void 54 mt7530_mutex_unlock(struct mt7530_priv *priv) 55 { 56 if (priv->bus) 57 mutex_unlock(&priv->bus->mdio_lock); 58 } 59 60 static void 61 core_write(struct mt7530_priv *priv, u32 reg, u32 val) 62 { 63 struct mii_bus *bus = priv->bus; 64 int ret; 65 66 mt7530_mutex_lock(priv); 67 68 /* Write the desired MMD Devad */ 69 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 70 MII_MMD_CTRL, MDIO_MMD_VEND2); 71 if (ret < 0) 72 goto err; 73 74 /* Write the desired MMD register address */ 75 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 76 MII_MMD_DATA, reg); 77 if (ret < 0) 78 goto err; 79 80 /* Select the Function : DATA with no post increment */ 81 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 82 MII_MMD_CTRL, MDIO_MMD_VEND2 | MII_MMD_CTRL_NOINCR); 83 if (ret < 0) 84 goto err; 85 86 /* Write the data into MMD's selected register */ 87 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 88 MII_MMD_DATA, val); 89 err: 90 if (ret < 0) 91 dev_err(&bus->dev, "failed to write mmd register\n"); 92 93 mt7530_mutex_unlock(priv); 94 } 95 96 static void 97 core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set) 98 { 99 struct mii_bus *bus = priv->bus; 100 u32 val; 101 int ret; 102 103 mt7530_mutex_lock(priv); 104 105 /* Write the desired MMD Devad */ 106 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 107 MII_MMD_CTRL, MDIO_MMD_VEND2); 108 if (ret < 0) 109 goto err; 110 111 /* Write the desired MMD register address */ 112 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 113 MII_MMD_DATA, reg); 114 if (ret < 0) 115 goto err; 116 117 /* Select the Function : DATA with no post increment */ 118 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 119 MII_MMD_CTRL, MDIO_MMD_VEND2 | MII_MMD_CTRL_NOINCR); 120 if (ret < 0) 121 goto err; 122 123 /* Read the content of the MMD's selected register */ 124 val = bus->read(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 125 MII_MMD_DATA); 126 val &= ~mask; 127 val |= set; 128 /* Write the data into MMD's selected register */ 129 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 130 MII_MMD_DATA, val); 131 err: 132 if (ret < 0) 133 dev_err(&bus->dev, "failed to write mmd register\n"); 134 135 mt7530_mutex_unlock(priv); 136 } 137 138 static void 139 core_set(struct mt7530_priv *priv, u32 reg, u32 val) 140 { 141 core_rmw(priv, reg, 0, val); 142 } 143 144 static void 145 core_clear(struct mt7530_priv *priv, u32 reg, u32 val) 146 { 147 core_rmw(priv, reg, val, 0); 148 } 149 150 static int 151 mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val) 152 { 153 int ret; 154 155 ret = regmap_write(priv->regmap, reg, val); 156 157 if (ret < 0) 158 dev_err(priv->dev, 159 "failed to write mt7530 register\n"); 160 161 return ret; 162 } 163 164 static u32 165 mt7530_mii_read(struct mt7530_priv *priv, u32 reg) 166 { 167 int ret; 168 u32 val; 169 170 ret = regmap_read(priv->regmap, reg, &val); 171 if (ret) { 172 WARN_ON_ONCE(1); 173 dev_err(priv->dev, 174 "failed to read mt7530 register\n"); 175 return 0; 176 } 177 178 return val; 179 } 180 181 static void 182 mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val) 183 { 184 mt7530_mutex_lock(priv); 185 186 mt7530_mii_write(priv, reg, val); 187 188 mt7530_mutex_unlock(priv); 189 } 190 191 static u32 192 _mt7530_unlocked_read(struct mt7530_dummy_poll *p) 193 { 194 return mt7530_mii_read(p->priv, p->reg); 195 } 196 197 static u32 198 _mt7530_read(struct mt7530_dummy_poll *p) 199 { 200 u32 val; 201 202 mt7530_mutex_lock(p->priv); 203 204 val = mt7530_mii_read(p->priv, p->reg); 205 206 mt7530_mutex_unlock(p->priv); 207 208 return val; 209 } 210 211 static u32 212 mt7530_read(struct mt7530_priv *priv, u32 reg) 213 { 214 struct mt7530_dummy_poll p; 215 216 INIT_MT7530_DUMMY_POLL(&p, priv, reg); 217 return _mt7530_read(&p); 218 } 219 220 static void 221 mt7530_rmw(struct mt7530_priv *priv, u32 reg, 222 u32 mask, u32 set) 223 { 224 mt7530_mutex_lock(priv); 225 226 regmap_update_bits(priv->regmap, reg, mask, set); 227 228 mt7530_mutex_unlock(priv); 229 } 230 231 static void 232 mt7530_set(struct mt7530_priv *priv, u32 reg, u32 val) 233 { 234 mt7530_rmw(priv, reg, val, val); 235 } 236 237 static void 238 mt7530_clear(struct mt7530_priv *priv, u32 reg, u32 val) 239 { 240 mt7530_rmw(priv, reg, val, 0); 241 } 242 243 static int 244 mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp) 245 { 246 u32 val; 247 int ret; 248 struct mt7530_dummy_poll p; 249 250 /* Set the command operating upon the MAC address entries */ 251 val = ATC_BUSY | ATC_MAT(0) | cmd; 252 mt7530_write(priv, MT7530_ATC, val); 253 254 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_ATC); 255 ret = readx_poll_timeout(_mt7530_read, &p, val, 256 !(val & ATC_BUSY), 20, 20000); 257 if (ret < 0) { 258 dev_err(priv->dev, "reset timeout\n"); 259 return ret; 260 } 261 262 /* Additional sanity for read command if the specified 263 * entry is invalid 264 */ 265 val = mt7530_read(priv, MT7530_ATC); 266 if ((cmd == MT7530_FDB_READ) && (val & ATC_INVALID)) 267 return -EINVAL; 268 269 if (rsp) 270 *rsp = val; 271 272 return 0; 273 } 274 275 static void 276 mt7530_fdb_read(struct mt7530_priv *priv, struct mt7530_fdb *fdb) 277 { 278 u32 reg[3]; 279 int i; 280 281 /* Read from ARL table into an array */ 282 for (i = 0; i < 3; i++) { 283 reg[i] = mt7530_read(priv, MT7530_TSRA1 + (i * 4)); 284 285 dev_dbg(priv->dev, "%s(%d) reg[%d]=0x%x\n", 286 __func__, __LINE__, i, reg[i]); 287 } 288 289 fdb->vid = (reg[1] >> CVID) & CVID_MASK; 290 fdb->aging = (reg[2] >> AGE_TIMER) & AGE_TIMER_MASK; 291 fdb->port_mask = (reg[2] >> PORT_MAP) & PORT_MAP_MASK; 292 fdb->mac[0] = (reg[0] >> MAC_BYTE_0) & MAC_BYTE_MASK; 293 fdb->mac[1] = (reg[0] >> MAC_BYTE_1) & MAC_BYTE_MASK; 294 fdb->mac[2] = (reg[0] >> MAC_BYTE_2) & MAC_BYTE_MASK; 295 fdb->mac[3] = (reg[0] >> MAC_BYTE_3) & MAC_BYTE_MASK; 296 fdb->mac[4] = (reg[1] >> MAC_BYTE_4) & MAC_BYTE_MASK; 297 fdb->mac[5] = (reg[1] >> MAC_BYTE_5) & MAC_BYTE_MASK; 298 fdb->noarp = ((reg[2] >> ENT_STATUS) & ENT_STATUS_MASK) == STATIC_ENT; 299 } 300 301 static void 302 mt7530_fdb_write(struct mt7530_priv *priv, u16 vid, 303 u8 port_mask, const u8 *mac, 304 u8 aging, u8 type) 305 { 306 u32 reg[3] = { 0 }; 307 int i; 308 309 reg[1] |= vid & CVID_MASK; 310 reg[1] |= ATA2_IVL; 311 reg[1] |= ATA2_FID(FID_BRIDGED); 312 reg[2] |= (aging & AGE_TIMER_MASK) << AGE_TIMER; 313 reg[2] |= (port_mask & PORT_MAP_MASK) << PORT_MAP; 314 /* STATIC_ENT indicate that entry is static wouldn't 315 * be aged out and STATIC_EMP specified as erasing an 316 * entry 317 */ 318 reg[2] |= (type & ENT_STATUS_MASK) << ENT_STATUS; 319 reg[1] |= mac[5] << MAC_BYTE_5; 320 reg[1] |= mac[4] << MAC_BYTE_4; 321 reg[0] |= mac[3] << MAC_BYTE_3; 322 reg[0] |= mac[2] << MAC_BYTE_2; 323 reg[0] |= mac[1] << MAC_BYTE_1; 324 reg[0] |= mac[0] << MAC_BYTE_0; 325 326 /* Write array into the ARL table */ 327 for (i = 0; i < 3; i++) 328 mt7530_write(priv, MT7530_ATA1 + (i * 4), reg[i]); 329 } 330 331 /* Set up switch core clock for MT7530 */ 332 static void mt7530_pll_setup(struct mt7530_priv *priv) 333 { 334 /* Disable core clock */ 335 core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); 336 337 /* Disable PLL */ 338 core_write(priv, CORE_GSWPLL_GRP1, 0); 339 340 /* Set core clock into 500Mhz */ 341 core_write(priv, CORE_GSWPLL_GRP2, 342 RG_GSWPLL_POSDIV_500M(1) | 343 RG_GSWPLL_FBKDIV_500M(25)); 344 345 /* Enable PLL */ 346 core_write(priv, CORE_GSWPLL_GRP1, 347 RG_GSWPLL_EN_PRE | 348 RG_GSWPLL_POSDIV_200M(2) | 349 RG_GSWPLL_FBKDIV_200M(32)); 350 351 udelay(20); 352 353 /* Enable core clock */ 354 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); 355 } 356 357 /* If port 6 is available as a CPU port, always prefer that as the default, 358 * otherwise don't care. 359 */ 360 static struct dsa_port * 361 mt753x_preferred_default_local_cpu_port(struct dsa_switch *ds) 362 { 363 struct dsa_port *cpu_dp = dsa_to_port(ds, 6); 364 365 if (dsa_port_is_cpu(cpu_dp)) 366 return cpu_dp; 367 368 return NULL; 369 } 370 371 /* Setup port 6 interface mode and TRGMII TX circuit */ 372 static void 373 mt7530_setup_port6(struct dsa_switch *ds, phy_interface_t interface) 374 { 375 struct mt7530_priv *priv = ds->priv; 376 u32 ncpo1, ssc_delta, xtal; 377 378 /* Disable the MT7530 TRGMII clocks */ 379 core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN); 380 381 if (interface == PHY_INTERFACE_MODE_RGMII) { 382 mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, 383 P6_INTF_MODE(0)); 384 return; 385 } 386 387 mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, P6_INTF_MODE(1)); 388 389 xtal = mt7530_read(priv, MT753X_MTRAP) & MT7530_XTAL_MASK; 390 391 if (xtal == MT7530_XTAL_25MHZ) 392 ssc_delta = 0x57; 393 else 394 ssc_delta = 0x87; 395 396 if (priv->id == ID_MT7621) { 397 /* PLL frequency: 125MHz: 1.0GBit */ 398 if (xtal == MT7530_XTAL_40MHZ) 399 ncpo1 = 0x0640; 400 if (xtal == MT7530_XTAL_25MHZ) 401 ncpo1 = 0x0a00; 402 } else { /* PLL frequency: 250MHz: 2.0Gbit */ 403 if (xtal == MT7530_XTAL_40MHZ) 404 ncpo1 = 0x0c80; 405 if (xtal == MT7530_XTAL_25MHZ) 406 ncpo1 = 0x1400; 407 } 408 409 /* Setup the MT7530 TRGMII Tx Clock */ 410 core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1)); 411 core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0)); 412 core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta)); 413 core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta)); 414 core_write(priv, CORE_PLL_GROUP4, RG_SYSPLL_DDSFBK_EN | 415 RG_SYSPLL_BIAS_EN | RG_SYSPLL_BIAS_LPF_EN); 416 core_write(priv, CORE_PLL_GROUP2, RG_SYSPLL_EN_NORMAL | 417 RG_SYSPLL_VODEN | RG_SYSPLL_POSDIV(1)); 418 core_write(priv, CORE_PLL_GROUP7, RG_LCDDS_PCW_NCPO_CHG | 419 RG_LCCDS_C(3) | RG_LCDDS_PWDB | RG_LCDDS_ISO_EN); 420 421 /* Enable the MT7530 TRGMII clocks */ 422 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN); 423 } 424 425 static void 426 mt7531_pll_setup(struct mt7530_priv *priv) 427 { 428 enum mt7531_xtal_fsel xtal; 429 u32 top_sig; 430 u32 hwstrap; 431 u32 val; 432 433 val = mt7530_read(priv, MT7531_CREV); 434 top_sig = mt7530_read(priv, MT7531_TOP_SIG_SR); 435 hwstrap = mt7530_read(priv, MT753X_TRAP); 436 if ((val & CHIP_REV_M) > 0) 437 xtal = (top_sig & PAD_MCM_SMI_EN) ? MT7531_XTAL_FSEL_40MHZ : 438 MT7531_XTAL_FSEL_25MHZ; 439 else 440 xtal = (hwstrap & MT7531_XTAL25) ? MT7531_XTAL_FSEL_25MHZ : 441 MT7531_XTAL_FSEL_40MHZ; 442 443 /* Step 1 : Disable MT7531 COREPLL */ 444 val = mt7530_read(priv, MT7531_PLLGP_EN); 445 val &= ~EN_COREPLL; 446 mt7530_write(priv, MT7531_PLLGP_EN, val); 447 448 /* Step 2: switch to XTAL output */ 449 val = mt7530_read(priv, MT7531_PLLGP_EN); 450 val |= SW_CLKSW; 451 mt7530_write(priv, MT7531_PLLGP_EN, val); 452 453 val = mt7530_read(priv, MT7531_PLLGP_CR0); 454 val &= ~RG_COREPLL_EN; 455 mt7530_write(priv, MT7531_PLLGP_CR0, val); 456 457 /* Step 3: disable PLLGP and enable program PLLGP */ 458 val = mt7530_read(priv, MT7531_PLLGP_EN); 459 val |= SW_PLLGP; 460 mt7530_write(priv, MT7531_PLLGP_EN, val); 461 462 /* Step 4: program COREPLL output frequency to 500MHz */ 463 val = mt7530_read(priv, MT7531_PLLGP_CR0); 464 val &= ~RG_COREPLL_POSDIV_M; 465 val |= 2 << RG_COREPLL_POSDIV_S; 466 mt7530_write(priv, MT7531_PLLGP_CR0, val); 467 usleep_range(25, 35); 468 469 switch (xtal) { 470 case MT7531_XTAL_FSEL_25MHZ: 471 val = mt7530_read(priv, MT7531_PLLGP_CR0); 472 val &= ~RG_COREPLL_SDM_PCW_M; 473 val |= 0x140000 << RG_COREPLL_SDM_PCW_S; 474 mt7530_write(priv, MT7531_PLLGP_CR0, val); 475 break; 476 case MT7531_XTAL_FSEL_40MHZ: 477 val = mt7530_read(priv, MT7531_PLLGP_CR0); 478 val &= ~RG_COREPLL_SDM_PCW_M; 479 val |= 0x190000 << RG_COREPLL_SDM_PCW_S; 480 mt7530_write(priv, MT7531_PLLGP_CR0, val); 481 break; 482 } 483 484 /* Set feedback divide ratio update signal to high */ 485 val = mt7530_read(priv, MT7531_PLLGP_CR0); 486 val |= RG_COREPLL_SDM_PCW_CHG; 487 mt7530_write(priv, MT7531_PLLGP_CR0, val); 488 /* Wait for at least 16 XTAL clocks */ 489 usleep_range(10, 20); 490 491 /* Step 5: set feedback divide ratio update signal to low */ 492 val = mt7530_read(priv, MT7531_PLLGP_CR0); 493 val &= ~RG_COREPLL_SDM_PCW_CHG; 494 mt7530_write(priv, MT7531_PLLGP_CR0, val); 495 496 /* Enable 325M clock for SGMII */ 497 mt7530_write(priv, MT7531_ANA_PLLGP_CR5, 0xad0000); 498 499 /* Enable 250SSC clock for RGMII */ 500 mt7530_write(priv, MT7531_ANA_PLLGP_CR2, 0x4f40000); 501 502 /* Step 6: Enable MT7531 PLL */ 503 val = mt7530_read(priv, MT7531_PLLGP_CR0); 504 val |= RG_COREPLL_EN; 505 mt7530_write(priv, MT7531_PLLGP_CR0, val); 506 507 val = mt7530_read(priv, MT7531_PLLGP_EN); 508 val |= EN_COREPLL; 509 mt7530_write(priv, MT7531_PLLGP_EN, val); 510 usleep_range(25, 35); 511 } 512 513 static void 514 mt7530_mib_reset(struct dsa_switch *ds) 515 { 516 struct mt7530_priv *priv = ds->priv; 517 518 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_FLUSH); 519 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE); 520 } 521 522 static int mt7530_phy_read_c22(struct mt7530_priv *priv, int port, int regnum) 523 { 524 return mdiobus_read_nested(priv->bus, port, regnum); 525 } 526 527 static int mt7530_phy_write_c22(struct mt7530_priv *priv, int port, int regnum, 528 u16 val) 529 { 530 return mdiobus_write_nested(priv->bus, port, regnum, val); 531 } 532 533 static int mt7530_phy_read_c45(struct mt7530_priv *priv, int port, 534 int devad, int regnum) 535 { 536 return mdiobus_c45_read_nested(priv->bus, port, devad, regnum); 537 } 538 539 static int mt7530_phy_write_c45(struct mt7530_priv *priv, int port, int devad, 540 int regnum, u16 val) 541 { 542 return mdiobus_c45_write_nested(priv->bus, port, devad, regnum, val); 543 } 544 545 static int 546 mt7531_ind_c45_phy_read(struct mt7530_priv *priv, int port, int devad, 547 int regnum) 548 { 549 struct mt7530_dummy_poll p; 550 u32 reg, val; 551 int ret; 552 553 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 554 555 mt7530_mutex_lock(priv); 556 557 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 558 !(val & MT7531_PHY_ACS_ST), 20, 100000); 559 if (ret < 0) { 560 dev_err(priv->dev, "poll timeout\n"); 561 goto out; 562 } 563 564 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) | 565 MT7531_MDIO_DEV_ADDR(devad) | regnum; 566 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 567 568 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 569 !(val & MT7531_PHY_ACS_ST), 20, 100000); 570 if (ret < 0) { 571 dev_err(priv->dev, "poll timeout\n"); 572 goto out; 573 } 574 575 reg = MT7531_MDIO_CL45_READ | MT7531_MDIO_PHY_ADDR(port) | 576 MT7531_MDIO_DEV_ADDR(devad); 577 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 578 579 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 580 !(val & MT7531_PHY_ACS_ST), 20, 100000); 581 if (ret < 0) { 582 dev_err(priv->dev, "poll timeout\n"); 583 goto out; 584 } 585 586 ret = val & MT7531_MDIO_RW_DATA_MASK; 587 out: 588 mt7530_mutex_unlock(priv); 589 590 return ret; 591 } 592 593 static int 594 mt7531_ind_c45_phy_write(struct mt7530_priv *priv, int port, int devad, 595 int regnum, u16 data) 596 { 597 struct mt7530_dummy_poll p; 598 u32 val, reg; 599 int ret; 600 601 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 602 603 mt7530_mutex_lock(priv); 604 605 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 606 !(val & MT7531_PHY_ACS_ST), 20, 100000); 607 if (ret < 0) { 608 dev_err(priv->dev, "poll timeout\n"); 609 goto out; 610 } 611 612 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) | 613 MT7531_MDIO_DEV_ADDR(devad) | regnum; 614 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 615 616 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 617 !(val & MT7531_PHY_ACS_ST), 20, 100000); 618 if (ret < 0) { 619 dev_err(priv->dev, "poll timeout\n"); 620 goto out; 621 } 622 623 reg = MT7531_MDIO_CL45_WRITE | MT7531_MDIO_PHY_ADDR(port) | 624 MT7531_MDIO_DEV_ADDR(devad) | data; 625 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 626 627 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 628 !(val & MT7531_PHY_ACS_ST), 20, 100000); 629 if (ret < 0) { 630 dev_err(priv->dev, "poll timeout\n"); 631 goto out; 632 } 633 634 out: 635 mt7530_mutex_unlock(priv); 636 637 return ret; 638 } 639 640 static int 641 mt7531_ind_c22_phy_read(struct mt7530_priv *priv, int port, int regnum) 642 { 643 struct mt7530_dummy_poll p; 644 int ret; 645 u32 val; 646 647 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 648 649 mt7530_mutex_lock(priv); 650 651 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 652 !(val & MT7531_PHY_ACS_ST), 20, 100000); 653 if (ret < 0) { 654 dev_err(priv->dev, "poll timeout\n"); 655 goto out; 656 } 657 658 val = MT7531_MDIO_CL22_READ | MT7531_MDIO_PHY_ADDR(port) | 659 MT7531_MDIO_REG_ADDR(regnum); 660 661 mt7530_mii_write(priv, MT7531_PHY_IAC, val | MT7531_PHY_ACS_ST); 662 663 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 664 !(val & MT7531_PHY_ACS_ST), 20, 100000); 665 if (ret < 0) { 666 dev_err(priv->dev, "poll timeout\n"); 667 goto out; 668 } 669 670 ret = val & MT7531_MDIO_RW_DATA_MASK; 671 out: 672 mt7530_mutex_unlock(priv); 673 674 return ret; 675 } 676 677 static int 678 mt7531_ind_c22_phy_write(struct mt7530_priv *priv, int port, int regnum, 679 u16 data) 680 { 681 struct mt7530_dummy_poll p; 682 int ret; 683 u32 reg; 684 685 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 686 687 mt7530_mutex_lock(priv); 688 689 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg, 690 !(reg & MT7531_PHY_ACS_ST), 20, 100000); 691 if (ret < 0) { 692 dev_err(priv->dev, "poll timeout\n"); 693 goto out; 694 } 695 696 reg = MT7531_MDIO_CL22_WRITE | MT7531_MDIO_PHY_ADDR(port) | 697 MT7531_MDIO_REG_ADDR(regnum) | data; 698 699 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 700 701 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg, 702 !(reg & MT7531_PHY_ACS_ST), 20, 100000); 703 if (ret < 0) { 704 dev_err(priv->dev, "poll timeout\n"); 705 goto out; 706 } 707 708 out: 709 mt7530_mutex_unlock(priv); 710 711 return ret; 712 } 713 714 static int 715 mt753x_phy_read_c22(struct mii_bus *bus, int port, int regnum) 716 { 717 struct mt7530_priv *priv = bus->priv; 718 719 return priv->info->phy_read_c22(priv, port, regnum); 720 } 721 722 static int 723 mt753x_phy_read_c45(struct mii_bus *bus, int port, int devad, int regnum) 724 { 725 struct mt7530_priv *priv = bus->priv; 726 727 return priv->info->phy_read_c45(priv, port, devad, regnum); 728 } 729 730 static int 731 mt753x_phy_write_c22(struct mii_bus *bus, int port, int regnum, u16 val) 732 { 733 struct mt7530_priv *priv = bus->priv; 734 735 return priv->info->phy_write_c22(priv, port, regnum, val); 736 } 737 738 static int 739 mt753x_phy_write_c45(struct mii_bus *bus, int port, int devad, int regnum, 740 u16 val) 741 { 742 struct mt7530_priv *priv = bus->priv; 743 744 return priv->info->phy_write_c45(priv, port, devad, regnum, val); 745 } 746 747 static void 748 mt7530_get_strings(struct dsa_switch *ds, int port, u32 stringset, 749 uint8_t *data) 750 { 751 int i; 752 753 if (stringset != ETH_SS_STATS) 754 return; 755 756 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) 757 ethtool_puts(&data, mt7530_mib[i].name); 758 } 759 760 static void 761 mt7530_read_port_stats(struct mt7530_priv *priv, int port, 762 u32 offset, u8 size, uint64_t *data) 763 { 764 u32 val, reg = MT7530_PORT_MIB_COUNTER(port) + offset; 765 766 val = mt7530_read(priv, reg); 767 *data = val; 768 769 if (size == 2) { 770 val = mt7530_read(priv, reg + 4); 771 *data |= (u64)val << 32; 772 } 773 } 774 775 static void 776 mt7530_get_ethtool_stats(struct dsa_switch *ds, int port, 777 uint64_t *data) 778 { 779 struct mt7530_priv *priv = ds->priv; 780 const struct mt7530_mib_desc *mib; 781 int i; 782 783 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) { 784 mib = &mt7530_mib[i]; 785 786 mt7530_read_port_stats(priv, port, mib->offset, mib->size, 787 data + i); 788 } 789 } 790 791 static int 792 mt7530_get_sset_count(struct dsa_switch *ds, int port, int sset) 793 { 794 if (sset != ETH_SS_STATS) 795 return 0; 796 797 return ARRAY_SIZE(mt7530_mib); 798 } 799 800 static void mt7530_get_eth_mac_stats(struct dsa_switch *ds, int port, 801 struct ethtool_eth_mac_stats *mac_stats) 802 { 803 struct mt7530_priv *priv = ds->priv; 804 805 /* MIB counter doesn't provide a FramesTransmittedOK but instead 806 * provide stats for Unicast, Broadcast and Multicast frames separately. 807 * To simulate a global frame counter, read Unicast and addition Multicast 808 * and Broadcast later 809 */ 810 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_UNICAST, 1, 811 &mac_stats->FramesTransmittedOK); 812 813 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_SINGLE_COLLISION, 1, 814 &mac_stats->SingleCollisionFrames); 815 816 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_MULTIPLE_COLLISION, 1, 817 &mac_stats->MultipleCollisionFrames); 818 819 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_UNICAST, 1, 820 &mac_stats->FramesReceivedOK); 821 822 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_BYTES, 2, 823 &mac_stats->OctetsTransmittedOK); 824 825 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_ALIGN_ERR, 1, 826 &mac_stats->AlignmentErrors); 827 828 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_DEFERRED, 1, 829 &mac_stats->FramesWithDeferredXmissions); 830 831 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_LATE_COLLISION, 1, 832 &mac_stats->LateCollisions); 833 834 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_EXCESSIVE_COLLISION, 1, 835 &mac_stats->FramesAbortedDueToXSColls); 836 837 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_BYTES, 2, 838 &mac_stats->OctetsReceivedOK); 839 840 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_MULTICAST, 1, 841 &mac_stats->MulticastFramesXmittedOK); 842 mac_stats->FramesTransmittedOK += mac_stats->MulticastFramesXmittedOK; 843 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_BROADCAST, 1, 844 &mac_stats->BroadcastFramesXmittedOK); 845 mac_stats->FramesTransmittedOK += mac_stats->BroadcastFramesXmittedOK; 846 847 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_MULTICAST, 1, 848 &mac_stats->MulticastFramesReceivedOK); 849 mac_stats->FramesReceivedOK += mac_stats->MulticastFramesReceivedOK; 850 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_BROADCAST, 1, 851 &mac_stats->BroadcastFramesReceivedOK); 852 mac_stats->FramesReceivedOK += mac_stats->BroadcastFramesReceivedOK; 853 } 854 855 static const struct ethtool_rmon_hist_range mt7530_rmon_ranges[] = { 856 { 0, 64 }, 857 { 65, 127 }, 858 { 128, 255 }, 859 { 256, 511 }, 860 { 512, 1023 }, 861 { 1024, MT7530_MAX_MTU }, 862 {} 863 }; 864 865 static void mt7530_get_rmon_stats(struct dsa_switch *ds, int port, 866 struct ethtool_rmon_stats *rmon_stats, 867 const struct ethtool_rmon_hist_range **ranges) 868 { 869 struct mt7530_priv *priv = ds->priv; 870 871 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_UNDER_SIZE_ERR, 1, 872 &rmon_stats->undersize_pkts); 873 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_OVER_SZ_ERR, 1, 874 &rmon_stats->oversize_pkts); 875 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_FRAG_ERR, 1, 876 &rmon_stats->fragments); 877 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_JABBER_ERR, 1, 878 &rmon_stats->jabbers); 879 880 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PKT_SZ_64, 1, 881 &rmon_stats->hist[0]); 882 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PKT_SZ_65_TO_127, 1, 883 &rmon_stats->hist[1]); 884 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PKT_SZ_128_TO_255, 1, 885 &rmon_stats->hist[2]); 886 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PKT_SZ_256_TO_511, 1, 887 &rmon_stats->hist[3]); 888 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PKT_SZ_512_TO_1023, 1, 889 &rmon_stats->hist[4]); 890 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PKT_SZ_1024_TO_MAX, 1, 891 &rmon_stats->hist[5]); 892 893 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PKT_SZ_64, 1, 894 &rmon_stats->hist_tx[0]); 895 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PKT_SZ_65_TO_127, 1, 896 &rmon_stats->hist_tx[1]); 897 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PKT_SZ_128_TO_255, 1, 898 &rmon_stats->hist_tx[2]); 899 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PKT_SZ_256_TO_511, 1, 900 &rmon_stats->hist_tx[3]); 901 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PKT_SZ_512_TO_1023, 1, 902 &rmon_stats->hist_tx[4]); 903 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PKT_SZ_1024_TO_MAX, 1, 904 &rmon_stats->hist_tx[5]); 905 906 *ranges = mt7530_rmon_ranges; 907 } 908 909 static void mt7530_get_stats64(struct dsa_switch *ds, int port, 910 struct rtnl_link_stats64 *storage) 911 { 912 struct mt7530_priv *priv = ds->priv; 913 uint64_t data; 914 915 /* MIB counter doesn't provide a FramesTransmittedOK but instead 916 * provide stats for Unicast, Broadcast and Multicast frames separately. 917 * To simulate a global frame counter, read Unicast and addition Multicast 918 * and Broadcast later 919 */ 920 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_UNICAST, 1, 921 &storage->rx_packets); 922 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_MULTICAST, 1, 923 &storage->multicast); 924 storage->rx_packets += storage->multicast; 925 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_BROADCAST, 1, 926 &data); 927 storage->rx_packets += data; 928 929 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_UNICAST, 1, 930 &storage->tx_packets); 931 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_MULTICAST, 1, 932 &data); 933 storage->tx_packets += data; 934 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_BROADCAST, 1, 935 &data); 936 storage->tx_packets += data; 937 938 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_BYTES, 2, 939 &storage->rx_bytes); 940 941 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_BYTES, 2, 942 &storage->tx_bytes); 943 944 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_DROP, 1, 945 &storage->rx_dropped); 946 947 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_DROP, 1, 948 &storage->tx_dropped); 949 950 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_CRC_ERR, 1, 951 &storage->rx_crc_errors); 952 } 953 954 static void mt7530_get_eth_ctrl_stats(struct dsa_switch *ds, int port, 955 struct ethtool_eth_ctrl_stats *ctrl_stats) 956 { 957 struct mt7530_priv *priv = ds->priv; 958 959 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PAUSE, 1, 960 &ctrl_stats->MACControlFramesTransmitted); 961 962 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PAUSE, 1, 963 &ctrl_stats->MACControlFramesReceived); 964 } 965 966 static int 967 mt7530_set_ageing_time(struct dsa_switch *ds, unsigned int msecs) 968 { 969 struct mt7530_priv *priv = ds->priv; 970 unsigned int secs = msecs / 1000; 971 unsigned int tmp_age_count; 972 unsigned int error = -1; 973 unsigned int age_count; 974 unsigned int age_unit; 975 976 /* Applied timer is (AGE_CNT + 1) * (AGE_UNIT + 1) seconds */ 977 if (secs < 1 || secs > (AGE_CNT_MAX + 1) * (AGE_UNIT_MAX + 1)) 978 return -ERANGE; 979 980 /* iterate through all possible age_count to find the closest pair */ 981 for (tmp_age_count = 0; tmp_age_count <= AGE_CNT_MAX; ++tmp_age_count) { 982 unsigned int tmp_age_unit = secs / (tmp_age_count + 1) - 1; 983 984 if (tmp_age_unit <= AGE_UNIT_MAX) { 985 unsigned int tmp_error = secs - 986 (tmp_age_count + 1) * (tmp_age_unit + 1); 987 988 /* found a closer pair */ 989 if (error > tmp_error) { 990 error = tmp_error; 991 age_count = tmp_age_count; 992 age_unit = tmp_age_unit; 993 } 994 995 /* found the exact match, so break the loop */ 996 if (!error) 997 break; 998 } 999 } 1000 1001 mt7530_write(priv, MT7530_AAC, AGE_CNT(age_count) | AGE_UNIT(age_unit)); 1002 1003 return 0; 1004 } 1005 1006 static const char *mt7530_p5_mode_str(unsigned int mode) 1007 { 1008 switch (mode) { 1009 case MUX_PHY_P0: 1010 return "MUX PHY P0"; 1011 case MUX_PHY_P4: 1012 return "MUX PHY P4"; 1013 default: 1014 return "GMAC5"; 1015 } 1016 } 1017 1018 static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface) 1019 { 1020 struct mt7530_priv *priv = ds->priv; 1021 u8 tx_delay = 0; 1022 int val; 1023 1024 mutex_lock(&priv->reg_mutex); 1025 1026 val = mt7530_read(priv, MT753X_MTRAP); 1027 1028 val &= ~MT7530_P5_PHY0_SEL & ~MT7530_P5_MAC_SEL & ~MT7530_P5_RGMII_MODE; 1029 1030 switch (priv->p5_mode) { 1031 /* MUX_PHY_P0: P0 -> P5 -> SoC MAC */ 1032 case MUX_PHY_P0: 1033 val |= MT7530_P5_PHY0_SEL; 1034 fallthrough; 1035 1036 /* MUX_PHY_P4: P4 -> P5 -> SoC MAC */ 1037 case MUX_PHY_P4: 1038 /* Setup the MAC by default for the cpu port */ 1039 mt7530_write(priv, MT753X_PMCR_P(5), 0x56300); 1040 break; 1041 1042 /* GMAC5: P5 -> SoC MAC or external PHY */ 1043 default: 1044 val |= MT7530_P5_MAC_SEL; 1045 break; 1046 } 1047 1048 /* Setup RGMII settings */ 1049 if (phy_interface_mode_is_rgmii(interface)) { 1050 val |= MT7530_P5_RGMII_MODE; 1051 1052 /* P5 RGMII RX Clock Control: delay setting for 1000M */ 1053 mt7530_write(priv, MT7530_P5RGMIIRXCR, CSR_RGMII_EDGE_ALIGN); 1054 1055 /* Don't set delay in DSA mode */ 1056 if (!dsa_is_dsa_port(priv->ds, 5) && 1057 (interface == PHY_INTERFACE_MODE_RGMII_TXID || 1058 interface == PHY_INTERFACE_MODE_RGMII_ID)) 1059 tx_delay = 4; /* n * 0.5 ns */ 1060 1061 /* P5 RGMII TX Clock Control: delay x */ 1062 mt7530_write(priv, MT7530_P5RGMIITXCR, 1063 CSR_RGMII_TXC_CFG(0x10 + tx_delay)); 1064 1065 /* reduce P5 RGMII Tx driving, 8mA */ 1066 mt7530_write(priv, MT7530_IO_DRV_CR, 1067 P5_IO_CLK_DRV(1) | P5_IO_DATA_DRV(1)); 1068 } 1069 1070 mt7530_write(priv, MT753X_MTRAP, val); 1071 1072 dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, mode=%s, phy-mode=%s\n", val, 1073 mt7530_p5_mode_str(priv->p5_mode), phy_modes(interface)); 1074 1075 mutex_unlock(&priv->reg_mutex); 1076 } 1077 1078 /* In Clause 5 of IEEE Std 802-2014, two sublayers of the data link layer (DLL) 1079 * of the Open Systems Interconnection basic reference model (OSI/RM) are 1080 * described; the medium access control (MAC) and logical link control (LLC) 1081 * sublayers. The MAC sublayer is the one facing the physical layer. 1082 * 1083 * In 8.2 of IEEE Std 802.1Q-2022, the Bridge architecture is described. A 1084 * Bridge component comprises a MAC Relay Entity for interconnecting the Ports 1085 * of the Bridge, at least two Ports, and higher layer entities with at least a 1086 * Spanning Tree Protocol Entity included. 1087 * 1088 * Each Bridge Port also functions as an end station and shall provide the MAC 1089 * Service to an LLC Entity. Each instance of the MAC Service is provided to a 1090 * distinct LLC Entity that supports protocol identification, multiplexing, and 1091 * demultiplexing, for protocol data unit (PDU) transmission and reception by 1092 * one or more higher layer entities. 1093 * 1094 * It is described in 8.13.9 of IEEE Std 802.1Q-2022 that in a Bridge, the LLC 1095 * Entity associated with each Bridge Port is modeled as being directly 1096 * connected to the attached Local Area Network (LAN). 1097 * 1098 * On the switch with CPU port architecture, CPU port functions as Management 1099 * Port, and the Management Port functionality is provided by software which 1100 * functions as an end station. Software is connected to an IEEE 802 LAN that is 1101 * wholly contained within the system that incorporates the Bridge. Software 1102 * provides access to the LLC Entity associated with each Bridge Port by the 1103 * value of the source port field on the special tag on the frame received by 1104 * software. 1105 * 1106 * We call frames that carry control information to determine the active 1107 * topology and current extent of each Virtual Local Area Network (VLAN), i.e., 1108 * spanning tree or Shortest Path Bridging (SPB) and Multiple VLAN Registration 1109 * Protocol Data Units (MVRPDUs), and frames from other link constrained 1110 * protocols, such as Extensible Authentication Protocol over LAN (EAPOL) and 1111 * Link Layer Discovery Protocol (LLDP), link-local frames. They are not 1112 * forwarded by a Bridge. Permanently configured entries in the filtering 1113 * database (FDB) ensure that such frames are discarded by the Forwarding 1114 * Process. In 8.6.3 of IEEE Std 802.1Q-2022, this is described in detail: 1115 * 1116 * Each of the reserved MAC addresses specified in Table 8-1 1117 * (01-80-C2-00-00-[00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F]) shall be 1118 * permanently configured in the FDB in C-VLAN components and ERs. 1119 * 1120 * Each of the reserved MAC addresses specified in Table 8-2 1121 * (01-80-C2-00-00-[01,02,03,04,05,06,07,08,09,0A,0E]) shall be permanently 1122 * configured in the FDB in S-VLAN components. 1123 * 1124 * Each of the reserved MAC addresses specified in Table 8-3 1125 * (01-80-C2-00-00-[01,02,04,0E]) shall be permanently configured in the FDB in 1126 * TPMR components. 1127 * 1128 * The FDB entries for reserved MAC addresses shall specify filtering for all 1129 * Bridge Ports and all VIDs. Management shall not provide the capability to 1130 * modify or remove entries for reserved MAC addresses. 1131 * 1132 * The addresses in Table 8-1, Table 8-2, and Table 8-3 determine the scope of 1133 * propagation of PDUs within a Bridged Network, as follows: 1134 * 1135 * The Nearest Bridge group address (01-80-C2-00-00-0E) is an address that no 1136 * conformant Two-Port MAC Relay (TPMR) component, Service VLAN (S-VLAN) 1137 * component, Customer VLAN (C-VLAN) component, or MAC Bridge can forward. 1138 * PDUs transmitted using this destination address, or any other addresses 1139 * that appear in Table 8-1, Table 8-2, and Table 8-3 1140 * (01-80-C2-00-00-[00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F]), can 1141 * therefore travel no further than those stations that can be reached via a 1142 * single individual LAN from the originating station. 1143 * 1144 * The Nearest non-TPMR Bridge group address (01-80-C2-00-00-03), is an 1145 * address that no conformant S-VLAN component, C-VLAN component, or MAC 1146 * Bridge can forward; however, this address is relayed by a TPMR component. 1147 * PDUs using this destination address, or any of the other addresses that 1148 * appear in both Table 8-1 and Table 8-2 but not in Table 8-3 1149 * (01-80-C2-00-00-[00,03,05,06,07,08,09,0A,0B,0C,0D,0F]), will be relayed by 1150 * any TPMRs but will propagate no further than the nearest S-VLAN component, 1151 * C-VLAN component, or MAC Bridge. 1152 * 1153 * The Nearest Customer Bridge group address (01-80-C2-00-00-00) is an address 1154 * that no conformant C-VLAN component, MAC Bridge can forward; however, it is 1155 * relayed by TPMR components and S-VLAN components. PDUs using this 1156 * destination address, or any of the other addresses that appear in Table 8-1 1157 * but not in either Table 8-2 or Table 8-3 (01-80-C2-00-00-[00,0B,0C,0D,0F]), 1158 * will be relayed by TPMR components and S-VLAN components but will propagate 1159 * no further than the nearest C-VLAN component or MAC Bridge. 1160 * 1161 * Because the LLC Entity associated with each Bridge Port is provided via CPU 1162 * port, we must not filter these frames but forward them to CPU port. 1163 * 1164 * In a Bridge, the transmission Port is majorly decided by ingress and egress 1165 * rules, FDB, and spanning tree Port State functions of the Forwarding Process. 1166 * For link-local frames, only CPU port should be designated as destination port 1167 * in the FDB, and the other functions of the Forwarding Process must not 1168 * interfere with the decision of the transmission Port. We call this process 1169 * trapping frames to CPU port. 1170 * 1171 * Therefore, on the switch with CPU port architecture, link-local frames must 1172 * be trapped to CPU port, and certain link-local frames received by a Port of a 1173 * Bridge comprising a TPMR component or an S-VLAN component must be excluded 1174 * from it. 1175 * 1176 * A Bridge of the switch with CPU port architecture cannot comprise a Two-Port 1177 * MAC Relay (TPMR) component as a TPMR component supports only a subset of the 1178 * functionality of a MAC Bridge. A Bridge comprising two Ports (Management Port 1179 * doesn't count) of this architecture will either function as a standard MAC 1180 * Bridge or a standard VLAN Bridge. 1181 * 1182 * Therefore, a Bridge of this architecture can only comprise S-VLAN components, 1183 * C-VLAN components, or MAC Bridge components. Since there's no TPMR component, 1184 * we don't need to relay PDUs using the destination addresses specified on the 1185 * Nearest non-TPMR section, and the proportion of the Nearest Customer Bridge 1186 * section where they must be relayed by TPMR components. 1187 * 1188 * One option to trap link-local frames to CPU port is to add static FDB entries 1189 * with CPU port designated as destination port. However, because that 1190 * Independent VLAN Learning (IVL) is being used on every VID, each entry only 1191 * applies to a single VLAN Identifier (VID). For a Bridge comprising a MAC 1192 * Bridge component or a C-VLAN component, there would have to be 16 times 4096 1193 * entries. This switch intellectual property can only hold a maximum of 2048 1194 * entries. Using this option, there also isn't a mechanism to prevent 1195 * link-local frames from being discarded when the spanning tree Port State of 1196 * the reception Port is discarding. 1197 * 1198 * The remaining option is to utilise the BPC, RGAC1, RGAC2, RGAC3, and RGAC4 1199 * registers. Whilst this applies to every VID, it doesn't contain all of the 1200 * reserved MAC addresses without affecting the remaining Standard Group MAC 1201 * Addresses. The REV_UN frame tag utilised using the RGAC4 register covers the 1202 * remaining 01-80-C2-00-00-[04,05,06,07,08,09,0A,0B,0C,0D,0F] destination 1203 * addresses. It also includes the 01-80-C2-00-00-22 to 01-80-C2-00-00-FF 1204 * destination addresses which may be relayed by MAC Bridges or VLAN Bridges. 1205 * The latter option provides better but not complete conformance. 1206 * 1207 * This switch intellectual property also does not provide a mechanism to trap 1208 * link-local frames with specific destination addresses to CPU port by Bridge, 1209 * to conform to the filtering rules for the distinct Bridge components. 1210 * 1211 * Therefore, regardless of the type of the Bridge component, link-local frames 1212 * with these destination addresses will be trapped to CPU port: 1213 * 1214 * 01-80-C2-00-00-[00,01,02,03,0E] 1215 * 1216 * In a Bridge comprising a MAC Bridge component or a C-VLAN component: 1217 * 1218 * Link-local frames with these destination addresses won't be trapped to CPU 1219 * port which won't conform to IEEE Std 802.1Q-2022: 1220 * 1221 * 01-80-C2-00-00-[04,05,06,07,08,09,0A,0B,0C,0D,0F] 1222 * 1223 * In a Bridge comprising an S-VLAN component: 1224 * 1225 * Link-local frames with these destination addresses will be trapped to CPU 1226 * port which won't conform to IEEE Std 802.1Q-2022: 1227 * 1228 * 01-80-C2-00-00-00 1229 * 1230 * Link-local frames with these destination addresses won't be trapped to CPU 1231 * port which won't conform to IEEE Std 802.1Q-2022: 1232 * 1233 * 01-80-C2-00-00-[04,05,06,07,08,09,0A] 1234 * 1235 * To trap link-local frames to CPU port as conformant as this switch 1236 * intellectual property can allow, link-local frames are made to be regarded as 1237 * Bridge Protocol Data Units (BPDUs). This is because this switch intellectual 1238 * property only lets the frames regarded as BPDUs bypass the spanning tree Port 1239 * State function of the Forwarding Process. 1240 * 1241 * The only remaining interference is the ingress rules. When the reception Port 1242 * has no PVID assigned on software, VLAN-untagged frames won't be allowed in. 1243 * There doesn't seem to be a mechanism on the switch intellectual property to 1244 * have link-local frames bypass this function of the Forwarding Process. 1245 */ 1246 static void 1247 mt753x_trap_frames(struct mt7530_priv *priv) 1248 { 1249 /* Trap 802.1X PAE frames and BPDUs to the CPU port(s) and egress them 1250 * VLAN-untagged. 1251 */ 1252 mt7530_rmw(priv, MT753X_BPC, 1253 PAE_BPDU_FR | PAE_EG_TAG_MASK | PAE_PORT_FW_MASK | 1254 BPDU_EG_TAG_MASK | BPDU_PORT_FW_MASK, 1255 PAE_BPDU_FR | PAE_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | 1256 PAE_PORT_FW(TO_CPU_FW_CPU_ONLY) | 1257 BPDU_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | 1258 TO_CPU_FW_CPU_ONLY); 1259 1260 /* Trap frames with :01 and :02 MAC DAs to the CPU port(s) and egress 1261 * them VLAN-untagged. 1262 */ 1263 mt7530_rmw(priv, MT753X_RGAC1, 1264 R02_BPDU_FR | R02_EG_TAG_MASK | R02_PORT_FW_MASK | 1265 R01_BPDU_FR | R01_EG_TAG_MASK | R01_PORT_FW_MASK, 1266 R02_BPDU_FR | R02_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | 1267 R02_PORT_FW(TO_CPU_FW_CPU_ONLY) | R01_BPDU_FR | 1268 R01_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | 1269 TO_CPU_FW_CPU_ONLY); 1270 1271 /* Trap frames with :03 and :0E MAC DAs to the CPU port(s) and egress 1272 * them VLAN-untagged. 1273 */ 1274 mt7530_rmw(priv, MT753X_RGAC2, 1275 R0E_BPDU_FR | R0E_EG_TAG_MASK | R0E_PORT_FW_MASK | 1276 R03_BPDU_FR | R03_EG_TAG_MASK | R03_PORT_FW_MASK, 1277 R0E_BPDU_FR | R0E_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | 1278 R0E_PORT_FW(TO_CPU_FW_CPU_ONLY) | R03_BPDU_FR | 1279 R03_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | 1280 TO_CPU_FW_CPU_ONLY); 1281 } 1282 1283 static void 1284 mt753x_cpu_port_enable(struct dsa_switch *ds, int port) 1285 { 1286 struct mt7530_priv *priv = ds->priv; 1287 1288 /* Enable Mediatek header mode on the cpu port */ 1289 mt7530_write(priv, MT7530_PVC_P(port), 1290 PORT_SPEC_TAG); 1291 1292 /* Enable flooding on the CPU port */ 1293 mt7530_set(priv, MT753X_MFC, BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) | 1294 UNU_FFP(BIT(port))); 1295 1296 /* Add the CPU port to the CPU port bitmap for MT7531 and the switch on 1297 * the MT7988 SoC. Trapped frames will be forwarded to the CPU port that 1298 * is affine to the inbound user port. 1299 */ 1300 if (priv->id == ID_MT7531 || priv->id == ID_MT7988 || 1301 priv->id == ID_EN7581 || priv->id == ID_AN7583) 1302 mt7530_set(priv, MT7531_CFC, MT7531_CPU_PMAP(BIT(port))); 1303 1304 /* CPU port gets connected to all user ports of 1305 * the switch. 1306 */ 1307 mt7530_write(priv, MT7530_PCR_P(port), 1308 PCR_MATRIX(dsa_user_ports(priv->ds))); 1309 1310 /* Set to fallback mode for independent VLAN learning */ 1311 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1312 MT7530_PORT_FALLBACK_MODE); 1313 } 1314 1315 static int 1316 mt7530_port_enable(struct dsa_switch *ds, int port, 1317 struct phy_device *phy) 1318 { 1319 struct dsa_port *dp = dsa_to_port(ds, port); 1320 struct mt7530_priv *priv = ds->priv; 1321 1322 mutex_lock(&priv->reg_mutex); 1323 1324 /* Allow the user port gets connected to the cpu port and also 1325 * restore the port matrix if the port is the member of a certain 1326 * bridge. 1327 */ 1328 if (dsa_port_is_user(dp)) { 1329 struct dsa_port *cpu_dp = dp->cpu_dp; 1330 1331 priv->ports[port].pm |= PCR_MATRIX(BIT(cpu_dp->index)); 1332 } 1333 priv->ports[port].enable = true; 1334 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1335 priv->ports[port].pm); 1336 1337 mutex_unlock(&priv->reg_mutex); 1338 1339 if (priv->id != ID_MT7530 && priv->id != ID_MT7621) 1340 return 0; 1341 1342 if (port == 5) 1343 mt7530_clear(priv, MT753X_MTRAP, MT7530_P5_DIS); 1344 else if (port == 6) 1345 mt7530_clear(priv, MT753X_MTRAP, MT7530_P6_DIS); 1346 1347 return 0; 1348 } 1349 1350 static void 1351 mt7530_port_disable(struct dsa_switch *ds, int port) 1352 { 1353 struct mt7530_priv *priv = ds->priv; 1354 1355 mutex_lock(&priv->reg_mutex); 1356 1357 /* Clear up all port matrix which could be restored in the next 1358 * enablement for the port. 1359 */ 1360 priv->ports[port].enable = false; 1361 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1362 PCR_MATRIX_CLR); 1363 1364 mutex_unlock(&priv->reg_mutex); 1365 1366 if (priv->id != ID_MT7530 && priv->id != ID_MT7621) 1367 return; 1368 1369 /* Do not set MT7530_P5_DIS when port 5 is being used for PHY muxing. */ 1370 if (port == 5 && priv->p5_mode == GMAC5) 1371 mt7530_set(priv, MT753X_MTRAP, MT7530_P5_DIS); 1372 else if (port == 6) 1373 mt7530_set(priv, MT753X_MTRAP, MT7530_P6_DIS); 1374 } 1375 1376 static int 1377 mt7530_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 1378 { 1379 struct mt7530_priv *priv = ds->priv; 1380 int length; 1381 u32 val; 1382 1383 /* When a new MTU is set, DSA always set the CPU port's MTU to the 1384 * largest MTU of the user ports. Because the switch only has a global 1385 * RX length register, only allowing CPU port here is enough. 1386 */ 1387 if (!dsa_is_cpu_port(ds, port)) 1388 return 0; 1389 1390 mt7530_mutex_lock(priv); 1391 1392 val = mt7530_mii_read(priv, MT7530_GMACCR); 1393 val &= ~MAX_RX_PKT_LEN_MASK; 1394 1395 /* RX length also includes Ethernet header, MTK tag, and FCS length */ 1396 length = new_mtu + ETH_HLEN + MTK_HDR_LEN + ETH_FCS_LEN; 1397 if (length <= 1522) { 1398 val |= MAX_RX_PKT_LEN_1522; 1399 } else if (length <= 1536) { 1400 val |= MAX_RX_PKT_LEN_1536; 1401 } else if (length <= 1552) { 1402 val |= MAX_RX_PKT_LEN_1552; 1403 } else { 1404 val &= ~MAX_RX_JUMBO_MASK; 1405 val |= MAX_RX_JUMBO(DIV_ROUND_UP(length, 1024)); 1406 val |= MAX_RX_PKT_LEN_JUMBO; 1407 } 1408 1409 mt7530_mii_write(priv, MT7530_GMACCR, val); 1410 1411 mt7530_mutex_unlock(priv); 1412 1413 return 0; 1414 } 1415 1416 static int 1417 mt7530_port_max_mtu(struct dsa_switch *ds, int port) 1418 { 1419 return MT7530_MAX_MTU; 1420 } 1421 1422 static void 1423 mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state) 1424 { 1425 struct mt7530_priv *priv = ds->priv; 1426 u32 stp_state; 1427 1428 switch (state) { 1429 case BR_STATE_DISABLED: 1430 stp_state = MT7530_STP_DISABLED; 1431 break; 1432 case BR_STATE_BLOCKING: 1433 stp_state = MT7530_STP_BLOCKING; 1434 break; 1435 case BR_STATE_LISTENING: 1436 stp_state = MT7530_STP_LISTENING; 1437 break; 1438 case BR_STATE_LEARNING: 1439 stp_state = MT7530_STP_LEARNING; 1440 break; 1441 case BR_STATE_FORWARDING: 1442 default: 1443 stp_state = MT7530_STP_FORWARDING; 1444 break; 1445 } 1446 1447 mt7530_rmw(priv, MT7530_SSP_P(port), FID_PST_MASK(FID_BRIDGED), 1448 FID_PST(FID_BRIDGED, stp_state)); 1449 } 1450 1451 static void mt7530_update_port_member(struct mt7530_priv *priv, int port, 1452 const struct net_device *bridge_dev, 1453 bool join) __must_hold(&priv->reg_mutex) 1454 { 1455 struct dsa_port *dp = dsa_to_port(priv->ds, port), *other_dp; 1456 struct mt7530_port *p = &priv->ports[port], *other_p; 1457 struct dsa_port *cpu_dp = dp->cpu_dp; 1458 u32 port_bitmap = BIT(cpu_dp->index); 1459 int other_port; 1460 bool isolated; 1461 1462 dsa_switch_for_each_user_port(other_dp, priv->ds) { 1463 other_port = other_dp->index; 1464 other_p = &priv->ports[other_port]; 1465 1466 if (dp == other_dp) 1467 continue; 1468 1469 /* Add/remove this port to/from the port matrix of the other 1470 * ports in the same bridge. If the port is disabled, port 1471 * matrix is kept and not being setup until the port becomes 1472 * enabled. 1473 */ 1474 if (!dsa_port_offloads_bridge_dev(other_dp, bridge_dev)) 1475 continue; 1476 1477 isolated = p->isolated && other_p->isolated; 1478 1479 if (join && !isolated) { 1480 other_p->pm |= PCR_MATRIX(BIT(port)); 1481 port_bitmap |= BIT(other_port); 1482 } else { 1483 other_p->pm &= ~PCR_MATRIX(BIT(port)); 1484 } 1485 1486 if (other_p->enable) 1487 mt7530_rmw(priv, MT7530_PCR_P(other_port), 1488 PCR_MATRIX_MASK, other_p->pm); 1489 } 1490 1491 /* Add/remove the all other ports to this port matrix. For !join 1492 * (leaving the bridge), only the CPU port will remain in the port matrix 1493 * of this port. 1494 */ 1495 p->pm = PCR_MATRIX(port_bitmap); 1496 if (priv->ports[port].enable) 1497 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, p->pm); 1498 } 1499 1500 static int 1501 mt7530_port_pre_bridge_flags(struct dsa_switch *ds, int port, 1502 struct switchdev_brport_flags flags, 1503 struct netlink_ext_ack *extack) 1504 { 1505 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 1506 BR_BCAST_FLOOD | BR_ISOLATED)) 1507 return -EINVAL; 1508 1509 return 0; 1510 } 1511 1512 static int 1513 mt7530_port_bridge_flags(struct dsa_switch *ds, int port, 1514 struct switchdev_brport_flags flags, 1515 struct netlink_ext_ack *extack) 1516 { 1517 struct mt7530_priv *priv = ds->priv; 1518 1519 if (flags.mask & BR_LEARNING) 1520 mt7530_rmw(priv, MT7530_PSC_P(port), SA_DIS, 1521 flags.val & BR_LEARNING ? 0 : SA_DIS); 1522 1523 if (flags.mask & BR_FLOOD) 1524 mt7530_rmw(priv, MT753X_MFC, UNU_FFP(BIT(port)), 1525 flags.val & BR_FLOOD ? UNU_FFP(BIT(port)) : 0); 1526 1527 if (flags.mask & BR_MCAST_FLOOD) 1528 mt7530_rmw(priv, MT753X_MFC, UNM_FFP(BIT(port)), 1529 flags.val & BR_MCAST_FLOOD ? UNM_FFP(BIT(port)) : 0); 1530 1531 if (flags.mask & BR_BCAST_FLOOD) 1532 mt7530_rmw(priv, MT753X_MFC, BC_FFP(BIT(port)), 1533 flags.val & BR_BCAST_FLOOD ? BC_FFP(BIT(port)) : 0); 1534 1535 if (flags.mask & BR_ISOLATED) { 1536 struct dsa_port *dp = dsa_to_port(ds, port); 1537 struct net_device *bridge_dev = dsa_port_bridge_dev_get(dp); 1538 1539 priv->ports[port].isolated = !!(flags.val & BR_ISOLATED); 1540 1541 mutex_lock(&priv->reg_mutex); 1542 mt7530_update_port_member(priv, port, bridge_dev, true); 1543 mutex_unlock(&priv->reg_mutex); 1544 } 1545 1546 return 0; 1547 } 1548 1549 static int 1550 mt7530_port_bridge_join(struct dsa_switch *ds, int port, 1551 struct dsa_bridge bridge, bool *tx_fwd_offload, 1552 struct netlink_ext_ack *extack) 1553 { 1554 struct mt7530_priv *priv = ds->priv; 1555 1556 mutex_lock(&priv->reg_mutex); 1557 1558 mt7530_update_port_member(priv, port, bridge.dev, true); 1559 1560 /* Set to fallback mode for independent VLAN learning */ 1561 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1562 MT7530_PORT_FALLBACK_MODE); 1563 1564 mutex_unlock(&priv->reg_mutex); 1565 1566 return 0; 1567 } 1568 1569 static void 1570 mt7530_port_set_vlan_unaware(struct dsa_switch *ds, int port) 1571 { 1572 struct mt7530_priv *priv = ds->priv; 1573 bool all_user_ports_removed = true; 1574 int i; 1575 1576 /* This is called after .port_bridge_leave when leaving a VLAN-aware 1577 * bridge. Don't set standalone ports to fallback mode. 1578 */ 1579 if (dsa_port_bridge_dev_get(dsa_to_port(ds, port))) 1580 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1581 MT7530_PORT_FALLBACK_MODE); 1582 1583 mt7530_rmw(priv, MT7530_PVC_P(port), 1584 VLAN_ATTR_MASK | PVC_EG_TAG_MASK | ACC_FRM_MASK, 1585 VLAN_ATTR(MT7530_VLAN_TRANSPARENT) | 1586 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT) | 1587 MT7530_VLAN_ACC_ALL); 1588 1589 /* Set PVID to 0 */ 1590 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1591 G0_PORT_VID_DEF); 1592 1593 for (i = 0; i < priv->ds->num_ports; i++) { 1594 if (dsa_is_user_port(ds, i) && 1595 dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) { 1596 all_user_ports_removed = false; 1597 break; 1598 } 1599 } 1600 1601 /* CPU port also does the same thing until all user ports belonging to 1602 * the CPU port get out of VLAN filtering mode. 1603 */ 1604 if (all_user_ports_removed) { 1605 struct dsa_port *dp = dsa_to_port(ds, port); 1606 struct dsa_port *cpu_dp = dp->cpu_dp; 1607 1608 mt7530_write(priv, MT7530_PCR_P(cpu_dp->index), 1609 PCR_MATRIX(dsa_user_ports(priv->ds))); 1610 mt7530_write(priv, MT7530_PVC_P(cpu_dp->index), PORT_SPEC_TAG 1611 | PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 1612 } 1613 } 1614 1615 static void 1616 mt7530_port_set_vlan_aware(struct dsa_switch *ds, int port) 1617 { 1618 struct mt7530_priv *priv = ds->priv; 1619 1620 /* Trapped into security mode allows packet forwarding through VLAN 1621 * table lookup. 1622 */ 1623 if (dsa_is_user_port(ds, port)) { 1624 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1625 MT7530_PORT_SECURITY_MODE); 1626 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1627 G0_PORT_VID(priv->ports[port].pvid)); 1628 1629 /* Only accept tagged frames if PVID is not set */ 1630 if (!priv->ports[port].pvid) 1631 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1632 MT7530_VLAN_ACC_TAGGED); 1633 1634 /* Set the port as a user port which is to be able to recognize 1635 * VID from incoming packets before fetching entry within the 1636 * VLAN table. 1637 */ 1638 mt7530_rmw(priv, MT7530_PVC_P(port), 1639 VLAN_ATTR_MASK | PVC_EG_TAG_MASK, 1640 VLAN_ATTR(MT7530_VLAN_USER) | 1641 PVC_EG_TAG(MT7530_VLAN_EG_DISABLED)); 1642 } else { 1643 /* Also set CPU ports to the "user" VLAN port attribute, to 1644 * allow VLAN classification, but keep the EG_TAG attribute as 1645 * "consistent" (i.o.w. don't change its value) for packets 1646 * received by the switch from the CPU, so that tagged packets 1647 * are forwarded to user ports as tagged, and untagged as 1648 * untagged. 1649 */ 1650 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK, 1651 VLAN_ATTR(MT7530_VLAN_USER)); 1652 } 1653 } 1654 1655 static void 1656 mt7530_port_bridge_leave(struct dsa_switch *ds, int port, 1657 struct dsa_bridge bridge) 1658 { 1659 struct mt7530_priv *priv = ds->priv; 1660 1661 mutex_lock(&priv->reg_mutex); 1662 1663 mt7530_update_port_member(priv, port, bridge.dev, false); 1664 1665 /* When a port is removed from the bridge, the port would be set up 1666 * back to the default as is at initial boot which is a VLAN-unaware 1667 * port. 1668 */ 1669 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1670 MT7530_PORT_MATRIX_MODE); 1671 1672 mutex_unlock(&priv->reg_mutex); 1673 } 1674 1675 static int 1676 mt7530_port_fdb_add(struct dsa_switch *ds, int port, 1677 const unsigned char *addr, u16 vid, 1678 struct dsa_db db) 1679 { 1680 struct mt7530_priv *priv = ds->priv; 1681 int ret; 1682 u8 port_mask = BIT(port); 1683 1684 mutex_lock(&priv->reg_mutex); 1685 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); 1686 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1687 mutex_unlock(&priv->reg_mutex); 1688 1689 return ret; 1690 } 1691 1692 static int 1693 mt7530_port_fdb_del(struct dsa_switch *ds, int port, 1694 const unsigned char *addr, u16 vid, 1695 struct dsa_db db) 1696 { 1697 struct mt7530_priv *priv = ds->priv; 1698 int ret; 1699 u8 port_mask = BIT(port); 1700 1701 mutex_lock(&priv->reg_mutex); 1702 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_EMP); 1703 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1704 mutex_unlock(&priv->reg_mutex); 1705 1706 return ret; 1707 } 1708 1709 static int 1710 mt7530_port_fdb_dump(struct dsa_switch *ds, int port, 1711 dsa_fdb_dump_cb_t *cb, void *data) 1712 { 1713 struct mt7530_priv *priv = ds->priv; 1714 struct mt7530_fdb _fdb = { 0 }; 1715 int cnt = MT7530_NUM_FDB_RECORDS; 1716 int ret = 0; 1717 u32 rsp = 0; 1718 1719 mutex_lock(&priv->reg_mutex); 1720 1721 ret = mt7530_fdb_cmd(priv, MT7530_FDB_START, &rsp); 1722 if (ret < 0) 1723 goto err; 1724 1725 do { 1726 if (rsp & ATC_SRCH_HIT) { 1727 mt7530_fdb_read(priv, &_fdb); 1728 if (_fdb.port_mask & BIT(port)) { 1729 ret = cb(_fdb.mac, _fdb.vid, _fdb.noarp, 1730 data); 1731 if (ret < 0) 1732 break; 1733 } 1734 } 1735 } while (--cnt && 1736 !(rsp & ATC_SRCH_END) && 1737 !mt7530_fdb_cmd(priv, MT7530_FDB_NEXT, &rsp)); 1738 err: 1739 mutex_unlock(&priv->reg_mutex); 1740 1741 return 0; 1742 } 1743 1744 static int 1745 mt7530_port_mdb_add(struct dsa_switch *ds, int port, 1746 const struct switchdev_obj_port_mdb *mdb, 1747 struct dsa_db db) 1748 { 1749 struct mt7530_priv *priv = ds->priv; 1750 const u8 *addr = mdb->addr; 1751 u16 vid = mdb->vid; 1752 u8 port_mask = 0; 1753 int ret; 1754 1755 mutex_lock(&priv->reg_mutex); 1756 1757 mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP); 1758 if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL)) 1759 port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP) 1760 & PORT_MAP_MASK; 1761 1762 port_mask |= BIT(port); 1763 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); 1764 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1765 1766 mutex_unlock(&priv->reg_mutex); 1767 1768 return ret; 1769 } 1770 1771 static int 1772 mt7530_port_mdb_del(struct dsa_switch *ds, int port, 1773 const struct switchdev_obj_port_mdb *mdb, 1774 struct dsa_db db) 1775 { 1776 struct mt7530_priv *priv = ds->priv; 1777 const u8 *addr = mdb->addr; 1778 u16 vid = mdb->vid; 1779 u8 port_mask = 0; 1780 int ret; 1781 1782 mutex_lock(&priv->reg_mutex); 1783 1784 mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP); 1785 if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL)) 1786 port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP) 1787 & PORT_MAP_MASK; 1788 1789 port_mask &= ~BIT(port); 1790 mt7530_fdb_write(priv, vid, port_mask, addr, -1, 1791 port_mask ? STATIC_ENT : STATIC_EMP); 1792 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1793 1794 mutex_unlock(&priv->reg_mutex); 1795 1796 return ret; 1797 } 1798 1799 static int 1800 mt7530_vlan_cmd(struct mt7530_priv *priv, enum mt7530_vlan_cmd cmd, u16 vid) 1801 { 1802 struct mt7530_dummy_poll p; 1803 u32 val; 1804 int ret; 1805 1806 val = VTCR_BUSY | VTCR_FUNC(cmd) | vid; 1807 mt7530_write(priv, MT7530_VTCR, val); 1808 1809 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_VTCR); 1810 ret = readx_poll_timeout(_mt7530_read, &p, val, 1811 !(val & VTCR_BUSY), 20, 20000); 1812 if (ret < 0) { 1813 dev_err(priv->dev, "poll timeout\n"); 1814 return ret; 1815 } 1816 1817 val = mt7530_read(priv, MT7530_VTCR); 1818 if (val & VTCR_INVALID) { 1819 dev_err(priv->dev, "read VTCR invalid\n"); 1820 return -EINVAL; 1821 } 1822 1823 return 0; 1824 } 1825 1826 static int 1827 mt7530_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering, 1828 struct netlink_ext_ack *extack) 1829 { 1830 struct dsa_port *dp = dsa_to_port(ds, port); 1831 struct dsa_port *cpu_dp = dp->cpu_dp; 1832 1833 if (vlan_filtering) { 1834 /* The port is being kept as VLAN-unaware port when bridge is 1835 * set up with vlan_filtering not being set, Otherwise, the 1836 * port and the corresponding CPU port is required the setup 1837 * for becoming a VLAN-aware port. 1838 */ 1839 mt7530_port_set_vlan_aware(ds, port); 1840 mt7530_port_set_vlan_aware(ds, cpu_dp->index); 1841 } else { 1842 mt7530_port_set_vlan_unaware(ds, port); 1843 } 1844 1845 return 0; 1846 } 1847 1848 static void 1849 mt7530_hw_vlan_add(struct mt7530_priv *priv, 1850 struct mt7530_hw_vlan_entry *entry) 1851 { 1852 struct dsa_port *dp = dsa_to_port(priv->ds, entry->port); 1853 u8 new_members; 1854 u32 val; 1855 1856 new_members = entry->old_members | BIT(entry->port); 1857 1858 /* Validate the entry with independent learning, create egress tag per 1859 * VLAN and joining the port as one of the port members. 1860 */ 1861 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | FID(FID_BRIDGED) | 1862 VLAN_VALID; 1863 mt7530_write(priv, MT7530_VAWD1, val); 1864 1865 /* Decide whether adding tag or not for those outgoing packets from the 1866 * port inside the VLAN. 1867 * CPU port is always taken as a tagged port for serving more than one 1868 * VLANs across and also being applied with egress type stack mode for 1869 * that VLAN tags would be appended after hardware special tag used as 1870 * DSA tag. 1871 */ 1872 if (dsa_port_is_cpu(dp)) 1873 val = MT7530_VLAN_EGRESS_STACK; 1874 else if (entry->untagged) 1875 val = MT7530_VLAN_EGRESS_UNTAG; 1876 else 1877 val = MT7530_VLAN_EGRESS_TAG; 1878 mt7530_rmw(priv, MT7530_VAWD2, 1879 ETAG_CTRL_P_MASK(entry->port), 1880 ETAG_CTRL_P(entry->port, val)); 1881 } 1882 1883 static void 1884 mt7530_hw_vlan_del(struct mt7530_priv *priv, 1885 struct mt7530_hw_vlan_entry *entry) 1886 { 1887 u8 new_members; 1888 u32 val; 1889 1890 new_members = entry->old_members & ~BIT(entry->port); 1891 1892 val = mt7530_read(priv, MT7530_VAWD1); 1893 if (!(val & VLAN_VALID)) { 1894 dev_err(priv->dev, 1895 "Cannot be deleted due to invalid entry\n"); 1896 return; 1897 } 1898 1899 if (new_members) { 1900 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | 1901 VLAN_VALID; 1902 mt7530_write(priv, MT7530_VAWD1, val); 1903 } else { 1904 mt7530_write(priv, MT7530_VAWD1, 0); 1905 mt7530_write(priv, MT7530_VAWD2, 0); 1906 } 1907 } 1908 1909 static void 1910 mt7530_hw_vlan_update(struct mt7530_priv *priv, u16 vid, 1911 struct mt7530_hw_vlan_entry *entry, 1912 mt7530_vlan_op vlan_op) 1913 { 1914 u32 val; 1915 1916 /* Fetch entry */ 1917 mt7530_vlan_cmd(priv, MT7530_VTCR_RD_VID, vid); 1918 1919 val = mt7530_read(priv, MT7530_VAWD1); 1920 1921 entry->old_members = (val >> PORT_MEM_SHFT) & PORT_MEM_MASK; 1922 1923 /* Manipulate entry */ 1924 vlan_op(priv, entry); 1925 1926 /* Flush result to hardware */ 1927 mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, vid); 1928 } 1929 1930 static int 1931 mt7530_setup_vlan0(struct mt7530_priv *priv) 1932 { 1933 u32 val; 1934 1935 /* Validate the entry with independent learning, keep the original 1936 * ingress tag attribute. 1937 */ 1938 val = IVL_MAC | EG_CON | PORT_MEM(MT7530_ALL_MEMBERS) | FID(FID_BRIDGED) | 1939 VLAN_VALID; 1940 mt7530_write(priv, MT7530_VAWD1, val); 1941 1942 return mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, 0); 1943 } 1944 1945 static int 1946 mt7530_port_vlan_add(struct dsa_switch *ds, int port, 1947 const struct switchdev_obj_port_vlan *vlan, 1948 struct netlink_ext_ack *extack) 1949 { 1950 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1951 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1952 struct mt7530_hw_vlan_entry new_entry; 1953 struct mt7530_priv *priv = ds->priv; 1954 1955 mutex_lock(&priv->reg_mutex); 1956 1957 mt7530_hw_vlan_entry_init(&new_entry, port, untagged); 1958 mt7530_hw_vlan_update(priv, vlan->vid, &new_entry, mt7530_hw_vlan_add); 1959 1960 if (pvid) { 1961 priv->ports[port].pvid = vlan->vid; 1962 1963 /* Accept all frames if PVID is set */ 1964 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1965 MT7530_VLAN_ACC_ALL); 1966 1967 /* Only configure PVID if VLAN filtering is enabled */ 1968 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) 1969 mt7530_rmw(priv, MT7530_PPBV1_P(port), 1970 G0_PORT_VID_MASK, 1971 G0_PORT_VID(vlan->vid)); 1972 } else if (vlan->vid && priv->ports[port].pvid == vlan->vid) { 1973 /* This VLAN is overwritten without PVID, so unset it */ 1974 priv->ports[port].pvid = G0_PORT_VID_DEF; 1975 1976 /* Only accept tagged frames if the port is VLAN-aware */ 1977 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) 1978 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1979 MT7530_VLAN_ACC_TAGGED); 1980 1981 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1982 G0_PORT_VID_DEF); 1983 } 1984 1985 mutex_unlock(&priv->reg_mutex); 1986 1987 return 0; 1988 } 1989 1990 static int 1991 mt7530_port_vlan_del(struct dsa_switch *ds, int port, 1992 const struct switchdev_obj_port_vlan *vlan) 1993 { 1994 struct mt7530_hw_vlan_entry target_entry; 1995 struct mt7530_priv *priv = ds->priv; 1996 1997 mutex_lock(&priv->reg_mutex); 1998 1999 mt7530_hw_vlan_entry_init(&target_entry, port, 0); 2000 mt7530_hw_vlan_update(priv, vlan->vid, &target_entry, 2001 mt7530_hw_vlan_del); 2002 2003 /* PVID is being restored to the default whenever the PVID port 2004 * is being removed from the VLAN. 2005 */ 2006 if (priv->ports[port].pvid == vlan->vid) { 2007 priv->ports[port].pvid = G0_PORT_VID_DEF; 2008 2009 /* Only accept tagged frames if the port is VLAN-aware */ 2010 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) 2011 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 2012 MT7530_VLAN_ACC_TAGGED); 2013 2014 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 2015 G0_PORT_VID_DEF); 2016 } 2017 2018 2019 mutex_unlock(&priv->reg_mutex); 2020 2021 return 0; 2022 } 2023 2024 static int mt753x_port_mirror_add(struct dsa_switch *ds, int port, 2025 struct dsa_mall_mirror_tc_entry *mirror, 2026 bool ingress, struct netlink_ext_ack *extack) 2027 { 2028 struct mt7530_priv *priv = ds->priv; 2029 int monitor_port; 2030 u32 val; 2031 2032 /* Check for existent entry */ 2033 if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port)) 2034 return -EEXIST; 2035 2036 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); 2037 2038 /* MT7530 only supports one monitor port */ 2039 monitor_port = MT753X_MIRROR_PORT_GET(priv->id, val); 2040 if (val & MT753X_MIRROR_EN(priv->id) && 2041 monitor_port != mirror->to_local_port) 2042 return -EEXIST; 2043 2044 val |= MT753X_MIRROR_EN(priv->id); 2045 val &= ~MT753X_MIRROR_PORT_MASK(priv->id); 2046 val |= MT753X_MIRROR_PORT_SET(priv->id, mirror->to_local_port); 2047 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); 2048 2049 val = mt7530_read(priv, MT7530_PCR_P(port)); 2050 if (ingress) { 2051 val |= PORT_RX_MIR; 2052 priv->mirror_rx |= BIT(port); 2053 } else { 2054 val |= PORT_TX_MIR; 2055 priv->mirror_tx |= BIT(port); 2056 } 2057 mt7530_write(priv, MT7530_PCR_P(port), val); 2058 2059 return 0; 2060 } 2061 2062 static void mt753x_port_mirror_del(struct dsa_switch *ds, int port, 2063 struct dsa_mall_mirror_tc_entry *mirror) 2064 { 2065 struct mt7530_priv *priv = ds->priv; 2066 u32 val; 2067 2068 val = mt7530_read(priv, MT7530_PCR_P(port)); 2069 if (mirror->ingress) { 2070 val &= ~PORT_RX_MIR; 2071 priv->mirror_rx &= ~BIT(port); 2072 } else { 2073 val &= ~PORT_TX_MIR; 2074 priv->mirror_tx &= ~BIT(port); 2075 } 2076 mt7530_write(priv, MT7530_PCR_P(port), val); 2077 2078 if (!priv->mirror_rx && !priv->mirror_tx) { 2079 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); 2080 val &= ~MT753X_MIRROR_EN(priv->id); 2081 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); 2082 } 2083 } 2084 2085 static enum dsa_tag_protocol 2086 mtk_get_tag_protocol(struct dsa_switch *ds, int port, 2087 enum dsa_tag_protocol mp) 2088 { 2089 return DSA_TAG_PROTO_MTK; 2090 } 2091 2092 #ifdef CONFIG_GPIOLIB 2093 static inline u32 2094 mt7530_gpio_to_bit(unsigned int offset) 2095 { 2096 /* Map GPIO offset to register bit 2097 * [ 2: 0] port 0 LED 0..2 as GPIO 0..2 2098 * [ 6: 4] port 1 LED 0..2 as GPIO 3..5 2099 * [10: 8] port 2 LED 0..2 as GPIO 6..8 2100 * [14:12] port 3 LED 0..2 as GPIO 9..11 2101 * [18:16] port 4 LED 0..2 as GPIO 12..14 2102 */ 2103 return BIT(offset + offset / 3); 2104 } 2105 2106 static int 2107 mt7530_gpio_get(struct gpio_chip *gc, unsigned int offset) 2108 { 2109 struct mt7530_priv *priv = gpiochip_get_data(gc); 2110 u32 bit = mt7530_gpio_to_bit(offset); 2111 2112 return !!(mt7530_read(priv, MT7530_LED_GPIO_DATA) & bit); 2113 } 2114 2115 static void 2116 mt7530_gpio_set(struct gpio_chip *gc, unsigned int offset, int value) 2117 { 2118 struct mt7530_priv *priv = gpiochip_get_data(gc); 2119 u32 bit = mt7530_gpio_to_bit(offset); 2120 2121 if (value) 2122 mt7530_set(priv, MT7530_LED_GPIO_DATA, bit); 2123 else 2124 mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit); 2125 } 2126 2127 static int 2128 mt7530_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) 2129 { 2130 struct mt7530_priv *priv = gpiochip_get_data(gc); 2131 u32 bit = mt7530_gpio_to_bit(offset); 2132 2133 return (mt7530_read(priv, MT7530_LED_GPIO_DIR) & bit) ? 2134 GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; 2135 } 2136 2137 static int 2138 mt7530_gpio_direction_input(struct gpio_chip *gc, unsigned int offset) 2139 { 2140 struct mt7530_priv *priv = gpiochip_get_data(gc); 2141 u32 bit = mt7530_gpio_to_bit(offset); 2142 2143 mt7530_clear(priv, MT7530_LED_GPIO_OE, bit); 2144 mt7530_clear(priv, MT7530_LED_GPIO_DIR, bit); 2145 2146 return 0; 2147 } 2148 2149 static int 2150 mt7530_gpio_direction_output(struct gpio_chip *gc, unsigned int offset, int value) 2151 { 2152 struct mt7530_priv *priv = gpiochip_get_data(gc); 2153 u32 bit = mt7530_gpio_to_bit(offset); 2154 2155 mt7530_set(priv, MT7530_LED_GPIO_DIR, bit); 2156 2157 if (value) 2158 mt7530_set(priv, MT7530_LED_GPIO_DATA, bit); 2159 else 2160 mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit); 2161 2162 mt7530_set(priv, MT7530_LED_GPIO_OE, bit); 2163 2164 return 0; 2165 } 2166 2167 static int 2168 mt7530_setup_gpio(struct mt7530_priv *priv) 2169 { 2170 struct device *dev = priv->dev; 2171 struct gpio_chip *gc; 2172 2173 gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL); 2174 if (!gc) 2175 return -ENOMEM; 2176 2177 mt7530_write(priv, MT7530_LED_GPIO_OE, 0); 2178 mt7530_write(priv, MT7530_LED_GPIO_DIR, 0); 2179 mt7530_write(priv, MT7530_LED_IO_MODE, 0); 2180 2181 gc->label = "mt7530"; 2182 gc->parent = dev; 2183 gc->owner = THIS_MODULE; 2184 gc->get_direction = mt7530_gpio_get_direction; 2185 gc->direction_input = mt7530_gpio_direction_input; 2186 gc->direction_output = mt7530_gpio_direction_output; 2187 gc->get = mt7530_gpio_get; 2188 gc->set = mt7530_gpio_set; 2189 gc->base = -1; 2190 gc->ngpio = 15; 2191 gc->can_sleep = true; 2192 2193 return devm_gpiochip_add_data(dev, gc, priv); 2194 } 2195 #endif /* CONFIG_GPIOLIB */ 2196 2197 static void 2198 mt7530_setup_mdio_irq(struct mt7530_priv *priv) 2199 { 2200 struct dsa_switch *ds = priv->ds; 2201 int p; 2202 2203 for (p = 0; p < MT7530_NUM_PHYS; p++) { 2204 if (BIT(p) & ds->phys_mii_mask) { 2205 unsigned int irq; 2206 2207 irq = irq_create_mapping(priv->irq_domain, p); 2208 ds->user_mii_bus->irq[p] = irq; 2209 } 2210 } 2211 } 2212 2213 static const struct regmap_irq mt7530_irqs[] = { 2214 REGMAP_IRQ_REG_LINE(0, 32), /* PHY0_LC */ 2215 REGMAP_IRQ_REG_LINE(1, 32), /* PHY1_LC */ 2216 REGMAP_IRQ_REG_LINE(2, 32), /* PHY2_LC */ 2217 REGMAP_IRQ_REG_LINE(3, 32), /* PHY3_LC */ 2218 REGMAP_IRQ_REG_LINE(4, 32), /* PHY4_LC */ 2219 REGMAP_IRQ_REG_LINE(5, 32), /* PHY5_LC */ 2220 REGMAP_IRQ_REG_LINE(6, 32), /* PHY6_LC */ 2221 REGMAP_IRQ_REG_LINE(16, 32), /* MAC_PC */ 2222 REGMAP_IRQ_REG_LINE(17, 32), /* BMU */ 2223 REGMAP_IRQ_REG_LINE(18, 32), /* MIB */ 2224 REGMAP_IRQ_REG_LINE(22, 32), /* ARL_COL_FULL_COL */ 2225 REGMAP_IRQ_REG_LINE(23, 32), /* ARL_COL_FULL */ 2226 REGMAP_IRQ_REG_LINE(24, 32), /* ARL_TBL_ERR */ 2227 REGMAP_IRQ_REG_LINE(25, 32), /* ARL_PKT_QERR */ 2228 REGMAP_IRQ_REG_LINE(26, 32), /* ARL_EQ_ERR */ 2229 REGMAP_IRQ_REG_LINE(27, 32), /* ARL_PKT_BC */ 2230 REGMAP_IRQ_REG_LINE(28, 32), /* ARL_SEC_IG1X */ 2231 REGMAP_IRQ_REG_LINE(29, 32), /* ARL_SEC_VLAN */ 2232 REGMAP_IRQ_REG_LINE(30, 32), /* ARL_SEC_TAG */ 2233 REGMAP_IRQ_REG_LINE(31, 32), /* ACL */ 2234 }; 2235 2236 static const struct regmap_irq_chip mt7530_regmap_irq_chip = { 2237 .name = KBUILD_MODNAME, 2238 .status_base = MT7530_SYS_INT_STS, 2239 .unmask_base = MT7530_SYS_INT_EN, 2240 .ack_base = MT7530_SYS_INT_STS, 2241 .init_ack_masked = true, 2242 .irqs = mt7530_irqs, 2243 .num_irqs = ARRAY_SIZE(mt7530_irqs), 2244 .num_regs = 1, 2245 }; 2246 2247 static int 2248 mt7530_setup_irq(struct mt7530_priv *priv) 2249 { 2250 struct regmap_irq_chip_data *irq_data; 2251 struct device *dev = priv->dev; 2252 struct device_node *np = dev->of_node; 2253 int irq, ret; 2254 2255 if (!of_property_read_bool(np, "interrupt-controller")) { 2256 dev_info(dev, "no interrupt support\n"); 2257 return 0; 2258 } 2259 2260 irq = of_irq_get(np, 0); 2261 if (irq <= 0) { 2262 dev_err(dev, "failed to get parent IRQ: %d\n", irq); 2263 return irq ? : -EINVAL; 2264 } 2265 2266 /* This register must be set for MT7530 to properly fire interrupts */ 2267 if (priv->id == ID_MT7530 || priv->id == ID_MT7621) 2268 mt7530_set(priv, MT7530_TOP_SIG_CTRL, TOP_SIG_CTRL_NORMAL); 2269 2270 ret = devm_regmap_add_irq_chip_fwnode(dev, dev_fwnode(dev), 2271 priv->regmap, irq, 2272 IRQF_ONESHOT, 2273 0, &mt7530_regmap_irq_chip, 2274 &irq_data); 2275 if (ret) 2276 return ret; 2277 2278 priv->irq_domain = regmap_irq_get_domain(irq_data); 2279 2280 return 0; 2281 } 2282 2283 static void 2284 mt7530_free_mdio_irq(struct mt7530_priv *priv) 2285 { 2286 int p; 2287 2288 for (p = 0; p < MT7530_NUM_PHYS; p++) { 2289 if (BIT(p) & priv->ds->phys_mii_mask) { 2290 unsigned int irq; 2291 2292 irq = irq_find_mapping(priv->irq_domain, p); 2293 irq_dispose_mapping(irq); 2294 } 2295 } 2296 } 2297 2298 static int 2299 mt7530_setup_mdio(struct mt7530_priv *priv) 2300 { 2301 struct device_node *mnp, *np = priv->dev->of_node; 2302 struct dsa_switch *ds = priv->ds; 2303 struct device *dev = priv->dev; 2304 struct mii_bus *bus; 2305 static int idx; 2306 int ret = 0; 2307 2308 mnp = of_get_child_by_name(np, "mdio"); 2309 2310 if (mnp && !of_device_is_available(mnp)) 2311 goto out; 2312 2313 bus = devm_mdiobus_alloc(dev); 2314 if (!bus) { 2315 ret = -ENOMEM; 2316 goto out; 2317 } 2318 2319 if (!mnp) 2320 ds->user_mii_bus = bus; 2321 2322 bus->priv = priv; 2323 bus->name = KBUILD_MODNAME "-mii"; 2324 snprintf(bus->id, MII_BUS_ID_SIZE, KBUILD_MODNAME "-%d", idx++); 2325 bus->read = mt753x_phy_read_c22; 2326 bus->write = mt753x_phy_write_c22; 2327 bus->read_c45 = mt753x_phy_read_c45; 2328 bus->write_c45 = mt753x_phy_write_c45; 2329 bus->parent = dev; 2330 bus->phy_mask = ~ds->phys_mii_mask; 2331 2332 if (priv->irq_domain && !mnp) 2333 mt7530_setup_mdio_irq(priv); 2334 2335 ret = devm_of_mdiobus_register(dev, bus, mnp); 2336 if (ret) { 2337 dev_err(dev, "failed to register MDIO bus: %d\n", ret); 2338 if (priv->irq_domain && !mnp) 2339 mt7530_free_mdio_irq(priv); 2340 } 2341 2342 out: 2343 of_node_put(mnp); 2344 return ret; 2345 } 2346 2347 static int 2348 mt7530_setup(struct dsa_switch *ds) 2349 { 2350 struct mt7530_priv *priv = ds->priv; 2351 struct device_node *dn = NULL; 2352 struct device_node *phy_node; 2353 struct device_node *mac_np; 2354 struct mt7530_dummy_poll p; 2355 phy_interface_t interface; 2356 struct dsa_port *cpu_dp; 2357 u32 id, val; 2358 int ret, i; 2359 2360 /* The parent node of conduit netdev which holds the common system 2361 * controller also is the container for two GMACs nodes representing 2362 * as two netdev instances. 2363 */ 2364 dsa_switch_for_each_cpu_port(cpu_dp, ds) { 2365 dn = cpu_dp->conduit->dev.of_node->parent; 2366 /* It doesn't matter which CPU port is found first, 2367 * their conduits should share the same parent OF node 2368 */ 2369 break; 2370 } 2371 2372 if (!dn) { 2373 dev_err(ds->dev, "parent OF node of DSA conduit not found"); 2374 return -EINVAL; 2375 } 2376 2377 ds->assisted_learning_on_cpu_port = true; 2378 ds->mtu_enforcement_ingress = true; 2379 2380 if (priv->id == ID_MT7530) { 2381 regulator_set_voltage(priv->core_pwr, 1000000, 1000000); 2382 ret = regulator_enable(priv->core_pwr); 2383 if (ret < 0) { 2384 dev_err(priv->dev, 2385 "Failed to enable core power: %d\n", ret); 2386 return ret; 2387 } 2388 2389 regulator_set_voltage(priv->io_pwr, 3300000, 3300000); 2390 ret = regulator_enable(priv->io_pwr); 2391 if (ret < 0) { 2392 dev_err(priv->dev, "Failed to enable io pwr: %d\n", 2393 ret); 2394 return ret; 2395 } 2396 } 2397 2398 /* Reset whole chip through gpio pin or memory-mapped registers for 2399 * different type of hardware 2400 */ 2401 if (priv->mcm) { 2402 reset_control_assert(priv->rstc); 2403 usleep_range(5000, 5100); 2404 reset_control_deassert(priv->rstc); 2405 } else { 2406 gpiod_set_value_cansleep(priv->reset, 0); 2407 usleep_range(5000, 5100); 2408 gpiod_set_value_cansleep(priv->reset, 1); 2409 } 2410 2411 /* Waiting for MT7530 got to stable */ 2412 INIT_MT7530_DUMMY_POLL(&p, priv, MT753X_TRAP); 2413 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0, 2414 20, 1000000); 2415 if (ret < 0) { 2416 dev_err(priv->dev, "reset timeout\n"); 2417 return ret; 2418 } 2419 2420 id = mt7530_read(priv, MT7530_CREV); 2421 id >>= CHIP_NAME_SHIFT; 2422 if (id != MT7530_ID) { 2423 dev_err(priv->dev, "chip %x can't be supported\n", id); 2424 return -ENODEV; 2425 } 2426 2427 if ((val & MT7530_XTAL_MASK) == MT7530_XTAL_20MHZ) { 2428 dev_err(priv->dev, 2429 "MT7530 with a 20MHz XTAL is not supported!\n"); 2430 return -EINVAL; 2431 } 2432 2433 /* Reset the switch through internal reset */ 2434 mt7530_write(priv, MT7530_SYS_CTRL, 2435 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | 2436 SYS_CTRL_REG_RST); 2437 2438 /* Lower Tx driving for TRGMII path */ 2439 for (i = 0; i < NUM_TRGMII_CTRL; i++) 2440 mt7530_write(priv, MT7530_TRGMII_TD_ODT(i), 2441 TD_DM_DRVP(8) | TD_DM_DRVN(8)); 2442 2443 for (i = 0; i < NUM_TRGMII_CTRL; i++) 2444 mt7530_rmw(priv, MT7530_TRGMII_RD(i), 2445 RD_TAP_MASK, RD_TAP(16)); 2446 2447 /* Allow modifying the trap and directly access PHY registers via the 2448 * MDIO bus the switch is on. 2449 */ 2450 mt7530_rmw(priv, MT753X_MTRAP, MT7530_CHG_TRAP | 2451 MT7530_PHY_INDIRECT_ACCESS, MT7530_CHG_TRAP); 2452 2453 if ((val & MT7530_XTAL_MASK) == MT7530_XTAL_40MHZ) 2454 mt7530_pll_setup(priv); 2455 2456 mt753x_trap_frames(priv); 2457 2458 /* Enable and reset MIB counters */ 2459 mt7530_mib_reset(ds); 2460 2461 for (i = 0; i < priv->ds->num_ports; i++) { 2462 /* Clear link settings and enable force mode to force link down 2463 * on all ports until they're enabled later. 2464 */ 2465 mt7530_rmw(priv, MT753X_PMCR_P(i), 2466 PMCR_LINK_SETTINGS_MASK | 2467 MT753X_FORCE_MODE(priv->id), 2468 MT753X_FORCE_MODE(priv->id)); 2469 2470 /* Disable forwarding by default on all ports */ 2471 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, 2472 PCR_MATRIX_CLR); 2473 2474 /* Disable learning by default on all ports */ 2475 mt7530_set(priv, MT7530_PSC_P(i), SA_DIS); 2476 2477 if (dsa_is_cpu_port(ds, i)) { 2478 mt753x_cpu_port_enable(ds, i); 2479 } else { 2480 mt7530_port_disable(ds, i); 2481 2482 /* Set default PVID to 0 on all user ports */ 2483 mt7530_rmw(priv, MT7530_PPBV1_P(i), G0_PORT_VID_MASK, 2484 G0_PORT_VID_DEF); 2485 } 2486 /* Enable consistent egress tag */ 2487 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK, 2488 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 2489 } 2490 2491 /* Allow mirroring frames received on the local port (monitor port). */ 2492 mt7530_set(priv, MT753X_AGC, LOCAL_EN); 2493 2494 /* Setup VLAN ID 0 for VLAN-unaware bridges */ 2495 ret = mt7530_setup_vlan0(priv); 2496 if (ret) 2497 return ret; 2498 2499 /* Check for PHY muxing on port 5 */ 2500 if (dsa_is_unused_port(ds, 5)) { 2501 /* Scan the ethernet nodes. Look for GMAC1, lookup the used PHY. 2502 * Set priv->p5_mode to the appropriate value if PHY muxing is 2503 * detected. 2504 */ 2505 for_each_child_of_node(dn, mac_np) { 2506 if (!of_device_is_compatible(mac_np, 2507 "mediatek,eth-mac")) 2508 continue; 2509 2510 ret = of_property_read_u32(mac_np, "reg", &id); 2511 if (ret < 0 || id != 1) 2512 continue; 2513 2514 phy_node = of_parse_phandle(mac_np, "phy-handle", 0); 2515 if (!phy_node) 2516 continue; 2517 2518 if (phy_node->parent == priv->dev->of_node->parent || 2519 phy_node->parent->parent == priv->dev->of_node) { 2520 ret = of_get_phy_mode(mac_np, &interface); 2521 if (ret && ret != -ENODEV) { 2522 of_node_put(mac_np); 2523 of_node_put(phy_node); 2524 return ret; 2525 } 2526 id = of_mdio_parse_addr(ds->dev, phy_node); 2527 if (id == 0) 2528 priv->p5_mode = MUX_PHY_P0; 2529 if (id == 4) 2530 priv->p5_mode = MUX_PHY_P4; 2531 } 2532 of_node_put(mac_np); 2533 of_node_put(phy_node); 2534 break; 2535 } 2536 2537 if (priv->p5_mode == MUX_PHY_P0 || 2538 priv->p5_mode == MUX_PHY_P4) { 2539 mt7530_clear(priv, MT753X_MTRAP, MT7530_P5_DIS); 2540 mt7530_setup_port5(ds, interface); 2541 } 2542 } 2543 2544 #ifdef CONFIG_GPIOLIB 2545 if (of_property_read_bool(priv->dev->of_node, "gpio-controller")) { 2546 ret = mt7530_setup_gpio(priv); 2547 if (ret) 2548 return ret; 2549 } 2550 #endif /* CONFIG_GPIOLIB */ 2551 2552 /* Flush the FDB table */ 2553 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL); 2554 if (ret < 0) 2555 return ret; 2556 2557 return 0; 2558 } 2559 2560 static int 2561 mt7531_setup_common(struct dsa_switch *ds) 2562 { 2563 struct mt7530_priv *priv = ds->priv; 2564 int ret, i; 2565 2566 ds->assisted_learning_on_cpu_port = true; 2567 ds->mtu_enforcement_ingress = true; 2568 2569 mt753x_trap_frames(priv); 2570 2571 /* Enable and reset MIB counters */ 2572 mt7530_mib_reset(ds); 2573 2574 /* Disable flooding on all ports */ 2575 mt7530_clear(priv, MT753X_MFC, BC_FFP_MASK | UNM_FFP_MASK | 2576 UNU_FFP_MASK); 2577 2578 for (i = 0; i < priv->ds->num_ports; i++) { 2579 /* Clear link settings and enable force mode to force link down 2580 * on all ports until they're enabled later. 2581 */ 2582 mt7530_rmw(priv, MT753X_PMCR_P(i), 2583 PMCR_LINK_SETTINGS_MASK | 2584 MT753X_FORCE_MODE(priv->id), 2585 MT753X_FORCE_MODE(priv->id)); 2586 2587 /* Disable forwarding by default on all ports */ 2588 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, 2589 PCR_MATRIX_CLR); 2590 2591 /* Disable learning by default on all ports */ 2592 mt7530_set(priv, MT7530_PSC_P(i), SA_DIS); 2593 2594 mt7530_set(priv, MT7531_DBG_CNT(i), MT7531_DIS_CLR); 2595 2596 if (dsa_is_cpu_port(ds, i)) { 2597 mt753x_cpu_port_enable(ds, i); 2598 } else { 2599 mt7530_port_disable(ds, i); 2600 2601 /* Set default PVID to 0 on all user ports */ 2602 mt7530_rmw(priv, MT7530_PPBV1_P(i), G0_PORT_VID_MASK, 2603 G0_PORT_VID_DEF); 2604 } 2605 2606 /* Enable consistent egress tag */ 2607 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK, 2608 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 2609 } 2610 2611 /* Allow mirroring frames received on the local port (monitor port). */ 2612 mt7530_set(priv, MT753X_AGC, LOCAL_EN); 2613 2614 /* Enable Special Tag for rx frames */ 2615 if (priv->id == ID_EN7581 || priv->id == ID_AN7583) 2616 mt7530_write(priv, MT753X_CPORT_SPTAG_CFG, 2617 CPORT_SW2FE_STAG_EN | CPORT_FE2SW_STAG_EN); 2618 2619 /* Flush the FDB table */ 2620 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL); 2621 if (ret < 0) 2622 return ret; 2623 2624 /* Setup VLAN ID 0 for VLAN-unaware bridges */ 2625 return mt7530_setup_vlan0(priv); 2626 } 2627 2628 static int 2629 mt7531_setup(struct dsa_switch *ds) 2630 { 2631 struct mt7530_priv *priv = ds->priv; 2632 struct mt7530_dummy_poll p; 2633 u32 val, id; 2634 int ret, i; 2635 2636 /* Reset whole chip through gpio pin or memory-mapped registers for 2637 * different type of hardware 2638 */ 2639 if (priv->mcm) { 2640 reset_control_assert(priv->rstc); 2641 usleep_range(5000, 5100); 2642 reset_control_deassert(priv->rstc); 2643 } else { 2644 gpiod_set_value_cansleep(priv->reset, 0); 2645 usleep_range(5000, 5100); 2646 gpiod_set_value_cansleep(priv->reset, 1); 2647 } 2648 2649 /* Waiting for MT7530 got to stable */ 2650 INIT_MT7530_DUMMY_POLL(&p, priv, MT753X_TRAP); 2651 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0, 2652 20, 1000000); 2653 if (ret < 0) { 2654 dev_err(priv->dev, "reset timeout\n"); 2655 return ret; 2656 } 2657 2658 id = mt7530_read(priv, MT7531_CREV); 2659 id >>= CHIP_NAME_SHIFT; 2660 2661 if (id != MT7531_ID) { 2662 dev_err(priv->dev, "chip %x can't be supported\n", id); 2663 return -ENODEV; 2664 } 2665 2666 /* MT7531AE has got two SGMII units. One for port 5, one for port 6. 2667 * MT7531BE has got only one SGMII unit which is for port 6. 2668 */ 2669 val = mt7530_read(priv, MT7531_TOP_SIG_SR); 2670 priv->p5_sgmii = !!(val & PAD_DUAL_SGMII_EN); 2671 2672 /* Force link down on all ports before internal reset */ 2673 for (i = 0; i < priv->ds->num_ports; i++) 2674 mt7530_write(priv, MT753X_PMCR_P(i), MT7531_FORCE_MODE_LNK); 2675 2676 /* Reset the switch through internal reset */ 2677 mt7530_write(priv, MT7530_SYS_CTRL, SYS_CTRL_SW_RST | SYS_CTRL_REG_RST); 2678 2679 if (!priv->p5_sgmii) { 2680 mt7531_pll_setup(priv); 2681 } else { 2682 /* Unlike MT7531BE, the GPIO 6-12 pins are not used for RGMII on 2683 * MT7531AE. Set the GPIO 11-12 pins to function as MDC and MDIO 2684 * to expose the MDIO bus of the switch. 2685 */ 2686 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO11_RG_RXD2_MASK, 2687 MT7531_EXT_P_MDC_11); 2688 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO12_RG_RXD3_MASK, 2689 MT7531_EXT_P_MDIO_12); 2690 } 2691 2692 mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK, 2693 MT7531_GPIO0_INTERRUPT); 2694 2695 /* Enable Energy-Efficient Ethernet (EEE) and PHY core PLL, since 2696 * phy_device has not yet been created provided for 2697 * phy_[read,write]_mmd_indirect is called, we provide our own 2698 * mt7531_ind_mmd_phy_[read,write] to complete this function. 2699 */ 2700 val = mt7531_ind_c45_phy_read(priv, 2701 MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 2702 MDIO_MMD_VEND2, CORE_PLL_GROUP4); 2703 val |= MT7531_RG_SYSPLL_DMY2 | MT7531_PHY_PLL_BYPASS_MODE; 2704 val &= ~MT7531_PHY_PLL_OFF; 2705 mt7531_ind_c45_phy_write(priv, 2706 MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 2707 MDIO_MMD_VEND2, CORE_PLL_GROUP4, val); 2708 2709 /* Disable EEE advertisement on the switch PHYs. */ 2710 for (i = MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr); 2711 i < MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr) + MT7530_NUM_PHYS; 2712 i++) { 2713 mt7531_ind_c45_phy_write(priv, i, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 2714 0); 2715 } 2716 2717 ret = mt7531_setup_common(ds); 2718 if (ret) 2719 return ret; 2720 2721 return 0; 2722 } 2723 2724 static void mt7530_mac_port_get_caps(struct dsa_switch *ds, int port, 2725 struct phylink_config *config) 2726 { 2727 config->mac_capabilities |= MAC_10 | MAC_100 | MAC_1000FD; 2728 2729 switch (port) { 2730 /* Ports which are connected to switch PHYs. There is no MII pinout. */ 2731 case 0 ... 4: 2732 __set_bit(PHY_INTERFACE_MODE_GMII, 2733 config->supported_interfaces); 2734 break; 2735 2736 /* Port 5 supports rgmii with delays, mii, and gmii. */ 2737 case 5: 2738 phy_interface_set_rgmii(config->supported_interfaces); 2739 __set_bit(PHY_INTERFACE_MODE_MII, 2740 config->supported_interfaces); 2741 __set_bit(PHY_INTERFACE_MODE_GMII, 2742 config->supported_interfaces); 2743 break; 2744 2745 /* Port 6 supports rgmii and trgmii. */ 2746 case 6: 2747 __set_bit(PHY_INTERFACE_MODE_RGMII, 2748 config->supported_interfaces); 2749 __set_bit(PHY_INTERFACE_MODE_TRGMII, 2750 config->supported_interfaces); 2751 break; 2752 } 2753 } 2754 2755 static void mt7531_mac_port_get_caps(struct dsa_switch *ds, int port, 2756 struct phylink_config *config) 2757 { 2758 struct mt7530_priv *priv = ds->priv; 2759 2760 config->mac_capabilities |= MAC_10 | MAC_100 | MAC_1000FD; 2761 2762 switch (port) { 2763 /* Ports which are connected to switch PHYs. There is no MII pinout. */ 2764 case 0 ... 4: 2765 __set_bit(PHY_INTERFACE_MODE_GMII, 2766 config->supported_interfaces); 2767 break; 2768 2769 /* Port 5 supports rgmii with delays on MT7531BE, sgmii/802.3z on 2770 * MT7531AE. 2771 */ 2772 case 5: 2773 if (!priv->p5_sgmii) { 2774 phy_interface_set_rgmii(config->supported_interfaces); 2775 break; 2776 } 2777 fallthrough; 2778 2779 /* Port 6 supports sgmii/802.3z. */ 2780 case 6: 2781 __set_bit(PHY_INTERFACE_MODE_SGMII, 2782 config->supported_interfaces); 2783 __set_bit(PHY_INTERFACE_MODE_1000BASEX, 2784 config->supported_interfaces); 2785 __set_bit(PHY_INTERFACE_MODE_2500BASEX, 2786 config->supported_interfaces); 2787 2788 config->mac_capabilities |= MAC_2500FD; 2789 break; 2790 } 2791 } 2792 2793 static void mt7988_mac_port_get_caps(struct dsa_switch *ds, int port, 2794 struct phylink_config *config) 2795 { 2796 switch (port) { 2797 /* Ports which are connected to switch PHYs. There is no MII pinout. */ 2798 case 0 ... 3: 2799 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 2800 config->supported_interfaces); 2801 2802 config->mac_capabilities |= MAC_10 | MAC_100 | MAC_1000FD; 2803 break; 2804 2805 /* Port 6 is connected to SoC's XGMII MAC. There is no MII pinout. */ 2806 case 6: 2807 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 2808 config->supported_interfaces); 2809 2810 config->mac_capabilities |= MAC_10000FD; 2811 break; 2812 } 2813 } 2814 2815 static void en7581_mac_port_get_caps(struct dsa_switch *ds, int port, 2816 struct phylink_config *config) 2817 { 2818 switch (port) { 2819 /* Ports which are connected to switch PHYs. There is no MII pinout. */ 2820 case 0 ... 4: 2821 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 2822 config->supported_interfaces); 2823 2824 config->mac_capabilities |= MAC_10 | MAC_100 | MAC_1000FD; 2825 break; 2826 2827 /* Port 6 is connected to SoC's XGMII MAC. There is no MII pinout. */ 2828 case 6: 2829 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 2830 config->supported_interfaces); 2831 2832 config->mac_capabilities |= MAC_10000FD; 2833 break; 2834 } 2835 } 2836 2837 static void 2838 mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2839 phy_interface_t interface) 2840 { 2841 struct mt7530_priv *priv = ds->priv; 2842 2843 if (port == 5) 2844 mt7530_setup_port5(priv->ds, interface); 2845 else if (port == 6) 2846 mt7530_setup_port6(priv->ds, interface); 2847 } 2848 2849 static void mt7531_rgmii_setup(struct mt7530_priv *priv, 2850 phy_interface_t interface, 2851 struct phy_device *phydev) 2852 { 2853 u32 val; 2854 2855 val = mt7530_read(priv, MT7531_CLKGEN_CTRL); 2856 val |= GP_CLK_EN; 2857 val &= ~GP_MODE_MASK; 2858 val |= GP_MODE(MT7531_GP_MODE_RGMII); 2859 val &= ~CLK_SKEW_IN_MASK; 2860 val |= CLK_SKEW_IN(MT7531_CLK_SKEW_NO_CHG); 2861 val &= ~CLK_SKEW_OUT_MASK; 2862 val |= CLK_SKEW_OUT(MT7531_CLK_SKEW_NO_CHG); 2863 val |= TXCLK_NO_REVERSE | RXCLK_NO_DELAY; 2864 2865 /* Do not adjust rgmii delay when vendor phy driver presents. */ 2866 if (!phydev || phy_driver_is_genphy(phydev)) { 2867 val &= ~(TXCLK_NO_REVERSE | RXCLK_NO_DELAY); 2868 switch (interface) { 2869 case PHY_INTERFACE_MODE_RGMII: 2870 val |= TXCLK_NO_REVERSE; 2871 val |= RXCLK_NO_DELAY; 2872 break; 2873 case PHY_INTERFACE_MODE_RGMII_RXID: 2874 val |= TXCLK_NO_REVERSE; 2875 break; 2876 case PHY_INTERFACE_MODE_RGMII_TXID: 2877 val |= RXCLK_NO_DELAY; 2878 break; 2879 case PHY_INTERFACE_MODE_RGMII_ID: 2880 break; 2881 default: 2882 break; 2883 } 2884 } 2885 2886 mt7530_write(priv, MT7531_CLKGEN_CTRL, val); 2887 } 2888 2889 static void 2890 mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2891 phy_interface_t interface) 2892 { 2893 struct mt7530_priv *priv = ds->priv; 2894 struct phy_device *phydev; 2895 struct dsa_port *dp; 2896 2897 if (phy_interface_mode_is_rgmii(interface)) { 2898 dp = dsa_to_port(ds, port); 2899 phydev = dp->user->phydev; 2900 mt7531_rgmii_setup(priv, interface, phydev); 2901 } 2902 } 2903 2904 static struct phylink_pcs * 2905 mt753x_phylink_mac_select_pcs(struct phylink_config *config, 2906 phy_interface_t interface) 2907 { 2908 struct dsa_port *dp = dsa_phylink_to_port(config); 2909 struct mt7530_priv *priv = dp->ds->priv; 2910 2911 switch (interface) { 2912 case PHY_INTERFACE_MODE_TRGMII: 2913 return &priv->pcs[dp->index].pcs; 2914 case PHY_INTERFACE_MODE_SGMII: 2915 case PHY_INTERFACE_MODE_1000BASEX: 2916 case PHY_INTERFACE_MODE_2500BASEX: 2917 return priv->ports[dp->index].sgmii_pcs; 2918 default: 2919 return NULL; 2920 } 2921 } 2922 2923 static void 2924 mt753x_phylink_mac_config(struct phylink_config *config, unsigned int mode, 2925 const struct phylink_link_state *state) 2926 { 2927 struct dsa_port *dp = dsa_phylink_to_port(config); 2928 struct dsa_switch *ds = dp->ds; 2929 struct mt7530_priv *priv; 2930 int port = dp->index; 2931 2932 priv = ds->priv; 2933 2934 if ((port == 5 || port == 6) && priv->info->mac_port_config) 2935 priv->info->mac_port_config(ds, port, mode, state->interface); 2936 2937 /* Are we connected to external phy */ 2938 if (port == 5 && dsa_is_user_port(ds, 5)) 2939 mt7530_set(priv, MT753X_PMCR_P(port), PMCR_EXT_PHY); 2940 } 2941 2942 static void mt753x_phylink_mac_link_down(struct phylink_config *config, 2943 unsigned int mode, 2944 phy_interface_t interface) 2945 { 2946 struct dsa_port *dp = dsa_phylink_to_port(config); 2947 struct mt7530_priv *priv = dp->ds->priv; 2948 2949 mt7530_clear(priv, MT753X_PMCR_P(dp->index), PMCR_LINK_SETTINGS_MASK); 2950 } 2951 2952 static void mt753x_phylink_mac_link_up(struct phylink_config *config, 2953 struct phy_device *phydev, 2954 unsigned int mode, 2955 phy_interface_t interface, 2956 int speed, int duplex, 2957 bool tx_pause, bool rx_pause) 2958 { 2959 struct dsa_port *dp = dsa_phylink_to_port(config); 2960 struct mt7530_priv *priv = dp->ds->priv; 2961 u32 mcr; 2962 2963 mcr = PMCR_MAC_RX_EN | PMCR_MAC_TX_EN | PMCR_FORCE_LNK; 2964 2965 switch (speed) { 2966 case SPEED_1000: 2967 case SPEED_2500: 2968 case SPEED_10000: 2969 mcr |= PMCR_FORCE_SPEED_1000; 2970 break; 2971 case SPEED_100: 2972 mcr |= PMCR_FORCE_SPEED_100; 2973 break; 2974 } 2975 if (duplex == DUPLEX_FULL) { 2976 mcr |= PMCR_FORCE_FDX; 2977 if (tx_pause) 2978 mcr |= PMCR_FORCE_TX_FC_EN; 2979 if (rx_pause) 2980 mcr |= PMCR_FORCE_RX_FC_EN; 2981 } 2982 2983 mt7530_set(priv, MT753X_PMCR_P(dp->index), mcr); 2984 } 2985 2986 static void mt753x_phylink_mac_disable_tx_lpi(struct phylink_config *config) 2987 { 2988 struct dsa_port *dp = dsa_phylink_to_port(config); 2989 struct mt7530_priv *priv = dp->ds->priv; 2990 2991 mt7530_clear(priv, MT753X_PMCR_P(dp->index), 2992 PMCR_FORCE_EEE1G | PMCR_FORCE_EEE100); 2993 } 2994 2995 static int mt753x_phylink_mac_enable_tx_lpi(struct phylink_config *config, 2996 u32 timer, bool tx_clock_stop) 2997 { 2998 struct dsa_port *dp = dsa_phylink_to_port(config); 2999 struct mt7530_priv *priv = dp->ds->priv; 3000 u32 val; 3001 3002 /* If the timer is zero, then set LPI_MODE_EN, which allows the 3003 * system to enter LPI mode immediately rather than waiting for 3004 * the LPI threshold. 3005 */ 3006 if (!timer) 3007 val = LPI_MODE_EN; 3008 else if (FIELD_FIT(LPI_THRESH_MASK, timer)) 3009 val = FIELD_PREP(LPI_THRESH_MASK, timer); 3010 else 3011 val = LPI_THRESH_MASK; 3012 3013 mt7530_rmw(priv, MT753X_PMEEECR_P(dp->index), 3014 LPI_THRESH_MASK | LPI_MODE_EN, val); 3015 3016 mt7530_set(priv, MT753X_PMCR_P(dp->index), 3017 PMCR_FORCE_EEE1G | PMCR_FORCE_EEE100); 3018 3019 return 0; 3020 } 3021 3022 static void mt753x_phylink_get_caps(struct dsa_switch *ds, int port, 3023 struct phylink_config *config) 3024 { 3025 struct mt7530_priv *priv = ds->priv; 3026 u32 eeecr; 3027 3028 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE; 3029 3030 config->lpi_capabilities = MAC_100FD | MAC_1000FD | MAC_2500FD; 3031 3032 eeecr = mt7530_read(priv, MT753X_PMEEECR_P(port)); 3033 /* tx_lpi_timer should be in microseconds. The time units for 3034 * LPI threshold are unspecified. 3035 */ 3036 config->lpi_timer_default = FIELD_GET(LPI_THRESH_MASK, eeecr); 3037 3038 priv->info->mac_port_get_caps(ds, port, config); 3039 } 3040 3041 static int mt753x_pcs_validate(struct phylink_pcs *pcs, 3042 unsigned long *supported, 3043 const struct phylink_link_state *state) 3044 { 3045 /* Autonegotiation is not supported in TRGMII nor 802.3z modes */ 3046 if (state->interface == PHY_INTERFACE_MODE_TRGMII || 3047 phy_interface_mode_is_8023z(state->interface)) 3048 phylink_clear(supported, Autoneg); 3049 3050 return 0; 3051 } 3052 3053 static void mt7530_pcs_get_state(struct phylink_pcs *pcs, unsigned int neg_mode, 3054 struct phylink_link_state *state) 3055 { 3056 struct mt7530_priv *priv = pcs_to_mt753x_pcs(pcs)->priv; 3057 int port = pcs_to_mt753x_pcs(pcs)->port; 3058 u32 pmsr; 3059 3060 pmsr = mt7530_read(priv, MT7530_PMSR_P(port)); 3061 3062 state->link = (pmsr & PMSR_LINK); 3063 state->an_complete = state->link; 3064 state->duplex = !!(pmsr & PMSR_DPX); 3065 3066 switch (pmsr & PMSR_SPEED_MASK) { 3067 case PMSR_SPEED_10: 3068 state->speed = SPEED_10; 3069 break; 3070 case PMSR_SPEED_100: 3071 state->speed = SPEED_100; 3072 break; 3073 case PMSR_SPEED_1000: 3074 state->speed = SPEED_1000; 3075 break; 3076 default: 3077 state->speed = SPEED_UNKNOWN; 3078 break; 3079 } 3080 3081 state->pause &= ~(MLO_PAUSE_RX | MLO_PAUSE_TX); 3082 if (pmsr & PMSR_RX_FC) 3083 state->pause |= MLO_PAUSE_RX; 3084 if (pmsr & PMSR_TX_FC) 3085 state->pause |= MLO_PAUSE_TX; 3086 } 3087 3088 static int mt753x_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode, 3089 phy_interface_t interface, 3090 const unsigned long *advertising, 3091 bool permit_pause_to_mac) 3092 { 3093 return 0; 3094 } 3095 3096 static void mt7530_pcs_an_restart(struct phylink_pcs *pcs) 3097 { 3098 } 3099 3100 static const struct phylink_pcs_ops mt7530_pcs_ops = { 3101 .pcs_validate = mt753x_pcs_validate, 3102 .pcs_get_state = mt7530_pcs_get_state, 3103 .pcs_config = mt753x_pcs_config, 3104 .pcs_an_restart = mt7530_pcs_an_restart, 3105 }; 3106 3107 static int 3108 mt753x_setup(struct dsa_switch *ds) 3109 { 3110 struct mt7530_priv *priv = ds->priv; 3111 int ret = priv->info->sw_setup(ds); 3112 int i; 3113 3114 if (ret) 3115 return ret; 3116 3117 ret = mt7530_setup_irq(priv); 3118 if (ret) 3119 return ret; 3120 3121 ret = mt7530_setup_mdio(priv); 3122 if (ret) 3123 return ret; 3124 3125 /* Initialise the PCS devices */ 3126 for (i = 0; i < priv->ds->num_ports; i++) { 3127 priv->pcs[i].pcs.ops = priv->info->pcs_ops; 3128 priv->pcs[i].priv = priv; 3129 priv->pcs[i].port = i; 3130 } 3131 3132 if (priv->create_sgmii) 3133 ret = priv->create_sgmii(priv); 3134 3135 if (ret && priv->irq_domain) 3136 mt7530_free_mdio_irq(priv); 3137 3138 return ret; 3139 } 3140 3141 static int mt753x_set_mac_eee(struct dsa_switch *ds, int port, 3142 struct ethtool_keee *e) 3143 { 3144 if (e->tx_lpi_timer > 0xFFF) 3145 return -EINVAL; 3146 3147 return 0; 3148 } 3149 3150 static void 3151 mt753x_conduit_state_change(struct dsa_switch *ds, 3152 const struct net_device *conduit, 3153 bool operational) 3154 { 3155 struct dsa_port *cpu_dp = conduit->dsa_ptr; 3156 struct mt7530_priv *priv = ds->priv; 3157 int val = 0; 3158 u8 mask; 3159 3160 /* Set the CPU port to trap frames to for MT7530. Trapped frames will be 3161 * forwarded to the numerically smallest CPU port whose conduit 3162 * interface is up. 3163 */ 3164 if (priv->id != ID_MT7530 && priv->id != ID_MT7621) 3165 return; 3166 3167 mask = BIT(cpu_dp->index); 3168 3169 if (operational) 3170 priv->active_cpu_ports |= mask; 3171 else 3172 priv->active_cpu_ports &= ~mask; 3173 3174 if (priv->active_cpu_ports) { 3175 val = MT7530_CPU_EN | 3176 MT7530_CPU_PORT(__ffs(priv->active_cpu_ports)); 3177 } 3178 3179 mt7530_rmw(priv, MT753X_MFC, MT7530_CPU_EN | MT7530_CPU_PORT_MASK, val); 3180 } 3181 3182 static int mt753x_tc_setup_qdisc_tbf(struct dsa_switch *ds, int port, 3183 struct tc_tbf_qopt_offload *qopt) 3184 { 3185 struct tc_tbf_qopt_offload_replace_params *p = &qopt->replace_params; 3186 struct mt7530_priv *priv = ds->priv; 3187 u32 rate = 0; 3188 3189 switch (qopt->command) { 3190 case TC_TBF_REPLACE: 3191 rate = div_u64(p->rate.rate_bytes_ps, 1000) << 3; /* kbps */ 3192 fallthrough; 3193 case TC_TBF_DESTROY: { 3194 u32 val, tick; 3195 3196 mt7530_rmw(priv, MT753X_GERLCR, EGR_BC_MASK, 3197 EGR_BC_CRC_IPG_PREAMBLE); 3198 3199 /* if rate is greater than 10Mbps tick is 1/32 ms, 3200 * 1ms otherwise 3201 */ 3202 tick = rate > 10000 ? 2 : 7; 3203 val = FIELD_PREP(ERLCR_CIR_MASK, (rate >> 5)) | 3204 FIELD_PREP(ERLCR_EN_MASK, !!rate) | 3205 FIELD_PREP(ERLCR_EXP_MASK, tick) | 3206 ERLCR_TBF_MODE_MASK | 3207 FIELD_PREP(ERLCR_MANT_MASK, 0xf); 3208 mt7530_write(priv, MT753X_ERLCR_P(port), val); 3209 break; 3210 } 3211 default: 3212 return -EOPNOTSUPP; 3213 } 3214 3215 return 0; 3216 } 3217 3218 static int mt753x_setup_tc(struct dsa_switch *ds, int port, 3219 enum tc_setup_type type, void *type_data) 3220 { 3221 switch (type) { 3222 case TC_SETUP_QDISC_TBF: 3223 return mt753x_tc_setup_qdisc_tbf(ds, port, type_data); 3224 default: 3225 return -EOPNOTSUPP; 3226 } 3227 } 3228 3229 static int mt7988_setup(struct dsa_switch *ds) 3230 { 3231 struct mt7530_priv *priv = ds->priv; 3232 3233 /* Reset the switch */ 3234 reset_control_assert(priv->rstc); 3235 usleep_range(20, 50); 3236 reset_control_deassert(priv->rstc); 3237 usleep_range(20, 50); 3238 3239 /* AN7583 require additional tweak to CONN_CFG */ 3240 if (priv->id == ID_AN7583) 3241 mt7530_rmw(priv, AN7583_GEPHY_CONN_CFG, 3242 AN7583_CSR_DPHY_CKIN_SEL | 3243 AN7583_CSR_PHY_CORE_REG_CLK_SEL | 3244 AN7583_CSR_ETHER_AFE_PWD, 3245 AN7583_CSR_DPHY_CKIN_SEL | 3246 AN7583_CSR_PHY_CORE_REG_CLK_SEL | 3247 FIELD_PREP(AN7583_CSR_ETHER_AFE_PWD, 0)); 3248 3249 /* Reset the switch PHYs */ 3250 mt7530_write(priv, MT7530_SYS_CTRL, SYS_CTRL_PHY_RST); 3251 3252 return mt7531_setup_common(ds); 3253 } 3254 3255 const struct dsa_switch_ops mt7530_switch_ops = { 3256 .get_tag_protocol = mtk_get_tag_protocol, 3257 .setup = mt753x_setup, 3258 .preferred_default_local_cpu_port = mt753x_preferred_default_local_cpu_port, 3259 .get_strings = mt7530_get_strings, 3260 .get_ethtool_stats = mt7530_get_ethtool_stats, 3261 .get_sset_count = mt7530_get_sset_count, 3262 .get_eth_mac_stats = mt7530_get_eth_mac_stats, 3263 .get_rmon_stats = mt7530_get_rmon_stats, 3264 .get_eth_ctrl_stats = mt7530_get_eth_ctrl_stats, 3265 .get_stats64 = mt7530_get_stats64, 3266 .set_ageing_time = mt7530_set_ageing_time, 3267 .port_enable = mt7530_port_enable, 3268 .port_disable = mt7530_port_disable, 3269 .port_change_mtu = mt7530_port_change_mtu, 3270 .port_max_mtu = mt7530_port_max_mtu, 3271 .port_stp_state_set = mt7530_stp_state_set, 3272 .port_pre_bridge_flags = mt7530_port_pre_bridge_flags, 3273 .port_bridge_flags = mt7530_port_bridge_flags, 3274 .port_bridge_join = mt7530_port_bridge_join, 3275 .port_bridge_leave = mt7530_port_bridge_leave, 3276 .port_fdb_add = mt7530_port_fdb_add, 3277 .port_fdb_del = mt7530_port_fdb_del, 3278 .port_fdb_dump = mt7530_port_fdb_dump, 3279 .port_mdb_add = mt7530_port_mdb_add, 3280 .port_mdb_del = mt7530_port_mdb_del, 3281 .port_vlan_filtering = mt7530_port_vlan_filtering, 3282 .port_vlan_add = mt7530_port_vlan_add, 3283 .port_vlan_del = mt7530_port_vlan_del, 3284 .port_mirror_add = mt753x_port_mirror_add, 3285 .port_mirror_del = mt753x_port_mirror_del, 3286 .phylink_get_caps = mt753x_phylink_get_caps, 3287 .support_eee = dsa_supports_eee, 3288 .set_mac_eee = mt753x_set_mac_eee, 3289 .conduit_state_change = mt753x_conduit_state_change, 3290 .port_setup_tc = mt753x_setup_tc, 3291 }; 3292 EXPORT_SYMBOL_GPL(mt7530_switch_ops); 3293 3294 static const struct phylink_mac_ops mt753x_phylink_mac_ops = { 3295 .mac_select_pcs = mt753x_phylink_mac_select_pcs, 3296 .mac_config = mt753x_phylink_mac_config, 3297 .mac_link_down = mt753x_phylink_mac_link_down, 3298 .mac_link_up = mt753x_phylink_mac_link_up, 3299 .mac_disable_tx_lpi = mt753x_phylink_mac_disable_tx_lpi, 3300 .mac_enable_tx_lpi = mt753x_phylink_mac_enable_tx_lpi, 3301 }; 3302 3303 const struct mt753x_info mt753x_table[] = { 3304 [ID_MT7621] = { 3305 .id = ID_MT7621, 3306 .pcs_ops = &mt7530_pcs_ops, 3307 .sw_setup = mt7530_setup, 3308 .phy_read_c22 = mt7530_phy_read_c22, 3309 .phy_write_c22 = mt7530_phy_write_c22, 3310 .phy_read_c45 = mt7530_phy_read_c45, 3311 .phy_write_c45 = mt7530_phy_write_c45, 3312 .mac_port_get_caps = mt7530_mac_port_get_caps, 3313 .mac_port_config = mt7530_mac_config, 3314 }, 3315 [ID_MT7530] = { 3316 .id = ID_MT7530, 3317 .pcs_ops = &mt7530_pcs_ops, 3318 .sw_setup = mt7530_setup, 3319 .phy_read_c22 = mt7530_phy_read_c22, 3320 .phy_write_c22 = mt7530_phy_write_c22, 3321 .phy_read_c45 = mt7530_phy_read_c45, 3322 .phy_write_c45 = mt7530_phy_write_c45, 3323 .mac_port_get_caps = mt7530_mac_port_get_caps, 3324 .mac_port_config = mt7530_mac_config, 3325 }, 3326 [ID_MT7531] = { 3327 .id = ID_MT7531, 3328 .pcs_ops = &mt7530_pcs_ops, 3329 .sw_setup = mt7531_setup, 3330 .phy_read_c22 = mt7531_ind_c22_phy_read, 3331 .phy_write_c22 = mt7531_ind_c22_phy_write, 3332 .phy_read_c45 = mt7531_ind_c45_phy_read, 3333 .phy_write_c45 = mt7531_ind_c45_phy_write, 3334 .mac_port_get_caps = mt7531_mac_port_get_caps, 3335 .mac_port_config = mt7531_mac_config, 3336 }, 3337 [ID_MT7988] = { 3338 .id = ID_MT7988, 3339 .pcs_ops = &mt7530_pcs_ops, 3340 .sw_setup = mt7988_setup, 3341 .phy_read_c22 = mt7531_ind_c22_phy_read, 3342 .phy_write_c22 = mt7531_ind_c22_phy_write, 3343 .phy_read_c45 = mt7531_ind_c45_phy_read, 3344 .phy_write_c45 = mt7531_ind_c45_phy_write, 3345 .mac_port_get_caps = mt7988_mac_port_get_caps, 3346 }, 3347 [ID_EN7581] = { 3348 .id = ID_EN7581, 3349 .pcs_ops = &mt7530_pcs_ops, 3350 .sw_setup = mt7988_setup, 3351 .phy_read_c22 = mt7531_ind_c22_phy_read, 3352 .phy_write_c22 = mt7531_ind_c22_phy_write, 3353 .phy_read_c45 = mt7531_ind_c45_phy_read, 3354 .phy_write_c45 = mt7531_ind_c45_phy_write, 3355 .mac_port_get_caps = en7581_mac_port_get_caps, 3356 }, 3357 [ID_AN7583] = { 3358 .id = ID_AN7583, 3359 .pcs_ops = &mt7530_pcs_ops, 3360 .sw_setup = mt7988_setup, 3361 .phy_read_c22 = mt7531_ind_c22_phy_read, 3362 .phy_write_c22 = mt7531_ind_c22_phy_write, 3363 .phy_read_c45 = mt7531_ind_c45_phy_read, 3364 .phy_write_c45 = mt7531_ind_c45_phy_write, 3365 .mac_port_get_caps = en7581_mac_port_get_caps, 3366 }, 3367 }; 3368 EXPORT_SYMBOL_GPL(mt753x_table); 3369 3370 int 3371 mt7530_probe_common(struct mt7530_priv *priv) 3372 { 3373 struct device *dev = priv->dev; 3374 3375 priv->ds = devm_kzalloc(dev, sizeof(*priv->ds), GFP_KERNEL); 3376 if (!priv->ds) 3377 return -ENOMEM; 3378 3379 priv->ds->dev = dev; 3380 priv->ds->num_ports = MT7530_NUM_PORTS; 3381 3382 /* Get the hardware identifier from the devicetree node. 3383 * We will need it for some of the clock and regulator setup. 3384 */ 3385 priv->info = of_device_get_match_data(dev); 3386 if (!priv->info) 3387 return -EINVAL; 3388 3389 priv->id = priv->info->id; 3390 priv->dev = dev; 3391 priv->ds->priv = priv; 3392 priv->ds->ops = &mt7530_switch_ops; 3393 priv->ds->phylink_mac_ops = &mt753x_phylink_mac_ops; 3394 mutex_init(&priv->reg_mutex); 3395 dev_set_drvdata(dev, priv); 3396 3397 return 0; 3398 } 3399 EXPORT_SYMBOL_GPL(mt7530_probe_common); 3400 3401 void 3402 mt7530_remove_common(struct mt7530_priv *priv) 3403 { 3404 if (priv->irq_domain) 3405 mt7530_free_mdio_irq(priv); 3406 3407 dsa_unregister_switch(priv->ds); 3408 3409 mutex_destroy(&priv->reg_mutex); 3410 } 3411 EXPORT_SYMBOL_GPL(mt7530_remove_common); 3412 3413 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>"); 3414 MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch"); 3415 MODULE_LICENSE("GPL"); 3416